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TARGET_DISCO_F769NI/TOOLCHAIN_ARM_STD/stm32f7xx_ll_dma.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f7xx_ll_dma.h |
AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of DMA LL module. |
AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 32 | * |
AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F7xx_LL_DMA_H |
AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F7xx_LL_DMA_H |
AnnaBridge | 171:3a7713b1edbc | 39 | |
AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f7xx.h" |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F7xx_LL_Driver |
AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 49 | */ |
AnnaBridge | 171:3a7713b1edbc | 50 | |
AnnaBridge | 171:3a7713b1edbc | 51 | #if defined (DMA1) || defined (DMA2) |
AnnaBridge | 171:3a7713b1edbc | 52 | |
AnnaBridge | 171:3a7713b1edbc | 53 | /** @defgroup DMA_LL DMA |
AnnaBridge | 171:3a7713b1edbc | 54 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 55 | */ |
AnnaBridge | 171:3a7713b1edbc | 56 | |
AnnaBridge | 171:3a7713b1edbc | 57 | /* Private types -------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 58 | /* Private variables ---------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 59 | /** @defgroup DMA_LL_Private_Variables DMA Private Variables |
AnnaBridge | 171:3a7713b1edbc | 60 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 61 | */ |
AnnaBridge | 171:3a7713b1edbc | 62 | /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ |
AnnaBridge | 171:3a7713b1edbc | 63 | static const uint8_t STREAM_OFFSET_TAB[] = |
AnnaBridge | 171:3a7713b1edbc | 64 | { |
AnnaBridge | 171:3a7713b1edbc | 65 | (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), |
AnnaBridge | 171:3a7713b1edbc | 66 | (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), |
AnnaBridge | 171:3a7713b1edbc | 67 | (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), |
AnnaBridge | 171:3a7713b1edbc | 68 | (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), |
AnnaBridge | 171:3a7713b1edbc | 69 | (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), |
AnnaBridge | 171:3a7713b1edbc | 70 | (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), |
AnnaBridge | 171:3a7713b1edbc | 71 | (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), |
AnnaBridge | 171:3a7713b1edbc | 72 | (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) |
AnnaBridge | 171:3a7713b1edbc | 73 | }; |
AnnaBridge | 171:3a7713b1edbc | 74 | |
AnnaBridge | 171:3a7713b1edbc | 75 | /** |
AnnaBridge | 171:3a7713b1edbc | 76 | * @} |
AnnaBridge | 171:3a7713b1edbc | 77 | */ |
AnnaBridge | 171:3a7713b1edbc | 78 | |
AnnaBridge | 171:3a7713b1edbc | 79 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 80 | /** @defgroup DMA_LL_Private_Constants DMA Private Constants |
AnnaBridge | 171:3a7713b1edbc | 81 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 82 | */ |
AnnaBridge | 171:3a7713b1edbc | 83 | #if defined(DMA_SxCR_CHSEL_3) |
AnnaBridge | 171:3a7713b1edbc | 84 | #define DMA_CHANNEL_SELECTION_8_15 |
AnnaBridge | 171:3a7713b1edbc | 85 | #endif /* DMA_SxCR_CHSEL_3 */ |
AnnaBridge | 171:3a7713b1edbc | 86 | /** |
AnnaBridge | 171:3a7713b1edbc | 87 | * @} |
AnnaBridge | 171:3a7713b1edbc | 88 | */ |
AnnaBridge | 171:3a7713b1edbc | 89 | |
AnnaBridge | 171:3a7713b1edbc | 90 | |
AnnaBridge | 171:3a7713b1edbc | 91 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 92 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 93 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 94 | /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure |
AnnaBridge | 171:3a7713b1edbc | 95 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 96 | */ |
AnnaBridge | 171:3a7713b1edbc | 97 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 98 | { |
AnnaBridge | 171:3a7713b1edbc | 99 | uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer |
AnnaBridge | 171:3a7713b1edbc | 100 | or as Source base address in case of memory to memory transfer direction. |
AnnaBridge | 171:3a7713b1edbc | 101 | |
AnnaBridge | 171:3a7713b1edbc | 102 | This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ |
AnnaBridge | 171:3a7713b1edbc | 103 | |
AnnaBridge | 171:3a7713b1edbc | 104 | uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer |
AnnaBridge | 171:3a7713b1edbc | 105 | or as Destination base address in case of memory to memory transfer direction. |
AnnaBridge | 171:3a7713b1edbc | 106 | |
AnnaBridge | 171:3a7713b1edbc | 107 | This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ |
AnnaBridge | 171:3a7713b1edbc | 108 | |
AnnaBridge | 171:3a7713b1edbc | 109 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
AnnaBridge | 171:3a7713b1edbc | 110 | from memory to memory or from peripheral to memory. |
AnnaBridge | 171:3a7713b1edbc | 111 | This parameter can be a value of @ref DMA_LL_EC_DIRECTION |
AnnaBridge | 171:3a7713b1edbc | 112 | |
AnnaBridge | 171:3a7713b1edbc | 113 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ |
AnnaBridge | 171:3a7713b1edbc | 114 | |
AnnaBridge | 171:3a7713b1edbc | 115 | uint32_t Mode; /*!< Specifies the normal or circular operation mode. |
AnnaBridge | 171:3a7713b1edbc | 116 | This parameter can be a value of @ref DMA_LL_EC_MODE |
AnnaBridge | 171:3a7713b1edbc | 117 | @note The circular buffer mode cannot be used if the memory to memory |
AnnaBridge | 171:3a7713b1edbc | 118 | data transfer direction is configured on the selected Stream |
AnnaBridge | 171:3a7713b1edbc | 119 | |
AnnaBridge | 171:3a7713b1edbc | 120 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ |
AnnaBridge | 171:3a7713b1edbc | 121 | |
AnnaBridge | 171:3a7713b1edbc | 122 | uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction |
AnnaBridge | 171:3a7713b1edbc | 123 | is incremented or not. |
AnnaBridge | 171:3a7713b1edbc | 124 | This parameter can be a value of @ref DMA_LL_EC_PERIPH |
AnnaBridge | 171:3a7713b1edbc | 125 | |
AnnaBridge | 171:3a7713b1edbc | 126 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ |
AnnaBridge | 171:3a7713b1edbc | 127 | |
AnnaBridge | 171:3a7713b1edbc | 128 | uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction |
AnnaBridge | 171:3a7713b1edbc | 129 | is incremented or not. |
AnnaBridge | 171:3a7713b1edbc | 130 | This parameter can be a value of @ref DMA_LL_EC_MEMORY |
AnnaBridge | 171:3a7713b1edbc | 131 | |
AnnaBridge | 171:3a7713b1edbc | 132 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ |
AnnaBridge | 171:3a7713b1edbc | 133 | |
AnnaBridge | 171:3a7713b1edbc | 134 | uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) |
AnnaBridge | 171:3a7713b1edbc | 135 | in case of memory to memory transfer direction. |
AnnaBridge | 171:3a7713b1edbc | 136 | This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN |
AnnaBridge | 171:3a7713b1edbc | 137 | |
AnnaBridge | 171:3a7713b1edbc | 138 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ |
AnnaBridge | 171:3a7713b1edbc | 139 | |
AnnaBridge | 171:3a7713b1edbc | 140 | uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) |
AnnaBridge | 171:3a7713b1edbc | 141 | in case of memory to memory transfer direction. |
AnnaBridge | 171:3a7713b1edbc | 142 | This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN |
AnnaBridge | 171:3a7713b1edbc | 143 | |
AnnaBridge | 171:3a7713b1edbc | 144 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ |
AnnaBridge | 171:3a7713b1edbc | 145 | |
AnnaBridge | 171:3a7713b1edbc | 146 | uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. |
AnnaBridge | 171:3a7713b1edbc | 147 | The data unit is equal to the source buffer configuration set in PeripheralSize |
AnnaBridge | 171:3a7713b1edbc | 148 | or MemorySize parameters depending in the transfer direction. |
AnnaBridge | 171:3a7713b1edbc | 149 | This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF |
AnnaBridge | 171:3a7713b1edbc | 150 | |
AnnaBridge | 171:3a7713b1edbc | 151 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ |
AnnaBridge | 171:3a7713b1edbc | 152 | |
AnnaBridge | 171:3a7713b1edbc | 153 | uint32_t Channel; /*!< Specifies the peripheral channel. |
AnnaBridge | 171:3a7713b1edbc | 154 | This parameter can be a value of @ref DMA_LL_EC_CHANNEL |
AnnaBridge | 171:3a7713b1edbc | 155 | |
AnnaBridge | 171:3a7713b1edbc | 156 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */ |
AnnaBridge | 171:3a7713b1edbc | 157 | |
AnnaBridge | 171:3a7713b1edbc | 158 | uint32_t Priority; /*!< Specifies the channel priority level. |
AnnaBridge | 171:3a7713b1edbc | 159 | This parameter can be a value of @ref DMA_LL_EC_PRIORITY |
AnnaBridge | 171:3a7713b1edbc | 160 | |
AnnaBridge | 171:3a7713b1edbc | 161 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */ |
AnnaBridge | 171:3a7713b1edbc | 162 | |
AnnaBridge | 171:3a7713b1edbc | 163 | uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. |
AnnaBridge | 171:3a7713b1edbc | 164 | This parameter can be a value of @ref DMA_LL_FIFOMODE |
AnnaBridge | 171:3a7713b1edbc | 165 | @note The Direct mode (FIFO mode disabled) cannot be used if the |
AnnaBridge | 171:3a7713b1edbc | 166 | memory-to-memory data transfer is configured on the selected stream |
AnnaBridge | 171:3a7713b1edbc | 167 | |
AnnaBridge | 171:3a7713b1edbc | 168 | This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */ |
AnnaBridge | 171:3a7713b1edbc | 169 | |
AnnaBridge | 171:3a7713b1edbc | 170 | uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. |
AnnaBridge | 171:3a7713b1edbc | 171 | This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD |
AnnaBridge | 171:3a7713b1edbc | 172 | |
AnnaBridge | 171:3a7713b1edbc | 173 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */ |
AnnaBridge | 171:3a7713b1edbc | 174 | |
AnnaBridge | 171:3a7713b1edbc | 175 | uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. |
AnnaBridge | 171:3a7713b1edbc | 176 | It specifies the amount of data to be transferred in a single non interruptible |
AnnaBridge | 171:3a7713b1edbc | 177 | transaction. |
AnnaBridge | 171:3a7713b1edbc | 178 | This parameter can be a value of @ref DMA_LL_EC_MBURST |
AnnaBridge | 171:3a7713b1edbc | 179 | @note The burst mode is possible only if the address Increment mode is enabled. |
AnnaBridge | 171:3a7713b1edbc | 180 | |
AnnaBridge | 171:3a7713b1edbc | 181 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */ |
AnnaBridge | 171:3a7713b1edbc | 182 | |
AnnaBridge | 171:3a7713b1edbc | 183 | uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. |
AnnaBridge | 171:3a7713b1edbc | 184 | It specifies the amount of data to be transferred in a single non interruptible |
AnnaBridge | 171:3a7713b1edbc | 185 | transaction. |
AnnaBridge | 171:3a7713b1edbc | 186 | This parameter can be a value of @ref DMA_LL_EC_PBURST |
AnnaBridge | 171:3a7713b1edbc | 187 | @note The burst mode is possible only if the address Increment mode is enabled. |
AnnaBridge | 171:3a7713b1edbc | 188 | |
AnnaBridge | 171:3a7713b1edbc | 189 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */ |
AnnaBridge | 171:3a7713b1edbc | 190 | |
AnnaBridge | 171:3a7713b1edbc | 191 | } LL_DMA_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 192 | /** |
AnnaBridge | 171:3a7713b1edbc | 193 | * @} |
AnnaBridge | 171:3a7713b1edbc | 194 | */ |
AnnaBridge | 171:3a7713b1edbc | 195 | #endif /*USE_FULL_LL_DRIVER*/ |
AnnaBridge | 171:3a7713b1edbc | 196 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 197 | /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants |
AnnaBridge | 171:3a7713b1edbc | 198 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 199 | */ |
AnnaBridge | 171:3a7713b1edbc | 200 | |
AnnaBridge | 171:3a7713b1edbc | 201 | /** @defgroup DMA_LL_EC_STREAM STREAM |
AnnaBridge | 171:3a7713b1edbc | 202 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 203 | */ |
AnnaBridge | 171:3a7713b1edbc | 204 | #define LL_DMA_STREAM_0 0x00000000U |
AnnaBridge | 171:3a7713b1edbc | 205 | #define LL_DMA_STREAM_1 0x00000001U |
AnnaBridge | 171:3a7713b1edbc | 206 | #define LL_DMA_STREAM_2 0x00000002U |
AnnaBridge | 171:3a7713b1edbc | 207 | #define LL_DMA_STREAM_3 0x00000003U |
AnnaBridge | 171:3a7713b1edbc | 208 | #define LL_DMA_STREAM_4 0x00000004U |
AnnaBridge | 171:3a7713b1edbc | 209 | #define LL_DMA_STREAM_5 0x00000005U |
AnnaBridge | 171:3a7713b1edbc | 210 | #define LL_DMA_STREAM_6 0x00000006U |
AnnaBridge | 171:3a7713b1edbc | 211 | #define LL_DMA_STREAM_7 0x00000007U |
AnnaBridge | 171:3a7713b1edbc | 212 | #define LL_DMA_STREAM_ALL 0xFFFF0000U |
AnnaBridge | 171:3a7713b1edbc | 213 | /** |
AnnaBridge | 171:3a7713b1edbc | 214 | * @} |
AnnaBridge | 171:3a7713b1edbc | 215 | */ |
AnnaBridge | 171:3a7713b1edbc | 216 | |
AnnaBridge | 171:3a7713b1edbc | 217 | /** @defgroup DMA_LL_EC_DIRECTION DIRECTION |
AnnaBridge | 171:3a7713b1edbc | 218 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 219 | */ |
AnnaBridge | 171:3a7713b1edbc | 220 | #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ |
AnnaBridge | 171:3a7713b1edbc | 221 | #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ |
AnnaBridge | 171:3a7713b1edbc | 222 | #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ |
AnnaBridge | 171:3a7713b1edbc | 223 | /** |
AnnaBridge | 171:3a7713b1edbc | 224 | * @} |
AnnaBridge | 171:3a7713b1edbc | 225 | */ |
AnnaBridge | 171:3a7713b1edbc | 226 | |
AnnaBridge | 171:3a7713b1edbc | 227 | /** @defgroup DMA_LL_EC_MODE MODE |
AnnaBridge | 171:3a7713b1edbc | 228 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 229 | */ |
AnnaBridge | 171:3a7713b1edbc | 230 | #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ |
AnnaBridge | 171:3a7713b1edbc | 231 | #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */ |
AnnaBridge | 171:3a7713b1edbc | 232 | #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ |
AnnaBridge | 171:3a7713b1edbc | 233 | /** |
AnnaBridge | 171:3a7713b1edbc | 234 | * @} |
AnnaBridge | 171:3a7713b1edbc | 235 | */ |
AnnaBridge | 171:3a7713b1edbc | 236 | |
AnnaBridge | 171:3a7713b1edbc | 237 | /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE MODE |
AnnaBridge | 171:3a7713b1edbc | 238 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 239 | */ |
AnnaBridge | 171:3a7713b1edbc | 240 | #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ |
AnnaBridge | 171:3a7713b1edbc | 241 | #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */ |
AnnaBridge | 171:3a7713b1edbc | 242 | /** |
AnnaBridge | 171:3a7713b1edbc | 243 | * @} |
AnnaBridge | 171:3a7713b1edbc | 244 | */ |
AnnaBridge | 171:3a7713b1edbc | 245 | |
AnnaBridge | 171:3a7713b1edbc | 246 | /** @defgroup DMA_LL_EC_PERIPH PERIPH |
AnnaBridge | 171:3a7713b1edbc | 247 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 248 | */ |
AnnaBridge | 171:3a7713b1edbc | 249 | #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ |
AnnaBridge | 171:3a7713b1edbc | 250 | #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */ |
AnnaBridge | 171:3a7713b1edbc | 251 | /** |
AnnaBridge | 171:3a7713b1edbc | 252 | * @} |
AnnaBridge | 171:3a7713b1edbc | 253 | */ |
AnnaBridge | 171:3a7713b1edbc | 254 | |
AnnaBridge | 171:3a7713b1edbc | 255 | /** @defgroup DMA_LL_EC_MEMORY MEMORY |
AnnaBridge | 171:3a7713b1edbc | 256 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 257 | */ |
AnnaBridge | 171:3a7713b1edbc | 258 | #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ |
AnnaBridge | 171:3a7713b1edbc | 259 | #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */ |
AnnaBridge | 171:3a7713b1edbc | 260 | /** |
AnnaBridge | 171:3a7713b1edbc | 261 | * @} |
AnnaBridge | 171:3a7713b1edbc | 262 | */ |
AnnaBridge | 171:3a7713b1edbc | 263 | |
AnnaBridge | 171:3a7713b1edbc | 264 | /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN |
AnnaBridge | 171:3a7713b1edbc | 265 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 266 | */ |
AnnaBridge | 171:3a7713b1edbc | 267 | #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ |
AnnaBridge | 171:3a7713b1edbc | 268 | #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ |
AnnaBridge | 171:3a7713b1edbc | 269 | #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */ |
AnnaBridge | 171:3a7713b1edbc | 270 | /** |
AnnaBridge | 171:3a7713b1edbc | 271 | * @} |
AnnaBridge | 171:3a7713b1edbc | 272 | */ |
AnnaBridge | 171:3a7713b1edbc | 273 | |
AnnaBridge | 171:3a7713b1edbc | 274 | /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN |
AnnaBridge | 171:3a7713b1edbc | 275 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 276 | */ |
AnnaBridge | 171:3a7713b1edbc | 277 | #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ |
AnnaBridge | 171:3a7713b1edbc | 278 | #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ |
AnnaBridge | 171:3a7713b1edbc | 279 | #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */ |
AnnaBridge | 171:3a7713b1edbc | 280 | /** |
AnnaBridge | 171:3a7713b1edbc | 281 | * @} |
AnnaBridge | 171:3a7713b1edbc | 282 | */ |
AnnaBridge | 171:3a7713b1edbc | 283 | |
AnnaBridge | 171:3a7713b1edbc | 284 | /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE |
AnnaBridge | 171:3a7713b1edbc | 285 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 286 | */ |
AnnaBridge | 171:3a7713b1edbc | 287 | #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */ |
AnnaBridge | 171:3a7713b1edbc | 288 | #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */ |
AnnaBridge | 171:3a7713b1edbc | 289 | /** |
AnnaBridge | 171:3a7713b1edbc | 290 | * @} |
AnnaBridge | 171:3a7713b1edbc | 291 | */ |
AnnaBridge | 171:3a7713b1edbc | 292 | |
AnnaBridge | 171:3a7713b1edbc | 293 | /** @defgroup DMA_LL_EC_PRIORITY PRIORITY |
AnnaBridge | 171:3a7713b1edbc | 294 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 295 | */ |
AnnaBridge | 171:3a7713b1edbc | 296 | #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ |
AnnaBridge | 171:3a7713b1edbc | 297 | #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */ |
AnnaBridge | 171:3a7713b1edbc | 298 | #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */ |
AnnaBridge | 171:3a7713b1edbc | 299 | #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */ |
AnnaBridge | 171:3a7713b1edbc | 300 | /** |
AnnaBridge | 171:3a7713b1edbc | 301 | * @} |
AnnaBridge | 171:3a7713b1edbc | 302 | */ |
AnnaBridge | 171:3a7713b1edbc | 303 | |
AnnaBridge | 171:3a7713b1edbc | 304 | /** @defgroup DMA_LL_EC_CHANNEL CHANNEL |
AnnaBridge | 171:3a7713b1edbc | 305 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 306 | */ |
AnnaBridge | 171:3a7713b1edbc | 307 | #define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */ |
AnnaBridge | 171:3a7713b1edbc | 308 | #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */ |
AnnaBridge | 171:3a7713b1edbc | 309 | #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */ |
AnnaBridge | 171:3a7713b1edbc | 310 | #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */ |
AnnaBridge | 171:3a7713b1edbc | 311 | #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */ |
AnnaBridge | 171:3a7713b1edbc | 312 | #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */ |
AnnaBridge | 171:3a7713b1edbc | 313 | #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */ |
AnnaBridge | 171:3a7713b1edbc | 314 | #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */ |
AnnaBridge | 171:3a7713b1edbc | 315 | #if defined(DMA_CHANNEL_SELECTION_8_15) |
AnnaBridge | 171:3a7713b1edbc | 316 | #define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 /* Select Channel8 of DMA Instance */ |
AnnaBridge | 171:3a7713b1edbc | 317 | #define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) /* Select Channel9 of DMA Instance */ |
AnnaBridge | 171:3a7713b1edbc | 318 | #define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) /* Select Channel10 of DMA Instance */ |
AnnaBridge | 171:3a7713b1edbc | 319 | #define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel11 of DMA Instance */ |
AnnaBridge | 171:3a7713b1edbc | 320 | #define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) /* Select Channel12 of DMA Instance */ |
AnnaBridge | 171:3a7713b1edbc | 321 | #define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel13 of DMA Instance */ |
AnnaBridge | 171:3a7713b1edbc | 322 | #define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel14 of DMA Instance */ |
AnnaBridge | 171:3a7713b1edbc | 323 | #define LL_DMA_CHANNEL_15 DMA_SxCR_CHSEL /* Select Channel15 of DMA Instance */ |
AnnaBridge | 171:3a7713b1edbc | 324 | #endif /* DMA_CHANNEL_SELECTION_8_15 */ |
AnnaBridge | 171:3a7713b1edbc | 325 | /** |
AnnaBridge | 171:3a7713b1edbc | 326 | * @} |
AnnaBridge | 171:3a7713b1edbc | 327 | */ |
AnnaBridge | 171:3a7713b1edbc | 328 | |
AnnaBridge | 171:3a7713b1edbc | 329 | /** @defgroup DMA_LL_EC_MBURST MBURST |
AnnaBridge | 171:3a7713b1edbc | 330 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 331 | */ |
AnnaBridge | 171:3a7713b1edbc | 332 | #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */ |
AnnaBridge | 171:3a7713b1edbc | 333 | #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */ |
AnnaBridge | 171:3a7713b1edbc | 334 | #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */ |
AnnaBridge | 171:3a7713b1edbc | 335 | #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */ |
AnnaBridge | 171:3a7713b1edbc | 336 | /** |
AnnaBridge | 171:3a7713b1edbc | 337 | * @} |
AnnaBridge | 171:3a7713b1edbc | 338 | */ |
AnnaBridge | 171:3a7713b1edbc | 339 | |
AnnaBridge | 171:3a7713b1edbc | 340 | /** @defgroup DMA_LL_EC_PBURST PBURST |
AnnaBridge | 171:3a7713b1edbc | 341 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 342 | */ |
AnnaBridge | 171:3a7713b1edbc | 343 | #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */ |
AnnaBridge | 171:3a7713b1edbc | 344 | #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */ |
AnnaBridge | 171:3a7713b1edbc | 345 | #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */ |
AnnaBridge | 171:3a7713b1edbc | 346 | #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */ |
AnnaBridge | 171:3a7713b1edbc | 347 | /** |
AnnaBridge | 171:3a7713b1edbc | 348 | * @} |
AnnaBridge | 171:3a7713b1edbc | 349 | */ |
AnnaBridge | 171:3a7713b1edbc | 350 | |
AnnaBridge | 171:3a7713b1edbc | 351 | /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE |
AnnaBridge | 171:3a7713b1edbc | 352 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 353 | */ |
AnnaBridge | 171:3a7713b1edbc | 354 | #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */ |
AnnaBridge | 171:3a7713b1edbc | 355 | #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ |
AnnaBridge | 171:3a7713b1edbc | 356 | /** |
AnnaBridge | 171:3a7713b1edbc | 357 | * @} |
AnnaBridge | 171:3a7713b1edbc | 358 | */ |
AnnaBridge | 171:3a7713b1edbc | 359 | |
AnnaBridge | 171:3a7713b1edbc | 360 | /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 |
AnnaBridge | 171:3a7713b1edbc | 361 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 362 | */ |
AnnaBridge | 171:3a7713b1edbc | 363 | #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */ |
AnnaBridge | 171:3a7713b1edbc | 364 | #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */ |
AnnaBridge | 171:3a7713b1edbc | 365 | #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */ |
AnnaBridge | 171:3a7713b1edbc | 366 | #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */ |
AnnaBridge | 171:3a7713b1edbc | 367 | #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */ |
AnnaBridge | 171:3a7713b1edbc | 368 | #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */ |
AnnaBridge | 171:3a7713b1edbc | 369 | /** |
AnnaBridge | 171:3a7713b1edbc | 370 | * @} |
AnnaBridge | 171:3a7713b1edbc | 371 | */ |
AnnaBridge | 171:3a7713b1edbc | 372 | |
AnnaBridge | 171:3a7713b1edbc | 373 | /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD |
AnnaBridge | 171:3a7713b1edbc | 374 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 375 | */ |
AnnaBridge | 171:3a7713b1edbc | 376 | #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */ |
AnnaBridge | 171:3a7713b1edbc | 377 | #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ |
AnnaBridge | 171:3a7713b1edbc | 378 | #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ |
AnnaBridge | 171:3a7713b1edbc | 379 | #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ |
AnnaBridge | 171:3a7713b1edbc | 380 | /** |
AnnaBridge | 171:3a7713b1edbc | 381 | * @} |
AnnaBridge | 171:3a7713b1edbc | 382 | */ |
AnnaBridge | 171:3a7713b1edbc | 383 | |
AnnaBridge | 171:3a7713b1edbc | 384 | /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM |
AnnaBridge | 171:3a7713b1edbc | 385 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 386 | */ |
AnnaBridge | 171:3a7713b1edbc | 387 | #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ |
AnnaBridge | 171:3a7713b1edbc | 388 | #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ |
AnnaBridge | 171:3a7713b1edbc | 389 | /** |
AnnaBridge | 171:3a7713b1edbc | 390 | * @} |
AnnaBridge | 171:3a7713b1edbc | 391 | */ |
AnnaBridge | 171:3a7713b1edbc | 392 | |
AnnaBridge | 171:3a7713b1edbc | 393 | /** |
AnnaBridge | 171:3a7713b1edbc | 394 | * @} |
AnnaBridge | 171:3a7713b1edbc | 395 | */ |
AnnaBridge | 171:3a7713b1edbc | 396 | |
AnnaBridge | 171:3a7713b1edbc | 397 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 398 | /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros |
AnnaBridge | 171:3a7713b1edbc | 399 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 400 | */ |
AnnaBridge | 171:3a7713b1edbc | 401 | |
AnnaBridge | 171:3a7713b1edbc | 402 | /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros |
AnnaBridge | 171:3a7713b1edbc | 403 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 404 | */ |
AnnaBridge | 171:3a7713b1edbc | 405 | /** |
AnnaBridge | 171:3a7713b1edbc | 406 | * @brief Write a value in DMA register |
AnnaBridge | 171:3a7713b1edbc | 407 | * @param __INSTANCE__ DMA Instance |
AnnaBridge | 171:3a7713b1edbc | 408 | * @param __REG__ Register to be written |
AnnaBridge | 171:3a7713b1edbc | 409 | * @param __VALUE__ Value to be written in the register |
AnnaBridge | 171:3a7713b1edbc | 410 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 411 | */ |
AnnaBridge | 171:3a7713b1edbc | 412 | #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
AnnaBridge | 171:3a7713b1edbc | 413 | |
AnnaBridge | 171:3a7713b1edbc | 414 | /** |
AnnaBridge | 171:3a7713b1edbc | 415 | * @brief Read a value in DMA register |
AnnaBridge | 171:3a7713b1edbc | 416 | * @param __INSTANCE__ DMA Instance |
AnnaBridge | 171:3a7713b1edbc | 417 | * @param __REG__ Register to be read |
AnnaBridge | 171:3a7713b1edbc | 418 | * @retval Register value |
AnnaBridge | 171:3a7713b1edbc | 419 | */ |
AnnaBridge | 171:3a7713b1edbc | 420 | #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
AnnaBridge | 171:3a7713b1edbc | 421 | /** |
AnnaBridge | 171:3a7713b1edbc | 422 | * @} |
AnnaBridge | 171:3a7713b1edbc | 423 | */ |
AnnaBridge | 171:3a7713b1edbc | 424 | |
AnnaBridge | 171:3a7713b1edbc | 425 | /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy |
AnnaBridge | 171:3a7713b1edbc | 426 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 427 | */ |
AnnaBridge | 171:3a7713b1edbc | 428 | /** |
AnnaBridge | 171:3a7713b1edbc | 429 | * @brief Convert DMAx_Streamy into DMAx |
AnnaBridge | 171:3a7713b1edbc | 430 | * @param __STREAM_INSTANCE__ DMAx_Streamy |
AnnaBridge | 171:3a7713b1edbc | 431 | * @retval DMAx |
AnnaBridge | 171:3a7713b1edbc | 432 | */ |
AnnaBridge | 171:3a7713b1edbc | 433 | #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 434 | (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) |
AnnaBridge | 171:3a7713b1edbc | 435 | |
AnnaBridge | 171:3a7713b1edbc | 436 | /** |
AnnaBridge | 171:3a7713b1edbc | 437 | * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y |
AnnaBridge | 171:3a7713b1edbc | 438 | * @param __STREAM_INSTANCE__ DMAx_Streamy |
AnnaBridge | 171:3a7713b1edbc | 439 | * @retval LL_DMA_CHANNEL_y |
AnnaBridge | 171:3a7713b1edbc | 440 | */ |
AnnaBridge | 171:3a7713b1edbc | 441 | #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ |
AnnaBridge | 171:3a7713b1edbc | 442 | (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ |
AnnaBridge | 171:3a7713b1edbc | 443 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ |
AnnaBridge | 171:3a7713b1edbc | 444 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ |
AnnaBridge | 171:3a7713b1edbc | 445 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ |
AnnaBridge | 171:3a7713b1edbc | 446 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ |
AnnaBridge | 171:3a7713b1edbc | 447 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ |
AnnaBridge | 171:3a7713b1edbc | 448 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ |
AnnaBridge | 171:3a7713b1edbc | 449 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ |
AnnaBridge | 171:3a7713b1edbc | 450 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ |
AnnaBridge | 171:3a7713b1edbc | 451 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ |
AnnaBridge | 171:3a7713b1edbc | 452 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ |
AnnaBridge | 171:3a7713b1edbc | 453 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ |
AnnaBridge | 171:3a7713b1edbc | 454 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ |
AnnaBridge | 171:3a7713b1edbc | 455 | ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ |
AnnaBridge | 171:3a7713b1edbc | 456 | LL_DMA_STREAM_7) |
AnnaBridge | 171:3a7713b1edbc | 457 | |
AnnaBridge | 171:3a7713b1edbc | 458 | /** |
AnnaBridge | 171:3a7713b1edbc | 459 | * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy |
AnnaBridge | 171:3a7713b1edbc | 460 | * @param __DMA_INSTANCE__ DMAx |
AnnaBridge | 171:3a7713b1edbc | 461 | * @param __STREAM__ LL_DMA_STREAM_y |
AnnaBridge | 171:3a7713b1edbc | 462 | * @retval DMAx_Streamy |
AnnaBridge | 171:3a7713b1edbc | 463 | */ |
AnnaBridge | 171:3a7713b1edbc | 464 | #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ |
AnnaBridge | 171:3a7713b1edbc | 465 | ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \ |
AnnaBridge | 171:3a7713b1edbc | 466 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \ |
AnnaBridge | 171:3a7713b1edbc | 467 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \ |
AnnaBridge | 171:3a7713b1edbc | 468 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \ |
AnnaBridge | 171:3a7713b1edbc | 469 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \ |
AnnaBridge | 171:3a7713b1edbc | 470 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \ |
AnnaBridge | 171:3a7713b1edbc | 471 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \ |
AnnaBridge | 171:3a7713b1edbc | 472 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \ |
AnnaBridge | 171:3a7713b1edbc | 473 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \ |
AnnaBridge | 171:3a7713b1edbc | 474 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \ |
AnnaBridge | 171:3a7713b1edbc | 475 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \ |
AnnaBridge | 171:3a7713b1edbc | 476 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \ |
AnnaBridge | 171:3a7713b1edbc | 477 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \ |
AnnaBridge | 171:3a7713b1edbc | 478 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \ |
AnnaBridge | 171:3a7713b1edbc | 479 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \ |
AnnaBridge | 171:3a7713b1edbc | 480 | DMA2_Stream7) |
AnnaBridge | 171:3a7713b1edbc | 481 | |
AnnaBridge | 171:3a7713b1edbc | 482 | /** |
AnnaBridge | 171:3a7713b1edbc | 483 | * @} |
AnnaBridge | 171:3a7713b1edbc | 484 | */ |
AnnaBridge | 171:3a7713b1edbc | 485 | |
AnnaBridge | 171:3a7713b1edbc | 486 | /** |
AnnaBridge | 171:3a7713b1edbc | 487 | * @} |
AnnaBridge | 171:3a7713b1edbc | 488 | */ |
AnnaBridge | 171:3a7713b1edbc | 489 | |
AnnaBridge | 171:3a7713b1edbc | 490 | |
AnnaBridge | 171:3a7713b1edbc | 491 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 492 | /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions |
AnnaBridge | 171:3a7713b1edbc | 493 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 494 | */ |
AnnaBridge | 171:3a7713b1edbc | 495 | |
AnnaBridge | 171:3a7713b1edbc | 496 | /** @defgroup DMA_LL_EF_Configuration Configuration |
AnnaBridge | 171:3a7713b1edbc | 497 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 498 | */ |
AnnaBridge | 171:3a7713b1edbc | 499 | /** |
AnnaBridge | 171:3a7713b1edbc | 500 | * @brief Enable DMA stream. |
AnnaBridge | 171:3a7713b1edbc | 501 | * @rmtoll CR EN LL_DMA_EnableStream |
AnnaBridge | 171:3a7713b1edbc | 502 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 503 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 504 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 505 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 506 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 507 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 508 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 509 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 510 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 511 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 512 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 513 | */ |
AnnaBridge | 171:3a7713b1edbc | 514 | __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 515 | { |
AnnaBridge | 171:3a7713b1edbc | 516 | SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); |
AnnaBridge | 171:3a7713b1edbc | 517 | } |
AnnaBridge | 171:3a7713b1edbc | 518 | |
AnnaBridge | 171:3a7713b1edbc | 519 | /** |
AnnaBridge | 171:3a7713b1edbc | 520 | * @brief Disable DMA stream. |
AnnaBridge | 171:3a7713b1edbc | 521 | * @rmtoll CR EN LL_DMA_DisableStream |
AnnaBridge | 171:3a7713b1edbc | 522 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 523 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 524 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 525 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 526 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 527 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 528 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 529 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 530 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 531 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 532 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 533 | */ |
AnnaBridge | 171:3a7713b1edbc | 534 | __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 535 | { |
AnnaBridge | 171:3a7713b1edbc | 536 | CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); |
AnnaBridge | 171:3a7713b1edbc | 537 | } |
AnnaBridge | 171:3a7713b1edbc | 538 | |
AnnaBridge | 171:3a7713b1edbc | 539 | /** |
AnnaBridge | 171:3a7713b1edbc | 540 | * @brief Check if DMA stream is enabled or disabled. |
AnnaBridge | 171:3a7713b1edbc | 541 | * @rmtoll CR EN LL_DMA_IsEnabledStream |
AnnaBridge | 171:3a7713b1edbc | 542 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 543 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 544 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 545 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 546 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 547 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 548 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 549 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 550 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 551 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 552 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 553 | */ |
AnnaBridge | 171:3a7713b1edbc | 554 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 555 | { |
AnnaBridge | 171:3a7713b1edbc | 556 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)); |
AnnaBridge | 171:3a7713b1edbc | 557 | } |
AnnaBridge | 171:3a7713b1edbc | 558 | |
AnnaBridge | 171:3a7713b1edbc | 559 | /** |
AnnaBridge | 171:3a7713b1edbc | 560 | * @brief Configure all parameters linked to DMA transfer. |
AnnaBridge | 171:3a7713b1edbc | 561 | * @rmtoll CR DIR LL_DMA_ConfigTransfer\n |
AnnaBridge | 171:3a7713b1edbc | 562 | * CR CIRC LL_DMA_ConfigTransfer\n |
AnnaBridge | 171:3a7713b1edbc | 563 | * CR PINC LL_DMA_ConfigTransfer\n |
AnnaBridge | 171:3a7713b1edbc | 564 | * CR MINC LL_DMA_ConfigTransfer\n |
AnnaBridge | 171:3a7713b1edbc | 565 | * CR PSIZE LL_DMA_ConfigTransfer\n |
AnnaBridge | 171:3a7713b1edbc | 566 | * CR MSIZE LL_DMA_ConfigTransfer\n |
AnnaBridge | 171:3a7713b1edbc | 567 | * CR PL LL_DMA_ConfigTransfer\n |
AnnaBridge | 171:3a7713b1edbc | 568 | * CR PFCTRL LL_DMA_ConfigTransfer |
AnnaBridge | 171:3a7713b1edbc | 569 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 570 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 571 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 572 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 573 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 574 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 575 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 576 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 577 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 578 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 579 | * @param Configuration This parameter must be a combination of all the following values: |
AnnaBridge | 171:3a7713b1edbc | 580 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
AnnaBridge | 171:3a7713b1edbc | 581 | * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL |
AnnaBridge | 171:3a7713b1edbc | 582 | * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT |
AnnaBridge | 171:3a7713b1edbc | 583 | * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT |
AnnaBridge | 171:3a7713b1edbc | 584 | * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD |
AnnaBridge | 171:3a7713b1edbc | 585 | * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD |
AnnaBridge | 171:3a7713b1edbc | 586 | * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH |
AnnaBridge | 171:3a7713b1edbc | 587 | *@retval None |
AnnaBridge | 171:3a7713b1edbc | 588 | */ |
AnnaBridge | 171:3a7713b1edbc | 589 | __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) |
AnnaBridge | 171:3a7713b1edbc | 590 | { |
AnnaBridge | 171:3a7713b1edbc | 591 | MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, |
AnnaBridge | 171:3a7713b1edbc | 592 | DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL, |
AnnaBridge | 171:3a7713b1edbc | 593 | Configuration); |
AnnaBridge | 171:3a7713b1edbc | 594 | } |
AnnaBridge | 171:3a7713b1edbc | 595 | |
AnnaBridge | 171:3a7713b1edbc | 596 | /** |
AnnaBridge | 171:3a7713b1edbc | 597 | * @brief Set Data transfer direction (read from peripheral or from memory). |
AnnaBridge | 171:3a7713b1edbc | 598 | * @rmtoll CR DIR LL_DMA_SetDataTransferDirection |
AnnaBridge | 171:3a7713b1edbc | 599 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 600 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 601 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 602 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 603 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 604 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 605 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 606 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 607 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 608 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 609 | * @param Direction This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 610 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY |
AnnaBridge | 171:3a7713b1edbc | 611 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH |
AnnaBridge | 171:3a7713b1edbc | 612 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
AnnaBridge | 171:3a7713b1edbc | 613 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 614 | */ |
AnnaBridge | 171:3a7713b1edbc | 615 | __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) |
AnnaBridge | 171:3a7713b1edbc | 616 | { |
AnnaBridge | 171:3a7713b1edbc | 617 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction); |
AnnaBridge | 171:3a7713b1edbc | 618 | } |
AnnaBridge | 171:3a7713b1edbc | 619 | |
AnnaBridge | 171:3a7713b1edbc | 620 | /** |
AnnaBridge | 171:3a7713b1edbc | 621 | * @brief Get Data transfer direction (read from peripheral or from memory). |
AnnaBridge | 171:3a7713b1edbc | 622 | * @rmtoll CR DIR LL_DMA_GetDataTransferDirection |
AnnaBridge | 171:3a7713b1edbc | 623 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 624 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 625 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 626 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 627 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 628 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 629 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 630 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 631 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 632 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 633 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 634 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY |
AnnaBridge | 171:3a7713b1edbc | 635 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH |
AnnaBridge | 171:3a7713b1edbc | 636 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
AnnaBridge | 171:3a7713b1edbc | 637 | */ |
AnnaBridge | 171:3a7713b1edbc | 638 | __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 639 | { |
AnnaBridge | 171:3a7713b1edbc | 640 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR)); |
AnnaBridge | 171:3a7713b1edbc | 641 | } |
AnnaBridge | 171:3a7713b1edbc | 642 | |
AnnaBridge | 171:3a7713b1edbc | 643 | /** |
AnnaBridge | 171:3a7713b1edbc | 644 | * @brief Set DMA mode normal, circular or peripheral flow control. |
AnnaBridge | 171:3a7713b1edbc | 645 | * @rmtoll CR CIRC LL_DMA_SetMode\n |
AnnaBridge | 171:3a7713b1edbc | 646 | * CR PFCTRL LL_DMA_SetMode |
AnnaBridge | 171:3a7713b1edbc | 647 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 648 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 649 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 650 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 651 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 652 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 653 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 654 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 655 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 656 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 657 | * @param Mode This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 658 | * @arg @ref LL_DMA_MODE_NORMAL |
AnnaBridge | 171:3a7713b1edbc | 659 | * @arg @ref LL_DMA_MODE_CIRCULAR |
AnnaBridge | 171:3a7713b1edbc | 660 | * @arg @ref LL_DMA_MODE_PFCTRL |
AnnaBridge | 171:3a7713b1edbc | 661 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 662 | */ |
AnnaBridge | 171:3a7713b1edbc | 663 | __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) |
AnnaBridge | 171:3a7713b1edbc | 664 | { |
AnnaBridge | 171:3a7713b1edbc | 665 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode); |
AnnaBridge | 171:3a7713b1edbc | 666 | } |
AnnaBridge | 171:3a7713b1edbc | 667 | |
AnnaBridge | 171:3a7713b1edbc | 668 | /** |
AnnaBridge | 171:3a7713b1edbc | 669 | * @brief Get DMA mode normal, circular or peripheral flow control. |
AnnaBridge | 171:3a7713b1edbc | 670 | * @rmtoll CR CIRC LL_DMA_GetMode\n |
AnnaBridge | 171:3a7713b1edbc | 671 | * CR PFCTRL LL_DMA_GetMode |
AnnaBridge | 171:3a7713b1edbc | 672 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 673 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 674 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 675 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 676 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 677 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 678 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 679 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 680 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 681 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 682 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 683 | * @arg @ref LL_DMA_MODE_NORMAL |
AnnaBridge | 171:3a7713b1edbc | 684 | * @arg @ref LL_DMA_MODE_CIRCULAR |
AnnaBridge | 171:3a7713b1edbc | 685 | * @arg @ref LL_DMA_MODE_PFCTRL |
AnnaBridge | 171:3a7713b1edbc | 686 | */ |
AnnaBridge | 171:3a7713b1edbc | 687 | __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 688 | { |
AnnaBridge | 171:3a7713b1edbc | 689 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL)); |
AnnaBridge | 171:3a7713b1edbc | 690 | } |
AnnaBridge | 171:3a7713b1edbc | 691 | |
AnnaBridge | 171:3a7713b1edbc | 692 | /** |
AnnaBridge | 171:3a7713b1edbc | 693 | * @brief Set Peripheral increment mode. |
AnnaBridge | 171:3a7713b1edbc | 694 | * @rmtoll CR PINC LL_DMA_SetPeriphIncMode |
AnnaBridge | 171:3a7713b1edbc | 695 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 696 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 697 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 698 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 699 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 700 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 701 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 702 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 703 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 704 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 705 | * @param IncrementMode This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 706 | * @arg @ref LL_DMA_PERIPH_NOINCREMENT |
AnnaBridge | 171:3a7713b1edbc | 707 | * @arg @ref LL_DMA_PERIPH_INCREMENT |
AnnaBridge | 171:3a7713b1edbc | 708 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 709 | */ |
AnnaBridge | 171:3a7713b1edbc | 710 | __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) |
AnnaBridge | 171:3a7713b1edbc | 711 | { |
AnnaBridge | 171:3a7713b1edbc | 712 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode); |
AnnaBridge | 171:3a7713b1edbc | 713 | } |
AnnaBridge | 171:3a7713b1edbc | 714 | |
AnnaBridge | 171:3a7713b1edbc | 715 | /** |
AnnaBridge | 171:3a7713b1edbc | 716 | * @brief Get Peripheral increment mode. |
AnnaBridge | 171:3a7713b1edbc | 717 | * @rmtoll CR PINC LL_DMA_GetPeriphIncMode |
AnnaBridge | 171:3a7713b1edbc | 718 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 719 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 720 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 721 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 722 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 723 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 724 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 725 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 726 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 727 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 728 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 729 | * @arg @ref LL_DMA_PERIPH_NOINCREMENT |
AnnaBridge | 171:3a7713b1edbc | 730 | * @arg @ref LL_DMA_PERIPH_INCREMENT |
AnnaBridge | 171:3a7713b1edbc | 731 | */ |
AnnaBridge | 171:3a7713b1edbc | 732 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 733 | { |
AnnaBridge | 171:3a7713b1edbc | 734 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC)); |
AnnaBridge | 171:3a7713b1edbc | 735 | } |
AnnaBridge | 171:3a7713b1edbc | 736 | |
AnnaBridge | 171:3a7713b1edbc | 737 | /** |
AnnaBridge | 171:3a7713b1edbc | 738 | * @brief Set Memory increment mode. |
AnnaBridge | 171:3a7713b1edbc | 739 | * @rmtoll CR MINC LL_DMA_SetMemoryIncMode |
AnnaBridge | 171:3a7713b1edbc | 740 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 741 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 742 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 743 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 744 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 745 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 746 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 747 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 748 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 749 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 750 | * @param IncrementMode This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 751 | * @arg @ref LL_DMA_MEMORY_NOINCREMENT |
AnnaBridge | 171:3a7713b1edbc | 752 | * @arg @ref LL_DMA_MEMORY_INCREMENT |
AnnaBridge | 171:3a7713b1edbc | 753 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 754 | */ |
AnnaBridge | 171:3a7713b1edbc | 755 | __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) |
AnnaBridge | 171:3a7713b1edbc | 756 | { |
AnnaBridge | 171:3a7713b1edbc | 757 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode); |
AnnaBridge | 171:3a7713b1edbc | 758 | } |
AnnaBridge | 171:3a7713b1edbc | 759 | |
AnnaBridge | 171:3a7713b1edbc | 760 | /** |
AnnaBridge | 171:3a7713b1edbc | 761 | * @brief Get Memory increment mode. |
AnnaBridge | 171:3a7713b1edbc | 762 | * @rmtoll CR MINC LL_DMA_GetMemoryIncMode |
AnnaBridge | 171:3a7713b1edbc | 763 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 764 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 765 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 766 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 767 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 768 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 769 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 770 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 771 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 772 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 773 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 774 | * @arg @ref LL_DMA_MEMORY_NOINCREMENT |
AnnaBridge | 171:3a7713b1edbc | 775 | * @arg @ref LL_DMA_MEMORY_INCREMENT |
AnnaBridge | 171:3a7713b1edbc | 776 | */ |
AnnaBridge | 171:3a7713b1edbc | 777 | __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 778 | { |
AnnaBridge | 171:3a7713b1edbc | 779 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC)); |
AnnaBridge | 171:3a7713b1edbc | 780 | } |
AnnaBridge | 171:3a7713b1edbc | 781 | |
AnnaBridge | 171:3a7713b1edbc | 782 | /** |
AnnaBridge | 171:3a7713b1edbc | 783 | * @brief Set Peripheral size. |
AnnaBridge | 171:3a7713b1edbc | 784 | * @rmtoll CR PSIZE LL_DMA_SetPeriphSize |
AnnaBridge | 171:3a7713b1edbc | 785 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 786 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 787 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 788 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 789 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 790 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 791 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 792 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 793 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 794 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 795 | * @param Size This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 796 | * @arg @ref LL_DMA_PDATAALIGN_BYTE |
AnnaBridge | 171:3a7713b1edbc | 797 | * @arg @ref LL_DMA_PDATAALIGN_HALFWORD |
AnnaBridge | 171:3a7713b1edbc | 798 | * @arg @ref LL_DMA_PDATAALIGN_WORD |
AnnaBridge | 171:3a7713b1edbc | 799 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 800 | */ |
AnnaBridge | 171:3a7713b1edbc | 801 | __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) |
AnnaBridge | 171:3a7713b1edbc | 802 | { |
AnnaBridge | 171:3a7713b1edbc | 803 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size); |
AnnaBridge | 171:3a7713b1edbc | 804 | } |
AnnaBridge | 171:3a7713b1edbc | 805 | |
AnnaBridge | 171:3a7713b1edbc | 806 | /** |
AnnaBridge | 171:3a7713b1edbc | 807 | * @brief Get Peripheral size. |
AnnaBridge | 171:3a7713b1edbc | 808 | * @rmtoll CR PSIZE LL_DMA_GetPeriphSize |
AnnaBridge | 171:3a7713b1edbc | 809 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 810 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 811 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 812 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 813 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 814 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 815 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 816 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 817 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 818 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 819 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 820 | * @arg @ref LL_DMA_PDATAALIGN_BYTE |
AnnaBridge | 171:3a7713b1edbc | 821 | * @arg @ref LL_DMA_PDATAALIGN_HALFWORD |
AnnaBridge | 171:3a7713b1edbc | 822 | * @arg @ref LL_DMA_PDATAALIGN_WORD |
AnnaBridge | 171:3a7713b1edbc | 823 | */ |
AnnaBridge | 171:3a7713b1edbc | 824 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 825 | { |
AnnaBridge | 171:3a7713b1edbc | 826 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE)); |
AnnaBridge | 171:3a7713b1edbc | 827 | } |
AnnaBridge | 171:3a7713b1edbc | 828 | |
AnnaBridge | 171:3a7713b1edbc | 829 | /** |
AnnaBridge | 171:3a7713b1edbc | 830 | * @brief Set Memory size. |
AnnaBridge | 171:3a7713b1edbc | 831 | * @rmtoll CR MSIZE LL_DMA_SetMemorySize |
AnnaBridge | 171:3a7713b1edbc | 832 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 833 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 834 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 835 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 836 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 837 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 838 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 839 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 840 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 841 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 842 | * @param Size This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 843 | * @arg @ref LL_DMA_MDATAALIGN_BYTE |
AnnaBridge | 171:3a7713b1edbc | 844 | * @arg @ref LL_DMA_MDATAALIGN_HALFWORD |
AnnaBridge | 171:3a7713b1edbc | 845 | * @arg @ref LL_DMA_MDATAALIGN_WORD |
AnnaBridge | 171:3a7713b1edbc | 846 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 847 | */ |
AnnaBridge | 171:3a7713b1edbc | 848 | __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) |
AnnaBridge | 171:3a7713b1edbc | 849 | { |
AnnaBridge | 171:3a7713b1edbc | 850 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size); |
AnnaBridge | 171:3a7713b1edbc | 851 | } |
AnnaBridge | 171:3a7713b1edbc | 852 | |
AnnaBridge | 171:3a7713b1edbc | 853 | /** |
AnnaBridge | 171:3a7713b1edbc | 854 | * @brief Get Memory size. |
AnnaBridge | 171:3a7713b1edbc | 855 | * @rmtoll CR MSIZE LL_DMA_GetMemorySize |
AnnaBridge | 171:3a7713b1edbc | 856 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 857 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 858 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 859 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 860 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 861 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 862 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 863 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 864 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 865 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 866 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 867 | * @arg @ref LL_DMA_MDATAALIGN_BYTE |
AnnaBridge | 171:3a7713b1edbc | 868 | * @arg @ref LL_DMA_MDATAALIGN_HALFWORD |
AnnaBridge | 171:3a7713b1edbc | 869 | * @arg @ref LL_DMA_MDATAALIGN_WORD |
AnnaBridge | 171:3a7713b1edbc | 870 | */ |
AnnaBridge | 171:3a7713b1edbc | 871 | __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 872 | { |
AnnaBridge | 171:3a7713b1edbc | 873 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE)); |
AnnaBridge | 171:3a7713b1edbc | 874 | } |
AnnaBridge | 171:3a7713b1edbc | 875 | |
AnnaBridge | 171:3a7713b1edbc | 876 | /** |
AnnaBridge | 171:3a7713b1edbc | 877 | * @brief Set Peripheral increment offset size. |
AnnaBridge | 171:3a7713b1edbc | 878 | * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize |
AnnaBridge | 171:3a7713b1edbc | 879 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 880 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 881 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 882 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 883 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 884 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 885 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 886 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 887 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 888 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 889 | * @param OffsetSize This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 890 | * @arg @ref LL_DMA_OFFSETSIZE_PSIZE |
AnnaBridge | 171:3a7713b1edbc | 891 | * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 |
AnnaBridge | 171:3a7713b1edbc | 892 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 893 | */ |
AnnaBridge | 171:3a7713b1edbc | 894 | __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) |
AnnaBridge | 171:3a7713b1edbc | 895 | { |
AnnaBridge | 171:3a7713b1edbc | 896 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize); |
AnnaBridge | 171:3a7713b1edbc | 897 | } |
AnnaBridge | 171:3a7713b1edbc | 898 | |
AnnaBridge | 171:3a7713b1edbc | 899 | /** |
AnnaBridge | 171:3a7713b1edbc | 900 | * @brief Get Peripheral increment offset size. |
AnnaBridge | 171:3a7713b1edbc | 901 | * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize |
AnnaBridge | 171:3a7713b1edbc | 902 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 903 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 904 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 905 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 906 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 907 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 908 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 909 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 910 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 911 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 912 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 913 | * @arg @ref LL_DMA_OFFSETSIZE_PSIZE |
AnnaBridge | 171:3a7713b1edbc | 914 | * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 |
AnnaBridge | 171:3a7713b1edbc | 915 | */ |
AnnaBridge | 171:3a7713b1edbc | 916 | __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 917 | { |
AnnaBridge | 171:3a7713b1edbc | 918 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS)); |
AnnaBridge | 171:3a7713b1edbc | 919 | } |
AnnaBridge | 171:3a7713b1edbc | 920 | |
AnnaBridge | 171:3a7713b1edbc | 921 | /** |
AnnaBridge | 171:3a7713b1edbc | 922 | * @brief Set Stream priority level. |
AnnaBridge | 171:3a7713b1edbc | 923 | * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel |
AnnaBridge | 171:3a7713b1edbc | 924 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 925 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 926 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 927 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 928 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 929 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 930 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 931 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 932 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 933 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 934 | * @param Priority This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 935 | * @arg @ref LL_DMA_PRIORITY_LOW |
AnnaBridge | 171:3a7713b1edbc | 936 | * @arg @ref LL_DMA_PRIORITY_MEDIUM |
AnnaBridge | 171:3a7713b1edbc | 937 | * @arg @ref LL_DMA_PRIORITY_HIGH |
AnnaBridge | 171:3a7713b1edbc | 938 | * @arg @ref LL_DMA_PRIORITY_VERYHIGH |
AnnaBridge | 171:3a7713b1edbc | 939 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 940 | */ |
AnnaBridge | 171:3a7713b1edbc | 941 | __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) |
AnnaBridge | 171:3a7713b1edbc | 942 | { |
AnnaBridge | 171:3a7713b1edbc | 943 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority); |
AnnaBridge | 171:3a7713b1edbc | 944 | } |
AnnaBridge | 171:3a7713b1edbc | 945 | |
AnnaBridge | 171:3a7713b1edbc | 946 | /** |
AnnaBridge | 171:3a7713b1edbc | 947 | * @brief Get Stream priority level. |
AnnaBridge | 171:3a7713b1edbc | 948 | * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel |
AnnaBridge | 171:3a7713b1edbc | 949 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 950 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 951 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 952 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 953 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 954 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 955 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 956 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 957 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 958 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 959 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 960 | * @arg @ref LL_DMA_PRIORITY_LOW |
AnnaBridge | 171:3a7713b1edbc | 961 | * @arg @ref LL_DMA_PRIORITY_MEDIUM |
AnnaBridge | 171:3a7713b1edbc | 962 | * @arg @ref LL_DMA_PRIORITY_HIGH |
AnnaBridge | 171:3a7713b1edbc | 963 | * @arg @ref LL_DMA_PRIORITY_VERYHIGH |
AnnaBridge | 171:3a7713b1edbc | 964 | */ |
AnnaBridge | 171:3a7713b1edbc | 965 | __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 966 | { |
AnnaBridge | 171:3a7713b1edbc | 967 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL)); |
AnnaBridge | 171:3a7713b1edbc | 968 | } |
AnnaBridge | 171:3a7713b1edbc | 969 | |
AnnaBridge | 171:3a7713b1edbc | 970 | /** |
AnnaBridge | 171:3a7713b1edbc | 971 | * @brief Set Number of data to transfer. |
AnnaBridge | 171:3a7713b1edbc | 972 | * @rmtoll NDTR NDT LL_DMA_SetDataLength |
AnnaBridge | 171:3a7713b1edbc | 973 | * @note This action has no effect if |
AnnaBridge | 171:3a7713b1edbc | 974 | * stream is enabled. |
AnnaBridge | 171:3a7713b1edbc | 975 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 976 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 977 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 978 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 979 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 980 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 981 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 982 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 983 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 984 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 985 | * @param NbData Between 0 to 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 986 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 987 | */ |
AnnaBridge | 171:3a7713b1edbc | 988 | __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) |
AnnaBridge | 171:3a7713b1edbc | 989 | { |
AnnaBridge | 171:3a7713b1edbc | 990 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData); |
AnnaBridge | 171:3a7713b1edbc | 991 | } |
AnnaBridge | 171:3a7713b1edbc | 992 | |
AnnaBridge | 171:3a7713b1edbc | 993 | /** |
AnnaBridge | 171:3a7713b1edbc | 994 | * @brief Get Number of data to transfer. |
AnnaBridge | 171:3a7713b1edbc | 995 | * @rmtoll NDTR NDT LL_DMA_GetDataLength |
AnnaBridge | 171:3a7713b1edbc | 996 | * @note Once the stream is enabled, the return value indicate the |
AnnaBridge | 171:3a7713b1edbc | 997 | * remaining bytes to be transmitted. |
AnnaBridge | 171:3a7713b1edbc | 998 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 999 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1000 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1001 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1002 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1003 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1004 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1005 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1006 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1007 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1008 | * @retval Between 0 to 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1009 | */ |
AnnaBridge | 171:3a7713b1edbc | 1010 | __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 1011 | { |
AnnaBridge | 171:3a7713b1edbc | 1012 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT)); |
AnnaBridge | 171:3a7713b1edbc | 1013 | } |
AnnaBridge | 171:3a7713b1edbc | 1014 | |
AnnaBridge | 171:3a7713b1edbc | 1015 | /** |
AnnaBridge | 171:3a7713b1edbc | 1016 | * @brief Select Channel number associated to the Stream. |
AnnaBridge | 171:3a7713b1edbc | 1017 | * @rmtoll CR CHSEL LL_DMA_SetChannelSelection |
AnnaBridge | 171:3a7713b1edbc | 1018 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1019 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1020 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1021 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1022 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1023 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1024 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1025 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1026 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1027 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1028 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1029 | * @arg @ref LL_DMA_CHANNEL_0 |
AnnaBridge | 171:3a7713b1edbc | 1030 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1031 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 1032 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 1033 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 1034 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 1035 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 1036 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 1037 | * @arg @ref LL_DMA_CHANNEL_8 (*) |
AnnaBridge | 171:3a7713b1edbc | 1038 | * @arg @ref LL_DMA_CHANNEL_9 (*) |
AnnaBridge | 171:3a7713b1edbc | 1039 | * @arg @ref LL_DMA_CHANNEL_10 (*) |
AnnaBridge | 171:3a7713b1edbc | 1040 | * @arg @ref LL_DMA_CHANNEL_11 (*) |
AnnaBridge | 171:3a7713b1edbc | 1041 | * @arg @ref LL_DMA_CHANNEL_12 (*) |
AnnaBridge | 171:3a7713b1edbc | 1042 | * @arg @ref LL_DMA_CHANNEL_13 (*) |
AnnaBridge | 171:3a7713b1edbc | 1043 | * @arg @ref LL_DMA_CHANNEL_14 (*) |
AnnaBridge | 171:3a7713b1edbc | 1044 | * @arg @ref LL_DMA_CHANNEL_15 (*) |
AnnaBridge | 171:3a7713b1edbc | 1045 | * |
AnnaBridge | 171:3a7713b1edbc | 1046 | * (*) value not defined in all devices. |
AnnaBridge | 171:3a7713b1edbc | 1047 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1048 | */ |
AnnaBridge | 171:3a7713b1edbc | 1049 | __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 1050 | { |
AnnaBridge | 171:3a7713b1edbc | 1051 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel); |
AnnaBridge | 171:3a7713b1edbc | 1052 | } |
AnnaBridge | 171:3a7713b1edbc | 1053 | |
AnnaBridge | 171:3a7713b1edbc | 1054 | /** |
AnnaBridge | 171:3a7713b1edbc | 1055 | * @brief Get the Channel number associated to the Stream. |
AnnaBridge | 171:3a7713b1edbc | 1056 | * @rmtoll CR CHSEL LL_DMA_GetChannelSelection |
AnnaBridge | 171:3a7713b1edbc | 1057 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1058 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1059 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1060 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1061 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1062 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1063 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1064 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1065 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1066 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1067 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1068 | * @arg @ref LL_DMA_CHANNEL_0 |
AnnaBridge | 171:3a7713b1edbc | 1069 | * @arg @ref LL_DMA_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1070 | * @arg @ref LL_DMA_CHANNEL_2 |
AnnaBridge | 171:3a7713b1edbc | 1071 | * @arg @ref LL_DMA_CHANNEL_3 |
AnnaBridge | 171:3a7713b1edbc | 1072 | * @arg @ref LL_DMA_CHANNEL_4 |
AnnaBridge | 171:3a7713b1edbc | 1073 | * @arg @ref LL_DMA_CHANNEL_5 |
AnnaBridge | 171:3a7713b1edbc | 1074 | * @arg @ref LL_DMA_CHANNEL_6 |
AnnaBridge | 171:3a7713b1edbc | 1075 | * @arg @ref LL_DMA_CHANNEL_7 |
AnnaBridge | 171:3a7713b1edbc | 1076 | * @arg @ref LL_DMA_CHANNEL_8 (*) |
AnnaBridge | 171:3a7713b1edbc | 1077 | * @arg @ref LL_DMA_CHANNEL_9 (*) |
AnnaBridge | 171:3a7713b1edbc | 1078 | * @arg @ref LL_DMA_CHANNEL_10 (*) |
AnnaBridge | 171:3a7713b1edbc | 1079 | * @arg @ref LL_DMA_CHANNEL_11 (*) |
AnnaBridge | 171:3a7713b1edbc | 1080 | * @arg @ref LL_DMA_CHANNEL_12 (*) |
AnnaBridge | 171:3a7713b1edbc | 1081 | * @arg @ref LL_DMA_CHANNEL_13 (*) |
AnnaBridge | 171:3a7713b1edbc | 1082 | * @arg @ref LL_DMA_CHANNEL_14 (*) |
AnnaBridge | 171:3a7713b1edbc | 1083 | * @arg @ref LL_DMA_CHANNEL_15 (*) |
AnnaBridge | 171:3a7713b1edbc | 1084 | * |
AnnaBridge | 171:3a7713b1edbc | 1085 | * (*) value not defined in all devices. |
AnnaBridge | 171:3a7713b1edbc | 1086 | */ |
AnnaBridge | 171:3a7713b1edbc | 1087 | __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 1088 | { |
AnnaBridge | 171:3a7713b1edbc | 1089 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL)); |
AnnaBridge | 171:3a7713b1edbc | 1090 | } |
AnnaBridge | 171:3a7713b1edbc | 1091 | |
AnnaBridge | 171:3a7713b1edbc | 1092 | /** |
AnnaBridge | 171:3a7713b1edbc | 1093 | * @brief Set Memory burst transfer configuration. |
AnnaBridge | 171:3a7713b1edbc | 1094 | * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer |
AnnaBridge | 171:3a7713b1edbc | 1095 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1096 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1097 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1098 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1099 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1100 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1101 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1102 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1103 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1104 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1105 | * @param Mburst This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1106 | * @arg @ref LL_DMA_MBURST_SINGLE |
AnnaBridge | 171:3a7713b1edbc | 1107 | * @arg @ref LL_DMA_MBURST_INC4 |
AnnaBridge | 171:3a7713b1edbc | 1108 | * @arg @ref LL_DMA_MBURST_INC8 |
AnnaBridge | 171:3a7713b1edbc | 1109 | * @arg @ref LL_DMA_MBURST_INC16 |
AnnaBridge | 171:3a7713b1edbc | 1110 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1111 | */ |
AnnaBridge | 171:3a7713b1edbc | 1112 | __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) |
AnnaBridge | 171:3a7713b1edbc | 1113 | { |
AnnaBridge | 171:3a7713b1edbc | 1114 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst); |
AnnaBridge | 171:3a7713b1edbc | 1115 | } |
AnnaBridge | 171:3a7713b1edbc | 1116 | |
AnnaBridge | 171:3a7713b1edbc | 1117 | /** |
AnnaBridge | 171:3a7713b1edbc | 1118 | * @brief Get Memory burst transfer configuration. |
AnnaBridge | 171:3a7713b1edbc | 1119 | * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer |
AnnaBridge | 171:3a7713b1edbc | 1120 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1121 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1122 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1123 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1124 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1125 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1126 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1127 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1128 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1129 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1130 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1131 | * @arg @ref LL_DMA_MBURST_SINGLE |
AnnaBridge | 171:3a7713b1edbc | 1132 | * @arg @ref LL_DMA_MBURST_INC4 |
AnnaBridge | 171:3a7713b1edbc | 1133 | * @arg @ref LL_DMA_MBURST_INC8 |
AnnaBridge | 171:3a7713b1edbc | 1134 | * @arg @ref LL_DMA_MBURST_INC16 |
AnnaBridge | 171:3a7713b1edbc | 1135 | */ |
AnnaBridge | 171:3a7713b1edbc | 1136 | __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 1137 | { |
AnnaBridge | 171:3a7713b1edbc | 1138 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST)); |
AnnaBridge | 171:3a7713b1edbc | 1139 | } |
AnnaBridge | 171:3a7713b1edbc | 1140 | |
AnnaBridge | 171:3a7713b1edbc | 1141 | /** |
AnnaBridge | 171:3a7713b1edbc | 1142 | * @brief Set Peripheral burst transfer configuration. |
AnnaBridge | 171:3a7713b1edbc | 1143 | * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer |
AnnaBridge | 171:3a7713b1edbc | 1144 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1145 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1146 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1147 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1148 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1149 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1150 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1151 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1152 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1153 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1154 | * @param Pburst This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1155 | * @arg @ref LL_DMA_PBURST_SINGLE |
AnnaBridge | 171:3a7713b1edbc | 1156 | * @arg @ref LL_DMA_PBURST_INC4 |
AnnaBridge | 171:3a7713b1edbc | 1157 | * @arg @ref LL_DMA_PBURST_INC8 |
AnnaBridge | 171:3a7713b1edbc | 1158 | * @arg @ref LL_DMA_PBURST_INC16 |
AnnaBridge | 171:3a7713b1edbc | 1159 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1160 | */ |
AnnaBridge | 171:3a7713b1edbc | 1161 | __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) |
AnnaBridge | 171:3a7713b1edbc | 1162 | { |
AnnaBridge | 171:3a7713b1edbc | 1163 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst); |
AnnaBridge | 171:3a7713b1edbc | 1164 | } |
AnnaBridge | 171:3a7713b1edbc | 1165 | |
AnnaBridge | 171:3a7713b1edbc | 1166 | /** |
AnnaBridge | 171:3a7713b1edbc | 1167 | * @brief Get Peripheral burst transfer configuration. |
AnnaBridge | 171:3a7713b1edbc | 1168 | * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer |
AnnaBridge | 171:3a7713b1edbc | 1169 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1170 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1171 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1172 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1173 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1174 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1175 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1176 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1177 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1178 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1179 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1180 | * @arg @ref LL_DMA_PBURST_SINGLE |
AnnaBridge | 171:3a7713b1edbc | 1181 | * @arg @ref LL_DMA_PBURST_INC4 |
AnnaBridge | 171:3a7713b1edbc | 1182 | * @arg @ref LL_DMA_PBURST_INC8 |
AnnaBridge | 171:3a7713b1edbc | 1183 | * @arg @ref LL_DMA_PBURST_INC16 |
AnnaBridge | 171:3a7713b1edbc | 1184 | */ |
AnnaBridge | 171:3a7713b1edbc | 1185 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 1186 | { |
AnnaBridge | 171:3a7713b1edbc | 1187 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST)); |
AnnaBridge | 171:3a7713b1edbc | 1188 | } |
AnnaBridge | 171:3a7713b1edbc | 1189 | |
AnnaBridge | 171:3a7713b1edbc | 1190 | /** |
AnnaBridge | 171:3a7713b1edbc | 1191 | * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. |
AnnaBridge | 171:3a7713b1edbc | 1192 | * @rmtoll CR CT LL_DMA_SetCurrentTargetMem |
AnnaBridge | 171:3a7713b1edbc | 1193 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1194 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1195 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1196 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1197 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1198 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1199 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1200 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1201 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1202 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1203 | * @param CurrentMemory This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1204 | * @arg @ref LL_DMA_CURRENTTARGETMEM0 |
AnnaBridge | 171:3a7713b1edbc | 1205 | * @arg @ref LL_DMA_CURRENTTARGETMEM1 |
AnnaBridge | 171:3a7713b1edbc | 1206 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1207 | */ |
AnnaBridge | 171:3a7713b1edbc | 1208 | __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) |
AnnaBridge | 171:3a7713b1edbc | 1209 | { |
AnnaBridge | 171:3a7713b1edbc | 1210 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory); |
AnnaBridge | 171:3a7713b1edbc | 1211 | } |
AnnaBridge | 171:3a7713b1edbc | 1212 | |
AnnaBridge | 171:3a7713b1edbc | 1213 | /** |
AnnaBridge | 171:3a7713b1edbc | 1214 | * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. |
AnnaBridge | 171:3a7713b1edbc | 1215 | * @rmtoll CR CT LL_DMA_GetCurrentTargetMem |
AnnaBridge | 171:3a7713b1edbc | 1216 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1217 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1218 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1219 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1220 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1221 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1222 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1223 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1224 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1225 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1226 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1227 | * @arg @ref LL_DMA_CURRENTTARGETMEM0 |
AnnaBridge | 171:3a7713b1edbc | 1228 | * @arg @ref LL_DMA_CURRENTTARGETMEM1 |
AnnaBridge | 171:3a7713b1edbc | 1229 | */ |
AnnaBridge | 171:3a7713b1edbc | 1230 | __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 1231 | { |
AnnaBridge | 171:3a7713b1edbc | 1232 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT)); |
AnnaBridge | 171:3a7713b1edbc | 1233 | } |
AnnaBridge | 171:3a7713b1edbc | 1234 | |
AnnaBridge | 171:3a7713b1edbc | 1235 | /** |
AnnaBridge | 171:3a7713b1edbc | 1236 | * @brief Enable the double buffer mode. |
AnnaBridge | 171:3a7713b1edbc | 1237 | * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode |
AnnaBridge | 171:3a7713b1edbc | 1238 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1239 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1240 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1241 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1242 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1243 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1244 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1245 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1246 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1247 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1248 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1249 | */ |
AnnaBridge | 171:3a7713b1edbc | 1250 | __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 1251 | { |
AnnaBridge | 171:3a7713b1edbc | 1252 | SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); |
AnnaBridge | 171:3a7713b1edbc | 1253 | } |
AnnaBridge | 171:3a7713b1edbc | 1254 | |
AnnaBridge | 171:3a7713b1edbc | 1255 | /** |
AnnaBridge | 171:3a7713b1edbc | 1256 | * @brief Disable the double buffer mode. |
AnnaBridge | 171:3a7713b1edbc | 1257 | * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode |
AnnaBridge | 171:3a7713b1edbc | 1258 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1259 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1260 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1261 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1262 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1263 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1264 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1265 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1266 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1267 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1268 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1269 | */ |
AnnaBridge | 171:3a7713b1edbc | 1270 | __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 1271 | { |
AnnaBridge | 171:3a7713b1edbc | 1272 | CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); |
AnnaBridge | 171:3a7713b1edbc | 1273 | } |
AnnaBridge | 171:3a7713b1edbc | 1274 | |
AnnaBridge | 171:3a7713b1edbc | 1275 | /** |
AnnaBridge | 171:3a7713b1edbc | 1276 | * @brief Get FIFO status. |
AnnaBridge | 171:3a7713b1edbc | 1277 | * @rmtoll FCR FS LL_DMA_GetFIFOStatus |
AnnaBridge | 171:3a7713b1edbc | 1278 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1279 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1280 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1281 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1282 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1283 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1284 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1285 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1286 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1287 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1288 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1289 | * @arg @ref LL_DMA_FIFOSTATUS_0_25 |
AnnaBridge | 171:3a7713b1edbc | 1290 | * @arg @ref LL_DMA_FIFOSTATUS_25_50 |
AnnaBridge | 171:3a7713b1edbc | 1291 | * @arg @ref LL_DMA_FIFOSTATUS_50_75 |
AnnaBridge | 171:3a7713b1edbc | 1292 | * @arg @ref LL_DMA_FIFOSTATUS_75_100 |
AnnaBridge | 171:3a7713b1edbc | 1293 | * @arg @ref LL_DMA_FIFOSTATUS_EMPTY |
AnnaBridge | 171:3a7713b1edbc | 1294 | * @arg @ref LL_DMA_FIFOSTATUS_FULL |
AnnaBridge | 171:3a7713b1edbc | 1295 | */ |
AnnaBridge | 171:3a7713b1edbc | 1296 | __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 1297 | { |
AnnaBridge | 171:3a7713b1edbc | 1298 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS)); |
AnnaBridge | 171:3a7713b1edbc | 1299 | } |
AnnaBridge | 171:3a7713b1edbc | 1300 | |
AnnaBridge | 171:3a7713b1edbc | 1301 | /** |
AnnaBridge | 171:3a7713b1edbc | 1302 | * @brief Disable Fifo mode. |
AnnaBridge | 171:3a7713b1edbc | 1303 | * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode |
AnnaBridge | 171:3a7713b1edbc | 1304 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1305 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1306 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1307 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1308 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1309 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1310 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1311 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1312 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1313 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1314 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1315 | */ |
AnnaBridge | 171:3a7713b1edbc | 1316 | __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 1317 | { |
AnnaBridge | 171:3a7713b1edbc | 1318 | CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); |
AnnaBridge | 171:3a7713b1edbc | 1319 | } |
AnnaBridge | 171:3a7713b1edbc | 1320 | |
AnnaBridge | 171:3a7713b1edbc | 1321 | /** |
AnnaBridge | 171:3a7713b1edbc | 1322 | * @brief Enable Fifo mode. |
AnnaBridge | 171:3a7713b1edbc | 1323 | * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode |
AnnaBridge | 171:3a7713b1edbc | 1324 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1325 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1326 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1327 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1328 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1329 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1330 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1331 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1332 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1333 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1334 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1335 | */ |
AnnaBridge | 171:3a7713b1edbc | 1336 | __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 1337 | { |
AnnaBridge | 171:3a7713b1edbc | 1338 | SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); |
AnnaBridge | 171:3a7713b1edbc | 1339 | } |
AnnaBridge | 171:3a7713b1edbc | 1340 | |
AnnaBridge | 171:3a7713b1edbc | 1341 | /** |
AnnaBridge | 171:3a7713b1edbc | 1342 | * @brief Select FIFO threshold. |
AnnaBridge | 171:3a7713b1edbc | 1343 | * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold |
AnnaBridge | 171:3a7713b1edbc | 1344 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1345 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1346 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1347 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1348 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1349 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1350 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1351 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1352 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1353 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1354 | * @param Threshold This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1355 | * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 |
AnnaBridge | 171:3a7713b1edbc | 1356 | * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 |
AnnaBridge | 171:3a7713b1edbc | 1357 | * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 |
AnnaBridge | 171:3a7713b1edbc | 1358 | * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL |
AnnaBridge | 171:3a7713b1edbc | 1359 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1360 | */ |
AnnaBridge | 171:3a7713b1edbc | 1361 | __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) |
AnnaBridge | 171:3a7713b1edbc | 1362 | { |
AnnaBridge | 171:3a7713b1edbc | 1363 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold); |
AnnaBridge | 171:3a7713b1edbc | 1364 | } |
AnnaBridge | 171:3a7713b1edbc | 1365 | |
AnnaBridge | 171:3a7713b1edbc | 1366 | /** |
AnnaBridge | 171:3a7713b1edbc | 1367 | * @brief Get FIFO threshold. |
AnnaBridge | 171:3a7713b1edbc | 1368 | * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold |
AnnaBridge | 171:3a7713b1edbc | 1369 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1370 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1371 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1372 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1373 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1374 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1375 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1376 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1377 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1378 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1379 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1380 | * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 |
AnnaBridge | 171:3a7713b1edbc | 1381 | * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 |
AnnaBridge | 171:3a7713b1edbc | 1382 | * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 |
AnnaBridge | 171:3a7713b1edbc | 1383 | * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL |
AnnaBridge | 171:3a7713b1edbc | 1384 | */ |
AnnaBridge | 171:3a7713b1edbc | 1385 | __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 1386 | { |
AnnaBridge | 171:3a7713b1edbc | 1387 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH)); |
AnnaBridge | 171:3a7713b1edbc | 1388 | } |
AnnaBridge | 171:3a7713b1edbc | 1389 | |
AnnaBridge | 171:3a7713b1edbc | 1390 | /** |
AnnaBridge | 171:3a7713b1edbc | 1391 | * @brief Configure the FIFO . |
AnnaBridge | 171:3a7713b1edbc | 1392 | * @rmtoll FCR FTH LL_DMA_ConfigFifo\n |
AnnaBridge | 171:3a7713b1edbc | 1393 | * FCR DMDIS LL_DMA_ConfigFifo |
AnnaBridge | 171:3a7713b1edbc | 1394 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1395 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1396 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1397 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1398 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1399 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1400 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1401 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1402 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1403 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1404 | * @param FifoMode This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1405 | * @arg @ref LL_DMA_FIFOMODE_ENABLE |
AnnaBridge | 171:3a7713b1edbc | 1406 | * @arg @ref LL_DMA_FIFOMODE_DISABLE |
AnnaBridge | 171:3a7713b1edbc | 1407 | * @param FifoThreshold This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1408 | * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 |
AnnaBridge | 171:3a7713b1edbc | 1409 | * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 |
AnnaBridge | 171:3a7713b1edbc | 1410 | * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 |
AnnaBridge | 171:3a7713b1edbc | 1411 | * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL |
AnnaBridge | 171:3a7713b1edbc | 1412 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1413 | */ |
AnnaBridge | 171:3a7713b1edbc | 1414 | __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) |
AnnaBridge | 171:3a7713b1edbc | 1415 | { |
AnnaBridge | 171:3a7713b1edbc | 1416 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold); |
AnnaBridge | 171:3a7713b1edbc | 1417 | } |
AnnaBridge | 171:3a7713b1edbc | 1418 | |
AnnaBridge | 171:3a7713b1edbc | 1419 | /** |
AnnaBridge | 171:3a7713b1edbc | 1420 | * @brief Configure the Source and Destination addresses. |
AnnaBridge | 171:3a7713b1edbc | 1421 | * @note This API must not be called when the DMA stream is enabled. |
AnnaBridge | 171:3a7713b1edbc | 1422 | * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n |
AnnaBridge | 171:3a7713b1edbc | 1423 | * PAR PA LL_DMA_ConfigAddresses |
AnnaBridge | 171:3a7713b1edbc | 1424 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1425 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1426 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1427 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1428 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1429 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1430 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1431 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1432 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1433 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1434 | * @param SrcAddress Between 0 to 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1435 | * @param DstAddress Between 0 to 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1436 | * @param Direction This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1437 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY |
AnnaBridge | 171:3a7713b1edbc | 1438 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH |
AnnaBridge | 171:3a7713b1edbc | 1439 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
AnnaBridge | 171:3a7713b1edbc | 1440 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1441 | */ |
AnnaBridge | 171:3a7713b1edbc | 1442 | __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) |
AnnaBridge | 171:3a7713b1edbc | 1443 | { |
AnnaBridge | 171:3a7713b1edbc | 1444 | /* Direction Memory to Periph */ |
AnnaBridge | 171:3a7713b1edbc | 1445 | if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) |
AnnaBridge | 171:3a7713b1edbc | 1446 | { |
AnnaBridge | 171:3a7713b1edbc | 1447 | WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress); |
AnnaBridge | 171:3a7713b1edbc | 1448 | WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress); |
AnnaBridge | 171:3a7713b1edbc | 1449 | } |
AnnaBridge | 171:3a7713b1edbc | 1450 | /* Direction Periph to Memory and Memory to Memory */ |
AnnaBridge | 171:3a7713b1edbc | 1451 | else |
AnnaBridge | 171:3a7713b1edbc | 1452 | { |
AnnaBridge | 171:3a7713b1edbc | 1453 | WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress); |
AnnaBridge | 171:3a7713b1edbc | 1454 | WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress); |
AnnaBridge | 171:3a7713b1edbc | 1455 | } |
AnnaBridge | 171:3a7713b1edbc | 1456 | } |
AnnaBridge | 171:3a7713b1edbc | 1457 | |
AnnaBridge | 171:3a7713b1edbc | 1458 | /** |
AnnaBridge | 171:3a7713b1edbc | 1459 | * @brief Set the Memory address. |
AnnaBridge | 171:3a7713b1edbc | 1460 | * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress |
AnnaBridge | 171:3a7713b1edbc | 1461 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
AnnaBridge | 171:3a7713b1edbc | 1462 | * @note This API must not be called when the DMA channel is enabled. |
AnnaBridge | 171:3a7713b1edbc | 1463 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1464 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1465 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1466 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1467 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1468 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1469 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1470 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1471 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1472 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1473 | * @param MemoryAddress Between 0 to 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1474 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1475 | */ |
AnnaBridge | 171:3a7713b1edbc | 1476 | __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) |
AnnaBridge | 171:3a7713b1edbc | 1477 | { |
AnnaBridge | 171:3a7713b1edbc | 1478 | WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); |
AnnaBridge | 171:3a7713b1edbc | 1479 | } |
AnnaBridge | 171:3a7713b1edbc | 1480 | |
AnnaBridge | 171:3a7713b1edbc | 1481 | /** |
AnnaBridge | 171:3a7713b1edbc | 1482 | * @brief Set the Peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 1483 | * @rmtoll PAR PA LL_DMA_SetPeriphAddress |
AnnaBridge | 171:3a7713b1edbc | 1484 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
AnnaBridge | 171:3a7713b1edbc | 1485 | * @note This API must not be called when the DMA channel is enabled. |
AnnaBridge | 171:3a7713b1edbc | 1486 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1487 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1488 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1489 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1490 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1491 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1492 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1493 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1494 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1495 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1496 | * @param PeriphAddress Between 0 to 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1497 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1498 | */ |
AnnaBridge | 171:3a7713b1edbc | 1499 | __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress) |
AnnaBridge | 171:3a7713b1edbc | 1500 | { |
AnnaBridge | 171:3a7713b1edbc | 1501 | WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress); |
AnnaBridge | 171:3a7713b1edbc | 1502 | } |
AnnaBridge | 171:3a7713b1edbc | 1503 | |
AnnaBridge | 171:3a7713b1edbc | 1504 | /** |
AnnaBridge | 171:3a7713b1edbc | 1505 | * @brief Get the Memory address. |
AnnaBridge | 171:3a7713b1edbc | 1506 | * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress |
AnnaBridge | 171:3a7713b1edbc | 1507 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
AnnaBridge | 171:3a7713b1edbc | 1508 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1509 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1510 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1511 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1512 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1513 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1514 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1515 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1516 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1517 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1518 | * @retval Between 0 to 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1519 | */ |
AnnaBridge | 171:3a7713b1edbc | 1520 | __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 1521 | { |
AnnaBridge | 171:3a7713b1edbc | 1522 | return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); |
AnnaBridge | 171:3a7713b1edbc | 1523 | } |
AnnaBridge | 171:3a7713b1edbc | 1524 | |
AnnaBridge | 171:3a7713b1edbc | 1525 | /** |
AnnaBridge | 171:3a7713b1edbc | 1526 | * @brief Get the Peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 1527 | * @rmtoll PAR PA LL_DMA_GetPeriphAddress |
AnnaBridge | 171:3a7713b1edbc | 1528 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
AnnaBridge | 171:3a7713b1edbc | 1529 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1530 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1531 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1532 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1533 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1534 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1535 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1536 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1537 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1538 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1539 | * @retval Between 0 to 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1540 | */ |
AnnaBridge | 171:3a7713b1edbc | 1541 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 1542 | { |
AnnaBridge | 171:3a7713b1edbc | 1543 | return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); |
AnnaBridge | 171:3a7713b1edbc | 1544 | } |
AnnaBridge | 171:3a7713b1edbc | 1545 | |
AnnaBridge | 171:3a7713b1edbc | 1546 | /** |
AnnaBridge | 171:3a7713b1edbc | 1547 | * @brief Set the Memory to Memory Source address. |
AnnaBridge | 171:3a7713b1edbc | 1548 | * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress |
AnnaBridge | 171:3a7713b1edbc | 1549 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
AnnaBridge | 171:3a7713b1edbc | 1550 | * @note This API must not be called when the DMA channel is enabled. |
AnnaBridge | 171:3a7713b1edbc | 1551 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1552 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1553 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1554 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1555 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1556 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1557 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1558 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1559 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1560 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1561 | * @param MemoryAddress Between 0 to 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1562 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1563 | */ |
AnnaBridge | 171:3a7713b1edbc | 1564 | __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) |
AnnaBridge | 171:3a7713b1edbc | 1565 | { |
AnnaBridge | 171:3a7713b1edbc | 1566 | WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress); |
AnnaBridge | 171:3a7713b1edbc | 1567 | } |
AnnaBridge | 171:3a7713b1edbc | 1568 | |
AnnaBridge | 171:3a7713b1edbc | 1569 | /** |
AnnaBridge | 171:3a7713b1edbc | 1570 | * @brief Set the Memory to Memory Destination address. |
AnnaBridge | 171:3a7713b1edbc | 1571 | * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress |
AnnaBridge | 171:3a7713b1edbc | 1572 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
AnnaBridge | 171:3a7713b1edbc | 1573 | * @note This API must not be called when the DMA channel is enabled. |
AnnaBridge | 171:3a7713b1edbc | 1574 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1575 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1576 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1577 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1578 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1579 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1580 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1581 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1582 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1583 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1584 | * @param MemoryAddress Between 0 to 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1585 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1586 | */ |
AnnaBridge | 171:3a7713b1edbc | 1587 | __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) |
AnnaBridge | 171:3a7713b1edbc | 1588 | { |
AnnaBridge | 171:3a7713b1edbc | 1589 | WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); |
AnnaBridge | 171:3a7713b1edbc | 1590 | } |
AnnaBridge | 171:3a7713b1edbc | 1591 | |
AnnaBridge | 171:3a7713b1edbc | 1592 | /** |
AnnaBridge | 171:3a7713b1edbc | 1593 | * @brief Get the Memory to Memory Source address. |
AnnaBridge | 171:3a7713b1edbc | 1594 | * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress |
AnnaBridge | 171:3a7713b1edbc | 1595 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
AnnaBridge | 171:3a7713b1edbc | 1596 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1597 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1598 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1599 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1600 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1601 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1602 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1603 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1604 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1605 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1606 | * @retval Between 0 to 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1607 | */ |
AnnaBridge | 171:3a7713b1edbc | 1608 | __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 1609 | { |
AnnaBridge | 171:3a7713b1edbc | 1610 | return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); |
AnnaBridge | 171:3a7713b1edbc | 1611 | } |
AnnaBridge | 171:3a7713b1edbc | 1612 | |
AnnaBridge | 171:3a7713b1edbc | 1613 | /** |
AnnaBridge | 171:3a7713b1edbc | 1614 | * @brief Get the Memory to Memory Destination address. |
AnnaBridge | 171:3a7713b1edbc | 1615 | * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress |
AnnaBridge | 171:3a7713b1edbc | 1616 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
AnnaBridge | 171:3a7713b1edbc | 1617 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1618 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1619 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1620 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1621 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1622 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1623 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1624 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1625 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1626 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1627 | * @retval Between 0 to 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1628 | */ |
AnnaBridge | 171:3a7713b1edbc | 1629 | __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 1630 | { |
AnnaBridge | 171:3a7713b1edbc | 1631 | return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); |
AnnaBridge | 171:3a7713b1edbc | 1632 | } |
AnnaBridge | 171:3a7713b1edbc | 1633 | |
AnnaBridge | 171:3a7713b1edbc | 1634 | /** |
AnnaBridge | 171:3a7713b1edbc | 1635 | * @brief Set Memory 1 address (used in case of Double buffer mode). |
AnnaBridge | 171:3a7713b1edbc | 1636 | * @rmtoll M1AR M1A LL_DMA_SetMemory1Address |
AnnaBridge | 171:3a7713b1edbc | 1637 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1638 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1639 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1640 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1641 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1642 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1643 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1644 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1645 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1646 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1647 | * @param Address Between 0 to 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1648 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1649 | */ |
AnnaBridge | 171:3a7713b1edbc | 1650 | __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) |
AnnaBridge | 171:3a7713b1edbc | 1651 | { |
AnnaBridge | 171:3a7713b1edbc | 1652 | MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address); |
AnnaBridge | 171:3a7713b1edbc | 1653 | } |
AnnaBridge | 171:3a7713b1edbc | 1654 | |
AnnaBridge | 171:3a7713b1edbc | 1655 | /** |
AnnaBridge | 171:3a7713b1edbc | 1656 | * @brief Get Memory 1 address (used in case of Double buffer mode). |
AnnaBridge | 171:3a7713b1edbc | 1657 | * @rmtoll M1AR M1A LL_DMA_GetMemory1Address |
AnnaBridge | 171:3a7713b1edbc | 1658 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1659 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1660 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 1661 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 1662 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 1663 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 1664 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 1665 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 1666 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 1667 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 1668 | * @retval Between 0 to 0xFFFFFFFF |
AnnaBridge | 171:3a7713b1edbc | 1669 | */ |
AnnaBridge | 171:3a7713b1edbc | 1670 | __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 1671 | { |
AnnaBridge | 171:3a7713b1edbc | 1672 | return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR); |
AnnaBridge | 171:3a7713b1edbc | 1673 | } |
AnnaBridge | 171:3a7713b1edbc | 1674 | |
AnnaBridge | 171:3a7713b1edbc | 1675 | /** |
AnnaBridge | 171:3a7713b1edbc | 1676 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1677 | */ |
AnnaBridge | 171:3a7713b1edbc | 1678 | |
AnnaBridge | 171:3a7713b1edbc | 1679 | /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management |
AnnaBridge | 171:3a7713b1edbc | 1680 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1681 | */ |
AnnaBridge | 171:3a7713b1edbc | 1682 | |
AnnaBridge | 171:3a7713b1edbc | 1683 | /** |
AnnaBridge | 171:3a7713b1edbc | 1684 | * @brief Get Stream 0 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1685 | * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 |
AnnaBridge | 171:3a7713b1edbc | 1686 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1687 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1688 | */ |
AnnaBridge | 171:3a7713b1edbc | 1689 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1690 | { |
AnnaBridge | 171:3a7713b1edbc | 1691 | return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0)); |
AnnaBridge | 171:3a7713b1edbc | 1692 | } |
AnnaBridge | 171:3a7713b1edbc | 1693 | |
AnnaBridge | 171:3a7713b1edbc | 1694 | /** |
AnnaBridge | 171:3a7713b1edbc | 1695 | * @brief Get Stream 1 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1696 | * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 |
AnnaBridge | 171:3a7713b1edbc | 1697 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1698 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1699 | */ |
AnnaBridge | 171:3a7713b1edbc | 1700 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1701 | { |
AnnaBridge | 171:3a7713b1edbc | 1702 | return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1)); |
AnnaBridge | 171:3a7713b1edbc | 1703 | } |
AnnaBridge | 171:3a7713b1edbc | 1704 | |
AnnaBridge | 171:3a7713b1edbc | 1705 | /** |
AnnaBridge | 171:3a7713b1edbc | 1706 | * @brief Get Stream 2 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1707 | * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 |
AnnaBridge | 171:3a7713b1edbc | 1708 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1709 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1710 | */ |
AnnaBridge | 171:3a7713b1edbc | 1711 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1712 | { |
AnnaBridge | 171:3a7713b1edbc | 1713 | return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2)); |
AnnaBridge | 171:3a7713b1edbc | 1714 | } |
AnnaBridge | 171:3a7713b1edbc | 1715 | |
AnnaBridge | 171:3a7713b1edbc | 1716 | /** |
AnnaBridge | 171:3a7713b1edbc | 1717 | * @brief Get Stream 3 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1718 | * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 |
AnnaBridge | 171:3a7713b1edbc | 1719 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1720 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1721 | */ |
AnnaBridge | 171:3a7713b1edbc | 1722 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1723 | { |
AnnaBridge | 171:3a7713b1edbc | 1724 | return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3)); |
AnnaBridge | 171:3a7713b1edbc | 1725 | } |
AnnaBridge | 171:3a7713b1edbc | 1726 | |
AnnaBridge | 171:3a7713b1edbc | 1727 | /** |
AnnaBridge | 171:3a7713b1edbc | 1728 | * @brief Get Stream 4 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1729 | * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 |
AnnaBridge | 171:3a7713b1edbc | 1730 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1731 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1732 | */ |
AnnaBridge | 171:3a7713b1edbc | 1733 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1734 | { |
AnnaBridge | 171:3a7713b1edbc | 1735 | return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); |
AnnaBridge | 171:3a7713b1edbc | 1736 | } |
AnnaBridge | 171:3a7713b1edbc | 1737 | |
AnnaBridge | 171:3a7713b1edbc | 1738 | /** |
AnnaBridge | 171:3a7713b1edbc | 1739 | * @brief Get Stream 5 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1740 | * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 |
AnnaBridge | 171:3a7713b1edbc | 1741 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1742 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1743 | */ |
AnnaBridge | 171:3a7713b1edbc | 1744 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1745 | { |
AnnaBridge | 171:3a7713b1edbc | 1746 | return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); |
AnnaBridge | 171:3a7713b1edbc | 1747 | } |
AnnaBridge | 171:3a7713b1edbc | 1748 | |
AnnaBridge | 171:3a7713b1edbc | 1749 | /** |
AnnaBridge | 171:3a7713b1edbc | 1750 | * @brief Get Stream 6 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1751 | * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 |
AnnaBridge | 171:3a7713b1edbc | 1752 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1753 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1754 | */ |
AnnaBridge | 171:3a7713b1edbc | 1755 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1756 | { |
AnnaBridge | 171:3a7713b1edbc | 1757 | return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); |
AnnaBridge | 171:3a7713b1edbc | 1758 | } |
AnnaBridge | 171:3a7713b1edbc | 1759 | |
AnnaBridge | 171:3a7713b1edbc | 1760 | /** |
AnnaBridge | 171:3a7713b1edbc | 1761 | * @brief Get Stream 7 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 1762 | * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 |
AnnaBridge | 171:3a7713b1edbc | 1763 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1764 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1765 | */ |
AnnaBridge | 171:3a7713b1edbc | 1766 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1767 | { |
AnnaBridge | 171:3a7713b1edbc | 1768 | return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); |
AnnaBridge | 171:3a7713b1edbc | 1769 | } |
AnnaBridge | 171:3a7713b1edbc | 1770 | |
AnnaBridge | 171:3a7713b1edbc | 1771 | /** |
AnnaBridge | 171:3a7713b1edbc | 1772 | * @brief Get Stream 0 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1773 | * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 |
AnnaBridge | 171:3a7713b1edbc | 1774 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1775 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1776 | */ |
AnnaBridge | 171:3a7713b1edbc | 1777 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1778 | { |
AnnaBridge | 171:3a7713b1edbc | 1779 | return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0)); |
AnnaBridge | 171:3a7713b1edbc | 1780 | } |
AnnaBridge | 171:3a7713b1edbc | 1781 | |
AnnaBridge | 171:3a7713b1edbc | 1782 | /** |
AnnaBridge | 171:3a7713b1edbc | 1783 | * @brief Get Stream 1 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1784 | * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 |
AnnaBridge | 171:3a7713b1edbc | 1785 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1786 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1787 | */ |
AnnaBridge | 171:3a7713b1edbc | 1788 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1789 | { |
AnnaBridge | 171:3a7713b1edbc | 1790 | return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1)); |
AnnaBridge | 171:3a7713b1edbc | 1791 | } |
AnnaBridge | 171:3a7713b1edbc | 1792 | |
AnnaBridge | 171:3a7713b1edbc | 1793 | /** |
AnnaBridge | 171:3a7713b1edbc | 1794 | * @brief Get Stream 2 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1795 | * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 |
AnnaBridge | 171:3a7713b1edbc | 1796 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1797 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1798 | */ |
AnnaBridge | 171:3a7713b1edbc | 1799 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1800 | { |
AnnaBridge | 171:3a7713b1edbc | 1801 | return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2)); |
AnnaBridge | 171:3a7713b1edbc | 1802 | } |
AnnaBridge | 171:3a7713b1edbc | 1803 | |
AnnaBridge | 171:3a7713b1edbc | 1804 | /** |
AnnaBridge | 171:3a7713b1edbc | 1805 | * @brief Get Stream 3 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1806 | * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 |
AnnaBridge | 171:3a7713b1edbc | 1807 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1808 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1809 | */ |
AnnaBridge | 171:3a7713b1edbc | 1810 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1811 | { |
AnnaBridge | 171:3a7713b1edbc | 1812 | return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3)); |
AnnaBridge | 171:3a7713b1edbc | 1813 | } |
AnnaBridge | 171:3a7713b1edbc | 1814 | |
AnnaBridge | 171:3a7713b1edbc | 1815 | /** |
AnnaBridge | 171:3a7713b1edbc | 1816 | * @brief Get Stream 4 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1817 | * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 |
AnnaBridge | 171:3a7713b1edbc | 1818 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1819 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1820 | */ |
AnnaBridge | 171:3a7713b1edbc | 1821 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1822 | { |
AnnaBridge | 171:3a7713b1edbc | 1823 | return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); |
AnnaBridge | 171:3a7713b1edbc | 1824 | } |
AnnaBridge | 171:3a7713b1edbc | 1825 | |
AnnaBridge | 171:3a7713b1edbc | 1826 | /** |
AnnaBridge | 171:3a7713b1edbc | 1827 | * @brief Get Stream 5 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1828 | * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 |
AnnaBridge | 171:3a7713b1edbc | 1829 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1830 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1831 | */ |
AnnaBridge | 171:3a7713b1edbc | 1832 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1833 | { |
AnnaBridge | 171:3a7713b1edbc | 1834 | return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); |
AnnaBridge | 171:3a7713b1edbc | 1835 | } |
AnnaBridge | 171:3a7713b1edbc | 1836 | |
AnnaBridge | 171:3a7713b1edbc | 1837 | /** |
AnnaBridge | 171:3a7713b1edbc | 1838 | * @brief Get Stream 6 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1839 | * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 |
AnnaBridge | 171:3a7713b1edbc | 1840 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1841 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1842 | */ |
AnnaBridge | 171:3a7713b1edbc | 1843 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1844 | { |
AnnaBridge | 171:3a7713b1edbc | 1845 | return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); |
AnnaBridge | 171:3a7713b1edbc | 1846 | } |
AnnaBridge | 171:3a7713b1edbc | 1847 | |
AnnaBridge | 171:3a7713b1edbc | 1848 | /** |
AnnaBridge | 171:3a7713b1edbc | 1849 | * @brief Get Stream 7 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 1850 | * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 |
AnnaBridge | 171:3a7713b1edbc | 1851 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1852 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1853 | */ |
AnnaBridge | 171:3a7713b1edbc | 1854 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1855 | { |
AnnaBridge | 171:3a7713b1edbc | 1856 | return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); |
AnnaBridge | 171:3a7713b1edbc | 1857 | } |
AnnaBridge | 171:3a7713b1edbc | 1858 | |
AnnaBridge | 171:3a7713b1edbc | 1859 | /** |
AnnaBridge | 171:3a7713b1edbc | 1860 | * @brief Get Stream 0 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1861 | * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 |
AnnaBridge | 171:3a7713b1edbc | 1862 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1863 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1864 | */ |
AnnaBridge | 171:3a7713b1edbc | 1865 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1866 | { |
AnnaBridge | 171:3a7713b1edbc | 1867 | return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0)); |
AnnaBridge | 171:3a7713b1edbc | 1868 | } |
AnnaBridge | 171:3a7713b1edbc | 1869 | |
AnnaBridge | 171:3a7713b1edbc | 1870 | /** |
AnnaBridge | 171:3a7713b1edbc | 1871 | * @brief Get Stream 1 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1872 | * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 |
AnnaBridge | 171:3a7713b1edbc | 1873 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1874 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1875 | */ |
AnnaBridge | 171:3a7713b1edbc | 1876 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1877 | { |
AnnaBridge | 171:3a7713b1edbc | 1878 | return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1)); |
AnnaBridge | 171:3a7713b1edbc | 1879 | } |
AnnaBridge | 171:3a7713b1edbc | 1880 | |
AnnaBridge | 171:3a7713b1edbc | 1881 | /** |
AnnaBridge | 171:3a7713b1edbc | 1882 | * @brief Get Stream 2 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1883 | * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 |
AnnaBridge | 171:3a7713b1edbc | 1884 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1885 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1886 | */ |
AnnaBridge | 171:3a7713b1edbc | 1887 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1888 | { |
AnnaBridge | 171:3a7713b1edbc | 1889 | return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2)); |
AnnaBridge | 171:3a7713b1edbc | 1890 | } |
AnnaBridge | 171:3a7713b1edbc | 1891 | |
AnnaBridge | 171:3a7713b1edbc | 1892 | /** |
AnnaBridge | 171:3a7713b1edbc | 1893 | * @brief Get Stream 3 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1894 | * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 |
AnnaBridge | 171:3a7713b1edbc | 1895 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1896 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1897 | */ |
AnnaBridge | 171:3a7713b1edbc | 1898 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1899 | { |
AnnaBridge | 171:3a7713b1edbc | 1900 | return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3)); |
AnnaBridge | 171:3a7713b1edbc | 1901 | } |
AnnaBridge | 171:3a7713b1edbc | 1902 | |
AnnaBridge | 171:3a7713b1edbc | 1903 | /** |
AnnaBridge | 171:3a7713b1edbc | 1904 | * @brief Get Stream 4 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1905 | * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 |
AnnaBridge | 171:3a7713b1edbc | 1906 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1907 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1908 | */ |
AnnaBridge | 171:3a7713b1edbc | 1909 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1910 | { |
AnnaBridge | 171:3a7713b1edbc | 1911 | return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); |
AnnaBridge | 171:3a7713b1edbc | 1912 | } |
AnnaBridge | 171:3a7713b1edbc | 1913 | |
AnnaBridge | 171:3a7713b1edbc | 1914 | /** |
AnnaBridge | 171:3a7713b1edbc | 1915 | * @brief Get Stream 5 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1916 | * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 |
AnnaBridge | 171:3a7713b1edbc | 1917 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1918 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1919 | */ |
AnnaBridge | 171:3a7713b1edbc | 1920 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1921 | { |
AnnaBridge | 171:3a7713b1edbc | 1922 | return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); |
AnnaBridge | 171:3a7713b1edbc | 1923 | } |
AnnaBridge | 171:3a7713b1edbc | 1924 | |
AnnaBridge | 171:3a7713b1edbc | 1925 | /** |
AnnaBridge | 171:3a7713b1edbc | 1926 | * @brief Get Stream 6 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1927 | * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 |
AnnaBridge | 171:3a7713b1edbc | 1928 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1929 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1930 | */ |
AnnaBridge | 171:3a7713b1edbc | 1931 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1932 | { |
AnnaBridge | 171:3a7713b1edbc | 1933 | return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6)); |
AnnaBridge | 171:3a7713b1edbc | 1934 | } |
AnnaBridge | 171:3a7713b1edbc | 1935 | |
AnnaBridge | 171:3a7713b1edbc | 1936 | /** |
AnnaBridge | 171:3a7713b1edbc | 1937 | * @brief Get Stream 7 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 1938 | * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 |
AnnaBridge | 171:3a7713b1edbc | 1939 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1940 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1941 | */ |
AnnaBridge | 171:3a7713b1edbc | 1942 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1943 | { |
AnnaBridge | 171:3a7713b1edbc | 1944 | return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7)); |
AnnaBridge | 171:3a7713b1edbc | 1945 | } |
AnnaBridge | 171:3a7713b1edbc | 1946 | |
AnnaBridge | 171:3a7713b1edbc | 1947 | /** |
AnnaBridge | 171:3a7713b1edbc | 1948 | * @brief Get Stream 0 direct mode error flag. |
AnnaBridge | 171:3a7713b1edbc | 1949 | * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 |
AnnaBridge | 171:3a7713b1edbc | 1950 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1951 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1952 | */ |
AnnaBridge | 171:3a7713b1edbc | 1953 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1954 | { |
AnnaBridge | 171:3a7713b1edbc | 1955 | return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0)); |
AnnaBridge | 171:3a7713b1edbc | 1956 | } |
AnnaBridge | 171:3a7713b1edbc | 1957 | |
AnnaBridge | 171:3a7713b1edbc | 1958 | /** |
AnnaBridge | 171:3a7713b1edbc | 1959 | * @brief Get Stream 1 direct mode error flag. |
AnnaBridge | 171:3a7713b1edbc | 1960 | * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 |
AnnaBridge | 171:3a7713b1edbc | 1961 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1962 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1963 | */ |
AnnaBridge | 171:3a7713b1edbc | 1964 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1965 | { |
AnnaBridge | 171:3a7713b1edbc | 1966 | return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1)); |
AnnaBridge | 171:3a7713b1edbc | 1967 | } |
AnnaBridge | 171:3a7713b1edbc | 1968 | |
AnnaBridge | 171:3a7713b1edbc | 1969 | /** |
AnnaBridge | 171:3a7713b1edbc | 1970 | * @brief Get Stream 2 direct mode error flag. |
AnnaBridge | 171:3a7713b1edbc | 1971 | * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 |
AnnaBridge | 171:3a7713b1edbc | 1972 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1973 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1974 | */ |
AnnaBridge | 171:3a7713b1edbc | 1975 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1976 | { |
AnnaBridge | 171:3a7713b1edbc | 1977 | return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2)); |
AnnaBridge | 171:3a7713b1edbc | 1978 | } |
AnnaBridge | 171:3a7713b1edbc | 1979 | |
AnnaBridge | 171:3a7713b1edbc | 1980 | /** |
AnnaBridge | 171:3a7713b1edbc | 1981 | * @brief Get Stream 3 direct mode error flag. |
AnnaBridge | 171:3a7713b1edbc | 1982 | * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 |
AnnaBridge | 171:3a7713b1edbc | 1983 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1984 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1985 | */ |
AnnaBridge | 171:3a7713b1edbc | 1986 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1987 | { |
AnnaBridge | 171:3a7713b1edbc | 1988 | return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3)); |
AnnaBridge | 171:3a7713b1edbc | 1989 | } |
AnnaBridge | 171:3a7713b1edbc | 1990 | |
AnnaBridge | 171:3a7713b1edbc | 1991 | /** |
AnnaBridge | 171:3a7713b1edbc | 1992 | * @brief Get Stream 4 direct mode error flag. |
AnnaBridge | 171:3a7713b1edbc | 1993 | * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 |
AnnaBridge | 171:3a7713b1edbc | 1994 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 1995 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1996 | */ |
AnnaBridge | 171:3a7713b1edbc | 1997 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 1998 | { |
AnnaBridge | 171:3a7713b1edbc | 1999 | return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4)); |
AnnaBridge | 171:3a7713b1edbc | 2000 | } |
AnnaBridge | 171:3a7713b1edbc | 2001 | |
AnnaBridge | 171:3a7713b1edbc | 2002 | /** |
AnnaBridge | 171:3a7713b1edbc | 2003 | * @brief Get Stream 5 direct mode error flag. |
AnnaBridge | 171:3a7713b1edbc | 2004 | * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 |
AnnaBridge | 171:3a7713b1edbc | 2005 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2006 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2007 | */ |
AnnaBridge | 171:3a7713b1edbc | 2008 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2009 | { |
AnnaBridge | 171:3a7713b1edbc | 2010 | return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5)); |
AnnaBridge | 171:3a7713b1edbc | 2011 | } |
AnnaBridge | 171:3a7713b1edbc | 2012 | |
AnnaBridge | 171:3a7713b1edbc | 2013 | /** |
AnnaBridge | 171:3a7713b1edbc | 2014 | * @brief Get Stream 6 direct mode error flag. |
AnnaBridge | 171:3a7713b1edbc | 2015 | * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 |
AnnaBridge | 171:3a7713b1edbc | 2016 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2017 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2018 | */ |
AnnaBridge | 171:3a7713b1edbc | 2019 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2020 | { |
AnnaBridge | 171:3a7713b1edbc | 2021 | return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6)); |
AnnaBridge | 171:3a7713b1edbc | 2022 | } |
AnnaBridge | 171:3a7713b1edbc | 2023 | |
AnnaBridge | 171:3a7713b1edbc | 2024 | /** |
AnnaBridge | 171:3a7713b1edbc | 2025 | * @brief Get Stream 7 direct mode error flag. |
AnnaBridge | 171:3a7713b1edbc | 2026 | * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 |
AnnaBridge | 171:3a7713b1edbc | 2027 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2028 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2029 | */ |
AnnaBridge | 171:3a7713b1edbc | 2030 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2031 | { |
AnnaBridge | 171:3a7713b1edbc | 2032 | return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7)); |
AnnaBridge | 171:3a7713b1edbc | 2033 | } |
AnnaBridge | 171:3a7713b1edbc | 2034 | |
AnnaBridge | 171:3a7713b1edbc | 2035 | /** |
AnnaBridge | 171:3a7713b1edbc | 2036 | * @brief Get Stream 0 FIFO error flag. |
AnnaBridge | 171:3a7713b1edbc | 2037 | * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 |
AnnaBridge | 171:3a7713b1edbc | 2038 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2039 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2040 | */ |
AnnaBridge | 171:3a7713b1edbc | 2041 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2042 | { |
AnnaBridge | 171:3a7713b1edbc | 2043 | return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0)); |
AnnaBridge | 171:3a7713b1edbc | 2044 | } |
AnnaBridge | 171:3a7713b1edbc | 2045 | |
AnnaBridge | 171:3a7713b1edbc | 2046 | /** |
AnnaBridge | 171:3a7713b1edbc | 2047 | * @brief Get Stream 1 FIFO error flag. |
AnnaBridge | 171:3a7713b1edbc | 2048 | * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 |
AnnaBridge | 171:3a7713b1edbc | 2049 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2050 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2051 | */ |
AnnaBridge | 171:3a7713b1edbc | 2052 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2053 | { |
AnnaBridge | 171:3a7713b1edbc | 2054 | return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1)); |
AnnaBridge | 171:3a7713b1edbc | 2055 | } |
AnnaBridge | 171:3a7713b1edbc | 2056 | |
AnnaBridge | 171:3a7713b1edbc | 2057 | /** |
AnnaBridge | 171:3a7713b1edbc | 2058 | * @brief Get Stream 2 FIFO error flag. |
AnnaBridge | 171:3a7713b1edbc | 2059 | * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 |
AnnaBridge | 171:3a7713b1edbc | 2060 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2061 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2062 | */ |
AnnaBridge | 171:3a7713b1edbc | 2063 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2064 | { |
AnnaBridge | 171:3a7713b1edbc | 2065 | return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2)); |
AnnaBridge | 171:3a7713b1edbc | 2066 | } |
AnnaBridge | 171:3a7713b1edbc | 2067 | |
AnnaBridge | 171:3a7713b1edbc | 2068 | /** |
AnnaBridge | 171:3a7713b1edbc | 2069 | * @brief Get Stream 3 FIFO error flag. |
AnnaBridge | 171:3a7713b1edbc | 2070 | * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 |
AnnaBridge | 171:3a7713b1edbc | 2071 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2072 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2073 | */ |
AnnaBridge | 171:3a7713b1edbc | 2074 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2075 | { |
AnnaBridge | 171:3a7713b1edbc | 2076 | return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3)); |
AnnaBridge | 171:3a7713b1edbc | 2077 | } |
AnnaBridge | 171:3a7713b1edbc | 2078 | |
AnnaBridge | 171:3a7713b1edbc | 2079 | /** |
AnnaBridge | 171:3a7713b1edbc | 2080 | * @brief Get Stream 4 FIFO error flag. |
AnnaBridge | 171:3a7713b1edbc | 2081 | * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 |
AnnaBridge | 171:3a7713b1edbc | 2082 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2083 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2084 | */ |
AnnaBridge | 171:3a7713b1edbc | 2085 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2086 | { |
AnnaBridge | 171:3a7713b1edbc | 2087 | return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4)); |
AnnaBridge | 171:3a7713b1edbc | 2088 | } |
AnnaBridge | 171:3a7713b1edbc | 2089 | |
AnnaBridge | 171:3a7713b1edbc | 2090 | /** |
AnnaBridge | 171:3a7713b1edbc | 2091 | * @brief Get Stream 5 FIFO error flag. |
AnnaBridge | 171:3a7713b1edbc | 2092 | * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 |
AnnaBridge | 171:3a7713b1edbc | 2093 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2094 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2095 | */ |
AnnaBridge | 171:3a7713b1edbc | 2096 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2097 | { |
AnnaBridge | 171:3a7713b1edbc | 2098 | return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5)); |
AnnaBridge | 171:3a7713b1edbc | 2099 | } |
AnnaBridge | 171:3a7713b1edbc | 2100 | |
AnnaBridge | 171:3a7713b1edbc | 2101 | /** |
AnnaBridge | 171:3a7713b1edbc | 2102 | * @brief Get Stream 6 FIFO error flag. |
AnnaBridge | 171:3a7713b1edbc | 2103 | * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 |
AnnaBridge | 171:3a7713b1edbc | 2104 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2105 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2106 | */ |
AnnaBridge | 171:3a7713b1edbc | 2107 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2108 | { |
AnnaBridge | 171:3a7713b1edbc | 2109 | return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6)); |
AnnaBridge | 171:3a7713b1edbc | 2110 | } |
AnnaBridge | 171:3a7713b1edbc | 2111 | |
AnnaBridge | 171:3a7713b1edbc | 2112 | /** |
AnnaBridge | 171:3a7713b1edbc | 2113 | * @brief Get Stream 7 FIFO error flag. |
AnnaBridge | 171:3a7713b1edbc | 2114 | * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 |
AnnaBridge | 171:3a7713b1edbc | 2115 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2116 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2117 | */ |
AnnaBridge | 171:3a7713b1edbc | 2118 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2119 | { |
AnnaBridge | 171:3a7713b1edbc | 2120 | return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7)); |
AnnaBridge | 171:3a7713b1edbc | 2121 | } |
AnnaBridge | 171:3a7713b1edbc | 2122 | |
AnnaBridge | 171:3a7713b1edbc | 2123 | /** |
AnnaBridge | 171:3a7713b1edbc | 2124 | * @brief Clear Stream 0 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 2125 | * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 |
AnnaBridge | 171:3a7713b1edbc | 2126 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2127 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2128 | */ |
AnnaBridge | 171:3a7713b1edbc | 2129 | __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2130 | { |
AnnaBridge | 171:3a7713b1edbc | 2131 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); |
AnnaBridge | 171:3a7713b1edbc | 2132 | } |
AnnaBridge | 171:3a7713b1edbc | 2133 | |
AnnaBridge | 171:3a7713b1edbc | 2134 | /** |
AnnaBridge | 171:3a7713b1edbc | 2135 | * @brief Clear Stream 1 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 2136 | * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 |
AnnaBridge | 171:3a7713b1edbc | 2137 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2138 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2139 | */ |
AnnaBridge | 171:3a7713b1edbc | 2140 | __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2141 | { |
AnnaBridge | 171:3a7713b1edbc | 2142 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1); |
AnnaBridge | 171:3a7713b1edbc | 2143 | } |
AnnaBridge | 171:3a7713b1edbc | 2144 | |
AnnaBridge | 171:3a7713b1edbc | 2145 | /** |
AnnaBridge | 171:3a7713b1edbc | 2146 | * @brief Clear Stream 2 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 2147 | * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 |
AnnaBridge | 171:3a7713b1edbc | 2148 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2149 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2150 | */ |
AnnaBridge | 171:3a7713b1edbc | 2151 | __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2152 | { |
AnnaBridge | 171:3a7713b1edbc | 2153 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2); |
AnnaBridge | 171:3a7713b1edbc | 2154 | } |
AnnaBridge | 171:3a7713b1edbc | 2155 | |
AnnaBridge | 171:3a7713b1edbc | 2156 | /** |
AnnaBridge | 171:3a7713b1edbc | 2157 | * @brief Clear Stream 3 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 2158 | * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 |
AnnaBridge | 171:3a7713b1edbc | 2159 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2160 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2161 | */ |
AnnaBridge | 171:3a7713b1edbc | 2162 | __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2163 | { |
AnnaBridge | 171:3a7713b1edbc | 2164 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3); |
AnnaBridge | 171:3a7713b1edbc | 2165 | } |
AnnaBridge | 171:3a7713b1edbc | 2166 | |
AnnaBridge | 171:3a7713b1edbc | 2167 | /** |
AnnaBridge | 171:3a7713b1edbc | 2168 | * @brief Clear Stream 4 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 2169 | * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 |
AnnaBridge | 171:3a7713b1edbc | 2170 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2171 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2172 | */ |
AnnaBridge | 171:3a7713b1edbc | 2173 | __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2174 | { |
AnnaBridge | 171:3a7713b1edbc | 2175 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4); |
AnnaBridge | 171:3a7713b1edbc | 2176 | } |
AnnaBridge | 171:3a7713b1edbc | 2177 | |
AnnaBridge | 171:3a7713b1edbc | 2178 | /** |
AnnaBridge | 171:3a7713b1edbc | 2179 | * @brief Clear Stream 5 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 2180 | * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 |
AnnaBridge | 171:3a7713b1edbc | 2181 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2182 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2183 | */ |
AnnaBridge | 171:3a7713b1edbc | 2184 | __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2185 | { |
AnnaBridge | 171:3a7713b1edbc | 2186 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5); |
AnnaBridge | 171:3a7713b1edbc | 2187 | } |
AnnaBridge | 171:3a7713b1edbc | 2188 | |
AnnaBridge | 171:3a7713b1edbc | 2189 | /** |
AnnaBridge | 171:3a7713b1edbc | 2190 | * @brief Clear Stream 6 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 2191 | * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 |
AnnaBridge | 171:3a7713b1edbc | 2192 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2193 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2194 | */ |
AnnaBridge | 171:3a7713b1edbc | 2195 | __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2196 | { |
AnnaBridge | 171:3a7713b1edbc | 2197 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6); |
AnnaBridge | 171:3a7713b1edbc | 2198 | } |
AnnaBridge | 171:3a7713b1edbc | 2199 | |
AnnaBridge | 171:3a7713b1edbc | 2200 | /** |
AnnaBridge | 171:3a7713b1edbc | 2201 | * @brief Clear Stream 7 half transfer flag. |
AnnaBridge | 171:3a7713b1edbc | 2202 | * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 |
AnnaBridge | 171:3a7713b1edbc | 2203 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2204 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2205 | */ |
AnnaBridge | 171:3a7713b1edbc | 2206 | __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2207 | { |
AnnaBridge | 171:3a7713b1edbc | 2208 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7); |
AnnaBridge | 171:3a7713b1edbc | 2209 | } |
AnnaBridge | 171:3a7713b1edbc | 2210 | |
AnnaBridge | 171:3a7713b1edbc | 2211 | /** |
AnnaBridge | 171:3a7713b1edbc | 2212 | * @brief Clear Stream 0 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 2213 | * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 |
AnnaBridge | 171:3a7713b1edbc | 2214 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2215 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2216 | */ |
AnnaBridge | 171:3a7713b1edbc | 2217 | __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2218 | { |
AnnaBridge | 171:3a7713b1edbc | 2219 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0); |
AnnaBridge | 171:3a7713b1edbc | 2220 | } |
AnnaBridge | 171:3a7713b1edbc | 2221 | |
AnnaBridge | 171:3a7713b1edbc | 2222 | /** |
AnnaBridge | 171:3a7713b1edbc | 2223 | * @brief Clear Stream 1 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 2224 | * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 |
AnnaBridge | 171:3a7713b1edbc | 2225 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2226 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2227 | */ |
AnnaBridge | 171:3a7713b1edbc | 2228 | __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2229 | { |
AnnaBridge | 171:3a7713b1edbc | 2230 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1); |
AnnaBridge | 171:3a7713b1edbc | 2231 | } |
AnnaBridge | 171:3a7713b1edbc | 2232 | |
AnnaBridge | 171:3a7713b1edbc | 2233 | /** |
AnnaBridge | 171:3a7713b1edbc | 2234 | * @brief Clear Stream 2 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 2235 | * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 |
AnnaBridge | 171:3a7713b1edbc | 2236 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2237 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2238 | */ |
AnnaBridge | 171:3a7713b1edbc | 2239 | __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2240 | { |
AnnaBridge | 171:3a7713b1edbc | 2241 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2); |
AnnaBridge | 171:3a7713b1edbc | 2242 | } |
AnnaBridge | 171:3a7713b1edbc | 2243 | |
AnnaBridge | 171:3a7713b1edbc | 2244 | /** |
AnnaBridge | 171:3a7713b1edbc | 2245 | * @brief Clear Stream 3 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 2246 | * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 |
AnnaBridge | 171:3a7713b1edbc | 2247 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2248 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2249 | */ |
AnnaBridge | 171:3a7713b1edbc | 2250 | __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2251 | { |
AnnaBridge | 171:3a7713b1edbc | 2252 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3); |
AnnaBridge | 171:3a7713b1edbc | 2253 | } |
AnnaBridge | 171:3a7713b1edbc | 2254 | |
AnnaBridge | 171:3a7713b1edbc | 2255 | /** |
AnnaBridge | 171:3a7713b1edbc | 2256 | * @brief Clear Stream 4 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 2257 | * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 |
AnnaBridge | 171:3a7713b1edbc | 2258 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2259 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2260 | */ |
AnnaBridge | 171:3a7713b1edbc | 2261 | __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2262 | { |
AnnaBridge | 171:3a7713b1edbc | 2263 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4); |
AnnaBridge | 171:3a7713b1edbc | 2264 | } |
AnnaBridge | 171:3a7713b1edbc | 2265 | |
AnnaBridge | 171:3a7713b1edbc | 2266 | /** |
AnnaBridge | 171:3a7713b1edbc | 2267 | * @brief Clear Stream 5 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 2268 | * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 |
AnnaBridge | 171:3a7713b1edbc | 2269 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2270 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2271 | */ |
AnnaBridge | 171:3a7713b1edbc | 2272 | __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2273 | { |
AnnaBridge | 171:3a7713b1edbc | 2274 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5); |
AnnaBridge | 171:3a7713b1edbc | 2275 | } |
AnnaBridge | 171:3a7713b1edbc | 2276 | |
AnnaBridge | 171:3a7713b1edbc | 2277 | /** |
AnnaBridge | 171:3a7713b1edbc | 2278 | * @brief Clear Stream 6 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 2279 | * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 |
AnnaBridge | 171:3a7713b1edbc | 2280 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2281 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2282 | */ |
AnnaBridge | 171:3a7713b1edbc | 2283 | __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2284 | { |
AnnaBridge | 171:3a7713b1edbc | 2285 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6); |
AnnaBridge | 171:3a7713b1edbc | 2286 | } |
AnnaBridge | 171:3a7713b1edbc | 2287 | |
AnnaBridge | 171:3a7713b1edbc | 2288 | /** |
AnnaBridge | 171:3a7713b1edbc | 2289 | * @brief Clear Stream 7 transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 2290 | * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 |
AnnaBridge | 171:3a7713b1edbc | 2291 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2292 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2293 | */ |
AnnaBridge | 171:3a7713b1edbc | 2294 | __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2295 | { |
AnnaBridge | 171:3a7713b1edbc | 2296 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7); |
AnnaBridge | 171:3a7713b1edbc | 2297 | } |
AnnaBridge | 171:3a7713b1edbc | 2298 | |
AnnaBridge | 171:3a7713b1edbc | 2299 | /** |
AnnaBridge | 171:3a7713b1edbc | 2300 | * @brief Clear Stream 0 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 2301 | * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 |
AnnaBridge | 171:3a7713b1edbc | 2302 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2303 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2304 | */ |
AnnaBridge | 171:3a7713b1edbc | 2305 | __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2306 | { |
AnnaBridge | 171:3a7713b1edbc | 2307 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0); |
AnnaBridge | 171:3a7713b1edbc | 2308 | } |
AnnaBridge | 171:3a7713b1edbc | 2309 | |
AnnaBridge | 171:3a7713b1edbc | 2310 | /** |
AnnaBridge | 171:3a7713b1edbc | 2311 | * @brief Clear Stream 1 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 2312 | * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 |
AnnaBridge | 171:3a7713b1edbc | 2313 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2314 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2315 | */ |
AnnaBridge | 171:3a7713b1edbc | 2316 | __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2317 | { |
AnnaBridge | 171:3a7713b1edbc | 2318 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1); |
AnnaBridge | 171:3a7713b1edbc | 2319 | } |
AnnaBridge | 171:3a7713b1edbc | 2320 | |
AnnaBridge | 171:3a7713b1edbc | 2321 | /** |
AnnaBridge | 171:3a7713b1edbc | 2322 | * @brief Clear Stream 2 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 2323 | * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 |
AnnaBridge | 171:3a7713b1edbc | 2324 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2325 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2326 | */ |
AnnaBridge | 171:3a7713b1edbc | 2327 | __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2328 | { |
AnnaBridge | 171:3a7713b1edbc | 2329 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2); |
AnnaBridge | 171:3a7713b1edbc | 2330 | } |
AnnaBridge | 171:3a7713b1edbc | 2331 | |
AnnaBridge | 171:3a7713b1edbc | 2332 | /** |
AnnaBridge | 171:3a7713b1edbc | 2333 | * @brief Clear Stream 3 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 2334 | * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 |
AnnaBridge | 171:3a7713b1edbc | 2335 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2336 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2337 | */ |
AnnaBridge | 171:3a7713b1edbc | 2338 | __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2339 | { |
AnnaBridge | 171:3a7713b1edbc | 2340 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3); |
AnnaBridge | 171:3a7713b1edbc | 2341 | } |
AnnaBridge | 171:3a7713b1edbc | 2342 | |
AnnaBridge | 171:3a7713b1edbc | 2343 | /** |
AnnaBridge | 171:3a7713b1edbc | 2344 | * @brief Clear Stream 4 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 2345 | * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 |
AnnaBridge | 171:3a7713b1edbc | 2346 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2347 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2348 | */ |
AnnaBridge | 171:3a7713b1edbc | 2349 | __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2350 | { |
AnnaBridge | 171:3a7713b1edbc | 2351 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4); |
AnnaBridge | 171:3a7713b1edbc | 2352 | } |
AnnaBridge | 171:3a7713b1edbc | 2353 | |
AnnaBridge | 171:3a7713b1edbc | 2354 | /** |
AnnaBridge | 171:3a7713b1edbc | 2355 | * @brief Clear Stream 5 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 2356 | * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 |
AnnaBridge | 171:3a7713b1edbc | 2357 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2358 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2359 | */ |
AnnaBridge | 171:3a7713b1edbc | 2360 | __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2361 | { |
AnnaBridge | 171:3a7713b1edbc | 2362 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5); |
AnnaBridge | 171:3a7713b1edbc | 2363 | } |
AnnaBridge | 171:3a7713b1edbc | 2364 | |
AnnaBridge | 171:3a7713b1edbc | 2365 | /** |
AnnaBridge | 171:3a7713b1edbc | 2366 | * @brief Clear Stream 6 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 2367 | * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 |
AnnaBridge | 171:3a7713b1edbc | 2368 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2369 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2370 | */ |
AnnaBridge | 171:3a7713b1edbc | 2371 | __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2372 | { |
AnnaBridge | 171:3a7713b1edbc | 2373 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6); |
AnnaBridge | 171:3a7713b1edbc | 2374 | } |
AnnaBridge | 171:3a7713b1edbc | 2375 | |
AnnaBridge | 171:3a7713b1edbc | 2376 | /** |
AnnaBridge | 171:3a7713b1edbc | 2377 | * @brief Clear Stream 7 transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 2378 | * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 |
AnnaBridge | 171:3a7713b1edbc | 2379 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2380 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2381 | */ |
AnnaBridge | 171:3a7713b1edbc | 2382 | __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2383 | { |
AnnaBridge | 171:3a7713b1edbc | 2384 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7); |
AnnaBridge | 171:3a7713b1edbc | 2385 | } |
AnnaBridge | 171:3a7713b1edbc | 2386 | |
AnnaBridge | 171:3a7713b1edbc | 2387 | /** |
AnnaBridge | 171:3a7713b1edbc | 2388 | * @brief Clear Stream 0 direct mode error flag. |
AnnaBridge | 171:3a7713b1edbc | 2389 | * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 |
AnnaBridge | 171:3a7713b1edbc | 2390 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2391 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2392 | */ |
AnnaBridge | 171:3a7713b1edbc | 2393 | __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2394 | { |
AnnaBridge | 171:3a7713b1edbc | 2395 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0); |
AnnaBridge | 171:3a7713b1edbc | 2396 | } |
AnnaBridge | 171:3a7713b1edbc | 2397 | |
AnnaBridge | 171:3a7713b1edbc | 2398 | /** |
AnnaBridge | 171:3a7713b1edbc | 2399 | * @brief Clear Stream 1 direct mode error flag. |
AnnaBridge | 171:3a7713b1edbc | 2400 | * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 |
AnnaBridge | 171:3a7713b1edbc | 2401 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2402 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2403 | */ |
AnnaBridge | 171:3a7713b1edbc | 2404 | __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2405 | { |
AnnaBridge | 171:3a7713b1edbc | 2406 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1); |
AnnaBridge | 171:3a7713b1edbc | 2407 | } |
AnnaBridge | 171:3a7713b1edbc | 2408 | |
AnnaBridge | 171:3a7713b1edbc | 2409 | /** |
AnnaBridge | 171:3a7713b1edbc | 2410 | * @brief Clear Stream 2 direct mode error flag. |
AnnaBridge | 171:3a7713b1edbc | 2411 | * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 |
AnnaBridge | 171:3a7713b1edbc | 2412 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2413 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2414 | */ |
AnnaBridge | 171:3a7713b1edbc | 2415 | __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2416 | { |
AnnaBridge | 171:3a7713b1edbc | 2417 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2); |
AnnaBridge | 171:3a7713b1edbc | 2418 | } |
AnnaBridge | 171:3a7713b1edbc | 2419 | |
AnnaBridge | 171:3a7713b1edbc | 2420 | /** |
AnnaBridge | 171:3a7713b1edbc | 2421 | * @brief Clear Stream 3 direct mode error flag. |
AnnaBridge | 171:3a7713b1edbc | 2422 | * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 |
AnnaBridge | 171:3a7713b1edbc | 2423 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2424 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2425 | */ |
AnnaBridge | 171:3a7713b1edbc | 2426 | __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2427 | { |
AnnaBridge | 171:3a7713b1edbc | 2428 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3); |
AnnaBridge | 171:3a7713b1edbc | 2429 | } |
AnnaBridge | 171:3a7713b1edbc | 2430 | |
AnnaBridge | 171:3a7713b1edbc | 2431 | /** |
AnnaBridge | 171:3a7713b1edbc | 2432 | * @brief Clear Stream 4 direct mode error flag. |
AnnaBridge | 171:3a7713b1edbc | 2433 | * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 |
AnnaBridge | 171:3a7713b1edbc | 2434 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2435 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2436 | */ |
AnnaBridge | 171:3a7713b1edbc | 2437 | __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2438 | { |
AnnaBridge | 171:3a7713b1edbc | 2439 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4); |
AnnaBridge | 171:3a7713b1edbc | 2440 | } |
AnnaBridge | 171:3a7713b1edbc | 2441 | |
AnnaBridge | 171:3a7713b1edbc | 2442 | /** |
AnnaBridge | 171:3a7713b1edbc | 2443 | * @brief Clear Stream 5 direct mode error flag. |
AnnaBridge | 171:3a7713b1edbc | 2444 | * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 |
AnnaBridge | 171:3a7713b1edbc | 2445 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2446 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2447 | */ |
AnnaBridge | 171:3a7713b1edbc | 2448 | __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2449 | { |
AnnaBridge | 171:3a7713b1edbc | 2450 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5); |
AnnaBridge | 171:3a7713b1edbc | 2451 | } |
AnnaBridge | 171:3a7713b1edbc | 2452 | |
AnnaBridge | 171:3a7713b1edbc | 2453 | /** |
AnnaBridge | 171:3a7713b1edbc | 2454 | * @brief Clear Stream 6 direct mode error flag. |
AnnaBridge | 171:3a7713b1edbc | 2455 | * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 |
AnnaBridge | 171:3a7713b1edbc | 2456 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2457 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2458 | */ |
AnnaBridge | 171:3a7713b1edbc | 2459 | __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2460 | { |
AnnaBridge | 171:3a7713b1edbc | 2461 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6); |
AnnaBridge | 171:3a7713b1edbc | 2462 | } |
AnnaBridge | 171:3a7713b1edbc | 2463 | |
AnnaBridge | 171:3a7713b1edbc | 2464 | /** |
AnnaBridge | 171:3a7713b1edbc | 2465 | * @brief Clear Stream 7 direct mode error flag. |
AnnaBridge | 171:3a7713b1edbc | 2466 | * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 |
AnnaBridge | 171:3a7713b1edbc | 2467 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2468 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2469 | */ |
AnnaBridge | 171:3a7713b1edbc | 2470 | __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2471 | { |
AnnaBridge | 171:3a7713b1edbc | 2472 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7); |
AnnaBridge | 171:3a7713b1edbc | 2473 | } |
AnnaBridge | 171:3a7713b1edbc | 2474 | |
AnnaBridge | 171:3a7713b1edbc | 2475 | /** |
AnnaBridge | 171:3a7713b1edbc | 2476 | * @brief Clear Stream 0 FIFO error flag. |
AnnaBridge | 171:3a7713b1edbc | 2477 | * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 |
AnnaBridge | 171:3a7713b1edbc | 2478 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2479 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2480 | */ |
AnnaBridge | 171:3a7713b1edbc | 2481 | __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2482 | { |
AnnaBridge | 171:3a7713b1edbc | 2483 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0); |
AnnaBridge | 171:3a7713b1edbc | 2484 | } |
AnnaBridge | 171:3a7713b1edbc | 2485 | |
AnnaBridge | 171:3a7713b1edbc | 2486 | /** |
AnnaBridge | 171:3a7713b1edbc | 2487 | * @brief Clear Stream 1 FIFO error flag. |
AnnaBridge | 171:3a7713b1edbc | 2488 | * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 |
AnnaBridge | 171:3a7713b1edbc | 2489 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2490 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2491 | */ |
AnnaBridge | 171:3a7713b1edbc | 2492 | __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2493 | { |
AnnaBridge | 171:3a7713b1edbc | 2494 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1); |
AnnaBridge | 171:3a7713b1edbc | 2495 | } |
AnnaBridge | 171:3a7713b1edbc | 2496 | |
AnnaBridge | 171:3a7713b1edbc | 2497 | /** |
AnnaBridge | 171:3a7713b1edbc | 2498 | * @brief Clear Stream 2 FIFO error flag. |
AnnaBridge | 171:3a7713b1edbc | 2499 | * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 |
AnnaBridge | 171:3a7713b1edbc | 2500 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2501 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2502 | */ |
AnnaBridge | 171:3a7713b1edbc | 2503 | __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2504 | { |
AnnaBridge | 171:3a7713b1edbc | 2505 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2); |
AnnaBridge | 171:3a7713b1edbc | 2506 | } |
AnnaBridge | 171:3a7713b1edbc | 2507 | |
AnnaBridge | 171:3a7713b1edbc | 2508 | /** |
AnnaBridge | 171:3a7713b1edbc | 2509 | * @brief Clear Stream 3 FIFO error flag. |
AnnaBridge | 171:3a7713b1edbc | 2510 | * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 |
AnnaBridge | 171:3a7713b1edbc | 2511 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2512 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2513 | */ |
AnnaBridge | 171:3a7713b1edbc | 2514 | __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2515 | { |
AnnaBridge | 171:3a7713b1edbc | 2516 | WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3); |
AnnaBridge | 171:3a7713b1edbc | 2517 | } |
AnnaBridge | 171:3a7713b1edbc | 2518 | |
AnnaBridge | 171:3a7713b1edbc | 2519 | /** |
AnnaBridge | 171:3a7713b1edbc | 2520 | * @brief Clear Stream 4 FIFO error flag. |
AnnaBridge | 171:3a7713b1edbc | 2521 | * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 |
AnnaBridge | 171:3a7713b1edbc | 2522 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2523 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2524 | */ |
AnnaBridge | 171:3a7713b1edbc | 2525 | __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2526 | { |
AnnaBridge | 171:3a7713b1edbc | 2527 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4); |
AnnaBridge | 171:3a7713b1edbc | 2528 | } |
AnnaBridge | 171:3a7713b1edbc | 2529 | |
AnnaBridge | 171:3a7713b1edbc | 2530 | /** |
AnnaBridge | 171:3a7713b1edbc | 2531 | * @brief Clear Stream 5 FIFO error flag. |
AnnaBridge | 171:3a7713b1edbc | 2532 | * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 |
AnnaBridge | 171:3a7713b1edbc | 2533 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2534 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2535 | */ |
AnnaBridge | 171:3a7713b1edbc | 2536 | __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2537 | { |
AnnaBridge | 171:3a7713b1edbc | 2538 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5); |
AnnaBridge | 171:3a7713b1edbc | 2539 | } |
AnnaBridge | 171:3a7713b1edbc | 2540 | |
AnnaBridge | 171:3a7713b1edbc | 2541 | /** |
AnnaBridge | 171:3a7713b1edbc | 2542 | * @brief Clear Stream 6 FIFO error flag. |
AnnaBridge | 171:3a7713b1edbc | 2543 | * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 |
AnnaBridge | 171:3a7713b1edbc | 2544 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2545 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2546 | */ |
AnnaBridge | 171:3a7713b1edbc | 2547 | __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2548 | { |
AnnaBridge | 171:3a7713b1edbc | 2549 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6); |
AnnaBridge | 171:3a7713b1edbc | 2550 | } |
AnnaBridge | 171:3a7713b1edbc | 2551 | |
AnnaBridge | 171:3a7713b1edbc | 2552 | /** |
AnnaBridge | 171:3a7713b1edbc | 2553 | * @brief Clear Stream 7 FIFO error flag. |
AnnaBridge | 171:3a7713b1edbc | 2554 | * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 |
AnnaBridge | 171:3a7713b1edbc | 2555 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2556 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2557 | */ |
AnnaBridge | 171:3a7713b1edbc | 2558 | __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) |
AnnaBridge | 171:3a7713b1edbc | 2559 | { |
AnnaBridge | 171:3a7713b1edbc | 2560 | WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7); |
AnnaBridge | 171:3a7713b1edbc | 2561 | } |
AnnaBridge | 171:3a7713b1edbc | 2562 | |
AnnaBridge | 171:3a7713b1edbc | 2563 | /** |
AnnaBridge | 171:3a7713b1edbc | 2564 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2565 | */ |
AnnaBridge | 171:3a7713b1edbc | 2566 | |
AnnaBridge | 171:3a7713b1edbc | 2567 | /** @defgroup DMA_LL_EF_IT_Management IT_Management |
AnnaBridge | 171:3a7713b1edbc | 2568 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2569 | */ |
AnnaBridge | 171:3a7713b1edbc | 2570 | |
AnnaBridge | 171:3a7713b1edbc | 2571 | /** |
AnnaBridge | 171:3a7713b1edbc | 2572 | * @brief Enable Half transfer interrupt. |
AnnaBridge | 171:3a7713b1edbc | 2573 | * @rmtoll CR HTIE LL_DMA_EnableIT_HT |
AnnaBridge | 171:3a7713b1edbc | 2574 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2575 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2576 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 2577 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 2578 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 2579 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 2580 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 2581 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 2582 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 2583 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 2584 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2585 | */ |
AnnaBridge | 171:3a7713b1edbc | 2586 | __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 2587 | { |
AnnaBridge | 171:3a7713b1edbc | 2588 | SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); |
AnnaBridge | 171:3a7713b1edbc | 2589 | } |
AnnaBridge | 171:3a7713b1edbc | 2590 | |
AnnaBridge | 171:3a7713b1edbc | 2591 | /** |
AnnaBridge | 171:3a7713b1edbc | 2592 | * @brief Enable Transfer error interrupt. |
AnnaBridge | 171:3a7713b1edbc | 2593 | * @rmtoll CR TEIE LL_DMA_EnableIT_TE |
AnnaBridge | 171:3a7713b1edbc | 2594 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2595 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2596 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 2597 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 2598 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 2599 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 2600 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 2601 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 2602 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 2603 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 2604 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2605 | */ |
AnnaBridge | 171:3a7713b1edbc | 2606 | __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 2607 | { |
AnnaBridge | 171:3a7713b1edbc | 2608 | SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); |
AnnaBridge | 171:3a7713b1edbc | 2609 | } |
AnnaBridge | 171:3a7713b1edbc | 2610 | |
AnnaBridge | 171:3a7713b1edbc | 2611 | /** |
AnnaBridge | 171:3a7713b1edbc | 2612 | * @brief Enable Transfer complete interrupt. |
AnnaBridge | 171:3a7713b1edbc | 2613 | * @rmtoll CR TCIE LL_DMA_EnableIT_TC |
AnnaBridge | 171:3a7713b1edbc | 2614 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2615 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2616 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 2617 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 2618 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 2619 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 2620 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 2621 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 2622 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 2623 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 2624 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2625 | */ |
AnnaBridge | 171:3a7713b1edbc | 2626 | __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 2627 | { |
AnnaBridge | 171:3a7713b1edbc | 2628 | SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); |
AnnaBridge | 171:3a7713b1edbc | 2629 | } |
AnnaBridge | 171:3a7713b1edbc | 2630 | |
AnnaBridge | 171:3a7713b1edbc | 2631 | /** |
AnnaBridge | 171:3a7713b1edbc | 2632 | * @brief Enable Direct mode error interrupt. |
AnnaBridge | 171:3a7713b1edbc | 2633 | * @rmtoll CR DMEIE LL_DMA_EnableIT_DME |
AnnaBridge | 171:3a7713b1edbc | 2634 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2635 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2636 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 2637 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 2638 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 2639 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 2640 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 2641 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 2642 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 2643 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 2644 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2645 | */ |
AnnaBridge | 171:3a7713b1edbc | 2646 | __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 2647 | { |
AnnaBridge | 171:3a7713b1edbc | 2648 | SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); |
AnnaBridge | 171:3a7713b1edbc | 2649 | } |
AnnaBridge | 171:3a7713b1edbc | 2650 | |
AnnaBridge | 171:3a7713b1edbc | 2651 | /** |
AnnaBridge | 171:3a7713b1edbc | 2652 | * @brief Enable FIFO error interrupt. |
AnnaBridge | 171:3a7713b1edbc | 2653 | * @rmtoll FCR FEIE LL_DMA_EnableIT_FE |
AnnaBridge | 171:3a7713b1edbc | 2654 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2655 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2656 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 2657 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 2658 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 2659 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 2660 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 2661 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 2662 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 2663 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 2664 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2665 | */ |
AnnaBridge | 171:3a7713b1edbc | 2666 | __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 2667 | { |
AnnaBridge | 171:3a7713b1edbc | 2668 | SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); |
AnnaBridge | 171:3a7713b1edbc | 2669 | } |
AnnaBridge | 171:3a7713b1edbc | 2670 | |
AnnaBridge | 171:3a7713b1edbc | 2671 | /** |
AnnaBridge | 171:3a7713b1edbc | 2672 | * @brief Disable Half transfer interrupt. |
AnnaBridge | 171:3a7713b1edbc | 2673 | * @rmtoll CR HTIE LL_DMA_DisableIT_HT |
AnnaBridge | 171:3a7713b1edbc | 2674 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2675 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2676 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 2677 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 2678 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 2679 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 2680 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 2681 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 2682 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 2683 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 2684 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2685 | */ |
AnnaBridge | 171:3a7713b1edbc | 2686 | __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 2687 | { |
AnnaBridge | 171:3a7713b1edbc | 2688 | CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); |
AnnaBridge | 171:3a7713b1edbc | 2689 | } |
AnnaBridge | 171:3a7713b1edbc | 2690 | |
AnnaBridge | 171:3a7713b1edbc | 2691 | /** |
AnnaBridge | 171:3a7713b1edbc | 2692 | * @brief Disable Transfer error interrupt. |
AnnaBridge | 171:3a7713b1edbc | 2693 | * @rmtoll CR TEIE LL_DMA_DisableIT_TE |
AnnaBridge | 171:3a7713b1edbc | 2694 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2695 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2696 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 2697 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 2698 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 2699 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 2700 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 2701 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 2702 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 2703 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 2704 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2705 | */ |
AnnaBridge | 171:3a7713b1edbc | 2706 | __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 2707 | { |
AnnaBridge | 171:3a7713b1edbc | 2708 | CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); |
AnnaBridge | 171:3a7713b1edbc | 2709 | } |
AnnaBridge | 171:3a7713b1edbc | 2710 | |
AnnaBridge | 171:3a7713b1edbc | 2711 | /** |
AnnaBridge | 171:3a7713b1edbc | 2712 | * @brief Disable Transfer complete interrupt. |
AnnaBridge | 171:3a7713b1edbc | 2713 | * @rmtoll CR TCIE LL_DMA_DisableIT_TC |
AnnaBridge | 171:3a7713b1edbc | 2714 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2715 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2716 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 2717 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 2718 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 2719 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 2720 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 2721 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 2722 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 2723 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 2724 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2725 | */ |
AnnaBridge | 171:3a7713b1edbc | 2726 | __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 2727 | { |
AnnaBridge | 171:3a7713b1edbc | 2728 | CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); |
AnnaBridge | 171:3a7713b1edbc | 2729 | } |
AnnaBridge | 171:3a7713b1edbc | 2730 | |
AnnaBridge | 171:3a7713b1edbc | 2731 | /** |
AnnaBridge | 171:3a7713b1edbc | 2732 | * @brief Disable Direct mode error interrupt. |
AnnaBridge | 171:3a7713b1edbc | 2733 | * @rmtoll CR DMEIE LL_DMA_DisableIT_DME |
AnnaBridge | 171:3a7713b1edbc | 2734 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2735 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2736 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 2737 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 2738 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 2739 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 2740 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 2741 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 2742 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 2743 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 2744 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2745 | */ |
AnnaBridge | 171:3a7713b1edbc | 2746 | __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 2747 | { |
AnnaBridge | 171:3a7713b1edbc | 2748 | CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); |
AnnaBridge | 171:3a7713b1edbc | 2749 | } |
AnnaBridge | 171:3a7713b1edbc | 2750 | |
AnnaBridge | 171:3a7713b1edbc | 2751 | /** |
AnnaBridge | 171:3a7713b1edbc | 2752 | * @brief Disable FIFO error interrupt. |
AnnaBridge | 171:3a7713b1edbc | 2753 | * @rmtoll FCR FEIE LL_DMA_DisableIT_FE |
AnnaBridge | 171:3a7713b1edbc | 2754 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2755 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2756 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 2757 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 2758 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 2759 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 2760 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 2761 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 2762 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 2763 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 2764 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2765 | */ |
AnnaBridge | 171:3a7713b1edbc | 2766 | __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 2767 | { |
AnnaBridge | 171:3a7713b1edbc | 2768 | CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); |
AnnaBridge | 171:3a7713b1edbc | 2769 | } |
AnnaBridge | 171:3a7713b1edbc | 2770 | |
AnnaBridge | 171:3a7713b1edbc | 2771 | /** |
AnnaBridge | 171:3a7713b1edbc | 2772 | * @brief Check if Half transfer interrup is enabled. |
AnnaBridge | 171:3a7713b1edbc | 2773 | * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT |
AnnaBridge | 171:3a7713b1edbc | 2774 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2775 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2776 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 2777 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 2778 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 2779 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 2780 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 2781 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 2782 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 2783 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 2784 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2785 | */ |
AnnaBridge | 171:3a7713b1edbc | 2786 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 2787 | { |
AnnaBridge | 171:3a7713b1edbc | 2788 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE); |
AnnaBridge | 171:3a7713b1edbc | 2789 | } |
AnnaBridge | 171:3a7713b1edbc | 2790 | |
AnnaBridge | 171:3a7713b1edbc | 2791 | /** |
AnnaBridge | 171:3a7713b1edbc | 2792 | * @brief Check if Transfer error nterrup is enabled. |
AnnaBridge | 171:3a7713b1edbc | 2793 | * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE |
AnnaBridge | 171:3a7713b1edbc | 2794 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2795 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2796 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 2797 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 2798 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 2799 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 2800 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 2801 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 2802 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 2803 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 2804 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2805 | */ |
AnnaBridge | 171:3a7713b1edbc | 2806 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 2807 | { |
AnnaBridge | 171:3a7713b1edbc | 2808 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE); |
AnnaBridge | 171:3a7713b1edbc | 2809 | } |
AnnaBridge | 171:3a7713b1edbc | 2810 | |
AnnaBridge | 171:3a7713b1edbc | 2811 | /** |
AnnaBridge | 171:3a7713b1edbc | 2812 | * @brief Check if Transfer complete interrup is enabled. |
AnnaBridge | 171:3a7713b1edbc | 2813 | * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC |
AnnaBridge | 171:3a7713b1edbc | 2814 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2815 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2816 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 2817 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 2818 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 2819 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 2820 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 2821 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 2822 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 2823 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 2824 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2825 | */ |
AnnaBridge | 171:3a7713b1edbc | 2826 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 2827 | { |
AnnaBridge | 171:3a7713b1edbc | 2828 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE); |
AnnaBridge | 171:3a7713b1edbc | 2829 | } |
AnnaBridge | 171:3a7713b1edbc | 2830 | |
AnnaBridge | 171:3a7713b1edbc | 2831 | /** |
AnnaBridge | 171:3a7713b1edbc | 2832 | * @brief Check if Direct mode error interrupt is enabled. |
AnnaBridge | 171:3a7713b1edbc | 2833 | * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME |
AnnaBridge | 171:3a7713b1edbc | 2834 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2835 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2836 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 2837 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 2838 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 2839 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 2840 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 2841 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 2842 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 2843 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 2844 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2845 | */ |
AnnaBridge | 171:3a7713b1edbc | 2846 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 2847 | { |
AnnaBridge | 171:3a7713b1edbc | 2848 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE); |
AnnaBridge | 171:3a7713b1edbc | 2849 | } |
AnnaBridge | 171:3a7713b1edbc | 2850 | |
AnnaBridge | 171:3a7713b1edbc | 2851 | /** |
AnnaBridge | 171:3a7713b1edbc | 2852 | * @brief Check if FIFO error interrup is enabled. |
AnnaBridge | 171:3a7713b1edbc | 2853 | * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE |
AnnaBridge | 171:3a7713b1edbc | 2854 | * @param DMAx DMAx Instance |
AnnaBridge | 171:3a7713b1edbc | 2855 | * @param Stream This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2856 | * @arg @ref LL_DMA_STREAM_0 |
AnnaBridge | 171:3a7713b1edbc | 2857 | * @arg @ref LL_DMA_STREAM_1 |
AnnaBridge | 171:3a7713b1edbc | 2858 | * @arg @ref LL_DMA_STREAM_2 |
AnnaBridge | 171:3a7713b1edbc | 2859 | * @arg @ref LL_DMA_STREAM_3 |
AnnaBridge | 171:3a7713b1edbc | 2860 | * @arg @ref LL_DMA_STREAM_4 |
AnnaBridge | 171:3a7713b1edbc | 2861 | * @arg @ref LL_DMA_STREAM_5 |
AnnaBridge | 171:3a7713b1edbc | 2862 | * @arg @ref LL_DMA_STREAM_6 |
AnnaBridge | 171:3a7713b1edbc | 2863 | * @arg @ref LL_DMA_STREAM_7 |
AnnaBridge | 171:3a7713b1edbc | 2864 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2865 | */ |
AnnaBridge | 171:3a7713b1edbc | 2866 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) |
AnnaBridge | 171:3a7713b1edbc | 2867 | { |
AnnaBridge | 171:3a7713b1edbc | 2868 | return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE); |
AnnaBridge | 171:3a7713b1edbc | 2869 | } |
AnnaBridge | 171:3a7713b1edbc | 2870 | |
AnnaBridge | 171:3a7713b1edbc | 2871 | /** |
AnnaBridge | 171:3a7713b1edbc | 2872 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2873 | */ |
AnnaBridge | 171:3a7713b1edbc | 2874 | |
AnnaBridge | 171:3a7713b1edbc | 2875 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 2876 | /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions |
AnnaBridge | 171:3a7713b1edbc | 2877 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2878 | */ |
AnnaBridge | 171:3a7713b1edbc | 2879 | |
AnnaBridge | 171:3a7713b1edbc | 2880 | uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct); |
AnnaBridge | 171:3a7713b1edbc | 2881 | uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream); |
AnnaBridge | 171:3a7713b1edbc | 2882 | void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); |
AnnaBridge | 171:3a7713b1edbc | 2883 | |
AnnaBridge | 171:3a7713b1edbc | 2884 | /** |
AnnaBridge | 171:3a7713b1edbc | 2885 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2886 | */ |
AnnaBridge | 171:3a7713b1edbc | 2887 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 171:3a7713b1edbc | 2888 | |
AnnaBridge | 171:3a7713b1edbc | 2889 | /** |
AnnaBridge | 171:3a7713b1edbc | 2890 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2891 | */ |
AnnaBridge | 171:3a7713b1edbc | 2892 | |
AnnaBridge | 171:3a7713b1edbc | 2893 | /** |
AnnaBridge | 171:3a7713b1edbc | 2894 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2895 | */ |
AnnaBridge | 171:3a7713b1edbc | 2896 | |
AnnaBridge | 171:3a7713b1edbc | 2897 | #endif /* DMA1 || DMA2 */ |
AnnaBridge | 171:3a7713b1edbc | 2898 | |
AnnaBridge | 171:3a7713b1edbc | 2899 | /** |
AnnaBridge | 171:3a7713b1edbc | 2900 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2901 | */ |
AnnaBridge | 171:3a7713b1edbc | 2902 | |
AnnaBridge | 171:3a7713b1edbc | 2903 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 2904 | } |
AnnaBridge | 171:3a7713b1edbc | 2905 | #endif |
AnnaBridge | 171:3a7713b1edbc | 2906 | |
AnnaBridge | 171:3a7713b1edbc | 2907 | #endif /* __STM32F7xx_LL_DMA_H */ |
AnnaBridge | 171:3a7713b1edbc | 2908 | |
AnnaBridge | 171:3a7713b1edbc | 2909 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |