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TARGET_DISCO_F429ZI/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dma.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 161:aa5281ff4a02 | 1 | /** |
AnnaBridge | 161:aa5281ff4a02 | 2 | ****************************************************************************** |
AnnaBridge | 161:aa5281ff4a02 | 3 | * @file stm32f4xx_hal_dma.h |
AnnaBridge | 161:aa5281ff4a02 | 4 | * @author MCD Application Team |
AnnaBridge | 161:aa5281ff4a02 | 5 | * @brief Header file of DMA HAL module. |
AnnaBridge | 161:aa5281ff4a02 | 6 | ****************************************************************************** |
AnnaBridge | 161:aa5281ff4a02 | 7 | * @attention |
AnnaBridge | 161:aa5281ff4a02 | 8 | * |
AnnaBridge | 161:aa5281ff4a02 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
AnnaBridge | 161:aa5281ff4a02 | 10 | * |
AnnaBridge | 161:aa5281ff4a02 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 161:aa5281ff4a02 | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 161:aa5281ff4a02 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 161:aa5281ff4a02 | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 161:aa5281ff4a02 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 161:aa5281ff4a02 | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 161:aa5281ff4a02 | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 161:aa5281ff4a02 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 161:aa5281ff4a02 | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 161:aa5281ff4a02 | 20 | * without specific prior written permission. |
AnnaBridge | 161:aa5281ff4a02 | 21 | * |
AnnaBridge | 161:aa5281ff4a02 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 161:aa5281ff4a02 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 161:aa5281ff4a02 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 161:aa5281ff4a02 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 161:aa5281ff4a02 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 161:aa5281ff4a02 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 161:aa5281ff4a02 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 161:aa5281ff4a02 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 161:aa5281ff4a02 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 161:aa5281ff4a02 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 161:aa5281ff4a02 | 32 | * |
AnnaBridge | 161:aa5281ff4a02 | 33 | ****************************************************************************** |
AnnaBridge | 161:aa5281ff4a02 | 34 | */ |
AnnaBridge | 161:aa5281ff4a02 | 35 | |
AnnaBridge | 161:aa5281ff4a02 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 37 | #ifndef __STM32F4xx_HAL_DMA_H |
AnnaBridge | 161:aa5281ff4a02 | 38 | #define __STM32F4xx_HAL_DMA_H |
AnnaBridge | 161:aa5281ff4a02 | 39 | |
AnnaBridge | 161:aa5281ff4a02 | 40 | #ifdef __cplusplus |
AnnaBridge | 161:aa5281ff4a02 | 41 | extern "C" { |
AnnaBridge | 161:aa5281ff4a02 | 42 | #endif |
AnnaBridge | 161:aa5281ff4a02 | 43 | |
AnnaBridge | 161:aa5281ff4a02 | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 45 | #include "stm32f4xx_hal_def.h" |
AnnaBridge | 161:aa5281ff4a02 | 46 | |
AnnaBridge | 161:aa5281ff4a02 | 47 | /** @addtogroup STM32F4xx_HAL_Driver |
AnnaBridge | 161:aa5281ff4a02 | 48 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 49 | */ |
AnnaBridge | 161:aa5281ff4a02 | 50 | |
AnnaBridge | 161:aa5281ff4a02 | 51 | /** @addtogroup DMA |
AnnaBridge | 161:aa5281ff4a02 | 52 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 53 | */ |
AnnaBridge | 161:aa5281ff4a02 | 54 | |
AnnaBridge | 161:aa5281ff4a02 | 55 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 56 | |
AnnaBridge | 161:aa5281ff4a02 | 57 | /** @defgroup DMA_Exported_Types DMA Exported Types |
AnnaBridge | 161:aa5281ff4a02 | 58 | * @brief DMA Exported Types |
AnnaBridge | 161:aa5281ff4a02 | 59 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 60 | */ |
AnnaBridge | 161:aa5281ff4a02 | 61 | |
AnnaBridge | 161:aa5281ff4a02 | 62 | /** |
AnnaBridge | 161:aa5281ff4a02 | 63 | * @brief DMA Configuration Structure definition |
AnnaBridge | 161:aa5281ff4a02 | 64 | */ |
AnnaBridge | 161:aa5281ff4a02 | 65 | typedef struct |
AnnaBridge | 161:aa5281ff4a02 | 66 | { |
AnnaBridge | 161:aa5281ff4a02 | 67 | uint32_t Channel; /*!< Specifies the channel used for the specified stream. |
AnnaBridge | 161:aa5281ff4a02 | 68 | This parameter can be a value of @ref DMA_Channel_selection */ |
AnnaBridge | 161:aa5281ff4a02 | 69 | |
AnnaBridge | 161:aa5281ff4a02 | 70 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
AnnaBridge | 161:aa5281ff4a02 | 71 | from memory to memory or from peripheral to memory. |
AnnaBridge | 161:aa5281ff4a02 | 72 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
AnnaBridge | 161:aa5281ff4a02 | 73 | |
AnnaBridge | 161:aa5281ff4a02 | 74 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
AnnaBridge | 161:aa5281ff4a02 | 75 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
AnnaBridge | 161:aa5281ff4a02 | 76 | |
AnnaBridge | 161:aa5281ff4a02 | 77 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
AnnaBridge | 161:aa5281ff4a02 | 78 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
AnnaBridge | 161:aa5281ff4a02 | 79 | |
AnnaBridge | 161:aa5281ff4a02 | 80 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
AnnaBridge | 161:aa5281ff4a02 | 81 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
AnnaBridge | 161:aa5281ff4a02 | 82 | |
AnnaBridge | 161:aa5281ff4a02 | 83 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
AnnaBridge | 161:aa5281ff4a02 | 84 | This parameter can be a value of @ref DMA_Memory_data_size */ |
AnnaBridge | 161:aa5281ff4a02 | 85 | |
AnnaBridge | 161:aa5281ff4a02 | 86 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. |
AnnaBridge | 161:aa5281ff4a02 | 87 | This parameter can be a value of @ref DMA_mode |
AnnaBridge | 161:aa5281ff4a02 | 88 | @note The circular buffer mode cannot be used if the memory-to-memory |
AnnaBridge | 161:aa5281ff4a02 | 89 | data transfer is configured on the selected Stream */ |
AnnaBridge | 161:aa5281ff4a02 | 90 | |
AnnaBridge | 161:aa5281ff4a02 | 91 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. |
AnnaBridge | 161:aa5281ff4a02 | 92 | This parameter can be a value of @ref DMA_Priority_level */ |
AnnaBridge | 161:aa5281ff4a02 | 93 | |
AnnaBridge | 161:aa5281ff4a02 | 94 | uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. |
AnnaBridge | 161:aa5281ff4a02 | 95 | This parameter can be a value of @ref DMA_FIFO_direct_mode |
AnnaBridge | 161:aa5281ff4a02 | 96 | @note The Direct mode (FIFO mode disabled) cannot be used if the |
AnnaBridge | 161:aa5281ff4a02 | 97 | memory-to-memory data transfer is configured on the selected stream */ |
AnnaBridge | 161:aa5281ff4a02 | 98 | |
AnnaBridge | 161:aa5281ff4a02 | 99 | uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. |
AnnaBridge | 161:aa5281ff4a02 | 100 | This parameter can be a value of @ref DMA_FIFO_threshold_level */ |
AnnaBridge | 161:aa5281ff4a02 | 101 | |
AnnaBridge | 161:aa5281ff4a02 | 102 | uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. |
AnnaBridge | 161:aa5281ff4a02 | 103 | It specifies the amount of data to be transferred in a single non interruptible |
AnnaBridge | 161:aa5281ff4a02 | 104 | transaction. |
AnnaBridge | 161:aa5281ff4a02 | 105 | This parameter can be a value of @ref DMA_Memory_burst |
AnnaBridge | 161:aa5281ff4a02 | 106 | @note The burst mode is possible only if the address Increment mode is enabled. */ |
AnnaBridge | 161:aa5281ff4a02 | 107 | |
AnnaBridge | 161:aa5281ff4a02 | 108 | uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. |
AnnaBridge | 161:aa5281ff4a02 | 109 | It specifies the amount of data to be transferred in a single non interruptible |
AnnaBridge | 161:aa5281ff4a02 | 110 | transaction. |
AnnaBridge | 161:aa5281ff4a02 | 111 | This parameter can be a value of @ref DMA_Peripheral_burst |
AnnaBridge | 161:aa5281ff4a02 | 112 | @note The burst mode is possible only if the address Increment mode is enabled. */ |
AnnaBridge | 161:aa5281ff4a02 | 113 | }DMA_InitTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 114 | |
AnnaBridge | 161:aa5281ff4a02 | 115 | |
AnnaBridge | 161:aa5281ff4a02 | 116 | /** |
AnnaBridge | 161:aa5281ff4a02 | 117 | * @brief HAL DMA State structures definition |
AnnaBridge | 161:aa5281ff4a02 | 118 | */ |
AnnaBridge | 161:aa5281ff4a02 | 119 | typedef enum |
AnnaBridge | 161:aa5281ff4a02 | 120 | { |
AnnaBridge | 161:aa5281ff4a02 | 121 | HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ |
AnnaBridge | 161:aa5281ff4a02 | 122 | HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ |
AnnaBridge | 161:aa5281ff4a02 | 123 | HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ |
AnnaBridge | 161:aa5281ff4a02 | 124 | HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ |
AnnaBridge | 161:aa5281ff4a02 | 125 | HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ |
AnnaBridge | 161:aa5281ff4a02 | 126 | HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ |
AnnaBridge | 161:aa5281ff4a02 | 127 | }HAL_DMA_StateTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 128 | |
AnnaBridge | 161:aa5281ff4a02 | 129 | /** |
AnnaBridge | 161:aa5281ff4a02 | 130 | * @brief HAL DMA Error Code structure definition |
AnnaBridge | 161:aa5281ff4a02 | 131 | */ |
AnnaBridge | 161:aa5281ff4a02 | 132 | typedef enum |
AnnaBridge | 161:aa5281ff4a02 | 133 | { |
AnnaBridge | 161:aa5281ff4a02 | 134 | HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ |
AnnaBridge | 161:aa5281ff4a02 | 135 | HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ |
AnnaBridge | 161:aa5281ff4a02 | 136 | }HAL_DMA_LevelCompleteTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 137 | |
AnnaBridge | 161:aa5281ff4a02 | 138 | /** |
AnnaBridge | 161:aa5281ff4a02 | 139 | * @brief HAL DMA Error Code structure definition |
AnnaBridge | 161:aa5281ff4a02 | 140 | */ |
AnnaBridge | 161:aa5281ff4a02 | 141 | typedef enum |
AnnaBridge | 161:aa5281ff4a02 | 142 | { |
AnnaBridge | 161:aa5281ff4a02 | 143 | HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ |
AnnaBridge | 161:aa5281ff4a02 | 144 | HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ |
AnnaBridge | 161:aa5281ff4a02 | 145 | HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ |
AnnaBridge | 161:aa5281ff4a02 | 146 | HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ |
AnnaBridge | 161:aa5281ff4a02 | 147 | HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ |
AnnaBridge | 161:aa5281ff4a02 | 148 | HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ |
AnnaBridge | 161:aa5281ff4a02 | 149 | HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ |
AnnaBridge | 161:aa5281ff4a02 | 150 | }HAL_DMA_CallbackIDTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 151 | |
AnnaBridge | 161:aa5281ff4a02 | 152 | /** |
AnnaBridge | 161:aa5281ff4a02 | 153 | * @brief DMA handle Structure definition |
AnnaBridge | 161:aa5281ff4a02 | 154 | */ |
AnnaBridge | 161:aa5281ff4a02 | 155 | typedef struct __DMA_HandleTypeDef |
AnnaBridge | 161:aa5281ff4a02 | 156 | { |
AnnaBridge | 161:aa5281ff4a02 | 157 | DMA_Stream_TypeDef *Instance; /*!< Register base address */ |
AnnaBridge | 161:aa5281ff4a02 | 158 | |
AnnaBridge | 161:aa5281ff4a02 | 159 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
AnnaBridge | 161:aa5281ff4a02 | 160 | |
AnnaBridge | 161:aa5281ff4a02 | 161 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
AnnaBridge | 161:aa5281ff4a02 | 162 | |
AnnaBridge | 161:aa5281ff4a02 | 163 | __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
AnnaBridge | 161:aa5281ff4a02 | 164 | |
AnnaBridge | 161:aa5281ff4a02 | 165 | void *Parent; /*!< Parent object state */ |
AnnaBridge | 161:aa5281ff4a02 | 166 | |
AnnaBridge | 161:aa5281ff4a02 | 167 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
AnnaBridge | 161:aa5281ff4a02 | 168 | |
AnnaBridge | 161:aa5281ff4a02 | 169 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
AnnaBridge | 161:aa5281ff4a02 | 170 | |
AnnaBridge | 161:aa5281ff4a02 | 171 | void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ |
AnnaBridge | 161:aa5281ff4a02 | 172 | |
AnnaBridge | 161:aa5281ff4a02 | 173 | void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ |
AnnaBridge | 161:aa5281ff4a02 | 174 | |
AnnaBridge | 161:aa5281ff4a02 | 175 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
AnnaBridge | 161:aa5281ff4a02 | 176 | |
AnnaBridge | 161:aa5281ff4a02 | 177 | void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ |
AnnaBridge | 161:aa5281ff4a02 | 178 | |
AnnaBridge | 161:aa5281ff4a02 | 179 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
AnnaBridge | 161:aa5281ff4a02 | 180 | |
AnnaBridge | 161:aa5281ff4a02 | 181 | uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ |
AnnaBridge | 161:aa5281ff4a02 | 182 | |
AnnaBridge | 161:aa5281ff4a02 | 183 | uint32_t StreamIndex; /*!< DMA Stream Index */ |
AnnaBridge | 161:aa5281ff4a02 | 184 | |
AnnaBridge | 161:aa5281ff4a02 | 185 | }DMA_HandleTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 186 | |
AnnaBridge | 161:aa5281ff4a02 | 187 | /** |
AnnaBridge | 161:aa5281ff4a02 | 188 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 189 | */ |
AnnaBridge | 161:aa5281ff4a02 | 190 | |
AnnaBridge | 161:aa5281ff4a02 | 191 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 192 | |
AnnaBridge | 161:aa5281ff4a02 | 193 | /** @defgroup DMA_Exported_Constants DMA Exported Constants |
AnnaBridge | 161:aa5281ff4a02 | 194 | * @brief DMA Exported constants |
AnnaBridge | 161:aa5281ff4a02 | 195 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 196 | */ |
AnnaBridge | 161:aa5281ff4a02 | 197 | |
AnnaBridge | 161:aa5281ff4a02 | 198 | /** @defgroup DMA_Error_Code DMA Error Code |
AnnaBridge | 161:aa5281ff4a02 | 199 | * @brief DMA Error Code |
AnnaBridge | 161:aa5281ff4a02 | 200 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 201 | */ |
AnnaBridge | 161:aa5281ff4a02 | 202 | #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ |
AnnaBridge | 161:aa5281ff4a02 | 203 | #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ |
AnnaBridge | 161:aa5281ff4a02 | 204 | #define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ |
AnnaBridge | 161:aa5281ff4a02 | 205 | #define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */ |
AnnaBridge | 161:aa5281ff4a02 | 206 | #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ |
AnnaBridge | 161:aa5281ff4a02 | 207 | #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ |
AnnaBridge | 161:aa5281ff4a02 | 208 | #define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */ |
AnnaBridge | 161:aa5281ff4a02 | 209 | #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ |
AnnaBridge | 161:aa5281ff4a02 | 210 | /** |
AnnaBridge | 161:aa5281ff4a02 | 211 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 212 | */ |
AnnaBridge | 161:aa5281ff4a02 | 213 | |
AnnaBridge | 161:aa5281ff4a02 | 214 | /** @defgroup DMA_Channel_selection DMA Channel selection |
AnnaBridge | 161:aa5281ff4a02 | 215 | * @brief DMA channel selection |
AnnaBridge | 161:aa5281ff4a02 | 216 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 217 | */ |
AnnaBridge | 161:aa5281ff4a02 | 218 | #define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ |
AnnaBridge | 161:aa5281ff4a02 | 219 | #define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */ |
AnnaBridge | 161:aa5281ff4a02 | 220 | #define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */ |
AnnaBridge | 161:aa5281ff4a02 | 221 | #define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */ |
AnnaBridge | 161:aa5281ff4a02 | 222 | #define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */ |
AnnaBridge | 161:aa5281ff4a02 | 223 | #define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */ |
AnnaBridge | 161:aa5281ff4a02 | 224 | #define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */ |
AnnaBridge | 161:aa5281ff4a02 | 225 | #define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ |
AnnaBridge | 161:aa5281ff4a02 | 226 | #if defined (DMA_SxCR_CHSEL_3) |
AnnaBridge | 161:aa5281ff4a02 | 227 | #define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ |
AnnaBridge | 161:aa5281ff4a02 | 228 | #define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ |
AnnaBridge | 161:aa5281ff4a02 | 229 | #define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */ |
AnnaBridge | 161:aa5281ff4a02 | 230 | #define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */ |
AnnaBridge | 161:aa5281ff4a02 | 231 | #define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */ |
AnnaBridge | 161:aa5281ff4a02 | 232 | #define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */ |
AnnaBridge | 161:aa5281ff4a02 | 233 | #define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */ |
AnnaBridge | 161:aa5281ff4a02 | 234 | #define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */ |
AnnaBridge | 161:aa5281ff4a02 | 235 | #endif /* DMA_SxCR_CHSEL_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 236 | /** |
AnnaBridge | 161:aa5281ff4a02 | 237 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 238 | */ |
AnnaBridge | 161:aa5281ff4a02 | 239 | |
AnnaBridge | 161:aa5281ff4a02 | 240 | /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction |
AnnaBridge | 161:aa5281ff4a02 | 241 | * @brief DMA data transfer direction |
AnnaBridge | 161:aa5281ff4a02 | 242 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 243 | */ |
AnnaBridge | 161:aa5281ff4a02 | 244 | #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ |
AnnaBridge | 161:aa5281ff4a02 | 245 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ |
AnnaBridge | 161:aa5281ff4a02 | 246 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ |
AnnaBridge | 161:aa5281ff4a02 | 247 | /** |
AnnaBridge | 161:aa5281ff4a02 | 248 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 249 | */ |
AnnaBridge | 161:aa5281ff4a02 | 250 | |
AnnaBridge | 161:aa5281ff4a02 | 251 | /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode |
AnnaBridge | 161:aa5281ff4a02 | 252 | * @brief DMA peripheral incremented mode |
AnnaBridge | 161:aa5281ff4a02 | 253 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 254 | */ |
AnnaBridge | 161:aa5281ff4a02 | 255 | #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ |
AnnaBridge | 161:aa5281ff4a02 | 256 | #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ |
AnnaBridge | 161:aa5281ff4a02 | 257 | /** |
AnnaBridge | 161:aa5281ff4a02 | 258 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 259 | */ |
AnnaBridge | 161:aa5281ff4a02 | 260 | |
AnnaBridge | 161:aa5281ff4a02 | 261 | /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode |
AnnaBridge | 161:aa5281ff4a02 | 262 | * @brief DMA memory incremented mode |
AnnaBridge | 161:aa5281ff4a02 | 263 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 264 | */ |
AnnaBridge | 161:aa5281ff4a02 | 265 | #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ |
AnnaBridge | 161:aa5281ff4a02 | 266 | #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ |
AnnaBridge | 161:aa5281ff4a02 | 267 | /** |
AnnaBridge | 161:aa5281ff4a02 | 268 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 269 | */ |
AnnaBridge | 161:aa5281ff4a02 | 270 | |
AnnaBridge | 161:aa5281ff4a02 | 271 | /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size |
AnnaBridge | 161:aa5281ff4a02 | 272 | * @brief DMA peripheral data size |
AnnaBridge | 161:aa5281ff4a02 | 273 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 274 | */ |
AnnaBridge | 161:aa5281ff4a02 | 275 | #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ |
AnnaBridge | 161:aa5281ff4a02 | 276 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ |
AnnaBridge | 161:aa5281ff4a02 | 277 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ |
AnnaBridge | 161:aa5281ff4a02 | 278 | /** |
AnnaBridge | 161:aa5281ff4a02 | 279 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 280 | */ |
AnnaBridge | 161:aa5281ff4a02 | 281 | |
AnnaBridge | 161:aa5281ff4a02 | 282 | /** @defgroup DMA_Memory_data_size DMA Memory data size |
AnnaBridge | 161:aa5281ff4a02 | 283 | * @brief DMA memory data size |
AnnaBridge | 161:aa5281ff4a02 | 284 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 285 | */ |
AnnaBridge | 161:aa5281ff4a02 | 286 | #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ |
AnnaBridge | 161:aa5281ff4a02 | 287 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ |
AnnaBridge | 161:aa5281ff4a02 | 288 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ |
AnnaBridge | 161:aa5281ff4a02 | 289 | /** |
AnnaBridge | 161:aa5281ff4a02 | 290 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 291 | */ |
AnnaBridge | 161:aa5281ff4a02 | 292 | |
AnnaBridge | 161:aa5281ff4a02 | 293 | /** @defgroup DMA_mode DMA mode |
AnnaBridge | 161:aa5281ff4a02 | 294 | * @brief DMA mode |
AnnaBridge | 161:aa5281ff4a02 | 295 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 296 | */ |
AnnaBridge | 161:aa5281ff4a02 | 297 | #define DMA_NORMAL 0x00000000U /*!< Normal mode */ |
AnnaBridge | 161:aa5281ff4a02 | 298 | #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ |
AnnaBridge | 161:aa5281ff4a02 | 299 | #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ |
AnnaBridge | 161:aa5281ff4a02 | 300 | /** |
AnnaBridge | 161:aa5281ff4a02 | 301 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 302 | */ |
AnnaBridge | 161:aa5281ff4a02 | 303 | |
AnnaBridge | 161:aa5281ff4a02 | 304 | /** @defgroup DMA_Priority_level DMA Priority level |
AnnaBridge | 161:aa5281ff4a02 | 305 | * @brief DMA priority levels |
AnnaBridge | 161:aa5281ff4a02 | 306 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 307 | */ |
AnnaBridge | 161:aa5281ff4a02 | 308 | #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ |
AnnaBridge | 161:aa5281ff4a02 | 309 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ |
AnnaBridge | 161:aa5281ff4a02 | 310 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ |
AnnaBridge | 161:aa5281ff4a02 | 311 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ |
AnnaBridge | 161:aa5281ff4a02 | 312 | /** |
AnnaBridge | 161:aa5281ff4a02 | 313 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 314 | */ |
AnnaBridge | 161:aa5281ff4a02 | 315 | |
AnnaBridge | 161:aa5281ff4a02 | 316 | /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode |
AnnaBridge | 161:aa5281ff4a02 | 317 | * @brief DMA FIFO direct mode |
AnnaBridge | 161:aa5281ff4a02 | 318 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 319 | */ |
AnnaBridge | 161:aa5281ff4a02 | 320 | #define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ |
AnnaBridge | 161:aa5281ff4a02 | 321 | #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ |
AnnaBridge | 161:aa5281ff4a02 | 322 | /** |
AnnaBridge | 161:aa5281ff4a02 | 323 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 324 | */ |
AnnaBridge | 161:aa5281ff4a02 | 325 | |
AnnaBridge | 161:aa5281ff4a02 | 326 | /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level |
AnnaBridge | 161:aa5281ff4a02 | 327 | * @brief DMA FIFO level |
AnnaBridge | 161:aa5281ff4a02 | 328 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 329 | */ |
AnnaBridge | 161:aa5281ff4a02 | 330 | #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ |
AnnaBridge | 161:aa5281ff4a02 | 331 | #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ |
AnnaBridge | 161:aa5281ff4a02 | 332 | #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ |
AnnaBridge | 161:aa5281ff4a02 | 333 | #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ |
AnnaBridge | 161:aa5281ff4a02 | 334 | /** |
AnnaBridge | 161:aa5281ff4a02 | 335 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 336 | */ |
AnnaBridge | 161:aa5281ff4a02 | 337 | |
AnnaBridge | 161:aa5281ff4a02 | 338 | /** @defgroup DMA_Memory_burst DMA Memory burst |
AnnaBridge | 161:aa5281ff4a02 | 339 | * @brief DMA memory burst |
AnnaBridge | 161:aa5281ff4a02 | 340 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 341 | */ |
AnnaBridge | 161:aa5281ff4a02 | 342 | #define DMA_MBURST_SINGLE 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 343 | #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) |
AnnaBridge | 161:aa5281ff4a02 | 344 | #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) |
AnnaBridge | 161:aa5281ff4a02 | 345 | #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) |
AnnaBridge | 161:aa5281ff4a02 | 346 | /** |
AnnaBridge | 161:aa5281ff4a02 | 347 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 348 | */ |
AnnaBridge | 161:aa5281ff4a02 | 349 | |
AnnaBridge | 161:aa5281ff4a02 | 350 | /** @defgroup DMA_Peripheral_burst DMA Peripheral burst |
AnnaBridge | 161:aa5281ff4a02 | 351 | * @brief DMA peripheral burst |
AnnaBridge | 161:aa5281ff4a02 | 352 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 353 | */ |
AnnaBridge | 161:aa5281ff4a02 | 354 | #define DMA_PBURST_SINGLE 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 355 | #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) |
AnnaBridge | 161:aa5281ff4a02 | 356 | #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) |
AnnaBridge | 161:aa5281ff4a02 | 357 | #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) |
AnnaBridge | 161:aa5281ff4a02 | 358 | /** |
AnnaBridge | 161:aa5281ff4a02 | 359 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 360 | */ |
AnnaBridge | 161:aa5281ff4a02 | 361 | |
AnnaBridge | 161:aa5281ff4a02 | 362 | /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions |
AnnaBridge | 161:aa5281ff4a02 | 363 | * @brief DMA interrupts definition |
AnnaBridge | 161:aa5281ff4a02 | 364 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 365 | */ |
AnnaBridge | 161:aa5281ff4a02 | 366 | #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) |
AnnaBridge | 161:aa5281ff4a02 | 367 | #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) |
AnnaBridge | 161:aa5281ff4a02 | 368 | #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) |
AnnaBridge | 161:aa5281ff4a02 | 369 | #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) |
AnnaBridge | 161:aa5281ff4a02 | 370 | #define DMA_IT_FE 0x00000080U |
AnnaBridge | 161:aa5281ff4a02 | 371 | /** |
AnnaBridge | 161:aa5281ff4a02 | 372 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 373 | */ |
AnnaBridge | 161:aa5281ff4a02 | 374 | |
AnnaBridge | 161:aa5281ff4a02 | 375 | /** @defgroup DMA_flag_definitions DMA flag definitions |
AnnaBridge | 161:aa5281ff4a02 | 376 | * @brief DMA flag definitions |
AnnaBridge | 161:aa5281ff4a02 | 377 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 378 | */ |
AnnaBridge | 163:e59c8e839560 | 379 | #define DMA_FLAG_FEIF0_4 0x00000001U |
AnnaBridge | 163:e59c8e839560 | 380 | #define DMA_FLAG_DMEIF0_4 0x00000004U |
AnnaBridge | 161:aa5281ff4a02 | 381 | #define DMA_FLAG_TEIF0_4 0x00000008U |
AnnaBridge | 161:aa5281ff4a02 | 382 | #define DMA_FLAG_HTIF0_4 0x00000010U |
AnnaBridge | 161:aa5281ff4a02 | 383 | #define DMA_FLAG_TCIF0_4 0x00000020U |
AnnaBridge | 161:aa5281ff4a02 | 384 | #define DMA_FLAG_FEIF1_5 0x00000040U |
AnnaBridge | 161:aa5281ff4a02 | 385 | #define DMA_FLAG_DMEIF1_5 0x00000100U |
AnnaBridge | 161:aa5281ff4a02 | 386 | #define DMA_FLAG_TEIF1_5 0x00000200U |
AnnaBridge | 161:aa5281ff4a02 | 387 | #define DMA_FLAG_HTIF1_5 0x00000400U |
AnnaBridge | 161:aa5281ff4a02 | 388 | #define DMA_FLAG_TCIF1_5 0x00000800U |
AnnaBridge | 161:aa5281ff4a02 | 389 | #define DMA_FLAG_FEIF2_6 0x00010000U |
AnnaBridge | 161:aa5281ff4a02 | 390 | #define DMA_FLAG_DMEIF2_6 0x00040000U |
AnnaBridge | 161:aa5281ff4a02 | 391 | #define DMA_FLAG_TEIF2_6 0x00080000U |
AnnaBridge | 161:aa5281ff4a02 | 392 | #define DMA_FLAG_HTIF2_6 0x00100000U |
AnnaBridge | 161:aa5281ff4a02 | 393 | #define DMA_FLAG_TCIF2_6 0x00200000U |
AnnaBridge | 161:aa5281ff4a02 | 394 | #define DMA_FLAG_FEIF3_7 0x00400000U |
AnnaBridge | 161:aa5281ff4a02 | 395 | #define DMA_FLAG_DMEIF3_7 0x01000000U |
AnnaBridge | 161:aa5281ff4a02 | 396 | #define DMA_FLAG_TEIF3_7 0x02000000U |
AnnaBridge | 161:aa5281ff4a02 | 397 | #define DMA_FLAG_HTIF3_7 0x04000000U |
AnnaBridge | 161:aa5281ff4a02 | 398 | #define DMA_FLAG_TCIF3_7 0x08000000U |
AnnaBridge | 161:aa5281ff4a02 | 399 | /** |
AnnaBridge | 161:aa5281ff4a02 | 400 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 401 | */ |
AnnaBridge | 161:aa5281ff4a02 | 402 | |
AnnaBridge | 161:aa5281ff4a02 | 403 | /** |
AnnaBridge | 161:aa5281ff4a02 | 404 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 405 | */ |
AnnaBridge | 161:aa5281ff4a02 | 406 | |
AnnaBridge | 161:aa5281ff4a02 | 407 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 408 | |
AnnaBridge | 161:aa5281ff4a02 | 409 | /** @brief Reset DMA handle state |
AnnaBridge | 163:e59c8e839560 | 410 | * @param __HANDLE__ specifies the DMA handle. |
AnnaBridge | 161:aa5281ff4a02 | 411 | * @retval None |
AnnaBridge | 161:aa5281ff4a02 | 412 | */ |
AnnaBridge | 161:aa5281ff4a02 | 413 | #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
AnnaBridge | 161:aa5281ff4a02 | 414 | |
AnnaBridge | 161:aa5281ff4a02 | 415 | /** |
AnnaBridge | 161:aa5281ff4a02 | 416 | * @brief Return the current DMA Stream FIFO filled level. |
AnnaBridge | 163:e59c8e839560 | 417 | * @param __HANDLE__ DMA handle |
AnnaBridge | 161:aa5281ff4a02 | 418 | * @retval The FIFO filling state. |
AnnaBridge | 161:aa5281ff4a02 | 419 | * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full |
AnnaBridge | 161:aa5281ff4a02 | 420 | * and not empty. |
AnnaBridge | 161:aa5281ff4a02 | 421 | * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. |
AnnaBridge | 161:aa5281ff4a02 | 422 | * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. |
AnnaBridge | 161:aa5281ff4a02 | 423 | * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. |
AnnaBridge | 161:aa5281ff4a02 | 424 | * - DMA_FIFOStatus_Empty: when FIFO is empty |
AnnaBridge | 161:aa5281ff4a02 | 425 | * - DMA_FIFOStatus_Full: when FIFO is full |
AnnaBridge | 161:aa5281ff4a02 | 426 | */ |
AnnaBridge | 161:aa5281ff4a02 | 427 | #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) |
AnnaBridge | 161:aa5281ff4a02 | 428 | |
AnnaBridge | 161:aa5281ff4a02 | 429 | /** |
AnnaBridge | 161:aa5281ff4a02 | 430 | * @brief Enable the specified DMA Stream. |
AnnaBridge | 163:e59c8e839560 | 431 | * @param __HANDLE__ DMA handle |
AnnaBridge | 161:aa5281ff4a02 | 432 | * @retval None |
AnnaBridge | 161:aa5281ff4a02 | 433 | */ |
AnnaBridge | 161:aa5281ff4a02 | 434 | #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) |
AnnaBridge | 161:aa5281ff4a02 | 435 | |
AnnaBridge | 161:aa5281ff4a02 | 436 | /** |
AnnaBridge | 161:aa5281ff4a02 | 437 | * @brief Disable the specified DMA Stream. |
AnnaBridge | 163:e59c8e839560 | 438 | * @param __HANDLE__ DMA handle |
AnnaBridge | 161:aa5281ff4a02 | 439 | * @retval None |
AnnaBridge | 161:aa5281ff4a02 | 440 | */ |
AnnaBridge | 161:aa5281ff4a02 | 441 | #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) |
AnnaBridge | 161:aa5281ff4a02 | 442 | |
AnnaBridge | 161:aa5281ff4a02 | 443 | /* Interrupt & Flag management */ |
AnnaBridge | 161:aa5281ff4a02 | 444 | |
AnnaBridge | 161:aa5281ff4a02 | 445 | /** |
AnnaBridge | 161:aa5281ff4a02 | 446 | * @brief Return the current DMA Stream transfer complete flag. |
AnnaBridge | 163:e59c8e839560 | 447 | * @param __HANDLE__ DMA handle |
AnnaBridge | 161:aa5281ff4a02 | 448 | * @retval The specified transfer complete flag index. |
AnnaBridge | 161:aa5281ff4a02 | 449 | */ |
AnnaBridge | 161:aa5281ff4a02 | 450 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
AnnaBridge | 161:aa5281ff4a02 | 451 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 452 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 453 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 454 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 455 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 456 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 457 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 458 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 459 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 460 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 461 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 462 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 463 | DMA_FLAG_TCIF3_7) |
AnnaBridge | 161:aa5281ff4a02 | 464 | |
AnnaBridge | 161:aa5281ff4a02 | 465 | /** |
AnnaBridge | 161:aa5281ff4a02 | 466 | * @brief Return the current DMA Stream half transfer complete flag. |
AnnaBridge | 163:e59c8e839560 | 467 | * @param __HANDLE__ DMA handle |
AnnaBridge | 161:aa5281ff4a02 | 468 | * @retval The specified half transfer complete flag index. |
AnnaBridge | 161:aa5281ff4a02 | 469 | */ |
AnnaBridge | 161:aa5281ff4a02 | 470 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 161:aa5281ff4a02 | 471 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 472 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 473 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 474 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 475 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 476 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 477 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 478 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 479 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 480 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 481 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 482 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 483 | DMA_FLAG_HTIF3_7) |
AnnaBridge | 161:aa5281ff4a02 | 484 | |
AnnaBridge | 161:aa5281ff4a02 | 485 | /** |
AnnaBridge | 161:aa5281ff4a02 | 486 | * @brief Return the current DMA Stream transfer error flag. |
AnnaBridge | 163:e59c8e839560 | 487 | * @param __HANDLE__ DMA handle |
AnnaBridge | 161:aa5281ff4a02 | 488 | * @retval The specified transfer error flag index. |
AnnaBridge | 161:aa5281ff4a02 | 489 | */ |
AnnaBridge | 161:aa5281ff4a02 | 490 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 161:aa5281ff4a02 | 491 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 492 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 493 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 494 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 495 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 496 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 497 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 498 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 499 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 500 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 501 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 502 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 503 | DMA_FLAG_TEIF3_7) |
AnnaBridge | 161:aa5281ff4a02 | 504 | |
AnnaBridge | 161:aa5281ff4a02 | 505 | /** |
AnnaBridge | 161:aa5281ff4a02 | 506 | * @brief Return the current DMA Stream FIFO error flag. |
AnnaBridge | 163:e59c8e839560 | 507 | * @param __HANDLE__ DMA handle |
AnnaBridge | 161:aa5281ff4a02 | 508 | * @retval The specified FIFO error flag index. |
AnnaBridge | 161:aa5281ff4a02 | 509 | */ |
AnnaBridge | 161:aa5281ff4a02 | 510 | #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 161:aa5281ff4a02 | 511 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 512 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 513 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 514 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 515 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 516 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 517 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 518 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 519 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 520 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 521 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 522 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 523 | DMA_FLAG_FEIF3_7) |
AnnaBridge | 161:aa5281ff4a02 | 524 | |
AnnaBridge | 161:aa5281ff4a02 | 525 | /** |
AnnaBridge | 161:aa5281ff4a02 | 526 | * @brief Return the current DMA Stream direct mode error flag. |
AnnaBridge | 163:e59c8e839560 | 527 | * @param __HANDLE__ DMA handle |
AnnaBridge | 161:aa5281ff4a02 | 528 | * @retval The specified direct mode error flag index. |
AnnaBridge | 161:aa5281ff4a02 | 529 | */ |
AnnaBridge | 161:aa5281ff4a02 | 530 | #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 161:aa5281ff4a02 | 531 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 532 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 533 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 534 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ |
AnnaBridge | 161:aa5281ff4a02 | 535 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 536 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 537 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 538 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ |
AnnaBridge | 161:aa5281ff4a02 | 539 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 540 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 541 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 542 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ |
AnnaBridge | 161:aa5281ff4a02 | 543 | DMA_FLAG_DMEIF3_7) |
AnnaBridge | 161:aa5281ff4a02 | 544 | |
AnnaBridge | 161:aa5281ff4a02 | 545 | /** |
AnnaBridge | 161:aa5281ff4a02 | 546 | * @brief Get the DMA Stream pending flags. |
AnnaBridge | 163:e59c8e839560 | 547 | * @param __HANDLE__ DMA handle |
AnnaBridge | 163:e59c8e839560 | 548 | * @param __FLAG__ Get the specified flag. |
AnnaBridge | 161:aa5281ff4a02 | 549 | * This parameter can be any combination of the following values: |
AnnaBridge | 161:aa5281ff4a02 | 550 | * @arg DMA_FLAG_TCIFx: Transfer complete flag. |
AnnaBridge | 161:aa5281ff4a02 | 551 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag. |
AnnaBridge | 161:aa5281ff4a02 | 552 | * @arg DMA_FLAG_TEIFx: Transfer error flag. |
AnnaBridge | 161:aa5281ff4a02 | 553 | * @arg DMA_FLAG_DMEIFx: Direct mode error flag. |
AnnaBridge | 161:aa5281ff4a02 | 554 | * @arg DMA_FLAG_FEIFx: FIFO error flag. |
AnnaBridge | 161:aa5281ff4a02 | 555 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. |
AnnaBridge | 161:aa5281ff4a02 | 556 | * @retval The state of FLAG (SET or RESET). |
AnnaBridge | 161:aa5281ff4a02 | 557 | */ |
AnnaBridge | 161:aa5281ff4a02 | 558 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ |
AnnaBridge | 161:aa5281ff4a02 | 559 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ |
AnnaBridge | 161:aa5281ff4a02 | 560 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ |
AnnaBridge | 161:aa5281ff4a02 | 561 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) |
AnnaBridge | 161:aa5281ff4a02 | 562 | |
AnnaBridge | 161:aa5281ff4a02 | 563 | /** |
AnnaBridge | 161:aa5281ff4a02 | 564 | * @brief Clear the DMA Stream pending flags. |
AnnaBridge | 163:e59c8e839560 | 565 | * @param __HANDLE__ DMA handle |
AnnaBridge | 163:e59c8e839560 | 566 | * @param __FLAG__ specifies the flag to clear. |
AnnaBridge | 161:aa5281ff4a02 | 567 | * This parameter can be any combination of the following values: |
AnnaBridge | 161:aa5281ff4a02 | 568 | * @arg DMA_FLAG_TCIFx: Transfer complete flag. |
AnnaBridge | 161:aa5281ff4a02 | 569 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag. |
AnnaBridge | 161:aa5281ff4a02 | 570 | * @arg DMA_FLAG_TEIFx: Transfer error flag. |
AnnaBridge | 161:aa5281ff4a02 | 571 | * @arg DMA_FLAG_DMEIFx: Direct mode error flag. |
AnnaBridge | 161:aa5281ff4a02 | 572 | * @arg DMA_FLAG_FEIFx: FIFO error flag. |
AnnaBridge | 161:aa5281ff4a02 | 573 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. |
AnnaBridge | 161:aa5281ff4a02 | 574 | * @retval None |
AnnaBridge | 161:aa5281ff4a02 | 575 | */ |
AnnaBridge | 161:aa5281ff4a02 | 576 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
AnnaBridge | 161:aa5281ff4a02 | 577 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ |
AnnaBridge | 161:aa5281ff4a02 | 578 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ |
AnnaBridge | 161:aa5281ff4a02 | 579 | ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) |
AnnaBridge | 161:aa5281ff4a02 | 580 | |
AnnaBridge | 161:aa5281ff4a02 | 581 | /** |
AnnaBridge | 161:aa5281ff4a02 | 582 | * @brief Enable the specified DMA Stream interrupts. |
AnnaBridge | 163:e59c8e839560 | 583 | * @param __HANDLE__ DMA handle |
AnnaBridge | 163:e59c8e839560 | 584 | * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. |
AnnaBridge | 161:aa5281ff4a02 | 585 | * This parameter can be any combination of the following values: |
AnnaBridge | 161:aa5281ff4a02 | 586 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
AnnaBridge | 161:aa5281ff4a02 | 587 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
AnnaBridge | 161:aa5281ff4a02 | 588 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
AnnaBridge | 161:aa5281ff4a02 | 589 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
AnnaBridge | 161:aa5281ff4a02 | 590 | * @arg DMA_IT_DME: Direct mode error interrupt. |
AnnaBridge | 161:aa5281ff4a02 | 591 | * @retval None |
AnnaBridge | 161:aa5281ff4a02 | 592 | */ |
AnnaBridge | 161:aa5281ff4a02 | 593 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
AnnaBridge | 161:aa5281ff4a02 | 594 | ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) |
AnnaBridge | 161:aa5281ff4a02 | 595 | |
AnnaBridge | 161:aa5281ff4a02 | 596 | /** |
AnnaBridge | 161:aa5281ff4a02 | 597 | * @brief Disable the specified DMA Stream interrupts. |
AnnaBridge | 163:e59c8e839560 | 598 | * @param __HANDLE__ DMA handle |
AnnaBridge | 163:e59c8e839560 | 599 | * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. |
AnnaBridge | 161:aa5281ff4a02 | 600 | * This parameter can be any combination of the following values: |
AnnaBridge | 161:aa5281ff4a02 | 601 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
AnnaBridge | 161:aa5281ff4a02 | 602 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
AnnaBridge | 161:aa5281ff4a02 | 603 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
AnnaBridge | 161:aa5281ff4a02 | 604 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
AnnaBridge | 161:aa5281ff4a02 | 605 | * @arg DMA_IT_DME: Direct mode error interrupt. |
AnnaBridge | 161:aa5281ff4a02 | 606 | * @retval None |
AnnaBridge | 161:aa5281ff4a02 | 607 | */ |
AnnaBridge | 161:aa5281ff4a02 | 608 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
AnnaBridge | 161:aa5281ff4a02 | 609 | ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) |
AnnaBridge | 161:aa5281ff4a02 | 610 | |
AnnaBridge | 161:aa5281ff4a02 | 611 | /** |
AnnaBridge | 161:aa5281ff4a02 | 612 | * @brief Check whether the specified DMA Stream interrupt is enabled or disabled. |
AnnaBridge | 163:e59c8e839560 | 613 | * @param __HANDLE__ DMA handle |
AnnaBridge | 163:e59c8e839560 | 614 | * @param __INTERRUPT__ specifies the DMA interrupt source to check. |
AnnaBridge | 161:aa5281ff4a02 | 615 | * This parameter can be one of the following values: |
AnnaBridge | 161:aa5281ff4a02 | 616 | * @arg DMA_IT_TC: Transfer complete interrupt mask. |
AnnaBridge | 161:aa5281ff4a02 | 617 | * @arg DMA_IT_HT: Half transfer complete interrupt mask. |
AnnaBridge | 161:aa5281ff4a02 | 618 | * @arg DMA_IT_TE: Transfer error interrupt mask. |
AnnaBridge | 161:aa5281ff4a02 | 619 | * @arg DMA_IT_FE: FIFO error interrupt mask. |
AnnaBridge | 161:aa5281ff4a02 | 620 | * @arg DMA_IT_DME: Direct mode error interrupt. |
AnnaBridge | 161:aa5281ff4a02 | 621 | * @retval The state of DMA_IT. |
AnnaBridge | 161:aa5281ff4a02 | 622 | */ |
AnnaBridge | 161:aa5281ff4a02 | 623 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ |
AnnaBridge | 161:aa5281ff4a02 | 624 | ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ |
AnnaBridge | 161:aa5281ff4a02 | 625 | ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) |
AnnaBridge | 161:aa5281ff4a02 | 626 | |
AnnaBridge | 161:aa5281ff4a02 | 627 | /** |
AnnaBridge | 161:aa5281ff4a02 | 628 | * @brief Writes the number of data units to be transferred on the DMA Stream. |
AnnaBridge | 163:e59c8e839560 | 629 | * @param __HANDLE__ DMA handle |
AnnaBridge | 163:e59c8e839560 | 630 | * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) |
AnnaBridge | 161:aa5281ff4a02 | 631 | * Number of data items depends only on the Peripheral data format. |
AnnaBridge | 161:aa5281ff4a02 | 632 | * |
AnnaBridge | 161:aa5281ff4a02 | 633 | * @note If Peripheral data format is Bytes: number of data units is equal |
AnnaBridge | 161:aa5281ff4a02 | 634 | * to total number of bytes to be transferred. |
AnnaBridge | 161:aa5281ff4a02 | 635 | * |
AnnaBridge | 161:aa5281ff4a02 | 636 | * @note If Peripheral data format is Half-Word: number of data units is |
AnnaBridge | 161:aa5281ff4a02 | 637 | * equal to total number of bytes to be transferred / 2. |
AnnaBridge | 161:aa5281ff4a02 | 638 | * |
AnnaBridge | 161:aa5281ff4a02 | 639 | * @note If Peripheral data format is Word: number of data units is equal |
AnnaBridge | 161:aa5281ff4a02 | 640 | * to total number of bytes to be transferred / 4. |
AnnaBridge | 161:aa5281ff4a02 | 641 | * |
AnnaBridge | 161:aa5281ff4a02 | 642 | * @retval The number of remaining data units in the current DMAy Streamx transfer. |
AnnaBridge | 161:aa5281ff4a02 | 643 | */ |
AnnaBridge | 161:aa5281ff4a02 | 644 | #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) |
AnnaBridge | 161:aa5281ff4a02 | 645 | |
AnnaBridge | 161:aa5281ff4a02 | 646 | /** |
AnnaBridge | 161:aa5281ff4a02 | 647 | * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. |
AnnaBridge | 163:e59c8e839560 | 648 | * @param __HANDLE__ DMA handle |
AnnaBridge | 161:aa5281ff4a02 | 649 | * |
AnnaBridge | 161:aa5281ff4a02 | 650 | * @retval The number of remaining data units in the current DMA Stream transfer. |
AnnaBridge | 161:aa5281ff4a02 | 651 | */ |
AnnaBridge | 161:aa5281ff4a02 | 652 | #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) |
AnnaBridge | 161:aa5281ff4a02 | 653 | |
AnnaBridge | 161:aa5281ff4a02 | 654 | |
AnnaBridge | 161:aa5281ff4a02 | 655 | /* Include DMA HAL Extension module */ |
AnnaBridge | 161:aa5281ff4a02 | 656 | #include "stm32f4xx_hal_dma_ex.h" |
AnnaBridge | 161:aa5281ff4a02 | 657 | |
AnnaBridge | 161:aa5281ff4a02 | 658 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 659 | |
AnnaBridge | 161:aa5281ff4a02 | 660 | /** @defgroup DMA_Exported_Functions DMA Exported Functions |
AnnaBridge | 161:aa5281ff4a02 | 661 | * @brief DMA Exported functions |
AnnaBridge | 161:aa5281ff4a02 | 662 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 663 | */ |
AnnaBridge | 161:aa5281ff4a02 | 664 | |
AnnaBridge | 161:aa5281ff4a02 | 665 | /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions |
AnnaBridge | 161:aa5281ff4a02 | 666 | * @brief Initialization and de-initialization functions |
AnnaBridge | 161:aa5281ff4a02 | 667 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 668 | */ |
AnnaBridge | 161:aa5281ff4a02 | 669 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
AnnaBridge | 161:aa5281ff4a02 | 670 | HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); |
AnnaBridge | 161:aa5281ff4a02 | 671 | /** |
AnnaBridge | 161:aa5281ff4a02 | 672 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 673 | */ |
AnnaBridge | 161:aa5281ff4a02 | 674 | |
AnnaBridge | 161:aa5281ff4a02 | 675 | /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions |
AnnaBridge | 161:aa5281ff4a02 | 676 | * @brief I/O operation functions |
AnnaBridge | 161:aa5281ff4a02 | 677 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 678 | */ |
AnnaBridge | 161:aa5281ff4a02 | 679 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
AnnaBridge | 161:aa5281ff4a02 | 680 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
AnnaBridge | 161:aa5281ff4a02 | 681 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
AnnaBridge | 161:aa5281ff4a02 | 682 | HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); |
AnnaBridge | 161:aa5281ff4a02 | 683 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); |
AnnaBridge | 161:aa5281ff4a02 | 684 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
AnnaBridge | 161:aa5281ff4a02 | 685 | HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma); |
AnnaBridge | 161:aa5281ff4a02 | 686 | HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); |
AnnaBridge | 161:aa5281ff4a02 | 687 | HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); |
AnnaBridge | 161:aa5281ff4a02 | 688 | |
AnnaBridge | 161:aa5281ff4a02 | 689 | /** |
AnnaBridge | 161:aa5281ff4a02 | 690 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 691 | */ |
AnnaBridge | 161:aa5281ff4a02 | 692 | |
AnnaBridge | 161:aa5281ff4a02 | 693 | /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions |
AnnaBridge | 161:aa5281ff4a02 | 694 | * @brief Peripheral State functions |
AnnaBridge | 161:aa5281ff4a02 | 695 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 696 | */ |
AnnaBridge | 161:aa5281ff4a02 | 697 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
AnnaBridge | 161:aa5281ff4a02 | 698 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
AnnaBridge | 161:aa5281ff4a02 | 699 | /** |
AnnaBridge | 161:aa5281ff4a02 | 700 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 701 | */ |
AnnaBridge | 161:aa5281ff4a02 | 702 | /** |
AnnaBridge | 161:aa5281ff4a02 | 703 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 704 | */ |
AnnaBridge | 161:aa5281ff4a02 | 705 | /* Private Constants -------------------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 706 | /** @defgroup DMA_Private_Constants DMA Private Constants |
AnnaBridge | 161:aa5281ff4a02 | 707 | * @brief DMA private defines and constants |
AnnaBridge | 161:aa5281ff4a02 | 708 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 709 | */ |
AnnaBridge | 161:aa5281ff4a02 | 710 | /** |
AnnaBridge | 161:aa5281ff4a02 | 711 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 712 | */ |
AnnaBridge | 161:aa5281ff4a02 | 713 | |
AnnaBridge | 161:aa5281ff4a02 | 714 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 715 | /** @defgroup DMA_Private_Macros DMA Private Macros |
AnnaBridge | 161:aa5281ff4a02 | 716 | * @brief DMA private macros |
AnnaBridge | 161:aa5281ff4a02 | 717 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 718 | */ |
AnnaBridge | 161:aa5281ff4a02 | 719 | #if defined (DMA_SxCR_CHSEL_3) |
AnnaBridge | 161:aa5281ff4a02 | 720 | #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ |
AnnaBridge | 161:aa5281ff4a02 | 721 | ((CHANNEL) == DMA_CHANNEL_1) || \ |
AnnaBridge | 161:aa5281ff4a02 | 722 | ((CHANNEL) == DMA_CHANNEL_2) || \ |
AnnaBridge | 161:aa5281ff4a02 | 723 | ((CHANNEL) == DMA_CHANNEL_3) || \ |
AnnaBridge | 161:aa5281ff4a02 | 724 | ((CHANNEL) == DMA_CHANNEL_4) || \ |
AnnaBridge | 161:aa5281ff4a02 | 725 | ((CHANNEL) == DMA_CHANNEL_5) || \ |
AnnaBridge | 161:aa5281ff4a02 | 726 | ((CHANNEL) == DMA_CHANNEL_6) || \ |
AnnaBridge | 161:aa5281ff4a02 | 727 | ((CHANNEL) == DMA_CHANNEL_7) || \ |
AnnaBridge | 161:aa5281ff4a02 | 728 | ((CHANNEL) == DMA_CHANNEL_8) || \ |
AnnaBridge | 161:aa5281ff4a02 | 729 | ((CHANNEL) == DMA_CHANNEL_9) || \ |
AnnaBridge | 161:aa5281ff4a02 | 730 | ((CHANNEL) == DMA_CHANNEL_10)|| \ |
AnnaBridge | 161:aa5281ff4a02 | 731 | ((CHANNEL) == DMA_CHANNEL_11)|| \ |
AnnaBridge | 161:aa5281ff4a02 | 732 | ((CHANNEL) == DMA_CHANNEL_12)|| \ |
AnnaBridge | 161:aa5281ff4a02 | 733 | ((CHANNEL) == DMA_CHANNEL_13)|| \ |
AnnaBridge | 161:aa5281ff4a02 | 734 | ((CHANNEL) == DMA_CHANNEL_14)|| \ |
AnnaBridge | 161:aa5281ff4a02 | 735 | ((CHANNEL) == DMA_CHANNEL_15)) |
AnnaBridge | 161:aa5281ff4a02 | 736 | #else |
AnnaBridge | 161:aa5281ff4a02 | 737 | #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ |
AnnaBridge | 161:aa5281ff4a02 | 738 | ((CHANNEL) == DMA_CHANNEL_1) || \ |
AnnaBridge | 161:aa5281ff4a02 | 739 | ((CHANNEL) == DMA_CHANNEL_2) || \ |
AnnaBridge | 161:aa5281ff4a02 | 740 | ((CHANNEL) == DMA_CHANNEL_3) || \ |
AnnaBridge | 161:aa5281ff4a02 | 741 | ((CHANNEL) == DMA_CHANNEL_4) || \ |
AnnaBridge | 161:aa5281ff4a02 | 742 | ((CHANNEL) == DMA_CHANNEL_5) || \ |
AnnaBridge | 161:aa5281ff4a02 | 743 | ((CHANNEL) == DMA_CHANNEL_6) || \ |
AnnaBridge | 161:aa5281ff4a02 | 744 | ((CHANNEL) == DMA_CHANNEL_7)) |
AnnaBridge | 161:aa5281ff4a02 | 745 | #endif /* DMA_SxCR_CHSEL_3 */ |
AnnaBridge | 161:aa5281ff4a02 | 746 | |
AnnaBridge | 161:aa5281ff4a02 | 747 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
AnnaBridge | 161:aa5281ff4a02 | 748 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
AnnaBridge | 161:aa5281ff4a02 | 749 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
AnnaBridge | 161:aa5281ff4a02 | 750 | |
AnnaBridge | 161:aa5281ff4a02 | 751 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) |
AnnaBridge | 161:aa5281ff4a02 | 752 | |
AnnaBridge | 161:aa5281ff4a02 | 753 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
AnnaBridge | 161:aa5281ff4a02 | 754 | ((STATE) == DMA_PINC_DISABLE)) |
AnnaBridge | 161:aa5281ff4a02 | 755 | |
AnnaBridge | 161:aa5281ff4a02 | 756 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
AnnaBridge | 161:aa5281ff4a02 | 757 | ((STATE) == DMA_MINC_DISABLE)) |
AnnaBridge | 161:aa5281ff4a02 | 758 | |
AnnaBridge | 161:aa5281ff4a02 | 759 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
AnnaBridge | 161:aa5281ff4a02 | 760 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
AnnaBridge | 161:aa5281ff4a02 | 761 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
AnnaBridge | 161:aa5281ff4a02 | 762 | |
AnnaBridge | 161:aa5281ff4a02 | 763 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
AnnaBridge | 161:aa5281ff4a02 | 764 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
AnnaBridge | 161:aa5281ff4a02 | 765 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
AnnaBridge | 161:aa5281ff4a02 | 766 | |
AnnaBridge | 161:aa5281ff4a02 | 767 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
AnnaBridge | 161:aa5281ff4a02 | 768 | ((MODE) == DMA_CIRCULAR) || \ |
AnnaBridge | 161:aa5281ff4a02 | 769 | ((MODE) == DMA_PFCTRL)) |
AnnaBridge | 161:aa5281ff4a02 | 770 | |
AnnaBridge | 161:aa5281ff4a02 | 771 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
AnnaBridge | 161:aa5281ff4a02 | 772 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
AnnaBridge | 161:aa5281ff4a02 | 773 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
AnnaBridge | 161:aa5281ff4a02 | 774 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
AnnaBridge | 161:aa5281ff4a02 | 775 | |
AnnaBridge | 161:aa5281ff4a02 | 776 | #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ |
AnnaBridge | 161:aa5281ff4a02 | 777 | ((STATE) == DMA_FIFOMODE_ENABLE)) |
AnnaBridge | 161:aa5281ff4a02 | 778 | |
AnnaBridge | 161:aa5281ff4a02 | 779 | #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ |
AnnaBridge | 161:aa5281ff4a02 | 780 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ |
AnnaBridge | 161:aa5281ff4a02 | 781 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ |
AnnaBridge | 161:aa5281ff4a02 | 782 | ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) |
AnnaBridge | 161:aa5281ff4a02 | 783 | |
AnnaBridge | 161:aa5281ff4a02 | 784 | #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ |
AnnaBridge | 161:aa5281ff4a02 | 785 | ((BURST) == DMA_MBURST_INC4) || \ |
AnnaBridge | 161:aa5281ff4a02 | 786 | ((BURST) == DMA_MBURST_INC8) || \ |
AnnaBridge | 161:aa5281ff4a02 | 787 | ((BURST) == DMA_MBURST_INC16)) |
AnnaBridge | 161:aa5281ff4a02 | 788 | |
AnnaBridge | 161:aa5281ff4a02 | 789 | #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ |
AnnaBridge | 161:aa5281ff4a02 | 790 | ((BURST) == DMA_PBURST_INC4) || \ |
AnnaBridge | 161:aa5281ff4a02 | 791 | ((BURST) == DMA_PBURST_INC8) || \ |
AnnaBridge | 161:aa5281ff4a02 | 792 | ((BURST) == DMA_PBURST_INC16)) |
AnnaBridge | 161:aa5281ff4a02 | 793 | /** |
AnnaBridge | 161:aa5281ff4a02 | 794 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 795 | */ |
AnnaBridge | 161:aa5281ff4a02 | 796 | |
AnnaBridge | 161:aa5281ff4a02 | 797 | /* Private functions ---------------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 798 | /** @defgroup DMA_Private_Functions DMA Private Functions |
AnnaBridge | 161:aa5281ff4a02 | 799 | * @brief DMA private functions |
AnnaBridge | 161:aa5281ff4a02 | 800 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 801 | */ |
AnnaBridge | 161:aa5281ff4a02 | 802 | /** |
AnnaBridge | 161:aa5281ff4a02 | 803 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 804 | */ |
AnnaBridge | 161:aa5281ff4a02 | 805 | |
AnnaBridge | 161:aa5281ff4a02 | 806 | /** |
AnnaBridge | 161:aa5281ff4a02 | 807 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 808 | */ |
AnnaBridge | 161:aa5281ff4a02 | 809 | |
AnnaBridge | 161:aa5281ff4a02 | 810 | /** |
AnnaBridge | 161:aa5281ff4a02 | 811 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 812 | */ |
AnnaBridge | 161:aa5281ff4a02 | 813 | |
AnnaBridge | 161:aa5281ff4a02 | 814 | #ifdef __cplusplus |
AnnaBridge | 161:aa5281ff4a02 | 815 | } |
AnnaBridge | 161:aa5281ff4a02 | 816 | #endif |
AnnaBridge | 161:aa5281ff4a02 | 817 | |
AnnaBridge | 161:aa5281ff4a02 | 818 | #endif /* __STM32F4xx_HAL_DMA_H */ |
AnnaBridge | 161:aa5281ff4a02 | 819 | |
AnnaBridge | 161:aa5281ff4a02 | 820 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |