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TARGET_DISCO_F334C8/TOOLCHAIN_GCC_ARM/stm32f3xx_ll_rcc.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 163:e59c8e839560 | 1 | /** |
AnnaBridge | 163:e59c8e839560 | 2 | ****************************************************************************** |
AnnaBridge | 163:e59c8e839560 | 3 | * @file stm32f3xx_ll_rcc.h |
AnnaBridge | 163:e59c8e839560 | 4 | * @author MCD Application Team |
AnnaBridge | 163:e59c8e839560 | 5 | * @brief Header file of RCC LL module. |
AnnaBridge | 163:e59c8e839560 | 6 | ****************************************************************************** |
AnnaBridge | 163:e59c8e839560 | 7 | * @attention |
AnnaBridge | 163:e59c8e839560 | 8 | * |
AnnaBridge | 163:e59c8e839560 | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 163:e59c8e839560 | 10 | * |
AnnaBridge | 163:e59c8e839560 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 163:e59c8e839560 | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 163:e59c8e839560 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 163:e59c8e839560 | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 163:e59c8e839560 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 163:e59c8e839560 | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 163:e59c8e839560 | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 163:e59c8e839560 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 163:e59c8e839560 | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 163:e59c8e839560 | 20 | * without specific prior written permission. |
AnnaBridge | 163:e59c8e839560 | 21 | * |
AnnaBridge | 163:e59c8e839560 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 163:e59c8e839560 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 163:e59c8e839560 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 163:e59c8e839560 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 163:e59c8e839560 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 163:e59c8e839560 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 163:e59c8e839560 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 163:e59c8e839560 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 163:e59c8e839560 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 163:e59c8e839560 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 163:e59c8e839560 | 32 | * |
AnnaBridge | 163:e59c8e839560 | 33 | ****************************************************************************** |
AnnaBridge | 163:e59c8e839560 | 34 | */ |
AnnaBridge | 163:e59c8e839560 | 35 | |
AnnaBridge | 163:e59c8e839560 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 37 | #ifndef __STM32F3xx_LL_RCC_H |
AnnaBridge | 163:e59c8e839560 | 38 | #define __STM32F3xx_LL_RCC_H |
AnnaBridge | 163:e59c8e839560 | 39 | |
AnnaBridge | 163:e59c8e839560 | 40 | #ifdef __cplusplus |
AnnaBridge | 163:e59c8e839560 | 41 | extern "C" { |
AnnaBridge | 163:e59c8e839560 | 42 | #endif |
AnnaBridge | 163:e59c8e839560 | 43 | |
AnnaBridge | 163:e59c8e839560 | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 45 | #include "stm32f3xx.h" |
AnnaBridge | 163:e59c8e839560 | 46 | |
AnnaBridge | 163:e59c8e839560 | 47 | /** @addtogroup STM32F3xx_LL_Driver |
AnnaBridge | 163:e59c8e839560 | 48 | * @{ |
AnnaBridge | 163:e59c8e839560 | 49 | */ |
AnnaBridge | 163:e59c8e839560 | 50 | |
AnnaBridge | 163:e59c8e839560 | 51 | #if defined(RCC) |
AnnaBridge | 163:e59c8e839560 | 52 | |
AnnaBridge | 163:e59c8e839560 | 53 | /** @defgroup RCC_LL RCC |
AnnaBridge | 163:e59c8e839560 | 54 | * @{ |
AnnaBridge | 163:e59c8e839560 | 55 | */ |
AnnaBridge | 163:e59c8e839560 | 56 | |
AnnaBridge | 163:e59c8e839560 | 57 | /* Private types -------------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 58 | /* Private variables ---------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 59 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 60 | /** @defgroup RCC_LL_Private_Constants RCC Private Constants |
AnnaBridge | 163:e59c8e839560 | 61 | * @{ |
AnnaBridge | 163:e59c8e839560 | 62 | */ |
AnnaBridge | 163:e59c8e839560 | 63 | /* Defines used for the bit position in the register and perform offsets*/ |
AnnaBridge | 163:e59c8e839560 | 64 | #define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE) /*!< field position in register RCC_CFGR */ |
AnnaBridge | 163:e59c8e839560 | 65 | #define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1) /*!< field position in register RCC_CFGR */ |
AnnaBridge | 163:e59c8e839560 | 66 | #define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2) /*!< field position in register RCC_CFGR */ |
AnnaBridge | 163:e59c8e839560 | 67 | #define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_CR_HSICAL) /*!< field position in register RCC_CR */ |
AnnaBridge | 163:e59c8e839560 | 68 | #define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_CR_HSITRIM) /*!< field position in register RCC_CR */ |
AnnaBridge | 163:e59c8e839560 | 69 | #define RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL) /*!< field position in register RCC_CFGR */ |
AnnaBridge | 163:e59c8e839560 | 70 | #define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */ |
AnnaBridge | 163:e59c8e839560 | 71 | #define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */ |
AnnaBridge | 163:e59c8e839560 | 72 | #define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */ |
AnnaBridge | 163:e59c8e839560 | 73 | #define RCC_POSITION_TIM1SW (uint32_t)8U /*!< field position in register RCC_CFGR3 */ |
AnnaBridge | 163:e59c8e839560 | 74 | #define RCC_POSITION_TIM8SW (uint32_t)9U /*!< field position in register RCC_CFGR3 */ |
AnnaBridge | 163:e59c8e839560 | 75 | #define RCC_POSITION_TIM15SW (uint32_t)10U /*!< field position in register RCC_CFGR3 */ |
AnnaBridge | 163:e59c8e839560 | 76 | #define RCC_POSITION_TIM16SW (uint32_t)11U /*!< field position in register RCC_CFGR3 */ |
AnnaBridge | 163:e59c8e839560 | 77 | #define RCC_POSITION_TIM17SW (uint32_t)13U /*!< field position in register RCC_CFGR3 */ |
AnnaBridge | 163:e59c8e839560 | 78 | #define RCC_POSITION_TIM20SW (uint32_t)15U /*!< field position in register RCC_CFGR3 */ |
AnnaBridge | 163:e59c8e839560 | 79 | #define RCC_POSITION_TIM2SW (uint32_t)24U /*!< field position in register RCC_CFGR3 */ |
AnnaBridge | 163:e59c8e839560 | 80 | #define RCC_POSITION_TIM34SW (uint32_t)25U /*!< field position in register RCC_CFGR3 */ |
AnnaBridge | 163:e59c8e839560 | 81 | |
AnnaBridge | 163:e59c8e839560 | 82 | /** |
AnnaBridge | 163:e59c8e839560 | 83 | * @} |
AnnaBridge | 163:e59c8e839560 | 84 | */ |
AnnaBridge | 163:e59c8e839560 | 85 | |
AnnaBridge | 163:e59c8e839560 | 86 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 87 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 163:e59c8e839560 | 88 | /** @defgroup RCC_LL_Private_Macros RCC Private Macros |
AnnaBridge | 163:e59c8e839560 | 89 | * @{ |
AnnaBridge | 163:e59c8e839560 | 90 | */ |
AnnaBridge | 163:e59c8e839560 | 91 | /** |
AnnaBridge | 163:e59c8e839560 | 92 | * @} |
AnnaBridge | 163:e59c8e839560 | 93 | */ |
AnnaBridge | 163:e59c8e839560 | 94 | #endif /*USE_FULL_LL_DRIVER*/ |
AnnaBridge | 163:e59c8e839560 | 95 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 96 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 163:e59c8e839560 | 97 | /** @defgroup RCC_LL_Exported_Types RCC Exported Types |
AnnaBridge | 163:e59c8e839560 | 98 | * @{ |
AnnaBridge | 163:e59c8e839560 | 99 | */ |
AnnaBridge | 163:e59c8e839560 | 100 | |
AnnaBridge | 163:e59c8e839560 | 101 | /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure |
AnnaBridge | 163:e59c8e839560 | 102 | * @{ |
AnnaBridge | 163:e59c8e839560 | 103 | */ |
AnnaBridge | 163:e59c8e839560 | 104 | |
AnnaBridge | 163:e59c8e839560 | 105 | /** |
AnnaBridge | 163:e59c8e839560 | 106 | * @brief RCC Clocks Frequency Structure |
AnnaBridge | 163:e59c8e839560 | 107 | */ |
AnnaBridge | 163:e59c8e839560 | 108 | typedef struct |
AnnaBridge | 163:e59c8e839560 | 109 | { |
AnnaBridge | 163:e59c8e839560 | 110 | uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ |
AnnaBridge | 163:e59c8e839560 | 111 | uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ |
AnnaBridge | 163:e59c8e839560 | 112 | uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ |
AnnaBridge | 163:e59c8e839560 | 113 | uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ |
AnnaBridge | 163:e59c8e839560 | 114 | } LL_RCC_ClocksTypeDef; |
AnnaBridge | 163:e59c8e839560 | 115 | |
AnnaBridge | 163:e59c8e839560 | 116 | /** |
AnnaBridge | 163:e59c8e839560 | 117 | * @} |
AnnaBridge | 163:e59c8e839560 | 118 | */ |
AnnaBridge | 163:e59c8e839560 | 119 | |
AnnaBridge | 163:e59c8e839560 | 120 | /** |
AnnaBridge | 163:e59c8e839560 | 121 | * @} |
AnnaBridge | 163:e59c8e839560 | 122 | */ |
AnnaBridge | 163:e59c8e839560 | 123 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 163:e59c8e839560 | 124 | |
AnnaBridge | 163:e59c8e839560 | 125 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 126 | /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants |
AnnaBridge | 163:e59c8e839560 | 127 | * @{ |
AnnaBridge | 163:e59c8e839560 | 128 | */ |
AnnaBridge | 163:e59c8e839560 | 129 | |
AnnaBridge | 163:e59c8e839560 | 130 | /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation |
AnnaBridge | 163:e59c8e839560 | 131 | * @brief Defines used to adapt values of different oscillators |
AnnaBridge | 163:e59c8e839560 | 132 | * @note These values could be modified in the user environment according to |
AnnaBridge | 163:e59c8e839560 | 133 | * HW set-up. |
AnnaBridge | 163:e59c8e839560 | 134 | * @{ |
AnnaBridge | 163:e59c8e839560 | 135 | */ |
AnnaBridge | 163:e59c8e839560 | 136 | #if !defined (HSE_VALUE) |
AnnaBridge | 168:b9e159c1930a | 137 | #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ |
AnnaBridge | 163:e59c8e839560 | 138 | #endif /* HSE_VALUE */ |
AnnaBridge | 163:e59c8e839560 | 139 | |
AnnaBridge | 163:e59c8e839560 | 140 | #if !defined (HSI_VALUE) |
AnnaBridge | 168:b9e159c1930a | 141 | #define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ |
AnnaBridge | 163:e59c8e839560 | 142 | #endif /* HSI_VALUE */ |
AnnaBridge | 163:e59c8e839560 | 143 | |
AnnaBridge | 163:e59c8e839560 | 144 | #if !defined (LSE_VALUE) |
AnnaBridge | 168:b9e159c1930a | 145 | #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ |
AnnaBridge | 163:e59c8e839560 | 146 | #endif /* LSE_VALUE */ |
AnnaBridge | 163:e59c8e839560 | 147 | |
AnnaBridge | 163:e59c8e839560 | 148 | #if !defined (LSI_VALUE) |
AnnaBridge | 168:b9e159c1930a | 149 | #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ |
AnnaBridge | 163:e59c8e839560 | 150 | #endif /* LSI_VALUE */ |
AnnaBridge | 163:e59c8e839560 | 151 | /** |
AnnaBridge | 163:e59c8e839560 | 152 | * @} |
AnnaBridge | 163:e59c8e839560 | 153 | */ |
AnnaBridge | 163:e59c8e839560 | 154 | |
AnnaBridge | 163:e59c8e839560 | 155 | /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines |
AnnaBridge | 163:e59c8e839560 | 156 | * @brief Flags defines which can be used with LL_RCC_WriteReg function |
AnnaBridge | 163:e59c8e839560 | 157 | * @{ |
AnnaBridge | 163:e59c8e839560 | 158 | */ |
AnnaBridge | 163:e59c8e839560 | 159 | #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ |
AnnaBridge | 163:e59c8e839560 | 160 | #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ |
AnnaBridge | 163:e59c8e839560 | 161 | #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ |
AnnaBridge | 163:e59c8e839560 | 162 | #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ |
AnnaBridge | 163:e59c8e839560 | 163 | #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ |
AnnaBridge | 163:e59c8e839560 | 164 | #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ |
AnnaBridge | 163:e59c8e839560 | 165 | /** |
AnnaBridge | 163:e59c8e839560 | 166 | * @} |
AnnaBridge | 163:e59c8e839560 | 167 | */ |
AnnaBridge | 163:e59c8e839560 | 168 | |
AnnaBridge | 163:e59c8e839560 | 169 | /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines |
AnnaBridge | 163:e59c8e839560 | 170 | * @brief Flags defines which can be used with LL_RCC_ReadReg function |
AnnaBridge | 163:e59c8e839560 | 171 | * @{ |
AnnaBridge | 163:e59c8e839560 | 172 | */ |
AnnaBridge | 163:e59c8e839560 | 173 | #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ |
AnnaBridge | 163:e59c8e839560 | 174 | #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ |
AnnaBridge | 163:e59c8e839560 | 175 | #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ |
AnnaBridge | 163:e59c8e839560 | 176 | #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ |
AnnaBridge | 163:e59c8e839560 | 177 | #define LL_RCC_CFGR_MCOF RCC_CFGR_MCOF /*!< MCO flag */ |
AnnaBridge | 163:e59c8e839560 | 178 | #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ |
AnnaBridge | 163:e59c8e839560 | 179 | #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ |
AnnaBridge | 163:e59c8e839560 | 180 | #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ |
AnnaBridge | 163:e59c8e839560 | 181 | #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ |
AnnaBridge | 163:e59c8e839560 | 182 | #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ |
AnnaBridge | 163:e59c8e839560 | 183 | #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ |
AnnaBridge | 163:e59c8e839560 | 184 | #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ |
AnnaBridge | 163:e59c8e839560 | 185 | #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ |
AnnaBridge | 163:e59c8e839560 | 186 | #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ |
AnnaBridge | 163:e59c8e839560 | 187 | #if defined(RCC_CSR_V18PWRRSTF) |
AnnaBridge | 163:e59c8e839560 | 188 | #define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V domain. */ |
AnnaBridge | 163:e59c8e839560 | 189 | #endif /* RCC_CSR_V18PWRRSTF */ |
AnnaBridge | 163:e59c8e839560 | 190 | /** |
AnnaBridge | 163:e59c8e839560 | 191 | * @} |
AnnaBridge | 163:e59c8e839560 | 192 | */ |
AnnaBridge | 163:e59c8e839560 | 193 | |
AnnaBridge | 163:e59c8e839560 | 194 | /** @defgroup RCC_LL_EC_IT IT Defines |
AnnaBridge | 163:e59c8e839560 | 195 | * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions |
AnnaBridge | 163:e59c8e839560 | 196 | * @{ |
AnnaBridge | 163:e59c8e839560 | 197 | */ |
AnnaBridge | 163:e59c8e839560 | 198 | #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ |
AnnaBridge | 163:e59c8e839560 | 199 | #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ |
AnnaBridge | 163:e59c8e839560 | 200 | #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ |
AnnaBridge | 163:e59c8e839560 | 201 | #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ |
AnnaBridge | 163:e59c8e839560 | 202 | #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ |
AnnaBridge | 163:e59c8e839560 | 203 | /** |
AnnaBridge | 163:e59c8e839560 | 204 | * @} |
AnnaBridge | 163:e59c8e839560 | 205 | */ |
AnnaBridge | 163:e59c8e839560 | 206 | |
AnnaBridge | 163:e59c8e839560 | 207 | /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability |
AnnaBridge | 163:e59c8e839560 | 208 | * @{ |
AnnaBridge | 163:e59c8e839560 | 209 | */ |
AnnaBridge | 163:e59c8e839560 | 210 | #define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */ |
AnnaBridge | 163:e59c8e839560 | 211 | #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ |
AnnaBridge | 163:e59c8e839560 | 212 | #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ |
AnnaBridge | 163:e59c8e839560 | 213 | #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ |
AnnaBridge | 163:e59c8e839560 | 214 | /** |
AnnaBridge | 163:e59c8e839560 | 215 | * @} |
AnnaBridge | 163:e59c8e839560 | 216 | */ |
AnnaBridge | 163:e59c8e839560 | 217 | |
AnnaBridge | 163:e59c8e839560 | 218 | /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch |
AnnaBridge | 163:e59c8e839560 | 219 | * @{ |
AnnaBridge | 163:e59c8e839560 | 220 | */ |
AnnaBridge | 163:e59c8e839560 | 221 | #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ |
AnnaBridge | 163:e59c8e839560 | 222 | #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ |
AnnaBridge | 163:e59c8e839560 | 223 | #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ |
AnnaBridge | 163:e59c8e839560 | 224 | /** |
AnnaBridge | 163:e59c8e839560 | 225 | * @} |
AnnaBridge | 163:e59c8e839560 | 226 | */ |
AnnaBridge | 163:e59c8e839560 | 227 | |
AnnaBridge | 163:e59c8e839560 | 228 | /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status |
AnnaBridge | 163:e59c8e839560 | 229 | * @{ |
AnnaBridge | 163:e59c8e839560 | 230 | */ |
AnnaBridge | 163:e59c8e839560 | 231 | #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ |
AnnaBridge | 163:e59c8e839560 | 232 | #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ |
AnnaBridge | 163:e59c8e839560 | 233 | #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ |
AnnaBridge | 163:e59c8e839560 | 234 | /** |
AnnaBridge | 163:e59c8e839560 | 235 | * @} |
AnnaBridge | 163:e59c8e839560 | 236 | */ |
AnnaBridge | 163:e59c8e839560 | 237 | |
AnnaBridge | 163:e59c8e839560 | 238 | /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler |
AnnaBridge | 163:e59c8e839560 | 239 | * @{ |
AnnaBridge | 163:e59c8e839560 | 240 | */ |
AnnaBridge | 163:e59c8e839560 | 241 | #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ |
AnnaBridge | 163:e59c8e839560 | 242 | #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ |
AnnaBridge | 163:e59c8e839560 | 243 | #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ |
AnnaBridge | 163:e59c8e839560 | 244 | #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ |
AnnaBridge | 163:e59c8e839560 | 245 | #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ |
AnnaBridge | 163:e59c8e839560 | 246 | #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ |
AnnaBridge | 163:e59c8e839560 | 247 | #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ |
AnnaBridge | 163:e59c8e839560 | 248 | #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ |
AnnaBridge | 163:e59c8e839560 | 249 | #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ |
AnnaBridge | 163:e59c8e839560 | 250 | /** |
AnnaBridge | 163:e59c8e839560 | 251 | * @} |
AnnaBridge | 163:e59c8e839560 | 252 | */ |
AnnaBridge | 163:e59c8e839560 | 253 | |
AnnaBridge | 163:e59c8e839560 | 254 | /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) |
AnnaBridge | 163:e59c8e839560 | 255 | * @{ |
AnnaBridge | 163:e59c8e839560 | 256 | */ |
AnnaBridge | 163:e59c8e839560 | 257 | #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ |
AnnaBridge | 163:e59c8e839560 | 258 | #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ |
AnnaBridge | 163:e59c8e839560 | 259 | #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ |
AnnaBridge | 163:e59c8e839560 | 260 | #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ |
AnnaBridge | 163:e59c8e839560 | 261 | #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ |
AnnaBridge | 163:e59c8e839560 | 262 | /** |
AnnaBridge | 163:e59c8e839560 | 263 | * @} |
AnnaBridge | 163:e59c8e839560 | 264 | */ |
AnnaBridge | 163:e59c8e839560 | 265 | |
AnnaBridge | 163:e59c8e839560 | 266 | /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) |
AnnaBridge | 163:e59c8e839560 | 267 | * @{ |
AnnaBridge | 163:e59c8e839560 | 268 | */ |
AnnaBridge | 163:e59c8e839560 | 269 | #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ |
AnnaBridge | 163:e59c8e839560 | 270 | #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ |
AnnaBridge | 163:e59c8e839560 | 271 | #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ |
AnnaBridge | 163:e59c8e839560 | 272 | #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ |
AnnaBridge | 163:e59c8e839560 | 273 | #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ |
AnnaBridge | 163:e59c8e839560 | 274 | /** |
AnnaBridge | 163:e59c8e839560 | 275 | * @} |
AnnaBridge | 163:e59c8e839560 | 276 | */ |
AnnaBridge | 163:e59c8e839560 | 277 | |
AnnaBridge | 163:e59c8e839560 | 278 | /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection |
AnnaBridge | 163:e59c8e839560 | 279 | * @{ |
AnnaBridge | 163:e59c8e839560 | 280 | */ |
AnnaBridge | 163:e59c8e839560 | 281 | #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */ |
AnnaBridge | 163:e59c8e839560 | 282 | #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */ |
AnnaBridge | 163:e59c8e839560 | 283 | #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */ |
AnnaBridge | 163:e59c8e839560 | 284 | #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */ |
AnnaBridge | 163:e59c8e839560 | 285 | #define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */ |
AnnaBridge | 163:e59c8e839560 | 286 | #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */ |
AnnaBridge | 163:e59c8e839560 | 287 | #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/ |
AnnaBridge | 163:e59c8e839560 | 288 | #if defined(RCC_CFGR_PLLNODIV) |
AnnaBridge | 163:e59c8e839560 | 289 | #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL clock selected*/ |
AnnaBridge | 163:e59c8e839560 | 290 | #endif /* RCC_CFGR_PLLNODIV */ |
AnnaBridge | 163:e59c8e839560 | 291 | /** |
AnnaBridge | 163:e59c8e839560 | 292 | * @} |
AnnaBridge | 163:e59c8e839560 | 293 | */ |
AnnaBridge | 163:e59c8e839560 | 294 | |
AnnaBridge | 163:e59c8e839560 | 295 | /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler |
AnnaBridge | 163:e59c8e839560 | 296 | * @{ |
AnnaBridge | 163:e59c8e839560 | 297 | */ |
AnnaBridge | 163:e59c8e839560 | 298 | #define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */ |
AnnaBridge | 163:e59c8e839560 | 299 | #if defined(RCC_CFGR_MCOPRE) |
AnnaBridge | 163:e59c8e839560 | 300 | #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ |
AnnaBridge | 163:e59c8e839560 | 301 | #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ |
AnnaBridge | 163:e59c8e839560 | 302 | #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ |
AnnaBridge | 163:e59c8e839560 | 303 | #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ |
AnnaBridge | 163:e59c8e839560 | 304 | #define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */ |
AnnaBridge | 163:e59c8e839560 | 305 | #define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */ |
AnnaBridge | 163:e59c8e839560 | 306 | #define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */ |
AnnaBridge | 163:e59c8e839560 | 307 | #endif /* RCC_CFGR_MCOPRE */ |
AnnaBridge | 163:e59c8e839560 | 308 | /** |
AnnaBridge | 163:e59c8e839560 | 309 | * @} |
AnnaBridge | 163:e59c8e839560 | 310 | */ |
AnnaBridge | 163:e59c8e839560 | 311 | |
AnnaBridge | 163:e59c8e839560 | 312 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 163:e59c8e839560 | 313 | /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency |
AnnaBridge | 163:e59c8e839560 | 314 | * @{ |
AnnaBridge | 163:e59c8e839560 | 315 | */ |
AnnaBridge | 168:b9e159c1930a | 316 | #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ |
AnnaBridge | 168:b9e159c1930a | 317 | #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ |
AnnaBridge | 163:e59c8e839560 | 318 | /** |
AnnaBridge | 163:e59c8e839560 | 319 | * @} |
AnnaBridge | 163:e59c8e839560 | 320 | */ |
AnnaBridge | 163:e59c8e839560 | 321 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 163:e59c8e839560 | 322 | |
AnnaBridge | 163:e59c8e839560 | 323 | /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection |
AnnaBridge | 163:e59c8e839560 | 324 | * @{ |
AnnaBridge | 163:e59c8e839560 | 325 | */ |
AnnaBridge | 163:e59c8e839560 | 326 | #if defined(RCC_CFGR3_USART1SW_PCLK1) |
AnnaBridge | 163:e59c8e839560 | 327 | #define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK1) /*!< PCLK1 clock used as USART1 clock source */ |
AnnaBridge | 163:e59c8e839560 | 328 | #else |
AnnaBridge | 163:e59c8e839560 | 329 | #define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK2) /*!< PCLK2 clock used as USART1 clock source */ |
AnnaBridge | 163:e59c8e839560 | 330 | #endif /*RCC_CFGR3_USART1SW_PCLK1*/ |
AnnaBridge | 163:e59c8e839560 | 331 | #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_SYSCLK) /*!< System clock selected as USART1 clock source */ |
AnnaBridge | 163:e59c8e839560 | 332 | #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_LSE) /*!< LSE oscillator clock used as USART1 clock source */ |
AnnaBridge | 163:e59c8e839560 | 333 | #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_HSI) /*!< HSI oscillator clock used as USART1 clock source */ |
AnnaBridge | 163:e59c8e839560 | 334 | #if defined(RCC_CFGR3_USART2SW) |
AnnaBridge | 163:e59c8e839560 | 335 | #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_PCLK) /*!< PCLK1 clock used as USART2 clock source */ |
AnnaBridge | 163:e59c8e839560 | 336 | #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_SYSCLK) /*!< System clock selected as USART2 clock source */ |
AnnaBridge | 163:e59c8e839560 | 337 | #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_LSE) /*!< LSE oscillator clock used as USART2 clock source */ |
AnnaBridge | 163:e59c8e839560 | 338 | #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_HSI) /*!< HSI oscillator clock used as USART2 clock source */ |
AnnaBridge | 163:e59c8e839560 | 339 | #endif /* RCC_CFGR3_USART2SW */ |
AnnaBridge | 163:e59c8e839560 | 340 | #if defined(RCC_CFGR3_USART3SW) |
AnnaBridge | 163:e59c8e839560 | 341 | #define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_PCLK) /*!< PCLK1 clock used as USART3 clock source */ |
AnnaBridge | 163:e59c8e839560 | 342 | #define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_SYSCLK) /*!< System clock selected as USART3 clock source */ |
AnnaBridge | 163:e59c8e839560 | 343 | #define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_LSE) /*!< LSE oscillator clock used as USART3 clock source */ |
AnnaBridge | 163:e59c8e839560 | 344 | #define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_HSI) /*!< HSI oscillator clock used as USART3 clock source */ |
AnnaBridge | 163:e59c8e839560 | 345 | #endif /* RCC_CFGR3_USART3SW */ |
AnnaBridge | 163:e59c8e839560 | 346 | /** |
AnnaBridge | 163:e59c8e839560 | 347 | * @} |
AnnaBridge | 163:e59c8e839560 | 348 | */ |
AnnaBridge | 163:e59c8e839560 | 349 | |
AnnaBridge | 163:e59c8e839560 | 350 | #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW) |
AnnaBridge | 163:e59c8e839560 | 351 | /** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection |
AnnaBridge | 163:e59c8e839560 | 352 | * @{ |
AnnaBridge | 163:e59c8e839560 | 353 | */ |
AnnaBridge | 163:e59c8e839560 | 354 | #define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_PCLK) /*!< PCLK1 clock used as UART4 clock source */ |
AnnaBridge | 163:e59c8e839560 | 355 | #define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_SYSCLK) /*!< System clock selected as UART4 clock source */ |
AnnaBridge | 163:e59c8e839560 | 356 | #define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_LSE) /*!< LSE oscillator clock used as UART4 clock source */ |
AnnaBridge | 163:e59c8e839560 | 357 | #define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_HSI) /*!< HSI oscillator clock used as UART4 clock source */ |
AnnaBridge | 163:e59c8e839560 | 358 | #define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_PCLK) /*!< PCLK1 clock used as UART5 clock source */ |
AnnaBridge | 163:e59c8e839560 | 359 | #define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_SYSCLK) /*!< System clock selected as UART5 clock source */ |
AnnaBridge | 163:e59c8e839560 | 360 | #define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_LSE) /*!< LSE oscillator clock used as UART5 clock source */ |
AnnaBridge | 163:e59c8e839560 | 361 | #define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_HSI) /*!< HSI oscillator clock used as UART5 clock source */ |
AnnaBridge | 163:e59c8e839560 | 362 | /** |
AnnaBridge | 163:e59c8e839560 | 363 | * @} |
AnnaBridge | 163:e59c8e839560 | 364 | */ |
AnnaBridge | 163:e59c8e839560 | 365 | |
AnnaBridge | 163:e59c8e839560 | 366 | #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */ |
AnnaBridge | 163:e59c8e839560 | 367 | |
AnnaBridge | 163:e59c8e839560 | 368 | /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection |
AnnaBridge | 163:e59c8e839560 | 369 | * @{ |
AnnaBridge | 163:e59c8e839560 | 370 | */ |
AnnaBridge | 163:e59c8e839560 | 371 | #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_HSI) /*!< HSI oscillator clock used as I2C1 clock source */ |
AnnaBridge | 163:e59c8e839560 | 372 | #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_SYSCLK) /*!< System clock selected as I2C1 clock source */ |
AnnaBridge | 163:e59c8e839560 | 373 | #if defined(RCC_CFGR3_I2C2SW) |
AnnaBridge | 163:e59c8e839560 | 374 | #define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_HSI) /*!< HSI oscillator clock used as I2C2 clock source */ |
AnnaBridge | 163:e59c8e839560 | 375 | #define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_SYSCLK) /*!< System clock selected as I2C2 clock source */ |
AnnaBridge | 163:e59c8e839560 | 376 | #endif /*RCC_CFGR3_I2C2SW*/ |
AnnaBridge | 163:e59c8e839560 | 377 | #if defined(RCC_CFGR3_I2C3SW) |
AnnaBridge | 163:e59c8e839560 | 378 | #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_HSI) /*!< HSI oscillator clock used as I2C3 clock source */ |
AnnaBridge | 163:e59c8e839560 | 379 | #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_SYSCLK) /*!< System clock selected as I2C3 clock source */ |
AnnaBridge | 163:e59c8e839560 | 380 | #endif /*RCC_CFGR3_I2C3SW*/ |
AnnaBridge | 163:e59c8e839560 | 381 | /** |
AnnaBridge | 163:e59c8e839560 | 382 | * @} |
AnnaBridge | 163:e59c8e839560 | 383 | */ |
AnnaBridge | 163:e59c8e839560 | 384 | |
AnnaBridge | 163:e59c8e839560 | 385 | #if defined(RCC_CFGR_I2SSRC) |
AnnaBridge | 163:e59c8e839560 | 386 | /** @defgroup RCC_LL_EC_I2S_CLKSOURCE Peripheral I2S clock source selection |
AnnaBridge | 163:e59c8e839560 | 387 | * @{ |
AnnaBridge | 163:e59c8e839560 | 388 | */ |
AnnaBridge | 163:e59c8e839560 | 389 | #define LL_RCC_I2S_CLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK /*!< System clock selected as I2S clock source */ |
AnnaBridge | 163:e59c8e839560 | 390 | #define LL_RCC_I2S_CLKSOURCE_PIN RCC_CFGR_I2SSRC_EXT /*!< External clock selected as I2S clock source */ |
AnnaBridge | 163:e59c8e839560 | 391 | /** |
AnnaBridge | 163:e59c8e839560 | 392 | * @} |
AnnaBridge | 163:e59c8e839560 | 393 | */ |
AnnaBridge | 163:e59c8e839560 | 394 | |
AnnaBridge | 163:e59c8e839560 | 395 | #endif /* RCC_CFGR_I2SSRC */ |
AnnaBridge | 163:e59c8e839560 | 396 | |
AnnaBridge | 163:e59c8e839560 | 397 | #if defined(RCC_CFGR3_TIMSW) |
AnnaBridge | 163:e59c8e839560 | 398 | /** @defgroup RCC_LL_EC_TIM1_CLKSOURCE Peripheral TIM clock source selection |
AnnaBridge | 163:e59c8e839560 | 399 | * @{ |
AnnaBridge | 163:e59c8e839560 | 400 | */ |
AnnaBridge | 163:e59c8e839560 | 401 | #define LL_RCC_TIM1_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PCLK2) /*!< PCLK2 used as TIM1 clock source */ |
AnnaBridge | 163:e59c8e839560 | 402 | #define LL_RCC_TIM1_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PLL) /*!< PLL clock used as TIM1 clock source */ |
AnnaBridge | 163:e59c8e839560 | 403 | #if defined(RCC_CFGR3_TIM8SW) |
AnnaBridge | 163:e59c8e839560 | 404 | #define LL_RCC_TIM8_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PCLK2) /*!< PCLK2 used as TIM8 clock source */ |
AnnaBridge | 163:e59c8e839560 | 405 | #define LL_RCC_TIM8_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PLL) /*!< PLL clock used as TIM8 clock source */ |
AnnaBridge | 163:e59c8e839560 | 406 | #endif /*RCC_CFGR3_TIM8SW*/ |
AnnaBridge | 163:e59c8e839560 | 407 | #if defined(RCC_CFGR3_TIM15SW) |
AnnaBridge | 163:e59c8e839560 | 408 | #define LL_RCC_TIM15_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PCLK2) /*!< PCLK2 used as TIM15 clock source */ |
AnnaBridge | 163:e59c8e839560 | 409 | #define LL_RCC_TIM15_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PLL) /*!< PLL clock used as TIM15 clock source */ |
AnnaBridge | 163:e59c8e839560 | 410 | #endif /*RCC_CFGR3_TIM15SW*/ |
AnnaBridge | 163:e59c8e839560 | 411 | #if defined(RCC_CFGR3_TIM16SW) |
AnnaBridge | 163:e59c8e839560 | 412 | #define LL_RCC_TIM16_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PCLK2) /*!< PCLK2 used as TIM16 clock source */ |
AnnaBridge | 163:e59c8e839560 | 413 | #define LL_RCC_TIM16_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PLL) /*!< PLL clock used as TIM16 clock source */ |
AnnaBridge | 163:e59c8e839560 | 414 | #endif /*RCC_CFGR3_TIM16SW*/ |
AnnaBridge | 163:e59c8e839560 | 415 | #if defined(RCC_CFGR3_TIM17SW) |
AnnaBridge | 163:e59c8e839560 | 416 | #define LL_RCC_TIM17_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PCLK2) /*!< PCLK2 used as TIM17 clock source */ |
AnnaBridge | 163:e59c8e839560 | 417 | #define LL_RCC_TIM17_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PLL) /*!< PLL clock used as TIM17 clock source */ |
AnnaBridge | 163:e59c8e839560 | 418 | #endif /*RCC_CFGR3_TIM17SW*/ |
AnnaBridge | 163:e59c8e839560 | 419 | #if defined(RCC_CFGR3_TIM20SW) |
AnnaBridge | 163:e59c8e839560 | 420 | #define LL_RCC_TIM20_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PCLK2) /*!< PCLK2 used as TIM20 clock source */ |
AnnaBridge | 163:e59c8e839560 | 421 | #define LL_RCC_TIM20_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PLL) /*!< PLL clock used as TIM20 clock source */ |
AnnaBridge | 163:e59c8e839560 | 422 | #endif /*RCC_CFGR3_TIM20SW*/ |
AnnaBridge | 163:e59c8e839560 | 423 | #if defined(RCC_CFGR3_TIM2SW) |
AnnaBridge | 163:e59c8e839560 | 424 | #define LL_RCC_TIM2_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PCLK1) /*!< PCLK1 used as TIM2 clock source */ |
AnnaBridge | 163:e59c8e839560 | 425 | #define LL_RCC_TIM2_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PLL) /*!< PLL clock used as TIM2 clock source */ |
AnnaBridge | 163:e59c8e839560 | 426 | #endif /*RCC_CFGR3_TIM2SW*/ |
AnnaBridge | 163:e59c8e839560 | 427 | #if defined(RCC_CFGR3_TIM34SW) |
AnnaBridge | 163:e59c8e839560 | 428 | #define LL_RCC_TIM34_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PCLK1) /*!< PCLK1 used as TIM3/4 clock source */ |
AnnaBridge | 163:e59c8e839560 | 429 | #define LL_RCC_TIM34_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PLL) /*!< PLL clock used as TIM3/4 clock source */ |
AnnaBridge | 163:e59c8e839560 | 430 | #endif /*RCC_CFGR3_TIM34SW*/ |
AnnaBridge | 163:e59c8e839560 | 431 | /** |
AnnaBridge | 163:e59c8e839560 | 432 | * @} |
AnnaBridge | 163:e59c8e839560 | 433 | */ |
AnnaBridge | 163:e59c8e839560 | 434 | |
AnnaBridge | 163:e59c8e839560 | 435 | #endif /* RCC_CFGR3_TIMSW */ |
AnnaBridge | 163:e59c8e839560 | 436 | |
AnnaBridge | 163:e59c8e839560 | 437 | #if defined(HRTIM1) |
AnnaBridge | 163:e59c8e839560 | 438 | /** @defgroup RCC_LL_EC_HRTIM1_CLKSOURCE Peripheral HRTIM1 clock source selection |
AnnaBridge | 163:e59c8e839560 | 439 | * @{ |
AnnaBridge | 163:e59c8e839560 | 440 | */ |
AnnaBridge | 163:e59c8e839560 | 441 | #define LL_RCC_HRTIM1_CLKSOURCE_PCLK2 RCC_CFGR3_HRTIM1SW_PCLK2 /*!< PCLK2 used as HRTIM1 clock source */ |
AnnaBridge | 163:e59c8e839560 | 442 | #define LL_RCC_HRTIM1_CLKSOURCE_PLL RCC_CFGR3_HRTIM1SW_PLL /*!< PLL clock used as HRTIM1 clock source */ |
AnnaBridge | 163:e59c8e839560 | 443 | /** |
AnnaBridge | 163:e59c8e839560 | 444 | * @} |
AnnaBridge | 163:e59c8e839560 | 445 | */ |
AnnaBridge | 163:e59c8e839560 | 446 | |
AnnaBridge | 163:e59c8e839560 | 447 | #endif /* HRTIM1 */ |
AnnaBridge | 163:e59c8e839560 | 448 | |
AnnaBridge | 163:e59c8e839560 | 449 | #if defined(CEC) |
AnnaBridge | 163:e59c8e839560 | 450 | /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection |
AnnaBridge | 163:e59c8e839560 | 451 | * @{ |
AnnaBridge | 163:e59c8e839560 | 452 | */ |
AnnaBridge | 163:e59c8e839560 | 453 | #define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 454 | #define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HDMI CEC entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 455 | /** |
AnnaBridge | 163:e59c8e839560 | 456 | * @} |
AnnaBridge | 163:e59c8e839560 | 457 | */ |
AnnaBridge | 163:e59c8e839560 | 458 | |
AnnaBridge | 163:e59c8e839560 | 459 | #endif /* CEC */ |
AnnaBridge | 163:e59c8e839560 | 460 | |
AnnaBridge | 163:e59c8e839560 | 461 | #if defined(USB) |
AnnaBridge | 163:e59c8e839560 | 462 | /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection |
AnnaBridge | 163:e59c8e839560 | 463 | * @{ |
AnnaBridge | 163:e59c8e839560 | 464 | */ |
AnnaBridge | 163:e59c8e839560 | 465 | #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1 /*!< USB prescaler is PLL clock divided by 1 */ |
AnnaBridge | 163:e59c8e839560 | 466 | #define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 RCC_CFGR_USBPRE_DIV1_5 /*!< USB prescaler is PLL clock divided by 1.5 */ |
AnnaBridge | 163:e59c8e839560 | 467 | /** |
AnnaBridge | 163:e59c8e839560 | 468 | * @} |
AnnaBridge | 163:e59c8e839560 | 469 | */ |
AnnaBridge | 163:e59c8e839560 | 470 | |
AnnaBridge | 163:e59c8e839560 | 471 | #endif /* USB */ |
AnnaBridge | 163:e59c8e839560 | 472 | |
AnnaBridge | 163:e59c8e839560 | 473 | #if defined(RCC_CFGR_ADCPRE) |
AnnaBridge | 163:e59c8e839560 | 474 | /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection |
AnnaBridge | 163:e59c8e839560 | 475 | * @{ |
AnnaBridge | 163:e59c8e839560 | 476 | */ |
AnnaBridge | 163:e59c8e839560 | 477 | #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*!< ADC prescaler PCLK divided by 2 */ |
AnnaBridge | 163:e59c8e839560 | 478 | #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*!< ADC prescaler PCLK divided by 4 */ |
AnnaBridge | 163:e59c8e839560 | 479 | #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*!< ADC prescaler PCLK divided by 6 */ |
AnnaBridge | 163:e59c8e839560 | 480 | #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*!< ADC prescaler PCLK divided by 8 */ |
AnnaBridge | 163:e59c8e839560 | 481 | /** |
AnnaBridge | 163:e59c8e839560 | 482 | * @} |
AnnaBridge | 163:e59c8e839560 | 483 | */ |
AnnaBridge | 163:e59c8e839560 | 484 | |
AnnaBridge | 163:e59c8e839560 | 485 | #elif defined(RCC_CFGR2_ADC1PRES) |
AnnaBridge | 163:e59c8e839560 | 486 | /** @defgroup RCC_LL_EC_ADC1_CLKSOURCE Peripheral ADC clock source selection |
AnnaBridge | 163:e59c8e839560 | 487 | * @{ |
AnnaBridge | 163:e59c8e839560 | 488 | */ |
AnnaBridge | 163:e59c8e839560 | 489 | #define LL_RCC_ADC1_CLKSRC_HCLK RCC_CFGR2_ADC1PRES_NO /*!< ADC1 clock disabled, ADC1 can use AHB clock */ |
AnnaBridge | 163:e59c8e839560 | 490 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADC1PRES_DIV1 /*!< ADC1 PLL clock divided by 1 */ |
AnnaBridge | 163:e59c8e839560 | 491 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADC1PRES_DIV2 /*!< ADC1 PLL clock divided by 2 */ |
AnnaBridge | 163:e59c8e839560 | 492 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADC1PRES_DIV4 /*!< ADC1 PLL clock divided by 4 */ |
AnnaBridge | 163:e59c8e839560 | 493 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADC1PRES_DIV6 /*!< ADC1 PLL clock divided by 6 */ |
AnnaBridge | 163:e59c8e839560 | 494 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADC1PRES_DIV8 /*!< ADC1 PLL clock divided by 8 */ |
AnnaBridge | 163:e59c8e839560 | 495 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADC1PRES_DIV10 /*!< ADC1 PLL clock divided by 10 */ |
AnnaBridge | 163:e59c8e839560 | 496 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADC1PRES_DIV12 /*!< ADC1 PLL clock divided by 12 */ |
AnnaBridge | 163:e59c8e839560 | 497 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADC1PRES_DIV16 /*!< ADC1 PLL clock divided by 16 */ |
AnnaBridge | 163:e59c8e839560 | 498 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADC1PRES_DIV32 /*!< ADC1 PLL clock divided by 32 */ |
AnnaBridge | 163:e59c8e839560 | 499 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADC1PRES_DIV64 /*!< ADC1 PLL clock divided by 64 */ |
AnnaBridge | 163:e59c8e839560 | 500 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADC1PRES_DIV128 /*!< ADC1 PLL clock divided by 128 */ |
AnnaBridge | 163:e59c8e839560 | 501 | #define LL_RCC_ADC1_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADC1PRES_DIV256 /*!< ADC1 PLL clock divided by 256 */ |
AnnaBridge | 163:e59c8e839560 | 502 | /** |
AnnaBridge | 163:e59c8e839560 | 503 | * @} |
AnnaBridge | 163:e59c8e839560 | 504 | */ |
AnnaBridge | 163:e59c8e839560 | 505 | |
AnnaBridge | 163:e59c8e839560 | 506 | #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) |
AnnaBridge | 163:e59c8e839560 | 507 | #if defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34) |
AnnaBridge | 163:e59c8e839560 | 508 | /** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC12 clock source selection |
AnnaBridge | 163:e59c8e839560 | 509 | * @{ |
AnnaBridge | 163:e59c8e839560 | 510 | */ |
AnnaBridge | 163:e59c8e839560 | 511 | #define LL_RCC_ADC12_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_NO) /*!< ADC12 clock disabled, ADC12 can use AHB clock */ |
AnnaBridge | 163:e59c8e839560 | 512 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV1) /*!< ADC12 PLL clock divided by 1 */ |
AnnaBridge | 163:e59c8e839560 | 513 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV2) /*!< ADC12 PLL clock divided by 2 */ |
AnnaBridge | 163:e59c8e839560 | 514 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV4) /*!< ADC12 PLL clock divided by 4 */ |
AnnaBridge | 163:e59c8e839560 | 515 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV6) /*!< ADC12 PLL clock divided by 6 */ |
AnnaBridge | 163:e59c8e839560 | 516 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV8) /*!< ADC12 PLL clock divided by 8 */ |
AnnaBridge | 163:e59c8e839560 | 517 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV10) /*!< ADC12 PLL clock divided by 10 */ |
AnnaBridge | 163:e59c8e839560 | 518 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV12) /*!< ADC12 PLL clock divided by 12 */ |
AnnaBridge | 163:e59c8e839560 | 519 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV16) /*!< ADC12 PLL clock divided by 16 */ |
AnnaBridge | 163:e59c8e839560 | 520 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV32) /*!< ADC12 PLL clock divided by 32 */ |
AnnaBridge | 163:e59c8e839560 | 521 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV64) /*!< ADC12 PLL clock divided by 64 */ |
AnnaBridge | 163:e59c8e839560 | 522 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV128) /*!< ADC12 PLL clock divided by 128 */ |
AnnaBridge | 163:e59c8e839560 | 523 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV256) /*!< ADC12 PLL clock divided by 256 */ |
AnnaBridge | 163:e59c8e839560 | 524 | /** |
AnnaBridge | 163:e59c8e839560 | 525 | * @} |
AnnaBridge | 163:e59c8e839560 | 526 | */ |
AnnaBridge | 163:e59c8e839560 | 527 | |
AnnaBridge | 163:e59c8e839560 | 528 | /** @defgroup RCC_LL_EC_ADC34_CLKSOURCE Peripheral ADC34 clock source selection |
AnnaBridge | 163:e59c8e839560 | 529 | * @{ |
AnnaBridge | 163:e59c8e839560 | 530 | */ |
AnnaBridge | 163:e59c8e839560 | 531 | #define LL_RCC_ADC34_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_NO) /*!< ADC34 clock disabled, ADC34 can use AHB clock */ |
AnnaBridge | 163:e59c8e839560 | 532 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV1) /*!< ADC34 PLL clock divided by 1 */ |
AnnaBridge | 163:e59c8e839560 | 533 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV2) /*!< ADC34 PLL clock divided by 2 */ |
AnnaBridge | 163:e59c8e839560 | 534 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV4) /*!< ADC34 PLL clock divided by 4 */ |
AnnaBridge | 163:e59c8e839560 | 535 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV6) /*!< ADC34 PLL clock divided by 6 */ |
AnnaBridge | 163:e59c8e839560 | 536 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV8) /*!< ADC34 PLL clock divided by 8 */ |
AnnaBridge | 163:e59c8e839560 | 537 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV10) /*!< ADC34 PLL clock divided by 10 */ |
AnnaBridge | 163:e59c8e839560 | 538 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV12) /*!< ADC34 PLL clock divided by 12 */ |
AnnaBridge | 163:e59c8e839560 | 539 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV16) /*!< ADC34 PLL clock divided by 16 */ |
AnnaBridge | 163:e59c8e839560 | 540 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV32) /*!< ADC34 PLL clock divided by 32 */ |
AnnaBridge | 163:e59c8e839560 | 541 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV64) /*!< ADC34 PLL clock divided by 64 */ |
AnnaBridge | 163:e59c8e839560 | 542 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV128) /*!< ADC34 PLL clock divided by 128 */ |
AnnaBridge | 163:e59c8e839560 | 543 | #define LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV256) /*!< ADC34 PLL clock divided by 256 */ |
AnnaBridge | 163:e59c8e839560 | 544 | /** |
AnnaBridge | 163:e59c8e839560 | 545 | * @} |
AnnaBridge | 163:e59c8e839560 | 546 | */ |
AnnaBridge | 163:e59c8e839560 | 547 | |
AnnaBridge | 163:e59c8e839560 | 548 | #else |
AnnaBridge | 163:e59c8e839560 | 549 | /** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC clock source selection |
AnnaBridge | 163:e59c8e839560 | 550 | * @{ |
AnnaBridge | 163:e59c8e839560 | 551 | */ |
AnnaBridge | 163:e59c8e839560 | 552 | #define LL_RCC_ADC12_CLKSRC_HCLK RCC_CFGR2_ADCPRE12_NO /*!< ADC12 clock disabled, ADC12 can use AHB clock */ |
AnnaBridge | 163:e59c8e839560 | 553 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADCPRE12_DIV1 /*!< ADC12 PLL clock divided by 1 */ |
AnnaBridge | 163:e59c8e839560 | 554 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADCPRE12_DIV2 /*!< ADC12 PLL clock divided by 2 */ |
AnnaBridge | 163:e59c8e839560 | 555 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADCPRE12_DIV4 /*!< ADC12 PLL clock divided by 4 */ |
AnnaBridge | 163:e59c8e839560 | 556 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADCPRE12_DIV6 /*!< ADC12 PLL clock divided by 6 */ |
AnnaBridge | 163:e59c8e839560 | 557 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADCPRE12_DIV8 /*!< ADC12 PLL clock divided by 8 */ |
AnnaBridge | 163:e59c8e839560 | 558 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADCPRE12_DIV10 /*!< ADC12 PLL clock divided by 10 */ |
AnnaBridge | 163:e59c8e839560 | 559 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADCPRE12_DIV12 /*!< ADC12 PLL clock divided by 12 */ |
AnnaBridge | 163:e59c8e839560 | 560 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADCPRE12_DIV16 /*!< ADC12 PLL clock divided by 16 */ |
AnnaBridge | 163:e59c8e839560 | 561 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADCPRE12_DIV32 /*!< ADC12 PLL clock divided by 32 */ |
AnnaBridge | 163:e59c8e839560 | 562 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADCPRE12_DIV64 /*!< ADC12 PLL clock divided by 64 */ |
AnnaBridge | 163:e59c8e839560 | 563 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADCPRE12_DIV128 /*!< ADC12 PLL clock divided by 128 */ |
AnnaBridge | 163:e59c8e839560 | 564 | #define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADCPRE12_DIV256 /*!< ADC12 PLL clock divided by 256 */ |
AnnaBridge | 163:e59c8e839560 | 565 | /** |
AnnaBridge | 163:e59c8e839560 | 566 | * @} |
AnnaBridge | 163:e59c8e839560 | 567 | */ |
AnnaBridge | 163:e59c8e839560 | 568 | |
AnnaBridge | 163:e59c8e839560 | 569 | #endif /* RCC_CFGR2_ADCPRE12 && RCC_CFGR2_ADCPRE34 */ |
AnnaBridge | 163:e59c8e839560 | 570 | |
AnnaBridge | 163:e59c8e839560 | 571 | #endif /* RCC_CFGR_ADCPRE */ |
AnnaBridge | 163:e59c8e839560 | 572 | |
AnnaBridge | 163:e59c8e839560 | 573 | #if defined(RCC_CFGR_SDPRE) |
AnnaBridge | 163:e59c8e839560 | 574 | /** @defgroup RCC_LL_EC_SDADC_CLKSOURCE_SYSCLK Peripheral SDADC clock source selection |
AnnaBridge | 163:e59c8e839560 | 575 | * @{ |
AnnaBridge | 163:e59c8e839560 | 576 | */ |
AnnaBridge | 163:e59c8e839560 | 577 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_1 RCC_CFGR_SDPRE_DIV1 /*!< SDADC CLK not divided */ |
AnnaBridge | 163:e59c8e839560 | 578 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_2 RCC_CFGR_SDPRE_DIV2 /*!< SDADC CLK divided by 2 */ |
AnnaBridge | 163:e59c8e839560 | 579 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_4 RCC_CFGR_SDPRE_DIV4 /*!< SDADC CLK divided by 4 */ |
AnnaBridge | 163:e59c8e839560 | 580 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_6 RCC_CFGR_SDPRE_DIV6 /*!< SDADC CLK divided by 6 */ |
AnnaBridge | 163:e59c8e839560 | 581 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_8 RCC_CFGR_SDPRE_DIV8 /*!< SDADC CLK divided by 8 */ |
AnnaBridge | 163:e59c8e839560 | 582 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_10 RCC_CFGR_SDPRE_DIV10 /*!< SDADC CLK divided by 10 */ |
AnnaBridge | 163:e59c8e839560 | 583 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_12 RCC_CFGR_SDPRE_DIV12 /*!< SDADC CLK divided by 12 */ |
AnnaBridge | 163:e59c8e839560 | 584 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_14 RCC_CFGR_SDPRE_DIV14 /*!< SDADC CLK divided by 14 */ |
AnnaBridge | 163:e59c8e839560 | 585 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_16 RCC_CFGR_SDPRE_DIV16 /*!< SDADC CLK divided by 16 */ |
AnnaBridge | 163:e59c8e839560 | 586 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_20 RCC_CFGR_SDPRE_DIV20 /*!< SDADC CLK divided by 20 */ |
AnnaBridge | 163:e59c8e839560 | 587 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_24 RCC_CFGR_SDPRE_DIV24 /*!< SDADC CLK divided by 24 */ |
AnnaBridge | 163:e59c8e839560 | 588 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_28 RCC_CFGR_SDPRE_DIV28 /*!< SDADC CLK divided by 28 */ |
AnnaBridge | 163:e59c8e839560 | 589 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_32 RCC_CFGR_SDPRE_DIV32 /*!< SDADC CLK divided by 32 */ |
AnnaBridge | 163:e59c8e839560 | 590 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_36 RCC_CFGR_SDPRE_DIV36 /*!< SDADC CLK divided by 36 */ |
AnnaBridge | 163:e59c8e839560 | 591 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_40 RCC_CFGR_SDPRE_DIV40 /*!< SDADC CLK divided by 40 */ |
AnnaBridge | 163:e59c8e839560 | 592 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_44 RCC_CFGR_SDPRE_DIV44 /*!< SDADC CLK divided by 44 */ |
AnnaBridge | 163:e59c8e839560 | 593 | #define LL_RCC_SDADC_CLKSRC_SYS_DIV_48 RCC_CFGR_SDPRE_DIV48 /*!< SDADC CLK divided by 48 */ |
AnnaBridge | 163:e59c8e839560 | 594 | /** |
AnnaBridge | 163:e59c8e839560 | 595 | * @} |
AnnaBridge | 163:e59c8e839560 | 596 | */ |
AnnaBridge | 163:e59c8e839560 | 597 | |
AnnaBridge | 163:e59c8e839560 | 598 | #endif /* RCC_CFGR_SDPRE */ |
AnnaBridge | 163:e59c8e839560 | 599 | |
AnnaBridge | 163:e59c8e839560 | 600 | /** @defgroup RCC_LL_EC_USART Peripheral USART get clock source |
AnnaBridge | 163:e59c8e839560 | 601 | * @{ |
AnnaBridge | 163:e59c8e839560 | 602 | */ |
AnnaBridge | 163:e59c8e839560 | 603 | #define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 604 | #if defined(RCC_CFGR3_USART2SW) |
AnnaBridge | 163:e59c8e839560 | 605 | #define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 606 | #endif /* RCC_CFGR3_USART2SW */ |
AnnaBridge | 163:e59c8e839560 | 607 | #if defined(RCC_CFGR3_USART3SW) |
AnnaBridge | 163:e59c8e839560 | 608 | #define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 609 | #endif /* RCC_CFGR3_USART3SW */ |
AnnaBridge | 163:e59c8e839560 | 610 | /** |
AnnaBridge | 163:e59c8e839560 | 611 | * @} |
AnnaBridge | 163:e59c8e839560 | 612 | */ |
AnnaBridge | 163:e59c8e839560 | 613 | |
AnnaBridge | 163:e59c8e839560 | 614 | #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW) |
AnnaBridge | 163:e59c8e839560 | 615 | /** @defgroup RCC_LL_EC_UART Peripheral UART get clock source |
AnnaBridge | 163:e59c8e839560 | 616 | * @{ |
AnnaBridge | 163:e59c8e839560 | 617 | */ |
AnnaBridge | 163:e59c8e839560 | 618 | #define LL_RCC_UART4_CLKSOURCE RCC_CFGR3_UART4SW /*!< UART4 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 619 | #define LL_RCC_UART5_CLKSOURCE RCC_CFGR3_UART5SW /*!< UART5 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 620 | /** |
AnnaBridge | 163:e59c8e839560 | 621 | * @} |
AnnaBridge | 163:e59c8e839560 | 622 | */ |
AnnaBridge | 163:e59c8e839560 | 623 | |
AnnaBridge | 163:e59c8e839560 | 624 | #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */ |
AnnaBridge | 163:e59c8e839560 | 625 | |
AnnaBridge | 163:e59c8e839560 | 626 | /** @defgroup RCC_LL_EC_I2C Peripheral I2C get clock source |
AnnaBridge | 163:e59c8e839560 | 627 | * @{ |
AnnaBridge | 163:e59c8e839560 | 628 | */ |
AnnaBridge | 163:e59c8e839560 | 629 | #define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 630 | #if defined(RCC_CFGR3_I2C2SW) |
AnnaBridge | 163:e59c8e839560 | 631 | #define LL_RCC_I2C2_CLKSOURCE RCC_CFGR3_I2C2SW /*!< I2C2 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 632 | #endif /*RCC_CFGR3_I2C2SW*/ |
AnnaBridge | 163:e59c8e839560 | 633 | #if defined(RCC_CFGR3_I2C3SW) |
AnnaBridge | 163:e59c8e839560 | 634 | #define LL_RCC_I2C3_CLKSOURCE RCC_CFGR3_I2C3SW /*!< I2C3 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 635 | #endif /*RCC_CFGR3_I2C3SW*/ |
AnnaBridge | 163:e59c8e839560 | 636 | /** |
AnnaBridge | 163:e59c8e839560 | 637 | * @} |
AnnaBridge | 163:e59c8e839560 | 638 | */ |
AnnaBridge | 163:e59c8e839560 | 639 | |
AnnaBridge | 163:e59c8e839560 | 640 | #if defined(RCC_CFGR_I2SSRC) |
AnnaBridge | 163:e59c8e839560 | 641 | /** @defgroup RCC_LL_EC_I2S Peripheral I2S get clock source |
AnnaBridge | 163:e59c8e839560 | 642 | * @{ |
AnnaBridge | 163:e59c8e839560 | 643 | */ |
AnnaBridge | 163:e59c8e839560 | 644 | #define LL_RCC_I2S_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 645 | /** |
AnnaBridge | 163:e59c8e839560 | 646 | * @} |
AnnaBridge | 163:e59c8e839560 | 647 | */ |
AnnaBridge | 163:e59c8e839560 | 648 | |
AnnaBridge | 163:e59c8e839560 | 649 | #endif /* RCC_CFGR_I2SSRC */ |
AnnaBridge | 163:e59c8e839560 | 650 | |
AnnaBridge | 163:e59c8e839560 | 651 | #if defined(RCC_CFGR3_TIMSW) |
AnnaBridge | 163:e59c8e839560 | 652 | /** @defgroup RCC_LL_EC_TIM TIMx Peripheral TIM get clock source |
AnnaBridge | 163:e59c8e839560 | 653 | * @{ |
AnnaBridge | 163:e59c8e839560 | 654 | */ |
AnnaBridge | 163:e59c8e839560 | 655 | #define LL_RCC_TIM1_CLKSOURCE (RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) /*!< TIM1 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 656 | #if defined(RCC_CFGR3_TIM2SW) |
AnnaBridge | 163:e59c8e839560 | 657 | #define LL_RCC_TIM2_CLKSOURCE (RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) /*!< TIM2 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 658 | #endif /*RCC_CFGR3_TIM2SW*/ |
AnnaBridge | 163:e59c8e839560 | 659 | #if defined(RCC_CFGR3_TIM8SW) |
AnnaBridge | 163:e59c8e839560 | 660 | #define LL_RCC_TIM8_CLKSOURCE (RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) /*!< TIM8 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 661 | #endif /*RCC_CFGR3_TIM8SW*/ |
AnnaBridge | 163:e59c8e839560 | 662 | #if defined(RCC_CFGR3_TIM15SW) |
AnnaBridge | 163:e59c8e839560 | 663 | #define LL_RCC_TIM15_CLKSOURCE (RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) /*!< TIM15 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 664 | #endif /*RCC_CFGR3_TIM15SW*/ |
AnnaBridge | 163:e59c8e839560 | 665 | #if defined(RCC_CFGR3_TIM16SW) |
AnnaBridge | 163:e59c8e839560 | 666 | #define LL_RCC_TIM16_CLKSOURCE (RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) /*!< TIM16 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 667 | #endif /*RCC_CFGR3_TIM16SW*/ |
AnnaBridge | 163:e59c8e839560 | 668 | #if defined(RCC_CFGR3_TIM17SW) |
AnnaBridge | 163:e59c8e839560 | 669 | #define LL_RCC_TIM17_CLKSOURCE (RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) /*!< TIM17 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 670 | #endif /*RCC_CFGR3_TIM17SW*/ |
AnnaBridge | 163:e59c8e839560 | 671 | #if defined(RCC_CFGR3_TIM20SW) |
AnnaBridge | 163:e59c8e839560 | 672 | #define LL_RCC_TIM20_CLKSOURCE (RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) /*!< TIM20 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 673 | #endif /*RCC_CFGR3_TIM20SW*/ |
AnnaBridge | 163:e59c8e839560 | 674 | #if defined(RCC_CFGR3_TIM34SW) |
AnnaBridge | 163:e59c8e839560 | 675 | #define LL_RCC_TIM34_CLKSOURCE (RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) /*!< TIM3/4 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 676 | #endif /*RCC_CFGR3_TIM34SW*/ |
AnnaBridge | 163:e59c8e839560 | 677 | /** |
AnnaBridge | 163:e59c8e839560 | 678 | * @} |
AnnaBridge | 163:e59c8e839560 | 679 | */ |
AnnaBridge | 163:e59c8e839560 | 680 | |
AnnaBridge | 163:e59c8e839560 | 681 | #endif /* RCC_CFGR3_TIMSW */ |
AnnaBridge | 163:e59c8e839560 | 682 | |
AnnaBridge | 163:e59c8e839560 | 683 | #if defined(HRTIM1) |
AnnaBridge | 163:e59c8e839560 | 684 | /** @defgroup RCC_LL_EC_HRTIM1 Peripheral HRTIM1 get clock source |
AnnaBridge | 163:e59c8e839560 | 685 | * @{ |
AnnaBridge | 163:e59c8e839560 | 686 | */ |
AnnaBridge | 163:e59c8e839560 | 687 | #define LL_RCC_HRTIM1_CLKSOURCE RCC_CFGR3_HRTIM1SW /*!< HRTIM1 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 688 | /** |
AnnaBridge | 163:e59c8e839560 | 689 | * @} |
AnnaBridge | 163:e59c8e839560 | 690 | */ |
AnnaBridge | 163:e59c8e839560 | 691 | |
AnnaBridge | 163:e59c8e839560 | 692 | #endif /* HRTIM1 */ |
AnnaBridge | 163:e59c8e839560 | 693 | |
AnnaBridge | 163:e59c8e839560 | 694 | #if defined(CEC) |
AnnaBridge | 163:e59c8e839560 | 695 | /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source |
AnnaBridge | 163:e59c8e839560 | 696 | * @{ |
AnnaBridge | 163:e59c8e839560 | 697 | */ |
AnnaBridge | 163:e59c8e839560 | 698 | #define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 699 | /** |
AnnaBridge | 163:e59c8e839560 | 700 | * @} |
AnnaBridge | 163:e59c8e839560 | 701 | */ |
AnnaBridge | 163:e59c8e839560 | 702 | |
AnnaBridge | 163:e59c8e839560 | 703 | #endif /* CEC */ |
AnnaBridge | 163:e59c8e839560 | 704 | |
AnnaBridge | 163:e59c8e839560 | 705 | #if defined(USB) |
AnnaBridge | 163:e59c8e839560 | 706 | /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source |
AnnaBridge | 163:e59c8e839560 | 707 | * @{ |
AnnaBridge | 163:e59c8e839560 | 708 | */ |
AnnaBridge | 163:e59c8e839560 | 709 | #define LL_RCC_USB_CLKSOURCE RCC_CFGR_USBPRE /*!< USB Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 710 | /** |
AnnaBridge | 163:e59c8e839560 | 711 | * @} |
AnnaBridge | 163:e59c8e839560 | 712 | */ |
AnnaBridge | 163:e59c8e839560 | 713 | |
AnnaBridge | 163:e59c8e839560 | 714 | #endif /* USB */ |
AnnaBridge | 163:e59c8e839560 | 715 | |
AnnaBridge | 163:e59c8e839560 | 716 | #if defined(RCC_CFGR_ADCPRE) |
AnnaBridge | 163:e59c8e839560 | 717 | /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source |
AnnaBridge | 163:e59c8e839560 | 718 | * @{ |
AnnaBridge | 163:e59c8e839560 | 719 | */ |
AnnaBridge | 163:e59c8e839560 | 720 | #define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 721 | /** |
AnnaBridge | 163:e59c8e839560 | 722 | * @} |
AnnaBridge | 163:e59c8e839560 | 723 | */ |
AnnaBridge | 163:e59c8e839560 | 724 | |
AnnaBridge | 163:e59c8e839560 | 725 | #endif /* RCC_CFGR_ADCPRE */ |
AnnaBridge | 163:e59c8e839560 | 726 | |
AnnaBridge | 163:e59c8e839560 | 727 | #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) |
AnnaBridge | 163:e59c8e839560 | 728 | /** @defgroup RCC_LL_EC_ADCXX Peripheral ADC get clock source |
AnnaBridge | 163:e59c8e839560 | 729 | * @{ |
AnnaBridge | 163:e59c8e839560 | 730 | */ |
AnnaBridge | 163:e59c8e839560 | 731 | #if defined(RCC_CFGR2_ADC1PRES) |
AnnaBridge | 163:e59c8e839560 | 732 | #define LL_RCC_ADC1_CLKSOURCE RCC_CFGR2_ADC1PRES /*!< ADC1 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 733 | #else |
AnnaBridge | 163:e59c8e839560 | 734 | #define LL_RCC_ADC12_CLKSOURCE RCC_CFGR2_ADCPRE12 /*!< ADC12 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 735 | #if defined(RCC_CFGR2_ADCPRE34) |
AnnaBridge | 163:e59c8e839560 | 736 | #define LL_RCC_ADC34_CLKSOURCE RCC_CFGR2_ADCPRE34 /*!< ADC34 Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 737 | #endif /*RCC_CFGR2_ADCPRE34*/ |
AnnaBridge | 163:e59c8e839560 | 738 | #endif /*RCC_CFGR2_ADC1PRES*/ |
AnnaBridge | 163:e59c8e839560 | 739 | /** |
AnnaBridge | 163:e59c8e839560 | 740 | * @} |
AnnaBridge | 163:e59c8e839560 | 741 | */ |
AnnaBridge | 163:e59c8e839560 | 742 | |
AnnaBridge | 163:e59c8e839560 | 743 | #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ |
AnnaBridge | 163:e59c8e839560 | 744 | |
AnnaBridge | 163:e59c8e839560 | 745 | #if defined(RCC_CFGR_SDPRE) |
AnnaBridge | 163:e59c8e839560 | 746 | /** @defgroup RCC_LL_EC_SDADC Peripheral SDADC get clock source |
AnnaBridge | 163:e59c8e839560 | 747 | * @{ |
AnnaBridge | 163:e59c8e839560 | 748 | */ |
AnnaBridge | 163:e59c8e839560 | 749 | #define LL_RCC_SDADC_CLKSOURCE RCC_CFGR_SDPRE /*!< SDADC Clock source selection */ |
AnnaBridge | 163:e59c8e839560 | 750 | /** |
AnnaBridge | 163:e59c8e839560 | 751 | * @} |
AnnaBridge | 163:e59c8e839560 | 752 | */ |
AnnaBridge | 163:e59c8e839560 | 753 | |
AnnaBridge | 163:e59c8e839560 | 754 | #endif /* RCC_CFGR_SDPRE */ |
AnnaBridge | 163:e59c8e839560 | 755 | |
AnnaBridge | 163:e59c8e839560 | 756 | |
AnnaBridge | 163:e59c8e839560 | 757 | /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection |
AnnaBridge | 163:e59c8e839560 | 758 | * @{ |
AnnaBridge | 163:e59c8e839560 | 759 | */ |
AnnaBridge | 168:b9e159c1930a | 760 | #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ |
AnnaBridge | 163:e59c8e839560 | 761 | #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ |
AnnaBridge | 163:e59c8e839560 | 762 | #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ |
AnnaBridge | 163:e59c8e839560 | 763 | #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ |
AnnaBridge | 163:e59c8e839560 | 764 | /** |
AnnaBridge | 163:e59c8e839560 | 765 | * @} |
AnnaBridge | 163:e59c8e839560 | 766 | */ |
AnnaBridge | 163:e59c8e839560 | 767 | |
AnnaBridge | 163:e59c8e839560 | 768 | /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor |
AnnaBridge | 163:e59c8e839560 | 769 | * @{ |
AnnaBridge | 163:e59c8e839560 | 770 | */ |
AnnaBridge | 163:e59c8e839560 | 771 | #define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */ |
AnnaBridge | 163:e59c8e839560 | 772 | #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */ |
AnnaBridge | 163:e59c8e839560 | 773 | #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */ |
AnnaBridge | 163:e59c8e839560 | 774 | #define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */ |
AnnaBridge | 163:e59c8e839560 | 775 | #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */ |
AnnaBridge | 163:e59c8e839560 | 776 | #define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */ |
AnnaBridge | 163:e59c8e839560 | 777 | #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */ |
AnnaBridge | 163:e59c8e839560 | 778 | #define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */ |
AnnaBridge | 163:e59c8e839560 | 779 | #define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */ |
AnnaBridge | 163:e59c8e839560 | 780 | #define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */ |
AnnaBridge | 163:e59c8e839560 | 781 | #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */ |
AnnaBridge | 163:e59c8e839560 | 782 | #define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */ |
AnnaBridge | 163:e59c8e839560 | 783 | #define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */ |
AnnaBridge | 163:e59c8e839560 | 784 | #define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */ |
AnnaBridge | 163:e59c8e839560 | 785 | #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */ |
AnnaBridge | 163:e59c8e839560 | 786 | /** |
AnnaBridge | 163:e59c8e839560 | 787 | * @} |
AnnaBridge | 163:e59c8e839560 | 788 | */ |
AnnaBridge | 163:e59c8e839560 | 789 | |
AnnaBridge | 163:e59c8e839560 | 790 | /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE |
AnnaBridge | 163:e59c8e839560 | 791 | * @{ |
AnnaBridge | 163:e59c8e839560 | 792 | */ |
AnnaBridge | 163:e59c8e839560 | 793 | #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 794 | #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) |
AnnaBridge | 163:e59c8e839560 | 795 | #define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 796 | #else |
AnnaBridge | 163:e59c8e839560 | 797 | #define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 798 | #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) /*!< HSE clock selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 799 | #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 800 | #define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 801 | #define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 802 | #define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 803 | #define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 804 | #define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 805 | #define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 806 | #define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 807 | #define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 808 | #define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 809 | #define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 810 | #define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 811 | #define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 812 | #define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 813 | #define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */ |
AnnaBridge | 163:e59c8e839560 | 814 | #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ |
AnnaBridge | 163:e59c8e839560 | 815 | /** |
AnnaBridge | 163:e59c8e839560 | 816 | * @} |
AnnaBridge | 163:e59c8e839560 | 817 | */ |
AnnaBridge | 163:e59c8e839560 | 818 | |
AnnaBridge | 163:e59c8e839560 | 819 | /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor |
AnnaBridge | 163:e59c8e839560 | 820 | * @{ |
AnnaBridge | 163:e59c8e839560 | 821 | */ |
AnnaBridge | 163:e59c8e839560 | 822 | #define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divided */ |
AnnaBridge | 163:e59c8e839560 | 823 | #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided by 2 */ |
AnnaBridge | 163:e59c8e839560 | 824 | #define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided by 3 */ |
AnnaBridge | 163:e59c8e839560 | 825 | #define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided by 4 */ |
AnnaBridge | 163:e59c8e839560 | 826 | #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided by 5 */ |
AnnaBridge | 163:e59c8e839560 | 827 | #define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided by 6 */ |
AnnaBridge | 163:e59c8e839560 | 828 | #define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided by 7 */ |
AnnaBridge | 163:e59c8e839560 | 829 | #define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided by 8 */ |
AnnaBridge | 163:e59c8e839560 | 830 | #define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided by 9 */ |
AnnaBridge | 163:e59c8e839560 | 831 | #define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided by 10 */ |
AnnaBridge | 163:e59c8e839560 | 832 | #define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided by 11 */ |
AnnaBridge | 163:e59c8e839560 | 833 | #define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided by 12 */ |
AnnaBridge | 163:e59c8e839560 | 834 | #define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided by 13 */ |
AnnaBridge | 163:e59c8e839560 | 835 | #define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided by 14 */ |
AnnaBridge | 163:e59c8e839560 | 836 | #define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided by 15 */ |
AnnaBridge | 163:e59c8e839560 | 837 | #define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided by 16 */ |
AnnaBridge | 163:e59c8e839560 | 838 | /** |
AnnaBridge | 163:e59c8e839560 | 839 | * @} |
AnnaBridge | 163:e59c8e839560 | 840 | */ |
AnnaBridge | 163:e59c8e839560 | 841 | |
AnnaBridge | 163:e59c8e839560 | 842 | /** |
AnnaBridge | 163:e59c8e839560 | 843 | * @} |
AnnaBridge | 163:e59c8e839560 | 844 | */ |
AnnaBridge | 163:e59c8e839560 | 845 | |
AnnaBridge | 163:e59c8e839560 | 846 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 847 | /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros |
AnnaBridge | 163:e59c8e839560 | 848 | * @{ |
AnnaBridge | 163:e59c8e839560 | 849 | */ |
AnnaBridge | 163:e59c8e839560 | 850 | |
AnnaBridge | 163:e59c8e839560 | 851 | /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros |
AnnaBridge | 163:e59c8e839560 | 852 | * @{ |
AnnaBridge | 163:e59c8e839560 | 853 | */ |
AnnaBridge | 163:e59c8e839560 | 854 | |
AnnaBridge | 163:e59c8e839560 | 855 | /** |
AnnaBridge | 163:e59c8e839560 | 856 | * @brief Write a value in RCC register |
AnnaBridge | 163:e59c8e839560 | 857 | * @param __REG__ Register to be written |
AnnaBridge | 163:e59c8e839560 | 858 | * @param __VALUE__ Value to be written in the register |
AnnaBridge | 163:e59c8e839560 | 859 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 860 | */ |
AnnaBridge | 163:e59c8e839560 | 861 | #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) |
AnnaBridge | 163:e59c8e839560 | 862 | |
AnnaBridge | 163:e59c8e839560 | 863 | /** |
AnnaBridge | 163:e59c8e839560 | 864 | * @brief Read a value in RCC register |
AnnaBridge | 163:e59c8e839560 | 865 | * @param __REG__ Register to be read |
AnnaBridge | 163:e59c8e839560 | 866 | * @retval Register value |
AnnaBridge | 163:e59c8e839560 | 867 | */ |
AnnaBridge | 163:e59c8e839560 | 868 | #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) |
AnnaBridge | 163:e59c8e839560 | 869 | /** |
AnnaBridge | 163:e59c8e839560 | 870 | * @} |
AnnaBridge | 163:e59c8e839560 | 871 | */ |
AnnaBridge | 163:e59c8e839560 | 872 | |
AnnaBridge | 163:e59c8e839560 | 873 | /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies |
AnnaBridge | 163:e59c8e839560 | 874 | * @{ |
AnnaBridge | 163:e59c8e839560 | 875 | */ |
AnnaBridge | 163:e59c8e839560 | 876 | |
AnnaBridge | 163:e59c8e839560 | 877 | #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) |
AnnaBridge | 163:e59c8e839560 | 878 | /** |
AnnaBridge | 163:e59c8e839560 | 879 | * @brief Helper macro to calculate the PLLCLK frequency |
AnnaBridge | 163:e59c8e839560 | 880 | * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator() |
AnnaBridge | 163:e59c8e839560 | 881 | * , @ref LL_RCC_PLL_GetPrediv()); |
AnnaBridge | 163:e59c8e839560 | 882 | * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) |
AnnaBridge | 168:b9e159c1930a | 883 | * @param __PLLMUL__ This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 884 | * @arg @ref LL_RCC_PLL_MUL_2 |
AnnaBridge | 163:e59c8e839560 | 885 | * @arg @ref LL_RCC_PLL_MUL_3 |
AnnaBridge | 163:e59c8e839560 | 886 | * @arg @ref LL_RCC_PLL_MUL_4 |
AnnaBridge | 163:e59c8e839560 | 887 | * @arg @ref LL_RCC_PLL_MUL_5 |
AnnaBridge | 163:e59c8e839560 | 888 | * @arg @ref LL_RCC_PLL_MUL_6 |
AnnaBridge | 163:e59c8e839560 | 889 | * @arg @ref LL_RCC_PLL_MUL_7 |
AnnaBridge | 163:e59c8e839560 | 890 | * @arg @ref LL_RCC_PLL_MUL_8 |
AnnaBridge | 163:e59c8e839560 | 891 | * @arg @ref LL_RCC_PLL_MUL_9 |
AnnaBridge | 163:e59c8e839560 | 892 | * @arg @ref LL_RCC_PLL_MUL_10 |
AnnaBridge | 163:e59c8e839560 | 893 | * @arg @ref LL_RCC_PLL_MUL_11 |
AnnaBridge | 163:e59c8e839560 | 894 | * @arg @ref LL_RCC_PLL_MUL_12 |
AnnaBridge | 163:e59c8e839560 | 895 | * @arg @ref LL_RCC_PLL_MUL_13 |
AnnaBridge | 163:e59c8e839560 | 896 | * @arg @ref LL_RCC_PLL_MUL_14 |
AnnaBridge | 163:e59c8e839560 | 897 | * @arg @ref LL_RCC_PLL_MUL_15 |
AnnaBridge | 163:e59c8e839560 | 898 | * @arg @ref LL_RCC_PLL_MUL_16 |
AnnaBridge | 168:b9e159c1930a | 899 | * @param __PLLPREDIV__ This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 900 | * @arg @ref LL_RCC_PREDIV_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 901 | * @arg @ref LL_RCC_PREDIV_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 902 | * @arg @ref LL_RCC_PREDIV_DIV_3 |
AnnaBridge | 163:e59c8e839560 | 903 | * @arg @ref LL_RCC_PREDIV_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 904 | * @arg @ref LL_RCC_PREDIV_DIV_5 |
AnnaBridge | 163:e59c8e839560 | 905 | * @arg @ref LL_RCC_PREDIV_DIV_6 |
AnnaBridge | 163:e59c8e839560 | 906 | * @arg @ref LL_RCC_PREDIV_DIV_7 |
AnnaBridge | 163:e59c8e839560 | 907 | * @arg @ref LL_RCC_PREDIV_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 908 | * @arg @ref LL_RCC_PREDIV_DIV_9 |
AnnaBridge | 163:e59c8e839560 | 909 | * @arg @ref LL_RCC_PREDIV_DIV_10 |
AnnaBridge | 163:e59c8e839560 | 910 | * @arg @ref LL_RCC_PREDIV_DIV_11 |
AnnaBridge | 163:e59c8e839560 | 911 | * @arg @ref LL_RCC_PREDIV_DIV_12 |
AnnaBridge | 163:e59c8e839560 | 912 | * @arg @ref LL_RCC_PREDIV_DIV_13 |
AnnaBridge | 163:e59c8e839560 | 913 | * @arg @ref LL_RCC_PREDIV_DIV_14 |
AnnaBridge | 163:e59c8e839560 | 914 | * @arg @ref LL_RCC_PREDIV_DIV_15 |
AnnaBridge | 163:e59c8e839560 | 915 | * @arg @ref LL_RCC_PREDIV_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 916 | * @retval PLL clock frequency (in Hz) |
AnnaBridge | 163:e59c8e839560 | 917 | */ |
AnnaBridge | 163:e59c8e839560 | 918 | #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \ |
AnnaBridge | 163:e59c8e839560 | 919 | (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) |
AnnaBridge | 163:e59c8e839560 | 920 | |
AnnaBridge | 163:e59c8e839560 | 921 | #else |
AnnaBridge | 163:e59c8e839560 | 922 | /** |
AnnaBridge | 163:e59c8e839560 | 923 | * @brief Helper macro to calculate the PLLCLK frequency |
AnnaBridge | 163:e59c8e839560 | 924 | * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator()); |
AnnaBridge | 163:e59c8e839560 | 925 | * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2) |
AnnaBridge | 168:b9e159c1930a | 926 | * @param __PLLMUL__ This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 927 | * @arg @ref LL_RCC_PLL_MUL_2 |
AnnaBridge | 163:e59c8e839560 | 928 | * @arg @ref LL_RCC_PLL_MUL_3 |
AnnaBridge | 163:e59c8e839560 | 929 | * @arg @ref LL_RCC_PLL_MUL_4 |
AnnaBridge | 163:e59c8e839560 | 930 | * @arg @ref LL_RCC_PLL_MUL_5 |
AnnaBridge | 163:e59c8e839560 | 931 | * @arg @ref LL_RCC_PLL_MUL_6 |
AnnaBridge | 163:e59c8e839560 | 932 | * @arg @ref LL_RCC_PLL_MUL_7 |
AnnaBridge | 163:e59c8e839560 | 933 | * @arg @ref LL_RCC_PLL_MUL_8 |
AnnaBridge | 163:e59c8e839560 | 934 | * @arg @ref LL_RCC_PLL_MUL_9 |
AnnaBridge | 163:e59c8e839560 | 935 | * @arg @ref LL_RCC_PLL_MUL_10 |
AnnaBridge | 163:e59c8e839560 | 936 | * @arg @ref LL_RCC_PLL_MUL_11 |
AnnaBridge | 163:e59c8e839560 | 937 | * @arg @ref LL_RCC_PLL_MUL_12 |
AnnaBridge | 163:e59c8e839560 | 938 | * @arg @ref LL_RCC_PLL_MUL_13 |
AnnaBridge | 163:e59c8e839560 | 939 | * @arg @ref LL_RCC_PLL_MUL_14 |
AnnaBridge | 163:e59c8e839560 | 940 | * @arg @ref LL_RCC_PLL_MUL_15 |
AnnaBridge | 163:e59c8e839560 | 941 | * @arg @ref LL_RCC_PLL_MUL_16 |
AnnaBridge | 163:e59c8e839560 | 942 | * @retval PLL clock frequency (in Hz) |
AnnaBridge | 163:e59c8e839560 | 943 | */ |
AnnaBridge | 163:e59c8e839560 | 944 | #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ |
AnnaBridge | 163:e59c8e839560 | 945 | ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) |
AnnaBridge | 163:e59c8e839560 | 946 | #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ |
AnnaBridge | 163:e59c8e839560 | 947 | /** |
AnnaBridge | 163:e59c8e839560 | 948 | * @brief Helper macro to calculate the HCLK frequency |
AnnaBridge | 163:e59c8e839560 | 949 | * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler |
AnnaBridge | 163:e59c8e839560 | 950 | * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) |
AnnaBridge | 163:e59c8e839560 | 951 | * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) |
AnnaBridge | 168:b9e159c1930a | 952 | * @param __AHBPRESCALER__ This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 953 | * @arg @ref LL_RCC_SYSCLK_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 954 | * @arg @ref LL_RCC_SYSCLK_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 955 | * @arg @ref LL_RCC_SYSCLK_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 956 | * @arg @ref LL_RCC_SYSCLK_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 957 | * @arg @ref LL_RCC_SYSCLK_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 958 | * @arg @ref LL_RCC_SYSCLK_DIV_64 |
AnnaBridge | 163:e59c8e839560 | 959 | * @arg @ref LL_RCC_SYSCLK_DIV_128 |
AnnaBridge | 163:e59c8e839560 | 960 | * @arg @ref LL_RCC_SYSCLK_DIV_256 |
AnnaBridge | 163:e59c8e839560 | 961 | * @arg @ref LL_RCC_SYSCLK_DIV_512 |
AnnaBridge | 163:e59c8e839560 | 962 | * @retval HCLK clock frequency (in Hz) |
AnnaBridge | 163:e59c8e839560 | 963 | */ |
AnnaBridge | 168:b9e159c1930a | 964 | #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) |
AnnaBridge | 163:e59c8e839560 | 965 | |
AnnaBridge | 163:e59c8e839560 | 966 | /** |
AnnaBridge | 163:e59c8e839560 | 967 | * @brief Helper macro to calculate the PCLK1 frequency (ABP1) |
AnnaBridge | 163:e59c8e839560 | 968 | * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler |
AnnaBridge | 163:e59c8e839560 | 969 | * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) |
AnnaBridge | 163:e59c8e839560 | 970 | * @param __HCLKFREQ__ HCLK frequency |
AnnaBridge | 163:e59c8e839560 | 971 | * @param __APB1PRESCALER__: This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 972 | * @arg @ref LL_RCC_APB1_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 973 | * @arg @ref LL_RCC_APB1_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 974 | * @arg @ref LL_RCC_APB1_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 975 | * @arg @ref LL_RCC_APB1_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 976 | * @arg @ref LL_RCC_APB1_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 977 | * @retval PCLK1 clock frequency (in Hz) |
AnnaBridge | 163:e59c8e839560 | 978 | */ |
AnnaBridge | 168:b9e159c1930a | 979 | #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) |
AnnaBridge | 163:e59c8e839560 | 980 | |
AnnaBridge | 163:e59c8e839560 | 981 | /** |
AnnaBridge | 163:e59c8e839560 | 982 | * @brief Helper macro to calculate the PCLK2 frequency (ABP2) |
AnnaBridge | 163:e59c8e839560 | 983 | * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler |
AnnaBridge | 163:e59c8e839560 | 984 | * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler()) |
AnnaBridge | 163:e59c8e839560 | 985 | * @param __HCLKFREQ__ HCLK frequency |
AnnaBridge | 163:e59c8e839560 | 986 | * @param __APB2PRESCALER__: This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 987 | * @arg @ref LL_RCC_APB2_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 988 | * @arg @ref LL_RCC_APB2_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 989 | * @arg @ref LL_RCC_APB2_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 990 | * @arg @ref LL_RCC_APB2_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 991 | * @arg @ref LL_RCC_APB2_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 992 | * @retval PCLK2 clock frequency (in Hz) |
AnnaBridge | 163:e59c8e839560 | 993 | */ |
AnnaBridge | 168:b9e159c1930a | 994 | #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) |
AnnaBridge | 163:e59c8e839560 | 995 | |
AnnaBridge | 163:e59c8e839560 | 996 | /** |
AnnaBridge | 163:e59c8e839560 | 997 | * @} |
AnnaBridge | 163:e59c8e839560 | 998 | */ |
AnnaBridge | 163:e59c8e839560 | 999 | |
AnnaBridge | 163:e59c8e839560 | 1000 | /** |
AnnaBridge | 163:e59c8e839560 | 1001 | * @} |
AnnaBridge | 163:e59c8e839560 | 1002 | */ |
AnnaBridge | 163:e59c8e839560 | 1003 | |
AnnaBridge | 163:e59c8e839560 | 1004 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 163:e59c8e839560 | 1005 | /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions |
AnnaBridge | 163:e59c8e839560 | 1006 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1007 | */ |
AnnaBridge | 163:e59c8e839560 | 1008 | |
AnnaBridge | 163:e59c8e839560 | 1009 | /** @defgroup RCC_LL_EF_HSE HSE |
AnnaBridge | 163:e59c8e839560 | 1010 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1011 | */ |
AnnaBridge | 163:e59c8e839560 | 1012 | |
AnnaBridge | 163:e59c8e839560 | 1013 | /** |
AnnaBridge | 163:e59c8e839560 | 1014 | * @brief Enable the Clock Security System. |
AnnaBridge | 163:e59c8e839560 | 1015 | * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS |
AnnaBridge | 163:e59c8e839560 | 1016 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1017 | */ |
AnnaBridge | 163:e59c8e839560 | 1018 | __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) |
AnnaBridge | 163:e59c8e839560 | 1019 | { |
AnnaBridge | 163:e59c8e839560 | 1020 | SET_BIT(RCC->CR, RCC_CR_CSSON); |
AnnaBridge | 163:e59c8e839560 | 1021 | } |
AnnaBridge | 163:e59c8e839560 | 1022 | |
AnnaBridge | 163:e59c8e839560 | 1023 | /** |
AnnaBridge | 163:e59c8e839560 | 1024 | * @brief Disable the Clock Security System. |
AnnaBridge | 163:e59c8e839560 | 1025 | * @note Cannot be disabled in HSE is ready (only by hardware) |
AnnaBridge | 163:e59c8e839560 | 1026 | * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS |
AnnaBridge | 163:e59c8e839560 | 1027 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1028 | */ |
AnnaBridge | 163:e59c8e839560 | 1029 | __STATIC_INLINE void LL_RCC_HSE_DisableCSS(void) |
AnnaBridge | 163:e59c8e839560 | 1030 | { |
AnnaBridge | 163:e59c8e839560 | 1031 | CLEAR_BIT(RCC->CR, RCC_CR_CSSON); |
AnnaBridge | 163:e59c8e839560 | 1032 | } |
AnnaBridge | 163:e59c8e839560 | 1033 | |
AnnaBridge | 163:e59c8e839560 | 1034 | /** |
AnnaBridge | 163:e59c8e839560 | 1035 | * @brief Enable HSE external oscillator (HSE Bypass) |
AnnaBridge | 163:e59c8e839560 | 1036 | * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass |
AnnaBridge | 163:e59c8e839560 | 1037 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1038 | */ |
AnnaBridge | 163:e59c8e839560 | 1039 | __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) |
AnnaBridge | 163:e59c8e839560 | 1040 | { |
AnnaBridge | 163:e59c8e839560 | 1041 | SET_BIT(RCC->CR, RCC_CR_HSEBYP); |
AnnaBridge | 163:e59c8e839560 | 1042 | } |
AnnaBridge | 163:e59c8e839560 | 1043 | |
AnnaBridge | 163:e59c8e839560 | 1044 | /** |
AnnaBridge | 163:e59c8e839560 | 1045 | * @brief Disable HSE external oscillator (HSE Bypass) |
AnnaBridge | 163:e59c8e839560 | 1046 | * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass |
AnnaBridge | 163:e59c8e839560 | 1047 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1048 | */ |
AnnaBridge | 163:e59c8e839560 | 1049 | __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) |
AnnaBridge | 163:e59c8e839560 | 1050 | { |
AnnaBridge | 163:e59c8e839560 | 1051 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); |
AnnaBridge | 163:e59c8e839560 | 1052 | } |
AnnaBridge | 163:e59c8e839560 | 1053 | |
AnnaBridge | 163:e59c8e839560 | 1054 | /** |
AnnaBridge | 163:e59c8e839560 | 1055 | * @brief Enable HSE crystal oscillator (HSE ON) |
AnnaBridge | 163:e59c8e839560 | 1056 | * @rmtoll CR HSEON LL_RCC_HSE_Enable |
AnnaBridge | 163:e59c8e839560 | 1057 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1058 | */ |
AnnaBridge | 163:e59c8e839560 | 1059 | __STATIC_INLINE void LL_RCC_HSE_Enable(void) |
AnnaBridge | 163:e59c8e839560 | 1060 | { |
AnnaBridge | 163:e59c8e839560 | 1061 | SET_BIT(RCC->CR, RCC_CR_HSEON); |
AnnaBridge | 163:e59c8e839560 | 1062 | } |
AnnaBridge | 163:e59c8e839560 | 1063 | |
AnnaBridge | 163:e59c8e839560 | 1064 | /** |
AnnaBridge | 163:e59c8e839560 | 1065 | * @brief Disable HSE crystal oscillator (HSE ON) |
AnnaBridge | 163:e59c8e839560 | 1066 | * @rmtoll CR HSEON LL_RCC_HSE_Disable |
AnnaBridge | 163:e59c8e839560 | 1067 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1068 | */ |
AnnaBridge | 163:e59c8e839560 | 1069 | __STATIC_INLINE void LL_RCC_HSE_Disable(void) |
AnnaBridge | 163:e59c8e839560 | 1070 | { |
AnnaBridge | 163:e59c8e839560 | 1071 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); |
AnnaBridge | 163:e59c8e839560 | 1072 | } |
AnnaBridge | 163:e59c8e839560 | 1073 | |
AnnaBridge | 163:e59c8e839560 | 1074 | /** |
AnnaBridge | 163:e59c8e839560 | 1075 | * @brief Check if HSE oscillator Ready |
AnnaBridge | 163:e59c8e839560 | 1076 | * @rmtoll CR HSERDY LL_RCC_HSE_IsReady |
AnnaBridge | 163:e59c8e839560 | 1077 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 1078 | */ |
AnnaBridge | 163:e59c8e839560 | 1079 | __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) |
AnnaBridge | 163:e59c8e839560 | 1080 | { |
AnnaBridge | 163:e59c8e839560 | 1081 | return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); |
AnnaBridge | 163:e59c8e839560 | 1082 | } |
AnnaBridge | 163:e59c8e839560 | 1083 | |
AnnaBridge | 163:e59c8e839560 | 1084 | /** |
AnnaBridge | 163:e59c8e839560 | 1085 | * @} |
AnnaBridge | 163:e59c8e839560 | 1086 | */ |
AnnaBridge | 163:e59c8e839560 | 1087 | |
AnnaBridge | 163:e59c8e839560 | 1088 | /** @defgroup RCC_LL_EF_HSI HSI |
AnnaBridge | 163:e59c8e839560 | 1089 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1090 | */ |
AnnaBridge | 163:e59c8e839560 | 1091 | |
AnnaBridge | 163:e59c8e839560 | 1092 | /** |
AnnaBridge | 163:e59c8e839560 | 1093 | * @brief Enable HSI oscillator |
AnnaBridge | 163:e59c8e839560 | 1094 | * @rmtoll CR HSION LL_RCC_HSI_Enable |
AnnaBridge | 163:e59c8e839560 | 1095 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1096 | */ |
AnnaBridge | 163:e59c8e839560 | 1097 | __STATIC_INLINE void LL_RCC_HSI_Enable(void) |
AnnaBridge | 163:e59c8e839560 | 1098 | { |
AnnaBridge | 163:e59c8e839560 | 1099 | SET_BIT(RCC->CR, RCC_CR_HSION); |
AnnaBridge | 163:e59c8e839560 | 1100 | } |
AnnaBridge | 163:e59c8e839560 | 1101 | |
AnnaBridge | 163:e59c8e839560 | 1102 | /** |
AnnaBridge | 163:e59c8e839560 | 1103 | * @brief Disable HSI oscillator |
AnnaBridge | 163:e59c8e839560 | 1104 | * @rmtoll CR HSION LL_RCC_HSI_Disable |
AnnaBridge | 163:e59c8e839560 | 1105 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1106 | */ |
AnnaBridge | 163:e59c8e839560 | 1107 | __STATIC_INLINE void LL_RCC_HSI_Disable(void) |
AnnaBridge | 163:e59c8e839560 | 1108 | { |
AnnaBridge | 163:e59c8e839560 | 1109 | CLEAR_BIT(RCC->CR, RCC_CR_HSION); |
AnnaBridge | 163:e59c8e839560 | 1110 | } |
AnnaBridge | 163:e59c8e839560 | 1111 | |
AnnaBridge | 163:e59c8e839560 | 1112 | /** |
AnnaBridge | 163:e59c8e839560 | 1113 | * @brief Check if HSI clock is ready |
AnnaBridge | 163:e59c8e839560 | 1114 | * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady |
AnnaBridge | 163:e59c8e839560 | 1115 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 1116 | */ |
AnnaBridge | 163:e59c8e839560 | 1117 | __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) |
AnnaBridge | 163:e59c8e839560 | 1118 | { |
AnnaBridge | 163:e59c8e839560 | 1119 | return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); |
AnnaBridge | 163:e59c8e839560 | 1120 | } |
AnnaBridge | 163:e59c8e839560 | 1121 | |
AnnaBridge | 163:e59c8e839560 | 1122 | /** |
AnnaBridge | 163:e59c8e839560 | 1123 | * @brief Get HSI Calibration value |
AnnaBridge | 163:e59c8e839560 | 1124 | * @note When HSITRIM is written, HSICAL is updated with the sum of |
AnnaBridge | 163:e59c8e839560 | 1125 | * HSITRIM and the factory trim value |
AnnaBridge | 163:e59c8e839560 | 1126 | * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration |
AnnaBridge | 163:e59c8e839560 | 1127 | * @retval Between Min_Data = 0x00 and Max_Data = 0xFF |
AnnaBridge | 163:e59c8e839560 | 1128 | */ |
AnnaBridge | 163:e59c8e839560 | 1129 | __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) |
AnnaBridge | 163:e59c8e839560 | 1130 | { |
AnnaBridge | 168:b9e159c1930a | 1131 | return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); |
AnnaBridge | 163:e59c8e839560 | 1132 | } |
AnnaBridge | 163:e59c8e839560 | 1133 | |
AnnaBridge | 163:e59c8e839560 | 1134 | /** |
AnnaBridge | 163:e59c8e839560 | 1135 | * @brief Set HSI Calibration trimming |
AnnaBridge | 163:e59c8e839560 | 1136 | * @note user-programmable trimming value that is added to the HSICAL |
AnnaBridge | 163:e59c8e839560 | 1137 | * @note Default value is 16, which, when added to the HSICAL value, |
AnnaBridge | 163:e59c8e839560 | 1138 | * should trim the HSI to 16 MHz +/- 1 % |
AnnaBridge | 163:e59c8e839560 | 1139 | * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming |
AnnaBridge | 163:e59c8e839560 | 1140 | * @param Value between Min_Data = 0x00 and Max_Data = 0x1F |
AnnaBridge | 163:e59c8e839560 | 1141 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1142 | */ |
AnnaBridge | 163:e59c8e839560 | 1143 | __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) |
AnnaBridge | 163:e59c8e839560 | 1144 | { |
AnnaBridge | 168:b9e159c1930a | 1145 | MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); |
AnnaBridge | 163:e59c8e839560 | 1146 | } |
AnnaBridge | 163:e59c8e839560 | 1147 | |
AnnaBridge | 163:e59c8e839560 | 1148 | /** |
AnnaBridge | 163:e59c8e839560 | 1149 | * @brief Get HSI Calibration trimming |
AnnaBridge | 163:e59c8e839560 | 1150 | * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming |
AnnaBridge | 163:e59c8e839560 | 1151 | * @retval Between Min_Data = 0x00 and Max_Data = 0x1F |
AnnaBridge | 163:e59c8e839560 | 1152 | */ |
AnnaBridge | 163:e59c8e839560 | 1153 | __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) |
AnnaBridge | 163:e59c8e839560 | 1154 | { |
AnnaBridge | 168:b9e159c1930a | 1155 | return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); |
AnnaBridge | 163:e59c8e839560 | 1156 | } |
AnnaBridge | 163:e59c8e839560 | 1157 | |
AnnaBridge | 163:e59c8e839560 | 1158 | /** |
AnnaBridge | 163:e59c8e839560 | 1159 | * @} |
AnnaBridge | 163:e59c8e839560 | 1160 | */ |
AnnaBridge | 163:e59c8e839560 | 1161 | |
AnnaBridge | 163:e59c8e839560 | 1162 | /** @defgroup RCC_LL_EF_LSE LSE |
AnnaBridge | 163:e59c8e839560 | 1163 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1164 | */ |
AnnaBridge | 163:e59c8e839560 | 1165 | |
AnnaBridge | 163:e59c8e839560 | 1166 | /** |
AnnaBridge | 163:e59c8e839560 | 1167 | * @brief Enable Low Speed External (LSE) crystal. |
AnnaBridge | 163:e59c8e839560 | 1168 | * @rmtoll BDCR LSEON LL_RCC_LSE_Enable |
AnnaBridge | 163:e59c8e839560 | 1169 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1170 | */ |
AnnaBridge | 163:e59c8e839560 | 1171 | __STATIC_INLINE void LL_RCC_LSE_Enable(void) |
AnnaBridge | 163:e59c8e839560 | 1172 | { |
AnnaBridge | 163:e59c8e839560 | 1173 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); |
AnnaBridge | 163:e59c8e839560 | 1174 | } |
AnnaBridge | 163:e59c8e839560 | 1175 | |
AnnaBridge | 163:e59c8e839560 | 1176 | /** |
AnnaBridge | 163:e59c8e839560 | 1177 | * @brief Disable Low Speed External (LSE) crystal. |
AnnaBridge | 163:e59c8e839560 | 1178 | * @rmtoll BDCR LSEON LL_RCC_LSE_Disable |
AnnaBridge | 163:e59c8e839560 | 1179 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1180 | */ |
AnnaBridge | 163:e59c8e839560 | 1181 | __STATIC_INLINE void LL_RCC_LSE_Disable(void) |
AnnaBridge | 163:e59c8e839560 | 1182 | { |
AnnaBridge | 163:e59c8e839560 | 1183 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); |
AnnaBridge | 163:e59c8e839560 | 1184 | } |
AnnaBridge | 163:e59c8e839560 | 1185 | |
AnnaBridge | 163:e59c8e839560 | 1186 | /** |
AnnaBridge | 163:e59c8e839560 | 1187 | * @brief Enable external clock source (LSE bypass). |
AnnaBridge | 163:e59c8e839560 | 1188 | * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass |
AnnaBridge | 163:e59c8e839560 | 1189 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1190 | */ |
AnnaBridge | 163:e59c8e839560 | 1191 | __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) |
AnnaBridge | 163:e59c8e839560 | 1192 | { |
AnnaBridge | 163:e59c8e839560 | 1193 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); |
AnnaBridge | 163:e59c8e839560 | 1194 | } |
AnnaBridge | 163:e59c8e839560 | 1195 | |
AnnaBridge | 163:e59c8e839560 | 1196 | /** |
AnnaBridge | 163:e59c8e839560 | 1197 | * @brief Disable external clock source (LSE bypass). |
AnnaBridge | 163:e59c8e839560 | 1198 | * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass |
AnnaBridge | 163:e59c8e839560 | 1199 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1200 | */ |
AnnaBridge | 163:e59c8e839560 | 1201 | __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) |
AnnaBridge | 163:e59c8e839560 | 1202 | { |
AnnaBridge | 163:e59c8e839560 | 1203 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); |
AnnaBridge | 163:e59c8e839560 | 1204 | } |
AnnaBridge | 163:e59c8e839560 | 1205 | |
AnnaBridge | 163:e59c8e839560 | 1206 | /** |
AnnaBridge | 163:e59c8e839560 | 1207 | * @brief Set LSE oscillator drive capability |
AnnaBridge | 163:e59c8e839560 | 1208 | * @note The oscillator is in Xtal mode when it is not in bypass mode. |
AnnaBridge | 163:e59c8e839560 | 1209 | * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability |
AnnaBridge | 163:e59c8e839560 | 1210 | * @param LSEDrive This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1211 | * @arg @ref LL_RCC_LSEDRIVE_LOW |
AnnaBridge | 163:e59c8e839560 | 1212 | * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW |
AnnaBridge | 163:e59c8e839560 | 1213 | * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH |
AnnaBridge | 163:e59c8e839560 | 1214 | * @arg @ref LL_RCC_LSEDRIVE_HIGH |
AnnaBridge | 163:e59c8e839560 | 1215 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1216 | */ |
AnnaBridge | 163:e59c8e839560 | 1217 | __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) |
AnnaBridge | 163:e59c8e839560 | 1218 | { |
AnnaBridge | 163:e59c8e839560 | 1219 | MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); |
AnnaBridge | 163:e59c8e839560 | 1220 | } |
AnnaBridge | 163:e59c8e839560 | 1221 | |
AnnaBridge | 163:e59c8e839560 | 1222 | /** |
AnnaBridge | 163:e59c8e839560 | 1223 | * @brief Get LSE oscillator drive capability |
AnnaBridge | 163:e59c8e839560 | 1224 | * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability |
AnnaBridge | 163:e59c8e839560 | 1225 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1226 | * @arg @ref LL_RCC_LSEDRIVE_LOW |
AnnaBridge | 163:e59c8e839560 | 1227 | * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW |
AnnaBridge | 163:e59c8e839560 | 1228 | * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH |
AnnaBridge | 163:e59c8e839560 | 1229 | * @arg @ref LL_RCC_LSEDRIVE_HIGH |
AnnaBridge | 163:e59c8e839560 | 1230 | */ |
AnnaBridge | 163:e59c8e839560 | 1231 | __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) |
AnnaBridge | 163:e59c8e839560 | 1232 | { |
AnnaBridge | 163:e59c8e839560 | 1233 | return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); |
AnnaBridge | 163:e59c8e839560 | 1234 | } |
AnnaBridge | 163:e59c8e839560 | 1235 | |
AnnaBridge | 163:e59c8e839560 | 1236 | /** |
AnnaBridge | 163:e59c8e839560 | 1237 | * @brief Check if LSE oscillator Ready |
AnnaBridge | 163:e59c8e839560 | 1238 | * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady |
AnnaBridge | 163:e59c8e839560 | 1239 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 1240 | */ |
AnnaBridge | 163:e59c8e839560 | 1241 | __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) |
AnnaBridge | 163:e59c8e839560 | 1242 | { |
AnnaBridge | 163:e59c8e839560 | 1243 | return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); |
AnnaBridge | 163:e59c8e839560 | 1244 | } |
AnnaBridge | 163:e59c8e839560 | 1245 | |
AnnaBridge | 163:e59c8e839560 | 1246 | /** |
AnnaBridge | 163:e59c8e839560 | 1247 | * @} |
AnnaBridge | 163:e59c8e839560 | 1248 | */ |
AnnaBridge | 163:e59c8e839560 | 1249 | |
AnnaBridge | 163:e59c8e839560 | 1250 | /** @defgroup RCC_LL_EF_LSI LSI |
AnnaBridge | 163:e59c8e839560 | 1251 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1252 | */ |
AnnaBridge | 163:e59c8e839560 | 1253 | |
AnnaBridge | 163:e59c8e839560 | 1254 | /** |
AnnaBridge | 163:e59c8e839560 | 1255 | * @brief Enable LSI Oscillator |
AnnaBridge | 163:e59c8e839560 | 1256 | * @rmtoll CSR LSION LL_RCC_LSI_Enable |
AnnaBridge | 163:e59c8e839560 | 1257 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1258 | */ |
AnnaBridge | 163:e59c8e839560 | 1259 | __STATIC_INLINE void LL_RCC_LSI_Enable(void) |
AnnaBridge | 163:e59c8e839560 | 1260 | { |
AnnaBridge | 163:e59c8e839560 | 1261 | SET_BIT(RCC->CSR, RCC_CSR_LSION); |
AnnaBridge | 163:e59c8e839560 | 1262 | } |
AnnaBridge | 163:e59c8e839560 | 1263 | |
AnnaBridge | 163:e59c8e839560 | 1264 | /** |
AnnaBridge | 163:e59c8e839560 | 1265 | * @brief Disable LSI Oscillator |
AnnaBridge | 163:e59c8e839560 | 1266 | * @rmtoll CSR LSION LL_RCC_LSI_Disable |
AnnaBridge | 163:e59c8e839560 | 1267 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1268 | */ |
AnnaBridge | 163:e59c8e839560 | 1269 | __STATIC_INLINE void LL_RCC_LSI_Disable(void) |
AnnaBridge | 163:e59c8e839560 | 1270 | { |
AnnaBridge | 163:e59c8e839560 | 1271 | CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); |
AnnaBridge | 163:e59c8e839560 | 1272 | } |
AnnaBridge | 163:e59c8e839560 | 1273 | |
AnnaBridge | 163:e59c8e839560 | 1274 | /** |
AnnaBridge | 163:e59c8e839560 | 1275 | * @brief Check if LSI is Ready |
AnnaBridge | 163:e59c8e839560 | 1276 | * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady |
AnnaBridge | 163:e59c8e839560 | 1277 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 1278 | */ |
AnnaBridge | 163:e59c8e839560 | 1279 | __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) |
AnnaBridge | 163:e59c8e839560 | 1280 | { |
AnnaBridge | 163:e59c8e839560 | 1281 | return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); |
AnnaBridge | 163:e59c8e839560 | 1282 | } |
AnnaBridge | 163:e59c8e839560 | 1283 | |
AnnaBridge | 163:e59c8e839560 | 1284 | /** |
AnnaBridge | 163:e59c8e839560 | 1285 | * @} |
AnnaBridge | 163:e59c8e839560 | 1286 | */ |
AnnaBridge | 163:e59c8e839560 | 1287 | |
AnnaBridge | 163:e59c8e839560 | 1288 | /** @defgroup RCC_LL_EF_System System |
AnnaBridge | 163:e59c8e839560 | 1289 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1290 | */ |
AnnaBridge | 163:e59c8e839560 | 1291 | |
AnnaBridge | 163:e59c8e839560 | 1292 | /** |
AnnaBridge | 163:e59c8e839560 | 1293 | * @brief Configure the system clock source |
AnnaBridge | 163:e59c8e839560 | 1294 | * @rmtoll CFGR SW LL_RCC_SetSysClkSource |
AnnaBridge | 163:e59c8e839560 | 1295 | * @param Source This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1296 | * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI |
AnnaBridge | 163:e59c8e839560 | 1297 | * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE |
AnnaBridge | 163:e59c8e839560 | 1298 | * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL |
AnnaBridge | 163:e59c8e839560 | 1299 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1300 | */ |
AnnaBridge | 163:e59c8e839560 | 1301 | __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) |
AnnaBridge | 163:e59c8e839560 | 1302 | { |
AnnaBridge | 163:e59c8e839560 | 1303 | MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); |
AnnaBridge | 163:e59c8e839560 | 1304 | } |
AnnaBridge | 163:e59c8e839560 | 1305 | |
AnnaBridge | 163:e59c8e839560 | 1306 | /** |
AnnaBridge | 163:e59c8e839560 | 1307 | * @brief Get the system clock source |
AnnaBridge | 163:e59c8e839560 | 1308 | * @rmtoll CFGR SWS LL_RCC_GetSysClkSource |
AnnaBridge | 163:e59c8e839560 | 1309 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1310 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI |
AnnaBridge | 163:e59c8e839560 | 1311 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE |
AnnaBridge | 163:e59c8e839560 | 1312 | * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL |
AnnaBridge | 163:e59c8e839560 | 1313 | */ |
AnnaBridge | 163:e59c8e839560 | 1314 | __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) |
AnnaBridge | 163:e59c8e839560 | 1315 | { |
AnnaBridge | 163:e59c8e839560 | 1316 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); |
AnnaBridge | 163:e59c8e839560 | 1317 | } |
AnnaBridge | 163:e59c8e839560 | 1318 | |
AnnaBridge | 163:e59c8e839560 | 1319 | /** |
AnnaBridge | 163:e59c8e839560 | 1320 | * @brief Set AHB prescaler |
AnnaBridge | 163:e59c8e839560 | 1321 | * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler |
AnnaBridge | 163:e59c8e839560 | 1322 | * @param Prescaler This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1323 | * @arg @ref LL_RCC_SYSCLK_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 1324 | * @arg @ref LL_RCC_SYSCLK_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 1325 | * @arg @ref LL_RCC_SYSCLK_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 1326 | * @arg @ref LL_RCC_SYSCLK_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 1327 | * @arg @ref LL_RCC_SYSCLK_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 1328 | * @arg @ref LL_RCC_SYSCLK_DIV_64 |
AnnaBridge | 163:e59c8e839560 | 1329 | * @arg @ref LL_RCC_SYSCLK_DIV_128 |
AnnaBridge | 163:e59c8e839560 | 1330 | * @arg @ref LL_RCC_SYSCLK_DIV_256 |
AnnaBridge | 163:e59c8e839560 | 1331 | * @arg @ref LL_RCC_SYSCLK_DIV_512 |
AnnaBridge | 163:e59c8e839560 | 1332 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1333 | */ |
AnnaBridge | 163:e59c8e839560 | 1334 | __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) |
AnnaBridge | 163:e59c8e839560 | 1335 | { |
AnnaBridge | 163:e59c8e839560 | 1336 | MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); |
AnnaBridge | 163:e59c8e839560 | 1337 | } |
AnnaBridge | 163:e59c8e839560 | 1338 | |
AnnaBridge | 163:e59c8e839560 | 1339 | /** |
AnnaBridge | 163:e59c8e839560 | 1340 | * @brief Set APB1 prescaler |
AnnaBridge | 163:e59c8e839560 | 1341 | * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler |
AnnaBridge | 163:e59c8e839560 | 1342 | * @param Prescaler This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1343 | * @arg @ref LL_RCC_APB1_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 1344 | * @arg @ref LL_RCC_APB1_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 1345 | * @arg @ref LL_RCC_APB1_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 1346 | * @arg @ref LL_RCC_APB1_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 1347 | * @arg @ref LL_RCC_APB1_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 1348 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1349 | */ |
AnnaBridge | 163:e59c8e839560 | 1350 | __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) |
AnnaBridge | 163:e59c8e839560 | 1351 | { |
AnnaBridge | 163:e59c8e839560 | 1352 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); |
AnnaBridge | 163:e59c8e839560 | 1353 | } |
AnnaBridge | 163:e59c8e839560 | 1354 | |
AnnaBridge | 163:e59c8e839560 | 1355 | /** |
AnnaBridge | 163:e59c8e839560 | 1356 | * @brief Set APB2 prescaler |
AnnaBridge | 163:e59c8e839560 | 1357 | * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler |
AnnaBridge | 163:e59c8e839560 | 1358 | * @param Prescaler This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1359 | * @arg @ref LL_RCC_APB2_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 1360 | * @arg @ref LL_RCC_APB2_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 1361 | * @arg @ref LL_RCC_APB2_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 1362 | * @arg @ref LL_RCC_APB2_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 1363 | * @arg @ref LL_RCC_APB2_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 1364 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1365 | */ |
AnnaBridge | 163:e59c8e839560 | 1366 | __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) |
AnnaBridge | 163:e59c8e839560 | 1367 | { |
AnnaBridge | 163:e59c8e839560 | 1368 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); |
AnnaBridge | 163:e59c8e839560 | 1369 | } |
AnnaBridge | 163:e59c8e839560 | 1370 | |
AnnaBridge | 163:e59c8e839560 | 1371 | /** |
AnnaBridge | 163:e59c8e839560 | 1372 | * @brief Get AHB prescaler |
AnnaBridge | 163:e59c8e839560 | 1373 | * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler |
AnnaBridge | 163:e59c8e839560 | 1374 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1375 | * @arg @ref LL_RCC_SYSCLK_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 1376 | * @arg @ref LL_RCC_SYSCLK_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 1377 | * @arg @ref LL_RCC_SYSCLK_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 1378 | * @arg @ref LL_RCC_SYSCLK_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 1379 | * @arg @ref LL_RCC_SYSCLK_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 1380 | * @arg @ref LL_RCC_SYSCLK_DIV_64 |
AnnaBridge | 163:e59c8e839560 | 1381 | * @arg @ref LL_RCC_SYSCLK_DIV_128 |
AnnaBridge | 163:e59c8e839560 | 1382 | * @arg @ref LL_RCC_SYSCLK_DIV_256 |
AnnaBridge | 163:e59c8e839560 | 1383 | * @arg @ref LL_RCC_SYSCLK_DIV_512 |
AnnaBridge | 163:e59c8e839560 | 1384 | */ |
AnnaBridge | 163:e59c8e839560 | 1385 | __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) |
AnnaBridge | 163:e59c8e839560 | 1386 | { |
AnnaBridge | 163:e59c8e839560 | 1387 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); |
AnnaBridge | 163:e59c8e839560 | 1388 | } |
AnnaBridge | 163:e59c8e839560 | 1389 | |
AnnaBridge | 163:e59c8e839560 | 1390 | /** |
AnnaBridge | 163:e59c8e839560 | 1391 | * @brief Get APB1 prescaler |
AnnaBridge | 163:e59c8e839560 | 1392 | * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler |
AnnaBridge | 163:e59c8e839560 | 1393 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1394 | * @arg @ref LL_RCC_APB1_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 1395 | * @arg @ref LL_RCC_APB1_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 1396 | * @arg @ref LL_RCC_APB1_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 1397 | * @arg @ref LL_RCC_APB1_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 1398 | * @arg @ref LL_RCC_APB1_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 1399 | */ |
AnnaBridge | 163:e59c8e839560 | 1400 | __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) |
AnnaBridge | 163:e59c8e839560 | 1401 | { |
AnnaBridge | 163:e59c8e839560 | 1402 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); |
AnnaBridge | 163:e59c8e839560 | 1403 | } |
AnnaBridge | 163:e59c8e839560 | 1404 | |
AnnaBridge | 163:e59c8e839560 | 1405 | /** |
AnnaBridge | 163:e59c8e839560 | 1406 | * @brief Get APB2 prescaler |
AnnaBridge | 163:e59c8e839560 | 1407 | * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler |
AnnaBridge | 163:e59c8e839560 | 1408 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1409 | * @arg @ref LL_RCC_APB2_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 1410 | * @arg @ref LL_RCC_APB2_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 1411 | * @arg @ref LL_RCC_APB2_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 1412 | * @arg @ref LL_RCC_APB2_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 1413 | * @arg @ref LL_RCC_APB2_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 1414 | */ |
AnnaBridge | 163:e59c8e839560 | 1415 | __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) |
AnnaBridge | 163:e59c8e839560 | 1416 | { |
AnnaBridge | 163:e59c8e839560 | 1417 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); |
AnnaBridge | 163:e59c8e839560 | 1418 | } |
AnnaBridge | 163:e59c8e839560 | 1419 | |
AnnaBridge | 163:e59c8e839560 | 1420 | /** |
AnnaBridge | 163:e59c8e839560 | 1421 | * @} |
AnnaBridge | 163:e59c8e839560 | 1422 | */ |
AnnaBridge | 163:e59c8e839560 | 1423 | |
AnnaBridge | 163:e59c8e839560 | 1424 | /** @defgroup RCC_LL_EF_MCO MCO |
AnnaBridge | 163:e59c8e839560 | 1425 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1426 | */ |
AnnaBridge | 163:e59c8e839560 | 1427 | |
AnnaBridge | 163:e59c8e839560 | 1428 | /** |
AnnaBridge | 163:e59c8e839560 | 1429 | * @brief Configure MCOx |
AnnaBridge | 163:e59c8e839560 | 1430 | * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n |
AnnaBridge | 163:e59c8e839560 | 1431 | * CFGR MCOPRE LL_RCC_ConfigMCO\n |
AnnaBridge | 163:e59c8e839560 | 1432 | * CFGR PLLNODIV LL_RCC_ConfigMCO |
AnnaBridge | 163:e59c8e839560 | 1433 | * @param MCOxSource This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1434 | * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK |
AnnaBridge | 163:e59c8e839560 | 1435 | * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK |
AnnaBridge | 163:e59c8e839560 | 1436 | * @arg @ref LL_RCC_MCO1SOURCE_HSI |
AnnaBridge | 163:e59c8e839560 | 1437 | * @arg @ref LL_RCC_MCO1SOURCE_HSE |
AnnaBridge | 163:e59c8e839560 | 1438 | * @arg @ref LL_RCC_MCO1SOURCE_LSI |
AnnaBridge | 163:e59c8e839560 | 1439 | * @arg @ref LL_RCC_MCO1SOURCE_LSE |
AnnaBridge | 163:e59c8e839560 | 1440 | * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*) |
AnnaBridge | 163:e59c8e839560 | 1441 | * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 1442 | * |
AnnaBridge | 163:e59c8e839560 | 1443 | * (*) value not defined in all devices |
AnnaBridge | 163:e59c8e839560 | 1444 | * @param MCOxPrescaler This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1445 | * @arg @ref LL_RCC_MCO1_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 1446 | * @arg @ref LL_RCC_MCO1_DIV_2 (*) |
AnnaBridge | 163:e59c8e839560 | 1447 | * @arg @ref LL_RCC_MCO1_DIV_4 (*) |
AnnaBridge | 163:e59c8e839560 | 1448 | * @arg @ref LL_RCC_MCO1_DIV_8 (*) |
AnnaBridge | 163:e59c8e839560 | 1449 | * @arg @ref LL_RCC_MCO1_DIV_16 (*) |
AnnaBridge | 163:e59c8e839560 | 1450 | * @arg @ref LL_RCC_MCO1_DIV_32 (*) |
AnnaBridge | 163:e59c8e839560 | 1451 | * @arg @ref LL_RCC_MCO1_DIV_64 (*) |
AnnaBridge | 163:e59c8e839560 | 1452 | * @arg @ref LL_RCC_MCO1_DIV_128 (*) |
AnnaBridge | 163:e59c8e839560 | 1453 | * |
AnnaBridge | 163:e59c8e839560 | 1454 | * (*) value not defined in all devices |
AnnaBridge | 163:e59c8e839560 | 1455 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1456 | */ |
AnnaBridge | 163:e59c8e839560 | 1457 | __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) |
AnnaBridge | 163:e59c8e839560 | 1458 | { |
AnnaBridge | 163:e59c8e839560 | 1459 | #if defined(RCC_CFGR_MCOPRE) |
AnnaBridge | 163:e59c8e839560 | 1460 | #if defined(RCC_CFGR_PLLNODIV) |
AnnaBridge | 163:e59c8e839560 | 1461 | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler); |
AnnaBridge | 163:e59c8e839560 | 1462 | #else |
AnnaBridge | 163:e59c8e839560 | 1463 | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); |
AnnaBridge | 163:e59c8e839560 | 1464 | #endif /* RCC_CFGR_PLLNODIV */ |
AnnaBridge | 163:e59c8e839560 | 1465 | #else |
AnnaBridge | 163:e59c8e839560 | 1466 | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource); |
AnnaBridge | 163:e59c8e839560 | 1467 | #endif /* RCC_CFGR_MCOPRE */ |
AnnaBridge | 163:e59c8e839560 | 1468 | } |
AnnaBridge | 163:e59c8e839560 | 1469 | |
AnnaBridge | 163:e59c8e839560 | 1470 | /** |
AnnaBridge | 163:e59c8e839560 | 1471 | * @} |
AnnaBridge | 163:e59c8e839560 | 1472 | */ |
AnnaBridge | 163:e59c8e839560 | 1473 | |
AnnaBridge | 163:e59c8e839560 | 1474 | /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source |
AnnaBridge | 163:e59c8e839560 | 1475 | * @{ |
AnnaBridge | 163:e59c8e839560 | 1476 | */ |
AnnaBridge | 163:e59c8e839560 | 1477 | |
AnnaBridge | 163:e59c8e839560 | 1478 | /** |
AnnaBridge | 163:e59c8e839560 | 1479 | * @brief Configure USARTx clock source |
AnnaBridge | 163:e59c8e839560 | 1480 | * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1481 | * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1482 | * CFGR3 USART3SW LL_RCC_SetUSARTClockSource |
AnnaBridge | 163:e59c8e839560 | 1483 | * @param USARTxSource This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1484 | * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*) |
AnnaBridge | 163:e59c8e839560 | 1485 | * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*) |
AnnaBridge | 163:e59c8e839560 | 1486 | * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK |
AnnaBridge | 163:e59c8e839560 | 1487 | * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE |
AnnaBridge | 163:e59c8e839560 | 1488 | * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI |
AnnaBridge | 163:e59c8e839560 | 1489 | * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) |
AnnaBridge | 163:e59c8e839560 | 1490 | * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) |
AnnaBridge | 163:e59c8e839560 | 1491 | * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) |
AnnaBridge | 163:e59c8e839560 | 1492 | * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) |
AnnaBridge | 163:e59c8e839560 | 1493 | * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) |
AnnaBridge | 163:e59c8e839560 | 1494 | * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) |
AnnaBridge | 163:e59c8e839560 | 1495 | * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) |
AnnaBridge | 163:e59c8e839560 | 1496 | * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) |
AnnaBridge | 163:e59c8e839560 | 1497 | * |
AnnaBridge | 163:e59c8e839560 | 1498 | * (*) value not defined in all devices. |
AnnaBridge | 163:e59c8e839560 | 1499 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1500 | */ |
AnnaBridge | 163:e59c8e839560 | 1501 | __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) |
AnnaBridge | 163:e59c8e839560 | 1502 | { |
AnnaBridge | 163:e59c8e839560 | 1503 | MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU)); |
AnnaBridge | 163:e59c8e839560 | 1504 | } |
AnnaBridge | 163:e59c8e839560 | 1505 | |
AnnaBridge | 163:e59c8e839560 | 1506 | #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW) |
AnnaBridge | 163:e59c8e839560 | 1507 | /** |
AnnaBridge | 163:e59c8e839560 | 1508 | * @brief Configure UARTx clock source |
AnnaBridge | 163:e59c8e839560 | 1509 | * @rmtoll CFGR3 UART4SW LL_RCC_SetUARTClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1510 | * CFGR3 UART5SW LL_RCC_SetUARTClockSource |
AnnaBridge | 163:e59c8e839560 | 1511 | * @param UARTxSource This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1512 | * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 |
AnnaBridge | 163:e59c8e839560 | 1513 | * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK |
AnnaBridge | 163:e59c8e839560 | 1514 | * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE |
AnnaBridge | 163:e59c8e839560 | 1515 | * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI |
AnnaBridge | 163:e59c8e839560 | 1516 | * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 |
AnnaBridge | 163:e59c8e839560 | 1517 | * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK |
AnnaBridge | 163:e59c8e839560 | 1518 | * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE |
AnnaBridge | 163:e59c8e839560 | 1519 | * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI |
AnnaBridge | 163:e59c8e839560 | 1520 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1521 | */ |
AnnaBridge | 163:e59c8e839560 | 1522 | __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) |
AnnaBridge | 163:e59c8e839560 | 1523 | { |
AnnaBridge | 163:e59c8e839560 | 1524 | MODIFY_REG(RCC->CFGR3, ((UARTxSource & 0x0000FFFFU) << 8U), (UARTxSource & (RCC_CFGR3_UART4SW | RCC_CFGR3_UART5SW))); |
AnnaBridge | 163:e59c8e839560 | 1525 | } |
AnnaBridge | 163:e59c8e839560 | 1526 | #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */ |
AnnaBridge | 163:e59c8e839560 | 1527 | |
AnnaBridge | 163:e59c8e839560 | 1528 | /** |
AnnaBridge | 163:e59c8e839560 | 1529 | * @brief Configure I2Cx clock source |
AnnaBridge | 163:e59c8e839560 | 1530 | * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1531 | * CFGR3 I2C2SW LL_RCC_SetI2CClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1532 | * CFGR3 I2C3SW LL_RCC_SetI2CClockSource |
AnnaBridge | 163:e59c8e839560 | 1533 | * @param I2CxSource This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1534 | * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI |
AnnaBridge | 163:e59c8e839560 | 1535 | * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK |
AnnaBridge | 163:e59c8e839560 | 1536 | * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) |
AnnaBridge | 163:e59c8e839560 | 1537 | * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) |
AnnaBridge | 163:e59c8e839560 | 1538 | * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) |
AnnaBridge | 163:e59c8e839560 | 1539 | * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*) |
AnnaBridge | 163:e59c8e839560 | 1540 | * |
AnnaBridge | 163:e59c8e839560 | 1541 | * (*) value not defined in all devices. |
AnnaBridge | 163:e59c8e839560 | 1542 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1543 | */ |
AnnaBridge | 163:e59c8e839560 | 1544 | __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) |
AnnaBridge | 163:e59c8e839560 | 1545 | { |
AnnaBridge | 163:e59c8e839560 | 1546 | MODIFY_REG(RCC->CFGR3, ((I2CxSource & 0xFF000000U) >> 24U), (I2CxSource & 0x00FFFFFFU)); |
AnnaBridge | 163:e59c8e839560 | 1547 | } |
AnnaBridge | 163:e59c8e839560 | 1548 | |
AnnaBridge | 163:e59c8e839560 | 1549 | #if defined(RCC_CFGR_I2SSRC) |
AnnaBridge | 163:e59c8e839560 | 1550 | /** |
AnnaBridge | 163:e59c8e839560 | 1551 | * @brief Configure I2Sx clock source |
AnnaBridge | 163:e59c8e839560 | 1552 | * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource |
AnnaBridge | 163:e59c8e839560 | 1553 | * @param I2SxSource This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1554 | * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK |
AnnaBridge | 163:e59c8e839560 | 1555 | * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN |
AnnaBridge | 163:e59c8e839560 | 1556 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1557 | */ |
AnnaBridge | 163:e59c8e839560 | 1558 | __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) |
AnnaBridge | 163:e59c8e839560 | 1559 | { |
AnnaBridge | 163:e59c8e839560 | 1560 | MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, I2SxSource); |
AnnaBridge | 163:e59c8e839560 | 1561 | } |
AnnaBridge | 163:e59c8e839560 | 1562 | #endif /* RCC_CFGR_I2SSRC */ |
AnnaBridge | 163:e59c8e839560 | 1563 | |
AnnaBridge | 163:e59c8e839560 | 1564 | #if defined(RCC_CFGR3_TIMSW) |
AnnaBridge | 163:e59c8e839560 | 1565 | /** |
AnnaBridge | 163:e59c8e839560 | 1566 | * @brief Configure TIMx clock source |
AnnaBridge | 163:e59c8e839560 | 1567 | * @rmtoll CFGR3 TIM1SW LL_RCC_SetTIMClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1568 | * CFGR3 TIM8SW LL_RCC_SetTIMClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1569 | * CFGR3 TIM15SW LL_RCC_SetTIMClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1570 | * CFGR3 TIM16SW LL_RCC_SetTIMClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1571 | * CFGR3 TIM17SW LL_RCC_SetTIMClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1572 | * CFGR3 TIM20SW LL_RCC_SetTIMClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1573 | * CFGR3 TIM2SW LL_RCC_SetTIMClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1574 | * CFGR3 TIM34SW LL_RCC_SetTIMClockSource |
AnnaBridge | 163:e59c8e839560 | 1575 | * @param TIMxSource This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1576 | * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2 |
AnnaBridge | 163:e59c8e839560 | 1577 | * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL |
AnnaBridge | 163:e59c8e839560 | 1578 | * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*) |
AnnaBridge | 163:e59c8e839560 | 1579 | * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*) |
AnnaBridge | 163:e59c8e839560 | 1580 | * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*) |
AnnaBridge | 163:e59c8e839560 | 1581 | * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*) |
AnnaBridge | 163:e59c8e839560 | 1582 | * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*) |
AnnaBridge | 163:e59c8e839560 | 1583 | * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*) |
AnnaBridge | 163:e59c8e839560 | 1584 | * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*) |
AnnaBridge | 163:e59c8e839560 | 1585 | * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*) |
AnnaBridge | 163:e59c8e839560 | 1586 | * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*) |
AnnaBridge | 163:e59c8e839560 | 1587 | * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*) |
AnnaBridge | 163:e59c8e839560 | 1588 | * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*) |
AnnaBridge | 163:e59c8e839560 | 1589 | * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*) |
AnnaBridge | 163:e59c8e839560 | 1590 | * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*) |
AnnaBridge | 163:e59c8e839560 | 1591 | * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*) |
AnnaBridge | 163:e59c8e839560 | 1592 | * |
AnnaBridge | 163:e59c8e839560 | 1593 | * (*) value not defined in all devices. |
AnnaBridge | 163:e59c8e839560 | 1594 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1595 | */ |
AnnaBridge | 163:e59c8e839560 | 1596 | __STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource) |
AnnaBridge | 163:e59c8e839560 | 1597 | { |
AnnaBridge | 163:e59c8e839560 | 1598 | MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_TIM1SW << (TIMxSource >> 27U)), (TIMxSource & 0x03FFFFFFU)); |
AnnaBridge | 163:e59c8e839560 | 1599 | } |
AnnaBridge | 163:e59c8e839560 | 1600 | #endif /* RCC_CFGR3_TIMSW */ |
AnnaBridge | 163:e59c8e839560 | 1601 | |
AnnaBridge | 163:e59c8e839560 | 1602 | #if defined(HRTIM1) |
AnnaBridge | 163:e59c8e839560 | 1603 | /** |
AnnaBridge | 163:e59c8e839560 | 1604 | * @brief Configure HRTIMx clock source |
AnnaBridge | 163:e59c8e839560 | 1605 | * @rmtoll CFGR3 HRTIMSW LL_RCC_SetHRTIMClockSource |
AnnaBridge | 163:e59c8e839560 | 1606 | * @param HRTIMxSource This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1607 | * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2 |
AnnaBridge | 163:e59c8e839560 | 1608 | * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL |
AnnaBridge | 163:e59c8e839560 | 1609 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1610 | */ |
AnnaBridge | 163:e59c8e839560 | 1611 | __STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t HRTIMxSource) |
AnnaBridge | 163:e59c8e839560 | 1612 | { |
AnnaBridge | 163:e59c8e839560 | 1613 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIMSW, HRTIMxSource); |
AnnaBridge | 163:e59c8e839560 | 1614 | } |
AnnaBridge | 163:e59c8e839560 | 1615 | #endif /* HRTIM1 */ |
AnnaBridge | 163:e59c8e839560 | 1616 | |
AnnaBridge | 163:e59c8e839560 | 1617 | #if defined(CEC) |
AnnaBridge | 163:e59c8e839560 | 1618 | /** |
AnnaBridge | 163:e59c8e839560 | 1619 | * @brief Configure CEC clock source |
AnnaBridge | 163:e59c8e839560 | 1620 | * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource |
AnnaBridge | 163:e59c8e839560 | 1621 | * @param CECxSource This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1622 | * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 |
AnnaBridge | 163:e59c8e839560 | 1623 | * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE |
AnnaBridge | 163:e59c8e839560 | 1624 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1625 | */ |
AnnaBridge | 163:e59c8e839560 | 1626 | __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource) |
AnnaBridge | 163:e59c8e839560 | 1627 | { |
AnnaBridge | 163:e59c8e839560 | 1628 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource); |
AnnaBridge | 163:e59c8e839560 | 1629 | } |
AnnaBridge | 163:e59c8e839560 | 1630 | #endif /* CEC */ |
AnnaBridge | 163:e59c8e839560 | 1631 | |
AnnaBridge | 163:e59c8e839560 | 1632 | #if defined(USB) |
AnnaBridge | 163:e59c8e839560 | 1633 | /** |
AnnaBridge | 163:e59c8e839560 | 1634 | * @brief Configure USB clock source |
AnnaBridge | 163:e59c8e839560 | 1635 | * @rmtoll CFGR USBPRE LL_RCC_SetUSBClockSource |
AnnaBridge | 163:e59c8e839560 | 1636 | * @param USBxSource This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1637 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL |
AnnaBridge | 163:e59c8e839560 | 1638 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 |
AnnaBridge | 163:e59c8e839560 | 1639 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1640 | */ |
AnnaBridge | 163:e59c8e839560 | 1641 | __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) |
AnnaBridge | 163:e59c8e839560 | 1642 | { |
AnnaBridge | 163:e59c8e839560 | 1643 | MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource); |
AnnaBridge | 163:e59c8e839560 | 1644 | } |
AnnaBridge | 163:e59c8e839560 | 1645 | #endif /* USB */ |
AnnaBridge | 163:e59c8e839560 | 1646 | |
AnnaBridge | 163:e59c8e839560 | 1647 | #if defined(RCC_CFGR_ADCPRE) |
AnnaBridge | 163:e59c8e839560 | 1648 | /** |
AnnaBridge | 163:e59c8e839560 | 1649 | * @brief Configure ADC clock source |
AnnaBridge | 163:e59c8e839560 | 1650 | * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource |
AnnaBridge | 163:e59c8e839560 | 1651 | * @param ADCxSource This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1652 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 1653 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 1654 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 |
AnnaBridge | 163:e59c8e839560 | 1655 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 1656 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1657 | */ |
AnnaBridge | 163:e59c8e839560 | 1658 | __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) |
AnnaBridge | 163:e59c8e839560 | 1659 | { |
AnnaBridge | 163:e59c8e839560 | 1660 | MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource); |
AnnaBridge | 163:e59c8e839560 | 1661 | } |
AnnaBridge | 163:e59c8e839560 | 1662 | |
AnnaBridge | 163:e59c8e839560 | 1663 | #elif defined(RCC_CFGR2_ADC1PRES) |
AnnaBridge | 163:e59c8e839560 | 1664 | /** |
AnnaBridge | 163:e59c8e839560 | 1665 | * @brief Configure ADC clock source |
AnnaBridge | 163:e59c8e839560 | 1666 | * @rmtoll CFGR2 ADC1PRES LL_RCC_SetADCClockSource |
AnnaBridge | 163:e59c8e839560 | 1667 | * @param ADCxSource This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1668 | * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK |
AnnaBridge | 163:e59c8e839560 | 1669 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 1670 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 1671 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 1672 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6 |
AnnaBridge | 163:e59c8e839560 | 1673 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 1674 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10 |
AnnaBridge | 163:e59c8e839560 | 1675 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12 |
AnnaBridge | 163:e59c8e839560 | 1676 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 1677 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32 |
AnnaBridge | 163:e59c8e839560 | 1678 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64 |
AnnaBridge | 163:e59c8e839560 | 1679 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128 |
AnnaBridge | 163:e59c8e839560 | 1680 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256 |
AnnaBridge | 163:e59c8e839560 | 1681 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1682 | */ |
AnnaBridge | 163:e59c8e839560 | 1683 | __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) |
AnnaBridge | 163:e59c8e839560 | 1684 | { |
AnnaBridge | 163:e59c8e839560 | 1685 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, ADCxSource); |
AnnaBridge | 163:e59c8e839560 | 1686 | } |
AnnaBridge | 163:e59c8e839560 | 1687 | |
AnnaBridge | 163:e59c8e839560 | 1688 | #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) |
AnnaBridge | 163:e59c8e839560 | 1689 | /** |
AnnaBridge | 163:e59c8e839560 | 1690 | * @brief Configure ADC clock source |
AnnaBridge | 163:e59c8e839560 | 1691 | * @rmtoll CFGR2 ADCPRE12 LL_RCC_SetADCClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1692 | * CFGR2 ADCPRE34 LL_RCC_SetADCClockSource |
AnnaBridge | 163:e59c8e839560 | 1693 | * @param ADCxSource This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1694 | * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK |
AnnaBridge | 163:e59c8e839560 | 1695 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 1696 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 1697 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 1698 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6 |
AnnaBridge | 163:e59c8e839560 | 1699 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 1700 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10 |
AnnaBridge | 163:e59c8e839560 | 1701 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12 |
AnnaBridge | 163:e59c8e839560 | 1702 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 1703 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32 |
AnnaBridge | 163:e59c8e839560 | 1704 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64 |
AnnaBridge | 163:e59c8e839560 | 1705 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128 |
AnnaBridge | 163:e59c8e839560 | 1706 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256 |
AnnaBridge | 163:e59c8e839560 | 1707 | * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*) |
AnnaBridge | 163:e59c8e839560 | 1708 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*) |
AnnaBridge | 163:e59c8e839560 | 1709 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*) |
AnnaBridge | 163:e59c8e839560 | 1710 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*) |
AnnaBridge | 163:e59c8e839560 | 1711 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*) |
AnnaBridge | 163:e59c8e839560 | 1712 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*) |
AnnaBridge | 163:e59c8e839560 | 1713 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*) |
AnnaBridge | 163:e59c8e839560 | 1714 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*) |
AnnaBridge | 163:e59c8e839560 | 1715 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*) |
AnnaBridge | 163:e59c8e839560 | 1716 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*) |
AnnaBridge | 163:e59c8e839560 | 1717 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*) |
AnnaBridge | 163:e59c8e839560 | 1718 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*) |
AnnaBridge | 163:e59c8e839560 | 1719 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*) |
AnnaBridge | 163:e59c8e839560 | 1720 | * |
AnnaBridge | 163:e59c8e839560 | 1721 | * (*) value not defined in all devices. |
AnnaBridge | 163:e59c8e839560 | 1722 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1723 | */ |
AnnaBridge | 163:e59c8e839560 | 1724 | __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) |
AnnaBridge | 163:e59c8e839560 | 1725 | { |
AnnaBridge | 163:e59c8e839560 | 1726 | #if defined(RCC_CFGR2_ADCPRE34) |
AnnaBridge | 163:e59c8e839560 | 1727 | MODIFY_REG(RCC->CFGR2, (ADCxSource >> 16U), (ADCxSource & 0x0000FFFFU)); |
AnnaBridge | 163:e59c8e839560 | 1728 | #else |
AnnaBridge | 163:e59c8e839560 | 1729 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, ADCxSource); |
AnnaBridge | 163:e59c8e839560 | 1730 | #endif /* RCC_CFGR2_ADCPRE34 */ |
AnnaBridge | 163:e59c8e839560 | 1731 | } |
AnnaBridge | 163:e59c8e839560 | 1732 | #endif /* RCC_CFGR_ADCPRE */ |
AnnaBridge | 163:e59c8e839560 | 1733 | |
AnnaBridge | 163:e59c8e839560 | 1734 | #if defined(RCC_CFGR_SDPRE) |
AnnaBridge | 163:e59c8e839560 | 1735 | /** |
AnnaBridge | 163:e59c8e839560 | 1736 | * @brief Configure SDADCx clock source |
AnnaBridge | 163:e59c8e839560 | 1737 | * @rmtoll CFGR SDPRE LL_RCC_SetSDADCClockSource |
AnnaBridge | 163:e59c8e839560 | 1738 | * @param SDADCxSource This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1739 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 1740 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 1741 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 1742 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6 |
AnnaBridge | 163:e59c8e839560 | 1743 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 1744 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10 |
AnnaBridge | 163:e59c8e839560 | 1745 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12 |
AnnaBridge | 163:e59c8e839560 | 1746 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14 |
AnnaBridge | 163:e59c8e839560 | 1747 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 1748 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20 |
AnnaBridge | 163:e59c8e839560 | 1749 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24 |
AnnaBridge | 163:e59c8e839560 | 1750 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28 |
AnnaBridge | 163:e59c8e839560 | 1751 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32 |
AnnaBridge | 163:e59c8e839560 | 1752 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36 |
AnnaBridge | 163:e59c8e839560 | 1753 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40 |
AnnaBridge | 163:e59c8e839560 | 1754 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44 |
AnnaBridge | 163:e59c8e839560 | 1755 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48 |
AnnaBridge | 163:e59c8e839560 | 1756 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 1757 | */ |
AnnaBridge | 163:e59c8e839560 | 1758 | __STATIC_INLINE void LL_RCC_SetSDADCClockSource(uint32_t SDADCxSource) |
AnnaBridge | 163:e59c8e839560 | 1759 | { |
AnnaBridge | 163:e59c8e839560 | 1760 | MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, SDADCxSource); |
AnnaBridge | 163:e59c8e839560 | 1761 | } |
AnnaBridge | 163:e59c8e839560 | 1762 | #endif /* RCC_CFGR_SDPRE */ |
AnnaBridge | 163:e59c8e839560 | 1763 | |
AnnaBridge | 163:e59c8e839560 | 1764 | /** |
AnnaBridge | 163:e59c8e839560 | 1765 | * @brief Get USARTx clock source |
AnnaBridge | 163:e59c8e839560 | 1766 | * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1767 | * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1768 | * CFGR3 USART3SW LL_RCC_GetUSARTClockSource |
AnnaBridge | 163:e59c8e839560 | 1769 | * @param USARTx This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1770 | * @arg @ref LL_RCC_USART1_CLKSOURCE |
AnnaBridge | 163:e59c8e839560 | 1771 | * @arg @ref LL_RCC_USART2_CLKSOURCE (*) |
AnnaBridge | 163:e59c8e839560 | 1772 | * @arg @ref LL_RCC_USART3_CLKSOURCE (*) |
AnnaBridge | 163:e59c8e839560 | 1773 | * |
AnnaBridge | 163:e59c8e839560 | 1774 | * (*) value not defined in all devices. |
AnnaBridge | 163:e59c8e839560 | 1775 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1776 | * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*) |
AnnaBridge | 163:e59c8e839560 | 1777 | * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*) |
AnnaBridge | 163:e59c8e839560 | 1778 | * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK |
AnnaBridge | 163:e59c8e839560 | 1779 | * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE |
AnnaBridge | 163:e59c8e839560 | 1780 | * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI |
AnnaBridge | 163:e59c8e839560 | 1781 | * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) |
AnnaBridge | 163:e59c8e839560 | 1782 | * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) |
AnnaBridge | 163:e59c8e839560 | 1783 | * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) |
AnnaBridge | 163:e59c8e839560 | 1784 | * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) |
AnnaBridge | 163:e59c8e839560 | 1785 | * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) |
AnnaBridge | 163:e59c8e839560 | 1786 | * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) |
AnnaBridge | 163:e59c8e839560 | 1787 | * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) |
AnnaBridge | 163:e59c8e839560 | 1788 | * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) |
AnnaBridge | 163:e59c8e839560 | 1789 | * |
AnnaBridge | 163:e59c8e839560 | 1790 | * (*) value not defined in all devices. |
AnnaBridge | 163:e59c8e839560 | 1791 | */ |
AnnaBridge | 163:e59c8e839560 | 1792 | __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) |
AnnaBridge | 163:e59c8e839560 | 1793 | { |
AnnaBridge | 163:e59c8e839560 | 1794 | return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U)); |
AnnaBridge | 163:e59c8e839560 | 1795 | } |
AnnaBridge | 163:e59c8e839560 | 1796 | |
AnnaBridge | 163:e59c8e839560 | 1797 | #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW) |
AnnaBridge | 163:e59c8e839560 | 1798 | /** |
AnnaBridge | 163:e59c8e839560 | 1799 | * @brief Get UARTx clock source |
AnnaBridge | 163:e59c8e839560 | 1800 | * @rmtoll CFGR3 UART4SW LL_RCC_GetUARTClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1801 | * CFGR3 UART5SW LL_RCC_GetUARTClockSource |
AnnaBridge | 163:e59c8e839560 | 1802 | * @param UARTx This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1803 | * @arg @ref LL_RCC_UART4_CLKSOURCE |
AnnaBridge | 163:e59c8e839560 | 1804 | * @arg @ref LL_RCC_UART5_CLKSOURCE |
AnnaBridge | 163:e59c8e839560 | 1805 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1806 | * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 |
AnnaBridge | 163:e59c8e839560 | 1807 | * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK |
AnnaBridge | 163:e59c8e839560 | 1808 | * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE |
AnnaBridge | 163:e59c8e839560 | 1809 | * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI |
AnnaBridge | 163:e59c8e839560 | 1810 | * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 |
AnnaBridge | 163:e59c8e839560 | 1811 | * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK |
AnnaBridge | 163:e59c8e839560 | 1812 | * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE |
AnnaBridge | 163:e59c8e839560 | 1813 | * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI |
AnnaBridge | 163:e59c8e839560 | 1814 | */ |
AnnaBridge | 163:e59c8e839560 | 1815 | __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) |
AnnaBridge | 163:e59c8e839560 | 1816 | { |
AnnaBridge | 163:e59c8e839560 | 1817 | return (uint32_t)(READ_BIT(RCC->CFGR3, UARTx) | (UARTx >> 8U)); |
AnnaBridge | 163:e59c8e839560 | 1818 | } |
AnnaBridge | 163:e59c8e839560 | 1819 | #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */ |
AnnaBridge | 163:e59c8e839560 | 1820 | |
AnnaBridge | 163:e59c8e839560 | 1821 | /** |
AnnaBridge | 163:e59c8e839560 | 1822 | * @brief Get I2Cx clock source |
AnnaBridge | 163:e59c8e839560 | 1823 | * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1824 | * CFGR3 I2C2SW LL_RCC_GetI2CClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1825 | * CFGR3 I2C3SW LL_RCC_GetI2CClockSource |
AnnaBridge | 163:e59c8e839560 | 1826 | * @param I2Cx This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1827 | * @arg @ref LL_RCC_I2C1_CLKSOURCE |
AnnaBridge | 163:e59c8e839560 | 1828 | * @arg @ref LL_RCC_I2C2_CLKSOURCE (*) |
AnnaBridge | 163:e59c8e839560 | 1829 | * @arg @ref LL_RCC_I2C3_CLKSOURCE (*) |
AnnaBridge | 163:e59c8e839560 | 1830 | * |
AnnaBridge | 163:e59c8e839560 | 1831 | * (*) value not defined in all devices. |
AnnaBridge | 163:e59c8e839560 | 1832 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1833 | * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI |
AnnaBridge | 163:e59c8e839560 | 1834 | * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK |
AnnaBridge | 163:e59c8e839560 | 1835 | * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) |
AnnaBridge | 163:e59c8e839560 | 1836 | * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) |
AnnaBridge | 163:e59c8e839560 | 1837 | * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) |
AnnaBridge | 163:e59c8e839560 | 1838 | * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*) |
AnnaBridge | 163:e59c8e839560 | 1839 | * |
AnnaBridge | 163:e59c8e839560 | 1840 | * (*) value not defined in all devices. |
AnnaBridge | 163:e59c8e839560 | 1841 | */ |
AnnaBridge | 163:e59c8e839560 | 1842 | __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) |
AnnaBridge | 163:e59c8e839560 | 1843 | { |
AnnaBridge | 163:e59c8e839560 | 1844 | return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx) | (I2Cx << 24U)); |
AnnaBridge | 163:e59c8e839560 | 1845 | } |
AnnaBridge | 163:e59c8e839560 | 1846 | |
AnnaBridge | 163:e59c8e839560 | 1847 | #if defined(RCC_CFGR_I2SSRC) |
AnnaBridge | 163:e59c8e839560 | 1848 | /** |
AnnaBridge | 163:e59c8e839560 | 1849 | * @brief Get I2Sx clock source |
AnnaBridge | 163:e59c8e839560 | 1850 | * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource |
AnnaBridge | 163:e59c8e839560 | 1851 | * @param I2Sx This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1852 | * @arg @ref LL_RCC_I2S_CLKSOURCE |
AnnaBridge | 163:e59c8e839560 | 1853 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1854 | * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK |
AnnaBridge | 163:e59c8e839560 | 1855 | * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN |
AnnaBridge | 163:e59c8e839560 | 1856 | */ |
AnnaBridge | 163:e59c8e839560 | 1857 | __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) |
AnnaBridge | 163:e59c8e839560 | 1858 | { |
AnnaBridge | 163:e59c8e839560 | 1859 | return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx)); |
AnnaBridge | 163:e59c8e839560 | 1860 | } |
AnnaBridge | 163:e59c8e839560 | 1861 | #endif /* RCC_CFGR_I2SSRC */ |
AnnaBridge | 163:e59c8e839560 | 1862 | |
AnnaBridge | 163:e59c8e839560 | 1863 | #if defined(RCC_CFGR3_TIMSW) |
AnnaBridge | 163:e59c8e839560 | 1864 | /** |
AnnaBridge | 163:e59c8e839560 | 1865 | * @brief Get TIMx clock source |
AnnaBridge | 163:e59c8e839560 | 1866 | * @rmtoll CFGR3 TIM1SW LL_RCC_GetTIMClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1867 | * CFGR3 TIM8SW LL_RCC_GetTIMClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1868 | * CFGR3 TIM15SW LL_RCC_GetTIMClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1869 | * CFGR3 TIM16SW LL_RCC_GetTIMClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1870 | * CFGR3 TIM17SW LL_RCC_GetTIMClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1871 | * CFGR3 TIM20SW LL_RCC_GetTIMClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1872 | * CFGR3 TIM2SW LL_RCC_GetTIMClockSource\n |
AnnaBridge | 163:e59c8e839560 | 1873 | * CFGR3 TIM34SW LL_RCC_GetTIMClockSource |
AnnaBridge | 163:e59c8e839560 | 1874 | * @param TIMx This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1875 | * @arg @ref LL_RCC_TIM1_CLKSOURCE |
AnnaBridge | 163:e59c8e839560 | 1876 | * @arg @ref LL_RCC_TIM2_CLKSOURCE (*) |
AnnaBridge | 163:e59c8e839560 | 1877 | * @arg @ref LL_RCC_TIM8_CLKSOURCE (*) |
AnnaBridge | 163:e59c8e839560 | 1878 | * @arg @ref LL_RCC_TIM15_CLKSOURCE (*) |
AnnaBridge | 163:e59c8e839560 | 1879 | * @arg @ref LL_RCC_TIM16_CLKSOURCE (*) |
AnnaBridge | 163:e59c8e839560 | 1880 | * @arg @ref LL_RCC_TIM17_CLKSOURCE (*) |
AnnaBridge | 163:e59c8e839560 | 1881 | * @arg @ref LL_RCC_TIM20_CLKSOURCE (*) |
AnnaBridge | 163:e59c8e839560 | 1882 | * @arg @ref LL_RCC_TIM34_CLKSOURCE (*) |
AnnaBridge | 163:e59c8e839560 | 1883 | * |
AnnaBridge | 163:e59c8e839560 | 1884 | * (*) value not defined in all devices. |
AnnaBridge | 163:e59c8e839560 | 1885 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1886 | * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2 |
AnnaBridge | 163:e59c8e839560 | 1887 | * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL |
AnnaBridge | 163:e59c8e839560 | 1888 | * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*) |
AnnaBridge | 163:e59c8e839560 | 1889 | * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*) |
AnnaBridge | 163:e59c8e839560 | 1890 | * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*) |
AnnaBridge | 163:e59c8e839560 | 1891 | * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*) |
AnnaBridge | 163:e59c8e839560 | 1892 | * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*) |
AnnaBridge | 163:e59c8e839560 | 1893 | * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*) |
AnnaBridge | 163:e59c8e839560 | 1894 | * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*) |
AnnaBridge | 163:e59c8e839560 | 1895 | * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*) |
AnnaBridge | 163:e59c8e839560 | 1896 | * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*) |
AnnaBridge | 163:e59c8e839560 | 1897 | * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*) |
AnnaBridge | 163:e59c8e839560 | 1898 | * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*) |
AnnaBridge | 163:e59c8e839560 | 1899 | * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*) |
AnnaBridge | 163:e59c8e839560 | 1900 | * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*) |
AnnaBridge | 163:e59c8e839560 | 1901 | * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*) |
AnnaBridge | 163:e59c8e839560 | 1902 | * |
AnnaBridge | 163:e59c8e839560 | 1903 | * (*) value not defined in all devices. |
AnnaBridge | 163:e59c8e839560 | 1904 | */ |
AnnaBridge | 163:e59c8e839560 | 1905 | __STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx) |
AnnaBridge | 163:e59c8e839560 | 1906 | { |
AnnaBridge | 163:e59c8e839560 | 1907 | return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_TIM1SW << TIMx)) | (TIMx << 27U)); |
AnnaBridge | 163:e59c8e839560 | 1908 | } |
AnnaBridge | 163:e59c8e839560 | 1909 | #endif /* RCC_CFGR3_TIMSW */ |
AnnaBridge | 163:e59c8e839560 | 1910 | |
AnnaBridge | 163:e59c8e839560 | 1911 | #if defined(HRTIM1) |
AnnaBridge | 163:e59c8e839560 | 1912 | /** |
AnnaBridge | 163:e59c8e839560 | 1913 | * @brief Get HRTIMx clock source |
AnnaBridge | 163:e59c8e839560 | 1914 | * @rmtoll CFGR3 HRTIMSW LL_RCC_GetHRTIMClockSource |
AnnaBridge | 163:e59c8e839560 | 1915 | * @param HRTIMx This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1916 | * @arg @ref LL_RCC_HRTIM1_CLKSOURCE |
AnnaBridge | 163:e59c8e839560 | 1917 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1918 | * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2 |
AnnaBridge | 163:e59c8e839560 | 1919 | * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL |
AnnaBridge | 163:e59c8e839560 | 1920 | */ |
AnnaBridge | 163:e59c8e839560 | 1921 | __STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(uint32_t HRTIMx) |
AnnaBridge | 163:e59c8e839560 | 1922 | { |
AnnaBridge | 163:e59c8e839560 | 1923 | return (uint32_t)(READ_BIT(RCC->CFGR3, HRTIMx)); |
AnnaBridge | 163:e59c8e839560 | 1924 | } |
AnnaBridge | 163:e59c8e839560 | 1925 | #endif /* HRTIM1 */ |
AnnaBridge | 163:e59c8e839560 | 1926 | |
AnnaBridge | 163:e59c8e839560 | 1927 | #if defined(CEC) |
AnnaBridge | 163:e59c8e839560 | 1928 | /** |
AnnaBridge | 163:e59c8e839560 | 1929 | * @brief Get CEC clock source |
AnnaBridge | 163:e59c8e839560 | 1930 | * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource |
AnnaBridge | 163:e59c8e839560 | 1931 | * @param CECx This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1932 | * @arg @ref LL_RCC_CEC_CLKSOURCE |
AnnaBridge | 163:e59c8e839560 | 1933 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1934 | * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 |
AnnaBridge | 163:e59c8e839560 | 1935 | * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE |
AnnaBridge | 163:e59c8e839560 | 1936 | */ |
AnnaBridge | 163:e59c8e839560 | 1937 | __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) |
AnnaBridge | 163:e59c8e839560 | 1938 | { |
AnnaBridge | 163:e59c8e839560 | 1939 | return (uint32_t)(READ_BIT(RCC->CFGR3, CECx)); |
AnnaBridge | 163:e59c8e839560 | 1940 | } |
AnnaBridge | 163:e59c8e839560 | 1941 | #endif /* CEC */ |
AnnaBridge | 163:e59c8e839560 | 1942 | |
AnnaBridge | 163:e59c8e839560 | 1943 | #if defined(USB) |
AnnaBridge | 163:e59c8e839560 | 1944 | /** |
AnnaBridge | 163:e59c8e839560 | 1945 | * @brief Get USBx clock source |
AnnaBridge | 163:e59c8e839560 | 1946 | * @rmtoll CFGR USBPRE LL_RCC_GetUSBClockSource |
AnnaBridge | 163:e59c8e839560 | 1947 | * @param USBx This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1948 | * @arg @ref LL_RCC_USB_CLKSOURCE |
AnnaBridge | 163:e59c8e839560 | 1949 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1950 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL |
AnnaBridge | 163:e59c8e839560 | 1951 | * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 |
AnnaBridge | 163:e59c8e839560 | 1952 | */ |
AnnaBridge | 163:e59c8e839560 | 1953 | __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) |
AnnaBridge | 163:e59c8e839560 | 1954 | { |
AnnaBridge | 163:e59c8e839560 | 1955 | return (uint32_t)(READ_BIT(RCC->CFGR, USBx)); |
AnnaBridge | 163:e59c8e839560 | 1956 | } |
AnnaBridge | 163:e59c8e839560 | 1957 | #endif /* USB */ |
AnnaBridge | 163:e59c8e839560 | 1958 | |
AnnaBridge | 163:e59c8e839560 | 1959 | #if defined(RCC_CFGR_ADCPRE) |
AnnaBridge | 163:e59c8e839560 | 1960 | /** |
AnnaBridge | 163:e59c8e839560 | 1961 | * @brief Get ADCx clock source |
AnnaBridge | 163:e59c8e839560 | 1962 | * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource |
AnnaBridge | 163:e59c8e839560 | 1963 | * @param ADCx This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1964 | * @arg @ref LL_RCC_ADC_CLKSOURCE |
AnnaBridge | 163:e59c8e839560 | 1965 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1966 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 1967 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 1968 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 |
AnnaBridge | 163:e59c8e839560 | 1969 | * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 1970 | */ |
AnnaBridge | 163:e59c8e839560 | 1971 | __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) |
AnnaBridge | 163:e59c8e839560 | 1972 | { |
AnnaBridge | 163:e59c8e839560 | 1973 | return (uint32_t)(READ_BIT(RCC->CFGR, ADCx)); |
AnnaBridge | 163:e59c8e839560 | 1974 | } |
AnnaBridge | 163:e59c8e839560 | 1975 | |
AnnaBridge | 163:e59c8e839560 | 1976 | #elif defined(RCC_CFGR2_ADC1PRES) |
AnnaBridge | 163:e59c8e839560 | 1977 | /** |
AnnaBridge | 163:e59c8e839560 | 1978 | * @brief Get ADCx clock source |
AnnaBridge | 163:e59c8e839560 | 1979 | * @rmtoll CFGR2 ADC1PRES LL_RCC_GetADCClockSource |
AnnaBridge | 163:e59c8e839560 | 1980 | * @param ADCx This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1981 | * @arg @ref LL_RCC_ADC1_CLKSOURCE |
AnnaBridge | 163:e59c8e839560 | 1982 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 1983 | * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK |
AnnaBridge | 163:e59c8e839560 | 1984 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 1985 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 1986 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 1987 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6 |
AnnaBridge | 163:e59c8e839560 | 1988 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 1989 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10 |
AnnaBridge | 163:e59c8e839560 | 1990 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12 |
AnnaBridge | 163:e59c8e839560 | 1991 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 1992 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32 |
AnnaBridge | 163:e59c8e839560 | 1993 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64 |
AnnaBridge | 163:e59c8e839560 | 1994 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128 |
AnnaBridge | 163:e59c8e839560 | 1995 | * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256 |
AnnaBridge | 163:e59c8e839560 | 1996 | */ |
AnnaBridge | 163:e59c8e839560 | 1997 | __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) |
AnnaBridge | 163:e59c8e839560 | 1998 | { |
AnnaBridge | 163:e59c8e839560 | 1999 | return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx)); |
AnnaBridge | 163:e59c8e839560 | 2000 | } |
AnnaBridge | 163:e59c8e839560 | 2001 | |
AnnaBridge | 163:e59c8e839560 | 2002 | #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) |
AnnaBridge | 163:e59c8e839560 | 2003 | /** |
AnnaBridge | 163:e59c8e839560 | 2004 | * @brief Get ADCx clock source |
AnnaBridge | 163:e59c8e839560 | 2005 | * @rmtoll CFGR2 ADCPRE12 LL_RCC_GetADCClockSource\n |
AnnaBridge | 163:e59c8e839560 | 2006 | * CFGR2 ADCPRE34 LL_RCC_GetADCClockSource |
AnnaBridge | 163:e59c8e839560 | 2007 | * @param ADCx This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 2008 | * @arg @ref LL_RCC_ADC12_CLKSOURCE |
AnnaBridge | 163:e59c8e839560 | 2009 | * @arg @ref LL_RCC_ADC34_CLKSOURCE (*) |
AnnaBridge | 163:e59c8e839560 | 2010 | * |
AnnaBridge | 163:e59c8e839560 | 2011 | * (*) value not defined in all devices. |
AnnaBridge | 163:e59c8e839560 | 2012 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 2013 | * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK |
AnnaBridge | 163:e59c8e839560 | 2014 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 2015 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 2016 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 2017 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6 |
AnnaBridge | 163:e59c8e839560 | 2018 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 2019 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10 |
AnnaBridge | 163:e59c8e839560 | 2020 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12 |
AnnaBridge | 163:e59c8e839560 | 2021 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 2022 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32 |
AnnaBridge | 163:e59c8e839560 | 2023 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64 |
AnnaBridge | 163:e59c8e839560 | 2024 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128 |
AnnaBridge | 163:e59c8e839560 | 2025 | * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256 |
AnnaBridge | 163:e59c8e839560 | 2026 | * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*) |
AnnaBridge | 163:e59c8e839560 | 2027 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*) |
AnnaBridge | 163:e59c8e839560 | 2028 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*) |
AnnaBridge | 163:e59c8e839560 | 2029 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*) |
AnnaBridge | 163:e59c8e839560 | 2030 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*) |
AnnaBridge | 163:e59c8e839560 | 2031 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*) |
AnnaBridge | 163:e59c8e839560 | 2032 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*) |
AnnaBridge | 163:e59c8e839560 | 2033 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*) |
AnnaBridge | 163:e59c8e839560 | 2034 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*) |
AnnaBridge | 163:e59c8e839560 | 2035 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*) |
AnnaBridge | 163:e59c8e839560 | 2036 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*) |
AnnaBridge | 163:e59c8e839560 | 2037 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*) |
AnnaBridge | 163:e59c8e839560 | 2038 | * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*) |
AnnaBridge | 163:e59c8e839560 | 2039 | * |
AnnaBridge | 163:e59c8e839560 | 2040 | * (*) value not defined in all devices. |
AnnaBridge | 163:e59c8e839560 | 2041 | */ |
AnnaBridge | 163:e59c8e839560 | 2042 | __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) |
AnnaBridge | 163:e59c8e839560 | 2043 | { |
AnnaBridge | 163:e59c8e839560 | 2044 | #if defined(RCC_CFGR2_ADCPRE34) |
AnnaBridge | 163:e59c8e839560 | 2045 | return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx) | (ADCx << 16U)); |
AnnaBridge | 163:e59c8e839560 | 2046 | #else |
AnnaBridge | 163:e59c8e839560 | 2047 | return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx)); |
AnnaBridge | 163:e59c8e839560 | 2048 | #endif /*RCC_CFGR2_ADCPRE34*/ |
AnnaBridge | 163:e59c8e839560 | 2049 | } |
AnnaBridge | 163:e59c8e839560 | 2050 | #endif /* RCC_CFGR_ADCPRE */ |
AnnaBridge | 163:e59c8e839560 | 2051 | |
AnnaBridge | 163:e59c8e839560 | 2052 | #if defined(RCC_CFGR_SDPRE) |
AnnaBridge | 163:e59c8e839560 | 2053 | /** |
AnnaBridge | 163:e59c8e839560 | 2054 | * @brief Get SDADCx clock source |
AnnaBridge | 163:e59c8e839560 | 2055 | * @rmtoll CFGR SDPRE LL_RCC_GetSDADCClockSource |
AnnaBridge | 163:e59c8e839560 | 2056 | * @param SDADCx This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 2057 | * @arg @ref LL_RCC_SDADC_CLKSOURCE |
AnnaBridge | 163:e59c8e839560 | 2058 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 2059 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 2060 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 2061 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 2062 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6 |
AnnaBridge | 163:e59c8e839560 | 2063 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 2064 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10 |
AnnaBridge | 163:e59c8e839560 | 2065 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12 |
AnnaBridge | 163:e59c8e839560 | 2066 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14 |
AnnaBridge | 163:e59c8e839560 | 2067 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 2068 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20 |
AnnaBridge | 163:e59c8e839560 | 2069 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24 |
AnnaBridge | 163:e59c8e839560 | 2070 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28 |
AnnaBridge | 163:e59c8e839560 | 2071 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32 |
AnnaBridge | 163:e59c8e839560 | 2072 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36 |
AnnaBridge | 163:e59c8e839560 | 2073 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40 |
AnnaBridge | 163:e59c8e839560 | 2074 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44 |
AnnaBridge | 163:e59c8e839560 | 2075 | * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48 |
AnnaBridge | 163:e59c8e839560 | 2076 | */ |
AnnaBridge | 163:e59c8e839560 | 2077 | __STATIC_INLINE uint32_t LL_RCC_GetSDADCClockSource(uint32_t SDADCx) |
AnnaBridge | 163:e59c8e839560 | 2078 | { |
AnnaBridge | 163:e59c8e839560 | 2079 | return (uint32_t)(READ_BIT(RCC->CFGR, SDADCx)); |
AnnaBridge | 163:e59c8e839560 | 2080 | } |
AnnaBridge | 163:e59c8e839560 | 2081 | #endif /* RCC_CFGR_SDPRE */ |
AnnaBridge | 163:e59c8e839560 | 2082 | |
AnnaBridge | 163:e59c8e839560 | 2083 | /** |
AnnaBridge | 163:e59c8e839560 | 2084 | * @} |
AnnaBridge | 163:e59c8e839560 | 2085 | */ |
AnnaBridge | 163:e59c8e839560 | 2086 | |
AnnaBridge | 163:e59c8e839560 | 2087 | /** @defgroup RCC_LL_EF_RTC RTC |
AnnaBridge | 163:e59c8e839560 | 2088 | * @{ |
AnnaBridge | 163:e59c8e839560 | 2089 | */ |
AnnaBridge | 163:e59c8e839560 | 2090 | |
AnnaBridge | 163:e59c8e839560 | 2091 | /** |
AnnaBridge | 163:e59c8e839560 | 2092 | * @brief Set RTC Clock Source |
AnnaBridge | 163:e59c8e839560 | 2093 | * @note Once the RTC clock source has been selected, it cannot be changed any more unless |
AnnaBridge | 163:e59c8e839560 | 2094 | * the Backup domain is reset. The BDRST bit can be used to reset them. |
AnnaBridge | 163:e59c8e839560 | 2095 | * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource |
AnnaBridge | 163:e59c8e839560 | 2096 | * @param Source This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 2097 | * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE |
AnnaBridge | 163:e59c8e839560 | 2098 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE |
AnnaBridge | 163:e59c8e839560 | 2099 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI |
AnnaBridge | 163:e59c8e839560 | 2100 | * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 |
AnnaBridge | 163:e59c8e839560 | 2101 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2102 | */ |
AnnaBridge | 163:e59c8e839560 | 2103 | __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) |
AnnaBridge | 163:e59c8e839560 | 2104 | { |
AnnaBridge | 163:e59c8e839560 | 2105 | MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); |
AnnaBridge | 163:e59c8e839560 | 2106 | } |
AnnaBridge | 163:e59c8e839560 | 2107 | |
AnnaBridge | 163:e59c8e839560 | 2108 | /** |
AnnaBridge | 163:e59c8e839560 | 2109 | * @brief Get RTC Clock Source |
AnnaBridge | 163:e59c8e839560 | 2110 | * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource |
AnnaBridge | 163:e59c8e839560 | 2111 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 2112 | * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE |
AnnaBridge | 163:e59c8e839560 | 2113 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE |
AnnaBridge | 163:e59c8e839560 | 2114 | * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI |
AnnaBridge | 163:e59c8e839560 | 2115 | * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 |
AnnaBridge | 163:e59c8e839560 | 2116 | */ |
AnnaBridge | 163:e59c8e839560 | 2117 | __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) |
AnnaBridge | 163:e59c8e839560 | 2118 | { |
AnnaBridge | 163:e59c8e839560 | 2119 | return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); |
AnnaBridge | 163:e59c8e839560 | 2120 | } |
AnnaBridge | 163:e59c8e839560 | 2121 | |
AnnaBridge | 163:e59c8e839560 | 2122 | /** |
AnnaBridge | 163:e59c8e839560 | 2123 | * @brief Enable RTC |
AnnaBridge | 163:e59c8e839560 | 2124 | * @rmtoll BDCR RTCEN LL_RCC_EnableRTC |
AnnaBridge | 163:e59c8e839560 | 2125 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2126 | */ |
AnnaBridge | 163:e59c8e839560 | 2127 | __STATIC_INLINE void LL_RCC_EnableRTC(void) |
AnnaBridge | 163:e59c8e839560 | 2128 | { |
AnnaBridge | 163:e59c8e839560 | 2129 | SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); |
AnnaBridge | 163:e59c8e839560 | 2130 | } |
AnnaBridge | 163:e59c8e839560 | 2131 | |
AnnaBridge | 163:e59c8e839560 | 2132 | /** |
AnnaBridge | 163:e59c8e839560 | 2133 | * @brief Disable RTC |
AnnaBridge | 163:e59c8e839560 | 2134 | * @rmtoll BDCR RTCEN LL_RCC_DisableRTC |
AnnaBridge | 163:e59c8e839560 | 2135 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2136 | */ |
AnnaBridge | 163:e59c8e839560 | 2137 | __STATIC_INLINE void LL_RCC_DisableRTC(void) |
AnnaBridge | 163:e59c8e839560 | 2138 | { |
AnnaBridge | 163:e59c8e839560 | 2139 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); |
AnnaBridge | 163:e59c8e839560 | 2140 | } |
AnnaBridge | 163:e59c8e839560 | 2141 | |
AnnaBridge | 163:e59c8e839560 | 2142 | /** |
AnnaBridge | 163:e59c8e839560 | 2143 | * @brief Check if RTC has been enabled or not |
AnnaBridge | 163:e59c8e839560 | 2144 | * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC |
AnnaBridge | 163:e59c8e839560 | 2145 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2146 | */ |
AnnaBridge | 163:e59c8e839560 | 2147 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) |
AnnaBridge | 163:e59c8e839560 | 2148 | { |
AnnaBridge | 163:e59c8e839560 | 2149 | return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); |
AnnaBridge | 163:e59c8e839560 | 2150 | } |
AnnaBridge | 163:e59c8e839560 | 2151 | |
AnnaBridge | 163:e59c8e839560 | 2152 | /** |
AnnaBridge | 163:e59c8e839560 | 2153 | * @brief Force the Backup domain reset |
AnnaBridge | 163:e59c8e839560 | 2154 | * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset |
AnnaBridge | 163:e59c8e839560 | 2155 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2156 | */ |
AnnaBridge | 163:e59c8e839560 | 2157 | __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) |
AnnaBridge | 163:e59c8e839560 | 2158 | { |
AnnaBridge | 163:e59c8e839560 | 2159 | SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); |
AnnaBridge | 163:e59c8e839560 | 2160 | } |
AnnaBridge | 163:e59c8e839560 | 2161 | |
AnnaBridge | 163:e59c8e839560 | 2162 | /** |
AnnaBridge | 163:e59c8e839560 | 2163 | * @brief Release the Backup domain reset |
AnnaBridge | 163:e59c8e839560 | 2164 | * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset |
AnnaBridge | 163:e59c8e839560 | 2165 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2166 | */ |
AnnaBridge | 163:e59c8e839560 | 2167 | __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) |
AnnaBridge | 163:e59c8e839560 | 2168 | { |
AnnaBridge | 163:e59c8e839560 | 2169 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); |
AnnaBridge | 163:e59c8e839560 | 2170 | } |
AnnaBridge | 163:e59c8e839560 | 2171 | |
AnnaBridge | 163:e59c8e839560 | 2172 | /** |
AnnaBridge | 163:e59c8e839560 | 2173 | * @} |
AnnaBridge | 163:e59c8e839560 | 2174 | */ |
AnnaBridge | 163:e59c8e839560 | 2175 | |
AnnaBridge | 163:e59c8e839560 | 2176 | /** @defgroup RCC_LL_EF_PLL PLL |
AnnaBridge | 163:e59c8e839560 | 2177 | * @{ |
AnnaBridge | 163:e59c8e839560 | 2178 | */ |
AnnaBridge | 163:e59c8e839560 | 2179 | |
AnnaBridge | 163:e59c8e839560 | 2180 | /** |
AnnaBridge | 163:e59c8e839560 | 2181 | * @brief Enable PLL |
AnnaBridge | 163:e59c8e839560 | 2182 | * @rmtoll CR PLLON LL_RCC_PLL_Enable |
AnnaBridge | 163:e59c8e839560 | 2183 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2184 | */ |
AnnaBridge | 163:e59c8e839560 | 2185 | __STATIC_INLINE void LL_RCC_PLL_Enable(void) |
AnnaBridge | 163:e59c8e839560 | 2186 | { |
AnnaBridge | 163:e59c8e839560 | 2187 | SET_BIT(RCC->CR, RCC_CR_PLLON); |
AnnaBridge | 163:e59c8e839560 | 2188 | } |
AnnaBridge | 163:e59c8e839560 | 2189 | |
AnnaBridge | 163:e59c8e839560 | 2190 | /** |
AnnaBridge | 163:e59c8e839560 | 2191 | * @brief Disable PLL |
AnnaBridge | 163:e59c8e839560 | 2192 | * @note Cannot be disabled if the PLL clock is used as the system clock |
AnnaBridge | 163:e59c8e839560 | 2193 | * @rmtoll CR PLLON LL_RCC_PLL_Disable |
AnnaBridge | 163:e59c8e839560 | 2194 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2195 | */ |
AnnaBridge | 163:e59c8e839560 | 2196 | __STATIC_INLINE void LL_RCC_PLL_Disable(void) |
AnnaBridge | 163:e59c8e839560 | 2197 | { |
AnnaBridge | 163:e59c8e839560 | 2198 | CLEAR_BIT(RCC->CR, RCC_CR_PLLON); |
AnnaBridge | 163:e59c8e839560 | 2199 | } |
AnnaBridge | 163:e59c8e839560 | 2200 | |
AnnaBridge | 163:e59c8e839560 | 2201 | /** |
AnnaBridge | 163:e59c8e839560 | 2202 | * @brief Check if PLL Ready |
AnnaBridge | 163:e59c8e839560 | 2203 | * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady |
AnnaBridge | 163:e59c8e839560 | 2204 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2205 | */ |
AnnaBridge | 163:e59c8e839560 | 2206 | __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) |
AnnaBridge | 163:e59c8e839560 | 2207 | { |
AnnaBridge | 163:e59c8e839560 | 2208 | return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); |
AnnaBridge | 163:e59c8e839560 | 2209 | } |
AnnaBridge | 163:e59c8e839560 | 2210 | |
AnnaBridge | 163:e59c8e839560 | 2211 | #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) |
AnnaBridge | 163:e59c8e839560 | 2212 | /** |
AnnaBridge | 163:e59c8e839560 | 2213 | * @brief Configure PLL used for SYSCLK Domain |
AnnaBridge | 163:e59c8e839560 | 2214 | * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n |
AnnaBridge | 163:e59c8e839560 | 2215 | * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n |
AnnaBridge | 163:e59c8e839560 | 2216 | * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS |
AnnaBridge | 163:e59c8e839560 | 2217 | * @param Source This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 2218 | * @arg @ref LL_RCC_PLLSOURCE_HSI |
AnnaBridge | 163:e59c8e839560 | 2219 | * @arg @ref LL_RCC_PLLSOURCE_HSE |
AnnaBridge | 163:e59c8e839560 | 2220 | * @param PLLMul This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 2221 | * @arg @ref LL_RCC_PLL_MUL_2 |
AnnaBridge | 163:e59c8e839560 | 2222 | * @arg @ref LL_RCC_PLL_MUL_3 |
AnnaBridge | 163:e59c8e839560 | 2223 | * @arg @ref LL_RCC_PLL_MUL_4 |
AnnaBridge | 163:e59c8e839560 | 2224 | * @arg @ref LL_RCC_PLL_MUL_5 |
AnnaBridge | 163:e59c8e839560 | 2225 | * @arg @ref LL_RCC_PLL_MUL_6 |
AnnaBridge | 163:e59c8e839560 | 2226 | * @arg @ref LL_RCC_PLL_MUL_7 |
AnnaBridge | 163:e59c8e839560 | 2227 | * @arg @ref LL_RCC_PLL_MUL_8 |
AnnaBridge | 163:e59c8e839560 | 2228 | * @arg @ref LL_RCC_PLL_MUL_9 |
AnnaBridge | 163:e59c8e839560 | 2229 | * @arg @ref LL_RCC_PLL_MUL_10 |
AnnaBridge | 163:e59c8e839560 | 2230 | * @arg @ref LL_RCC_PLL_MUL_11 |
AnnaBridge | 163:e59c8e839560 | 2231 | * @arg @ref LL_RCC_PLL_MUL_12 |
AnnaBridge | 163:e59c8e839560 | 2232 | * @arg @ref LL_RCC_PLL_MUL_13 |
AnnaBridge | 163:e59c8e839560 | 2233 | * @arg @ref LL_RCC_PLL_MUL_14 |
AnnaBridge | 163:e59c8e839560 | 2234 | * @arg @ref LL_RCC_PLL_MUL_15 |
AnnaBridge | 163:e59c8e839560 | 2235 | * @arg @ref LL_RCC_PLL_MUL_16 |
AnnaBridge | 163:e59c8e839560 | 2236 | * @param PLLDiv This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 2237 | * @arg @ref LL_RCC_PREDIV_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 2238 | * @arg @ref LL_RCC_PREDIV_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 2239 | * @arg @ref LL_RCC_PREDIV_DIV_3 |
AnnaBridge | 163:e59c8e839560 | 2240 | * @arg @ref LL_RCC_PREDIV_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 2241 | * @arg @ref LL_RCC_PREDIV_DIV_5 |
AnnaBridge | 163:e59c8e839560 | 2242 | * @arg @ref LL_RCC_PREDIV_DIV_6 |
AnnaBridge | 163:e59c8e839560 | 2243 | * @arg @ref LL_RCC_PREDIV_DIV_7 |
AnnaBridge | 163:e59c8e839560 | 2244 | * @arg @ref LL_RCC_PREDIV_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 2245 | * @arg @ref LL_RCC_PREDIV_DIV_9 |
AnnaBridge | 163:e59c8e839560 | 2246 | * @arg @ref LL_RCC_PREDIV_DIV_10 |
AnnaBridge | 163:e59c8e839560 | 2247 | * @arg @ref LL_RCC_PREDIV_DIV_11 |
AnnaBridge | 163:e59c8e839560 | 2248 | * @arg @ref LL_RCC_PREDIV_DIV_12 |
AnnaBridge | 163:e59c8e839560 | 2249 | * @arg @ref LL_RCC_PREDIV_DIV_13 |
AnnaBridge | 163:e59c8e839560 | 2250 | * @arg @ref LL_RCC_PREDIV_DIV_14 |
AnnaBridge | 163:e59c8e839560 | 2251 | * @arg @ref LL_RCC_PREDIV_DIV_15 |
AnnaBridge | 163:e59c8e839560 | 2252 | * @arg @ref LL_RCC_PREDIV_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 2253 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2254 | */ |
AnnaBridge | 163:e59c8e839560 | 2255 | __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) |
AnnaBridge | 163:e59c8e839560 | 2256 | { |
AnnaBridge | 163:e59c8e839560 | 2257 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul); |
AnnaBridge | 163:e59c8e839560 | 2258 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv); |
AnnaBridge | 163:e59c8e839560 | 2259 | } |
AnnaBridge | 163:e59c8e839560 | 2260 | |
AnnaBridge | 163:e59c8e839560 | 2261 | #else |
AnnaBridge | 163:e59c8e839560 | 2262 | |
AnnaBridge | 163:e59c8e839560 | 2263 | /** |
AnnaBridge | 163:e59c8e839560 | 2264 | * @brief Configure PLL used for SYSCLK Domain |
AnnaBridge | 163:e59c8e839560 | 2265 | * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n |
AnnaBridge | 163:e59c8e839560 | 2266 | * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n |
AnnaBridge | 163:e59c8e839560 | 2267 | * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS |
AnnaBridge | 163:e59c8e839560 | 2268 | * @param Source This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 2269 | * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 2270 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 2271 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 2272 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 |
AnnaBridge | 163:e59c8e839560 | 2273 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 2274 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 |
AnnaBridge | 163:e59c8e839560 | 2275 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 |
AnnaBridge | 163:e59c8e839560 | 2276 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 |
AnnaBridge | 163:e59c8e839560 | 2277 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 2278 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 |
AnnaBridge | 163:e59c8e839560 | 2279 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 |
AnnaBridge | 163:e59c8e839560 | 2280 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 |
AnnaBridge | 163:e59c8e839560 | 2281 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 |
AnnaBridge | 163:e59c8e839560 | 2282 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 |
AnnaBridge | 163:e59c8e839560 | 2283 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 |
AnnaBridge | 163:e59c8e839560 | 2284 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 |
AnnaBridge | 163:e59c8e839560 | 2285 | * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 2286 | * @param PLLMul This parameter can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 2287 | * @arg @ref LL_RCC_PLL_MUL_2 |
AnnaBridge | 163:e59c8e839560 | 2288 | * @arg @ref LL_RCC_PLL_MUL_3 |
AnnaBridge | 163:e59c8e839560 | 2289 | * @arg @ref LL_RCC_PLL_MUL_4 |
AnnaBridge | 163:e59c8e839560 | 2290 | * @arg @ref LL_RCC_PLL_MUL_5 |
AnnaBridge | 163:e59c8e839560 | 2291 | * @arg @ref LL_RCC_PLL_MUL_6 |
AnnaBridge | 163:e59c8e839560 | 2292 | * @arg @ref LL_RCC_PLL_MUL_7 |
AnnaBridge | 163:e59c8e839560 | 2293 | * @arg @ref LL_RCC_PLL_MUL_8 |
AnnaBridge | 163:e59c8e839560 | 2294 | * @arg @ref LL_RCC_PLL_MUL_9 |
AnnaBridge | 163:e59c8e839560 | 2295 | * @arg @ref LL_RCC_PLL_MUL_10 |
AnnaBridge | 163:e59c8e839560 | 2296 | * @arg @ref LL_RCC_PLL_MUL_11 |
AnnaBridge | 163:e59c8e839560 | 2297 | * @arg @ref LL_RCC_PLL_MUL_12 |
AnnaBridge | 163:e59c8e839560 | 2298 | * @arg @ref LL_RCC_PLL_MUL_13 |
AnnaBridge | 163:e59c8e839560 | 2299 | * @arg @ref LL_RCC_PLL_MUL_14 |
AnnaBridge | 163:e59c8e839560 | 2300 | * @arg @ref LL_RCC_PLL_MUL_15 |
AnnaBridge | 163:e59c8e839560 | 2301 | * @arg @ref LL_RCC_PLL_MUL_16 |
AnnaBridge | 163:e59c8e839560 | 2302 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2303 | */ |
AnnaBridge | 163:e59c8e839560 | 2304 | __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) |
AnnaBridge | 163:e59c8e839560 | 2305 | { |
AnnaBridge | 163:e59c8e839560 | 2306 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul); |
AnnaBridge | 163:e59c8e839560 | 2307 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV)); |
AnnaBridge | 163:e59c8e839560 | 2308 | } |
AnnaBridge | 163:e59c8e839560 | 2309 | #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ |
AnnaBridge | 163:e59c8e839560 | 2310 | |
AnnaBridge | 163:e59c8e839560 | 2311 | /** |
AnnaBridge | 163:e59c8e839560 | 2312 | * @brief Get the oscillator used as PLL clock source. |
AnnaBridge | 163:e59c8e839560 | 2313 | * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource |
AnnaBridge | 163:e59c8e839560 | 2314 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 2315 | * @arg @ref LL_RCC_PLLSOURCE_HSI (*) |
AnnaBridge | 163:e59c8e839560 | 2316 | * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*) |
AnnaBridge | 163:e59c8e839560 | 2317 | * @arg @ref LL_RCC_PLLSOURCE_HSE |
AnnaBridge | 163:e59c8e839560 | 2318 | * |
AnnaBridge | 163:e59c8e839560 | 2319 | * (*) value not defined in all devices |
AnnaBridge | 163:e59c8e839560 | 2320 | */ |
AnnaBridge | 163:e59c8e839560 | 2321 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) |
AnnaBridge | 163:e59c8e839560 | 2322 | { |
AnnaBridge | 163:e59c8e839560 | 2323 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); |
AnnaBridge | 163:e59c8e839560 | 2324 | } |
AnnaBridge | 163:e59c8e839560 | 2325 | |
AnnaBridge | 163:e59c8e839560 | 2326 | /** |
AnnaBridge | 163:e59c8e839560 | 2327 | * @brief Get PLL multiplication Factor |
AnnaBridge | 163:e59c8e839560 | 2328 | * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator |
AnnaBridge | 163:e59c8e839560 | 2329 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 2330 | * @arg @ref LL_RCC_PLL_MUL_2 |
AnnaBridge | 163:e59c8e839560 | 2331 | * @arg @ref LL_RCC_PLL_MUL_3 |
AnnaBridge | 163:e59c8e839560 | 2332 | * @arg @ref LL_RCC_PLL_MUL_4 |
AnnaBridge | 163:e59c8e839560 | 2333 | * @arg @ref LL_RCC_PLL_MUL_5 |
AnnaBridge | 163:e59c8e839560 | 2334 | * @arg @ref LL_RCC_PLL_MUL_6 |
AnnaBridge | 163:e59c8e839560 | 2335 | * @arg @ref LL_RCC_PLL_MUL_7 |
AnnaBridge | 163:e59c8e839560 | 2336 | * @arg @ref LL_RCC_PLL_MUL_8 |
AnnaBridge | 163:e59c8e839560 | 2337 | * @arg @ref LL_RCC_PLL_MUL_9 |
AnnaBridge | 163:e59c8e839560 | 2338 | * @arg @ref LL_RCC_PLL_MUL_10 |
AnnaBridge | 163:e59c8e839560 | 2339 | * @arg @ref LL_RCC_PLL_MUL_11 |
AnnaBridge | 163:e59c8e839560 | 2340 | * @arg @ref LL_RCC_PLL_MUL_12 |
AnnaBridge | 163:e59c8e839560 | 2341 | * @arg @ref LL_RCC_PLL_MUL_13 |
AnnaBridge | 163:e59c8e839560 | 2342 | * @arg @ref LL_RCC_PLL_MUL_14 |
AnnaBridge | 163:e59c8e839560 | 2343 | * @arg @ref LL_RCC_PLL_MUL_15 |
AnnaBridge | 163:e59c8e839560 | 2344 | * @arg @ref LL_RCC_PLL_MUL_16 |
AnnaBridge | 163:e59c8e839560 | 2345 | */ |
AnnaBridge | 163:e59c8e839560 | 2346 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) |
AnnaBridge | 163:e59c8e839560 | 2347 | { |
AnnaBridge | 163:e59c8e839560 | 2348 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL)); |
AnnaBridge | 163:e59c8e839560 | 2349 | } |
AnnaBridge | 163:e59c8e839560 | 2350 | |
AnnaBridge | 163:e59c8e839560 | 2351 | /** |
AnnaBridge | 163:e59c8e839560 | 2352 | * @brief Get PREDIV division factor for the main PLL |
AnnaBridge | 163:e59c8e839560 | 2353 | * @note They can be written only when the PLL is disabled |
AnnaBridge | 163:e59c8e839560 | 2354 | * @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv |
AnnaBridge | 163:e59c8e839560 | 2355 | * @retval Returned value can be one of the following values: |
AnnaBridge | 163:e59c8e839560 | 2356 | * @arg @ref LL_RCC_PREDIV_DIV_1 |
AnnaBridge | 163:e59c8e839560 | 2357 | * @arg @ref LL_RCC_PREDIV_DIV_2 |
AnnaBridge | 163:e59c8e839560 | 2358 | * @arg @ref LL_RCC_PREDIV_DIV_3 |
AnnaBridge | 163:e59c8e839560 | 2359 | * @arg @ref LL_RCC_PREDIV_DIV_4 |
AnnaBridge | 163:e59c8e839560 | 2360 | * @arg @ref LL_RCC_PREDIV_DIV_5 |
AnnaBridge | 163:e59c8e839560 | 2361 | * @arg @ref LL_RCC_PREDIV_DIV_6 |
AnnaBridge | 163:e59c8e839560 | 2362 | * @arg @ref LL_RCC_PREDIV_DIV_7 |
AnnaBridge | 163:e59c8e839560 | 2363 | * @arg @ref LL_RCC_PREDIV_DIV_8 |
AnnaBridge | 163:e59c8e839560 | 2364 | * @arg @ref LL_RCC_PREDIV_DIV_9 |
AnnaBridge | 163:e59c8e839560 | 2365 | * @arg @ref LL_RCC_PREDIV_DIV_10 |
AnnaBridge | 163:e59c8e839560 | 2366 | * @arg @ref LL_RCC_PREDIV_DIV_11 |
AnnaBridge | 163:e59c8e839560 | 2367 | * @arg @ref LL_RCC_PREDIV_DIV_12 |
AnnaBridge | 163:e59c8e839560 | 2368 | * @arg @ref LL_RCC_PREDIV_DIV_13 |
AnnaBridge | 163:e59c8e839560 | 2369 | * @arg @ref LL_RCC_PREDIV_DIV_14 |
AnnaBridge | 163:e59c8e839560 | 2370 | * @arg @ref LL_RCC_PREDIV_DIV_15 |
AnnaBridge | 163:e59c8e839560 | 2371 | * @arg @ref LL_RCC_PREDIV_DIV_16 |
AnnaBridge | 163:e59c8e839560 | 2372 | */ |
AnnaBridge | 163:e59c8e839560 | 2373 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void) |
AnnaBridge | 163:e59c8e839560 | 2374 | { |
AnnaBridge | 163:e59c8e839560 | 2375 | return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)); |
AnnaBridge | 163:e59c8e839560 | 2376 | } |
AnnaBridge | 163:e59c8e839560 | 2377 | |
AnnaBridge | 163:e59c8e839560 | 2378 | /** |
AnnaBridge | 163:e59c8e839560 | 2379 | * @} |
AnnaBridge | 163:e59c8e839560 | 2380 | */ |
AnnaBridge | 163:e59c8e839560 | 2381 | |
AnnaBridge | 163:e59c8e839560 | 2382 | /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management |
AnnaBridge | 163:e59c8e839560 | 2383 | * @{ |
AnnaBridge | 163:e59c8e839560 | 2384 | */ |
AnnaBridge | 163:e59c8e839560 | 2385 | |
AnnaBridge | 163:e59c8e839560 | 2386 | /** |
AnnaBridge | 163:e59c8e839560 | 2387 | * @brief Clear LSI ready interrupt flag |
AnnaBridge | 163:e59c8e839560 | 2388 | * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY |
AnnaBridge | 163:e59c8e839560 | 2389 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2390 | */ |
AnnaBridge | 163:e59c8e839560 | 2391 | __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) |
AnnaBridge | 163:e59c8e839560 | 2392 | { |
AnnaBridge | 163:e59c8e839560 | 2393 | SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); |
AnnaBridge | 163:e59c8e839560 | 2394 | } |
AnnaBridge | 163:e59c8e839560 | 2395 | |
AnnaBridge | 163:e59c8e839560 | 2396 | /** |
AnnaBridge | 163:e59c8e839560 | 2397 | * @brief Clear LSE ready interrupt flag |
AnnaBridge | 163:e59c8e839560 | 2398 | * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY |
AnnaBridge | 163:e59c8e839560 | 2399 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2400 | */ |
AnnaBridge | 163:e59c8e839560 | 2401 | __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) |
AnnaBridge | 163:e59c8e839560 | 2402 | { |
AnnaBridge | 163:e59c8e839560 | 2403 | SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); |
AnnaBridge | 163:e59c8e839560 | 2404 | } |
AnnaBridge | 163:e59c8e839560 | 2405 | |
AnnaBridge | 163:e59c8e839560 | 2406 | /** |
AnnaBridge | 163:e59c8e839560 | 2407 | * @brief Clear HSI ready interrupt flag |
AnnaBridge | 163:e59c8e839560 | 2408 | * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY |
AnnaBridge | 163:e59c8e839560 | 2409 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2410 | */ |
AnnaBridge | 163:e59c8e839560 | 2411 | __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) |
AnnaBridge | 163:e59c8e839560 | 2412 | { |
AnnaBridge | 163:e59c8e839560 | 2413 | SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); |
AnnaBridge | 163:e59c8e839560 | 2414 | } |
AnnaBridge | 163:e59c8e839560 | 2415 | |
AnnaBridge | 163:e59c8e839560 | 2416 | /** |
AnnaBridge | 163:e59c8e839560 | 2417 | * @brief Clear HSE ready interrupt flag |
AnnaBridge | 163:e59c8e839560 | 2418 | * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY |
AnnaBridge | 163:e59c8e839560 | 2419 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2420 | */ |
AnnaBridge | 163:e59c8e839560 | 2421 | __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) |
AnnaBridge | 163:e59c8e839560 | 2422 | { |
AnnaBridge | 163:e59c8e839560 | 2423 | SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); |
AnnaBridge | 163:e59c8e839560 | 2424 | } |
AnnaBridge | 163:e59c8e839560 | 2425 | |
AnnaBridge | 163:e59c8e839560 | 2426 | /** |
AnnaBridge | 163:e59c8e839560 | 2427 | * @brief Clear PLL ready interrupt flag |
AnnaBridge | 163:e59c8e839560 | 2428 | * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY |
AnnaBridge | 163:e59c8e839560 | 2429 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2430 | */ |
AnnaBridge | 163:e59c8e839560 | 2431 | __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) |
AnnaBridge | 163:e59c8e839560 | 2432 | { |
AnnaBridge | 163:e59c8e839560 | 2433 | SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); |
AnnaBridge | 163:e59c8e839560 | 2434 | } |
AnnaBridge | 163:e59c8e839560 | 2435 | |
AnnaBridge | 163:e59c8e839560 | 2436 | /** |
AnnaBridge | 163:e59c8e839560 | 2437 | * @brief Clear Clock security system interrupt flag |
AnnaBridge | 163:e59c8e839560 | 2438 | * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS |
AnnaBridge | 163:e59c8e839560 | 2439 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2440 | */ |
AnnaBridge | 163:e59c8e839560 | 2441 | __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) |
AnnaBridge | 163:e59c8e839560 | 2442 | { |
AnnaBridge | 163:e59c8e839560 | 2443 | SET_BIT(RCC->CIR, RCC_CIR_CSSC); |
AnnaBridge | 163:e59c8e839560 | 2444 | } |
AnnaBridge | 163:e59c8e839560 | 2445 | |
AnnaBridge | 163:e59c8e839560 | 2446 | /** |
AnnaBridge | 163:e59c8e839560 | 2447 | * @brief Check if LSI ready interrupt occurred or not |
AnnaBridge | 163:e59c8e839560 | 2448 | * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY |
AnnaBridge | 163:e59c8e839560 | 2449 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2450 | */ |
AnnaBridge | 163:e59c8e839560 | 2451 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) |
AnnaBridge | 163:e59c8e839560 | 2452 | { |
AnnaBridge | 163:e59c8e839560 | 2453 | return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); |
AnnaBridge | 163:e59c8e839560 | 2454 | } |
AnnaBridge | 163:e59c8e839560 | 2455 | |
AnnaBridge | 163:e59c8e839560 | 2456 | /** |
AnnaBridge | 163:e59c8e839560 | 2457 | * @brief Check if LSE ready interrupt occurred or not |
AnnaBridge | 163:e59c8e839560 | 2458 | * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY |
AnnaBridge | 163:e59c8e839560 | 2459 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2460 | */ |
AnnaBridge | 163:e59c8e839560 | 2461 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) |
AnnaBridge | 163:e59c8e839560 | 2462 | { |
AnnaBridge | 163:e59c8e839560 | 2463 | return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); |
AnnaBridge | 163:e59c8e839560 | 2464 | } |
AnnaBridge | 163:e59c8e839560 | 2465 | |
AnnaBridge | 163:e59c8e839560 | 2466 | /** |
AnnaBridge | 163:e59c8e839560 | 2467 | * @brief Check if HSI ready interrupt occurred or not |
AnnaBridge | 163:e59c8e839560 | 2468 | * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY |
AnnaBridge | 163:e59c8e839560 | 2469 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2470 | */ |
AnnaBridge | 163:e59c8e839560 | 2471 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) |
AnnaBridge | 163:e59c8e839560 | 2472 | { |
AnnaBridge | 163:e59c8e839560 | 2473 | return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); |
AnnaBridge | 163:e59c8e839560 | 2474 | } |
AnnaBridge | 163:e59c8e839560 | 2475 | |
AnnaBridge | 163:e59c8e839560 | 2476 | /** |
AnnaBridge | 163:e59c8e839560 | 2477 | * @brief Check if HSE ready interrupt occurred or not |
AnnaBridge | 163:e59c8e839560 | 2478 | * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY |
AnnaBridge | 163:e59c8e839560 | 2479 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2480 | */ |
AnnaBridge | 163:e59c8e839560 | 2481 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) |
AnnaBridge | 163:e59c8e839560 | 2482 | { |
AnnaBridge | 163:e59c8e839560 | 2483 | return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); |
AnnaBridge | 163:e59c8e839560 | 2484 | } |
AnnaBridge | 163:e59c8e839560 | 2485 | |
AnnaBridge | 163:e59c8e839560 | 2486 | #if defined(RCC_CFGR_MCOF) |
AnnaBridge | 163:e59c8e839560 | 2487 | /** |
AnnaBridge | 163:e59c8e839560 | 2488 | * @brief Check if switch to new MCO source is effective or not |
AnnaBridge | 163:e59c8e839560 | 2489 | * @rmtoll CFGR MCOF LL_RCC_IsActiveFlag_MCO1 |
AnnaBridge | 163:e59c8e839560 | 2490 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2491 | */ |
AnnaBridge | 163:e59c8e839560 | 2492 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MCO1(void) |
AnnaBridge | 163:e59c8e839560 | 2493 | { |
AnnaBridge | 163:e59c8e839560 | 2494 | return (READ_BIT(RCC->CFGR, RCC_CFGR_MCOF) == (RCC_CFGR_MCOF)); |
AnnaBridge | 163:e59c8e839560 | 2495 | } |
AnnaBridge | 163:e59c8e839560 | 2496 | #endif /* RCC_CFGR_MCOF */ |
AnnaBridge | 163:e59c8e839560 | 2497 | |
AnnaBridge | 163:e59c8e839560 | 2498 | /** |
AnnaBridge | 163:e59c8e839560 | 2499 | * @brief Check if PLL ready interrupt occurred or not |
AnnaBridge | 163:e59c8e839560 | 2500 | * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY |
AnnaBridge | 163:e59c8e839560 | 2501 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2502 | */ |
AnnaBridge | 163:e59c8e839560 | 2503 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) |
AnnaBridge | 163:e59c8e839560 | 2504 | { |
AnnaBridge | 163:e59c8e839560 | 2505 | return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); |
AnnaBridge | 163:e59c8e839560 | 2506 | } |
AnnaBridge | 163:e59c8e839560 | 2507 | |
AnnaBridge | 163:e59c8e839560 | 2508 | /** |
AnnaBridge | 163:e59c8e839560 | 2509 | * @brief Check if Clock security system interrupt occurred or not |
AnnaBridge | 163:e59c8e839560 | 2510 | * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS |
AnnaBridge | 163:e59c8e839560 | 2511 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2512 | */ |
AnnaBridge | 163:e59c8e839560 | 2513 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) |
AnnaBridge | 163:e59c8e839560 | 2514 | { |
AnnaBridge | 163:e59c8e839560 | 2515 | return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); |
AnnaBridge | 163:e59c8e839560 | 2516 | } |
AnnaBridge | 163:e59c8e839560 | 2517 | |
AnnaBridge | 163:e59c8e839560 | 2518 | /** |
AnnaBridge | 163:e59c8e839560 | 2519 | * @brief Check if RCC flag Independent Watchdog reset is set or not. |
AnnaBridge | 163:e59c8e839560 | 2520 | * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST |
AnnaBridge | 163:e59c8e839560 | 2521 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2522 | */ |
AnnaBridge | 163:e59c8e839560 | 2523 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) |
AnnaBridge | 163:e59c8e839560 | 2524 | { |
AnnaBridge | 163:e59c8e839560 | 2525 | return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); |
AnnaBridge | 163:e59c8e839560 | 2526 | } |
AnnaBridge | 163:e59c8e839560 | 2527 | |
AnnaBridge | 163:e59c8e839560 | 2528 | /** |
AnnaBridge | 163:e59c8e839560 | 2529 | * @brief Check if RCC flag Low Power reset is set or not. |
AnnaBridge | 163:e59c8e839560 | 2530 | * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST |
AnnaBridge | 163:e59c8e839560 | 2531 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2532 | */ |
AnnaBridge | 163:e59c8e839560 | 2533 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) |
AnnaBridge | 163:e59c8e839560 | 2534 | { |
AnnaBridge | 163:e59c8e839560 | 2535 | return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); |
AnnaBridge | 163:e59c8e839560 | 2536 | } |
AnnaBridge | 163:e59c8e839560 | 2537 | |
AnnaBridge | 163:e59c8e839560 | 2538 | /** |
AnnaBridge | 163:e59c8e839560 | 2539 | * @brief Check if RCC flag is set or not. |
AnnaBridge | 163:e59c8e839560 | 2540 | * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST |
AnnaBridge | 163:e59c8e839560 | 2541 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2542 | */ |
AnnaBridge | 163:e59c8e839560 | 2543 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) |
AnnaBridge | 163:e59c8e839560 | 2544 | { |
AnnaBridge | 163:e59c8e839560 | 2545 | return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)); |
AnnaBridge | 163:e59c8e839560 | 2546 | } |
AnnaBridge | 163:e59c8e839560 | 2547 | |
AnnaBridge | 163:e59c8e839560 | 2548 | /** |
AnnaBridge | 163:e59c8e839560 | 2549 | * @brief Check if RCC flag Pin reset is set or not. |
AnnaBridge | 163:e59c8e839560 | 2550 | * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST |
AnnaBridge | 163:e59c8e839560 | 2551 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2552 | */ |
AnnaBridge | 163:e59c8e839560 | 2553 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) |
AnnaBridge | 163:e59c8e839560 | 2554 | { |
AnnaBridge | 163:e59c8e839560 | 2555 | return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); |
AnnaBridge | 163:e59c8e839560 | 2556 | } |
AnnaBridge | 163:e59c8e839560 | 2557 | |
AnnaBridge | 163:e59c8e839560 | 2558 | /** |
AnnaBridge | 163:e59c8e839560 | 2559 | * @brief Check if RCC flag POR/PDR reset is set or not. |
AnnaBridge | 163:e59c8e839560 | 2560 | * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST |
AnnaBridge | 163:e59c8e839560 | 2561 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2562 | */ |
AnnaBridge | 163:e59c8e839560 | 2563 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) |
AnnaBridge | 163:e59c8e839560 | 2564 | { |
AnnaBridge | 163:e59c8e839560 | 2565 | return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); |
AnnaBridge | 163:e59c8e839560 | 2566 | } |
AnnaBridge | 163:e59c8e839560 | 2567 | |
AnnaBridge | 163:e59c8e839560 | 2568 | /** |
AnnaBridge | 163:e59c8e839560 | 2569 | * @brief Check if RCC flag Software reset is set or not. |
AnnaBridge | 163:e59c8e839560 | 2570 | * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST |
AnnaBridge | 163:e59c8e839560 | 2571 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2572 | */ |
AnnaBridge | 163:e59c8e839560 | 2573 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) |
AnnaBridge | 163:e59c8e839560 | 2574 | { |
AnnaBridge | 163:e59c8e839560 | 2575 | return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); |
AnnaBridge | 163:e59c8e839560 | 2576 | } |
AnnaBridge | 163:e59c8e839560 | 2577 | |
AnnaBridge | 163:e59c8e839560 | 2578 | /** |
AnnaBridge | 163:e59c8e839560 | 2579 | * @brief Check if RCC flag Window Watchdog reset is set or not. |
AnnaBridge | 163:e59c8e839560 | 2580 | * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST |
AnnaBridge | 163:e59c8e839560 | 2581 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2582 | */ |
AnnaBridge | 163:e59c8e839560 | 2583 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) |
AnnaBridge | 163:e59c8e839560 | 2584 | { |
AnnaBridge | 163:e59c8e839560 | 2585 | return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); |
AnnaBridge | 163:e59c8e839560 | 2586 | } |
AnnaBridge | 163:e59c8e839560 | 2587 | |
AnnaBridge | 163:e59c8e839560 | 2588 | #if defined(RCC_CSR_V18PWRRSTF) |
AnnaBridge | 163:e59c8e839560 | 2589 | /** |
AnnaBridge | 163:e59c8e839560 | 2590 | * @brief Check if RCC Reset flag of the 1.8 V domain is set or not. |
AnnaBridge | 163:e59c8e839560 | 2591 | * @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST |
AnnaBridge | 163:e59c8e839560 | 2592 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2593 | */ |
AnnaBridge | 163:e59c8e839560 | 2594 | __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void) |
AnnaBridge | 163:e59c8e839560 | 2595 | { |
AnnaBridge | 163:e59c8e839560 | 2596 | return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF)); |
AnnaBridge | 163:e59c8e839560 | 2597 | } |
AnnaBridge | 163:e59c8e839560 | 2598 | #endif /* RCC_CSR_V18PWRRSTF */ |
AnnaBridge | 163:e59c8e839560 | 2599 | |
AnnaBridge | 163:e59c8e839560 | 2600 | /** |
AnnaBridge | 163:e59c8e839560 | 2601 | * @brief Set RMVF bit to clear the reset flags. |
AnnaBridge | 163:e59c8e839560 | 2602 | * @rmtoll CSR RMVF LL_RCC_ClearResetFlags |
AnnaBridge | 163:e59c8e839560 | 2603 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2604 | */ |
AnnaBridge | 163:e59c8e839560 | 2605 | __STATIC_INLINE void LL_RCC_ClearResetFlags(void) |
AnnaBridge | 163:e59c8e839560 | 2606 | { |
AnnaBridge | 163:e59c8e839560 | 2607 | SET_BIT(RCC->CSR, RCC_CSR_RMVF); |
AnnaBridge | 163:e59c8e839560 | 2608 | } |
AnnaBridge | 163:e59c8e839560 | 2609 | |
AnnaBridge | 163:e59c8e839560 | 2610 | /** |
AnnaBridge | 163:e59c8e839560 | 2611 | * @} |
AnnaBridge | 163:e59c8e839560 | 2612 | */ |
AnnaBridge | 163:e59c8e839560 | 2613 | |
AnnaBridge | 163:e59c8e839560 | 2614 | /** @defgroup RCC_LL_EF_IT_Management IT Management |
AnnaBridge | 163:e59c8e839560 | 2615 | * @{ |
AnnaBridge | 163:e59c8e839560 | 2616 | */ |
AnnaBridge | 163:e59c8e839560 | 2617 | |
AnnaBridge | 163:e59c8e839560 | 2618 | /** |
AnnaBridge | 163:e59c8e839560 | 2619 | * @brief Enable LSI ready interrupt |
AnnaBridge | 163:e59c8e839560 | 2620 | * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY |
AnnaBridge | 163:e59c8e839560 | 2621 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2622 | */ |
AnnaBridge | 163:e59c8e839560 | 2623 | __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) |
AnnaBridge | 163:e59c8e839560 | 2624 | { |
AnnaBridge | 163:e59c8e839560 | 2625 | SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); |
AnnaBridge | 163:e59c8e839560 | 2626 | } |
AnnaBridge | 163:e59c8e839560 | 2627 | |
AnnaBridge | 163:e59c8e839560 | 2628 | /** |
AnnaBridge | 163:e59c8e839560 | 2629 | * @brief Enable LSE ready interrupt |
AnnaBridge | 163:e59c8e839560 | 2630 | * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY |
AnnaBridge | 163:e59c8e839560 | 2631 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2632 | */ |
AnnaBridge | 163:e59c8e839560 | 2633 | __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) |
AnnaBridge | 163:e59c8e839560 | 2634 | { |
AnnaBridge | 163:e59c8e839560 | 2635 | SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); |
AnnaBridge | 163:e59c8e839560 | 2636 | } |
AnnaBridge | 163:e59c8e839560 | 2637 | |
AnnaBridge | 163:e59c8e839560 | 2638 | /** |
AnnaBridge | 163:e59c8e839560 | 2639 | * @brief Enable HSI ready interrupt |
AnnaBridge | 163:e59c8e839560 | 2640 | * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY |
AnnaBridge | 163:e59c8e839560 | 2641 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2642 | */ |
AnnaBridge | 163:e59c8e839560 | 2643 | __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) |
AnnaBridge | 163:e59c8e839560 | 2644 | { |
AnnaBridge | 163:e59c8e839560 | 2645 | SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); |
AnnaBridge | 163:e59c8e839560 | 2646 | } |
AnnaBridge | 163:e59c8e839560 | 2647 | |
AnnaBridge | 163:e59c8e839560 | 2648 | /** |
AnnaBridge | 163:e59c8e839560 | 2649 | * @brief Enable HSE ready interrupt |
AnnaBridge | 163:e59c8e839560 | 2650 | * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY |
AnnaBridge | 163:e59c8e839560 | 2651 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2652 | */ |
AnnaBridge | 163:e59c8e839560 | 2653 | __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) |
AnnaBridge | 163:e59c8e839560 | 2654 | { |
AnnaBridge | 163:e59c8e839560 | 2655 | SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); |
AnnaBridge | 163:e59c8e839560 | 2656 | } |
AnnaBridge | 163:e59c8e839560 | 2657 | |
AnnaBridge | 163:e59c8e839560 | 2658 | /** |
AnnaBridge | 163:e59c8e839560 | 2659 | * @brief Enable PLL ready interrupt |
AnnaBridge | 163:e59c8e839560 | 2660 | * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY |
AnnaBridge | 163:e59c8e839560 | 2661 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2662 | */ |
AnnaBridge | 163:e59c8e839560 | 2663 | __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) |
AnnaBridge | 163:e59c8e839560 | 2664 | { |
AnnaBridge | 163:e59c8e839560 | 2665 | SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); |
AnnaBridge | 163:e59c8e839560 | 2666 | } |
AnnaBridge | 163:e59c8e839560 | 2667 | |
AnnaBridge | 163:e59c8e839560 | 2668 | /** |
AnnaBridge | 163:e59c8e839560 | 2669 | * @brief Disable LSI ready interrupt |
AnnaBridge | 163:e59c8e839560 | 2670 | * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY |
AnnaBridge | 163:e59c8e839560 | 2671 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2672 | */ |
AnnaBridge | 163:e59c8e839560 | 2673 | __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) |
AnnaBridge | 163:e59c8e839560 | 2674 | { |
AnnaBridge | 163:e59c8e839560 | 2675 | CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); |
AnnaBridge | 163:e59c8e839560 | 2676 | } |
AnnaBridge | 163:e59c8e839560 | 2677 | |
AnnaBridge | 163:e59c8e839560 | 2678 | /** |
AnnaBridge | 163:e59c8e839560 | 2679 | * @brief Disable LSE ready interrupt |
AnnaBridge | 163:e59c8e839560 | 2680 | * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY |
AnnaBridge | 163:e59c8e839560 | 2681 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2682 | */ |
AnnaBridge | 163:e59c8e839560 | 2683 | __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) |
AnnaBridge | 163:e59c8e839560 | 2684 | { |
AnnaBridge | 163:e59c8e839560 | 2685 | CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); |
AnnaBridge | 163:e59c8e839560 | 2686 | } |
AnnaBridge | 163:e59c8e839560 | 2687 | |
AnnaBridge | 163:e59c8e839560 | 2688 | /** |
AnnaBridge | 163:e59c8e839560 | 2689 | * @brief Disable HSI ready interrupt |
AnnaBridge | 163:e59c8e839560 | 2690 | * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY |
AnnaBridge | 163:e59c8e839560 | 2691 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2692 | */ |
AnnaBridge | 163:e59c8e839560 | 2693 | __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) |
AnnaBridge | 163:e59c8e839560 | 2694 | { |
AnnaBridge | 163:e59c8e839560 | 2695 | CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); |
AnnaBridge | 163:e59c8e839560 | 2696 | } |
AnnaBridge | 163:e59c8e839560 | 2697 | |
AnnaBridge | 163:e59c8e839560 | 2698 | /** |
AnnaBridge | 163:e59c8e839560 | 2699 | * @brief Disable HSE ready interrupt |
AnnaBridge | 163:e59c8e839560 | 2700 | * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY |
AnnaBridge | 163:e59c8e839560 | 2701 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2702 | */ |
AnnaBridge | 163:e59c8e839560 | 2703 | __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) |
AnnaBridge | 163:e59c8e839560 | 2704 | { |
AnnaBridge | 163:e59c8e839560 | 2705 | CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); |
AnnaBridge | 163:e59c8e839560 | 2706 | } |
AnnaBridge | 163:e59c8e839560 | 2707 | |
AnnaBridge | 163:e59c8e839560 | 2708 | /** |
AnnaBridge | 163:e59c8e839560 | 2709 | * @brief Disable PLL ready interrupt |
AnnaBridge | 163:e59c8e839560 | 2710 | * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY |
AnnaBridge | 163:e59c8e839560 | 2711 | * @retval None |
AnnaBridge | 163:e59c8e839560 | 2712 | */ |
AnnaBridge | 163:e59c8e839560 | 2713 | __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) |
AnnaBridge | 163:e59c8e839560 | 2714 | { |
AnnaBridge | 163:e59c8e839560 | 2715 | CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); |
AnnaBridge | 163:e59c8e839560 | 2716 | } |
AnnaBridge | 163:e59c8e839560 | 2717 | |
AnnaBridge | 163:e59c8e839560 | 2718 | /** |
AnnaBridge | 163:e59c8e839560 | 2719 | * @brief Checks if LSI ready interrupt source is enabled or disabled. |
AnnaBridge | 163:e59c8e839560 | 2720 | * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY |
AnnaBridge | 163:e59c8e839560 | 2721 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2722 | */ |
AnnaBridge | 163:e59c8e839560 | 2723 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) |
AnnaBridge | 163:e59c8e839560 | 2724 | { |
AnnaBridge | 163:e59c8e839560 | 2725 | return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); |
AnnaBridge | 163:e59c8e839560 | 2726 | } |
AnnaBridge | 163:e59c8e839560 | 2727 | |
AnnaBridge | 163:e59c8e839560 | 2728 | /** |
AnnaBridge | 163:e59c8e839560 | 2729 | * @brief Checks if LSE ready interrupt source is enabled or disabled. |
AnnaBridge | 163:e59c8e839560 | 2730 | * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY |
AnnaBridge | 163:e59c8e839560 | 2731 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2732 | */ |
AnnaBridge | 163:e59c8e839560 | 2733 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) |
AnnaBridge | 163:e59c8e839560 | 2734 | { |
AnnaBridge | 163:e59c8e839560 | 2735 | return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); |
AnnaBridge | 163:e59c8e839560 | 2736 | } |
AnnaBridge | 163:e59c8e839560 | 2737 | |
AnnaBridge | 163:e59c8e839560 | 2738 | /** |
AnnaBridge | 163:e59c8e839560 | 2739 | * @brief Checks if HSI ready interrupt source is enabled or disabled. |
AnnaBridge | 163:e59c8e839560 | 2740 | * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY |
AnnaBridge | 163:e59c8e839560 | 2741 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2742 | */ |
AnnaBridge | 163:e59c8e839560 | 2743 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) |
AnnaBridge | 163:e59c8e839560 | 2744 | { |
AnnaBridge | 163:e59c8e839560 | 2745 | return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); |
AnnaBridge | 163:e59c8e839560 | 2746 | } |
AnnaBridge | 163:e59c8e839560 | 2747 | |
AnnaBridge | 163:e59c8e839560 | 2748 | /** |
AnnaBridge | 163:e59c8e839560 | 2749 | * @brief Checks if HSE ready interrupt source is enabled or disabled. |
AnnaBridge | 163:e59c8e839560 | 2750 | * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY |
AnnaBridge | 163:e59c8e839560 | 2751 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2752 | */ |
AnnaBridge | 163:e59c8e839560 | 2753 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) |
AnnaBridge | 163:e59c8e839560 | 2754 | { |
AnnaBridge | 163:e59c8e839560 | 2755 | return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); |
AnnaBridge | 163:e59c8e839560 | 2756 | } |
AnnaBridge | 163:e59c8e839560 | 2757 | |
AnnaBridge | 163:e59c8e839560 | 2758 | /** |
AnnaBridge | 163:e59c8e839560 | 2759 | * @brief Checks if PLL ready interrupt source is enabled or disabled. |
AnnaBridge | 163:e59c8e839560 | 2760 | * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY |
AnnaBridge | 163:e59c8e839560 | 2761 | * @retval State of bit (1 or 0). |
AnnaBridge | 163:e59c8e839560 | 2762 | */ |
AnnaBridge | 163:e59c8e839560 | 2763 | __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) |
AnnaBridge | 163:e59c8e839560 | 2764 | { |
AnnaBridge | 163:e59c8e839560 | 2765 | return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); |
AnnaBridge | 163:e59c8e839560 | 2766 | } |
AnnaBridge | 163:e59c8e839560 | 2767 | |
AnnaBridge | 163:e59c8e839560 | 2768 | /** |
AnnaBridge | 163:e59c8e839560 | 2769 | * @} |
AnnaBridge | 163:e59c8e839560 | 2770 | */ |
AnnaBridge | 163:e59c8e839560 | 2771 | |
AnnaBridge | 163:e59c8e839560 | 2772 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 163:e59c8e839560 | 2773 | /** @defgroup RCC_LL_EF_Init De-initialization function |
AnnaBridge | 163:e59c8e839560 | 2774 | * @{ |
AnnaBridge | 163:e59c8e839560 | 2775 | */ |
AnnaBridge | 163:e59c8e839560 | 2776 | ErrorStatus LL_RCC_DeInit(void); |
AnnaBridge | 163:e59c8e839560 | 2777 | /** |
AnnaBridge | 163:e59c8e839560 | 2778 | * @} |
AnnaBridge | 163:e59c8e839560 | 2779 | */ |
AnnaBridge | 163:e59c8e839560 | 2780 | |
AnnaBridge | 163:e59c8e839560 | 2781 | /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions |
AnnaBridge | 163:e59c8e839560 | 2782 | * @{ |
AnnaBridge | 163:e59c8e839560 | 2783 | */ |
AnnaBridge | 163:e59c8e839560 | 2784 | void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); |
AnnaBridge | 163:e59c8e839560 | 2785 | uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); |
AnnaBridge | 163:e59c8e839560 | 2786 | #if defined(UART4) || defined(UART5) |
AnnaBridge | 163:e59c8e839560 | 2787 | uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); |
AnnaBridge | 163:e59c8e839560 | 2788 | #endif /* UART4 || UART5 */ |
AnnaBridge | 163:e59c8e839560 | 2789 | uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); |
AnnaBridge | 163:e59c8e839560 | 2790 | #if defined(RCC_CFGR_I2SSRC) |
AnnaBridge | 163:e59c8e839560 | 2791 | uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); |
AnnaBridge | 163:e59c8e839560 | 2792 | #endif /* RCC_CFGR_I2SSRC */ |
AnnaBridge | 163:e59c8e839560 | 2793 | #if defined(USB_OTG_FS) || defined(USB) |
AnnaBridge | 163:e59c8e839560 | 2794 | uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); |
AnnaBridge | 163:e59c8e839560 | 2795 | #endif /* USB_OTG_FS || USB */ |
AnnaBridge | 163:e59c8e839560 | 2796 | #if (defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)) |
AnnaBridge | 163:e59c8e839560 | 2797 | uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); |
AnnaBridge | 163:e59c8e839560 | 2798 | #endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ |
AnnaBridge | 163:e59c8e839560 | 2799 | #if defined(RCC_CFGR_SDPRE) |
AnnaBridge | 163:e59c8e839560 | 2800 | uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource); |
AnnaBridge | 163:e59c8e839560 | 2801 | #endif /*RCC_CFGR_SDPRE */ |
AnnaBridge | 163:e59c8e839560 | 2802 | #if defined(CEC) |
AnnaBridge | 163:e59c8e839560 | 2803 | uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); |
AnnaBridge | 163:e59c8e839560 | 2804 | #endif /* CEC */ |
AnnaBridge | 163:e59c8e839560 | 2805 | #if defined(RCC_CFGR3_TIMSW) |
AnnaBridge | 163:e59c8e839560 | 2806 | uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource); |
AnnaBridge | 163:e59c8e839560 | 2807 | #endif /*RCC_CFGR3_TIMSW*/ |
AnnaBridge | 163:e59c8e839560 | 2808 | uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource); |
AnnaBridge | 163:e59c8e839560 | 2809 | /** |
AnnaBridge | 163:e59c8e839560 | 2810 | * @} |
AnnaBridge | 163:e59c8e839560 | 2811 | */ |
AnnaBridge | 163:e59c8e839560 | 2812 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 163:e59c8e839560 | 2813 | |
AnnaBridge | 163:e59c8e839560 | 2814 | /** |
AnnaBridge | 163:e59c8e839560 | 2815 | * @} |
AnnaBridge | 163:e59c8e839560 | 2816 | */ |
AnnaBridge | 163:e59c8e839560 | 2817 | |
AnnaBridge | 163:e59c8e839560 | 2818 | /** |
AnnaBridge | 163:e59c8e839560 | 2819 | * @} |
AnnaBridge | 163:e59c8e839560 | 2820 | */ |
AnnaBridge | 163:e59c8e839560 | 2821 | |
AnnaBridge | 163:e59c8e839560 | 2822 | #endif /* RCC */ |
AnnaBridge | 163:e59c8e839560 | 2823 | |
AnnaBridge | 163:e59c8e839560 | 2824 | /** |
AnnaBridge | 163:e59c8e839560 | 2825 | * @} |
AnnaBridge | 163:e59c8e839560 | 2826 | */ |
AnnaBridge | 163:e59c8e839560 | 2827 | |
AnnaBridge | 163:e59c8e839560 | 2828 | #ifdef __cplusplus |
AnnaBridge | 163:e59c8e839560 | 2829 | } |
AnnaBridge | 163:e59c8e839560 | 2830 | #endif |
AnnaBridge | 163:e59c8e839560 | 2831 | |
AnnaBridge | 163:e59c8e839560 | 2832 | #endif /* __STM32F3xx_LL_RCC_H */ |
AnnaBridge | 163:e59c8e839560 | 2833 | |
AnnaBridge | 163:e59c8e839560 | 2834 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |