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TARGET_ARM_CM3DS_MPS2/TOOLCHAIN_IAR/CM3DS.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 169:a7c7b631e539 1 /*
Anna Bridge 169:a7c7b631e539 2 * Copyright (c) 2009-2018 ARM Limited. All rights reserved.
Anna Bridge 169:a7c7b631e539 3 *
Anna Bridge 169:a7c7b631e539 4 * SPDX-License-Identifier: Apache-2.0
Anna Bridge 169:a7c7b631e539 5 *
Anna Bridge 169:a7c7b631e539 6 * Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge 169:a7c7b631e539 7 * not use this file except in compliance with the License.
Anna Bridge 169:a7c7b631e539 8 * You may obtain a copy of the License at
Anna Bridge 169:a7c7b631e539 9 *
Anna Bridge 169:a7c7b631e539 10 * http://www.apache.org/licenses/LICENSE-2.0
Anna Bridge 169:a7c7b631e539 11 *
Anna Bridge 169:a7c7b631e539 12 * Unless required by applicable law or agreed to in writing, software
Anna Bridge 169:a7c7b631e539 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge 169:a7c7b631e539 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge 169:a7c7b631e539 15 * See the License for the specific language governing permissions and
Anna Bridge 169:a7c7b631e539 16 * limitations under the License.
Anna Bridge 169:a7c7b631e539 17 */
Anna Bridge 169:a7c7b631e539 18
Anna Bridge 169:a7c7b631e539 19 /*
Anna Bridge 169:a7c7b631e539 20 * This file is derivative of CMSIS V5.00 ARMCM3.h
Anna Bridge 169:a7c7b631e539 21 *
Anna Bridge 169:a7c7b631e539 22 * This file has merged with the former SMM_MPS2.h file, derivative from the
Anna Bridge 169:a7c7b631e539 23 * MPS2 Selftest implementation.
Anna Bridge 169:a7c7b631e539 24 * MPS2 Selftest: https://silver.arm.com/browse/VEI10 ->
Anna Bridge 169:a7c7b631e539 25 * \ISCM-1-0\AN491\software\Selftest\v2m_mps2\SMM_MPS2.h
Anna Bridge 169:a7c7b631e539 26 *
Anna Bridge 169:a7c7b631e539 27 * It includes code implementation file for the LAN Ethernet interface.
Anna Bridge 169:a7c7b631e539 28 */
Anna Bridge 169:a7c7b631e539 29
Anna Bridge 169:a7c7b631e539 30 #ifndef CM3DS_H
Anna Bridge 169:a7c7b631e539 31 #define CM3DS_H
Anna Bridge 169:a7c7b631e539 32
Anna Bridge 169:a7c7b631e539 33 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 34 extern "C" {
Anna Bridge 169:a7c7b631e539 35 #endif
Anna Bridge 169:a7c7b631e539 36
Anna Bridge 169:a7c7b631e539 37 /* ------------------------- Interrupt Number Definition ------------------------ */
Anna Bridge 169:a7c7b631e539 38
Anna Bridge 169:a7c7b631e539 39 typedef enum IRQn
Anna Bridge 169:a7c7b631e539 40 {
Anna Bridge 169:a7c7b631e539 41 /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
Anna Bridge 169:a7c7b631e539 42 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
Anna Bridge 169:a7c7b631e539 43 HardFault_IRQn = -13, /* 3 HardFault Interrupt */
Anna Bridge 169:a7c7b631e539 44 MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
Anna Bridge 169:a7c7b631e539 45 BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
Anna Bridge 169:a7c7b631e539 46 UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
Anna Bridge 169:a7c7b631e539 47 SVCall_IRQn = -5, /* 11 SV Call Interrupt */
Anna Bridge 169:a7c7b631e539 48 DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
Anna Bridge 169:a7c7b631e539 49 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
Anna Bridge 169:a7c7b631e539 50 SysTick_IRQn = -1, /* 15 System Tick Interrupt */
Anna Bridge 169:a7c7b631e539 51
Anna Bridge 169:a7c7b631e539 52 /* ---------------------- CM3DS Specific Interrupt Numbers ---------------------- */
Anna Bridge 169:a7c7b631e539 53 UART0_IRQn = 0, /* UART 0 RX and TX Combined Interrupt */
Anna Bridge 169:a7c7b631e539 54 Spare_IRQn = 1, /* Undefined */
Anna Bridge 169:a7c7b631e539 55 UART1_IRQn = 2, /* UART 1 RX and TX Combined Interrupt */
Anna Bridge 169:a7c7b631e539 56 APB_SLAVE_0_IRQ = 3, /* Reserved for APB Slave */
Anna Bridge 169:a7c7b631e539 57 APB_SLAVE_1_IRQ = 4, /* Reserved for APB Slave */
Anna Bridge 169:a7c7b631e539 58 RTC_IRQn = 5, /* RTC Interrupt */
Anna Bridge 169:a7c7b631e539 59 PORT0_ALL_IRQn = 6, /* GPIO Port 0 combined Interrupt */
Anna Bridge 169:a7c7b631e539 60 PORT1_ALL_IRQn = 7, /* GPIO Port 1 combined Interrupt */
Anna Bridge 169:a7c7b631e539 61 TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
Anna Bridge 169:a7c7b631e539 62 TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
Anna Bridge 169:a7c7b631e539 63 DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
Anna Bridge 169:a7c7b631e539 64 APB_SLAVE_2_IRQ = 11, /* Reserved for APB Slave */
Anna Bridge 169:a7c7b631e539 65 UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
Anna Bridge 169:a7c7b631e539 66 APB_SLAVE_3_IRQ = 13, /* Reserved for APB Slave */
Anna Bridge 169:a7c7b631e539 67 RESERVED0_IRQn = 14, /* Reserved */
Anna Bridge 169:a7c7b631e539 68 TSC_IRQn = 15, /* Touch Screen Interrupt */
Anna Bridge 169:a7c7b631e539 69 PORT0_0_IRQn = 16, /* GPIO Port 0 pin 0 Handler */
Anna Bridge 169:a7c7b631e539 70 PORT0_1_IRQn = 17, /* GPIO Port 0 pin 1 Handler */
Anna Bridge 169:a7c7b631e539 71 PORT0_2_IRQn = 18, /* GPIO Port 0 pin 2 Handler */
Anna Bridge 169:a7c7b631e539 72 PORT0_3_IRQn = 19, /* GPIO Port 0 pin 3 Handler */
Anna Bridge 169:a7c7b631e539 73 PORT0_4_IRQn = 20, /* GPIO Port 0 pin 4 Handler */
Anna Bridge 169:a7c7b631e539 74 PORT0_5_IRQn = 21, /* GPIO Port 0 pin 5 Handler */
Anna Bridge 169:a7c7b631e539 75 PORT0_6_IRQn = 22, /* GPIO Port 0 pin 6 Handler */
Anna Bridge 169:a7c7b631e539 76 PORT0_7_IRQn = 23, /* GPIO Port 0 pin 7 Handler */
Anna Bridge 169:a7c7b631e539 77 PORT0_8_IRQn = 24, /* GPIO Port 0 pin 8 Handler */
Anna Bridge 169:a7c7b631e539 78 PORT0_9_IRQn = 25, /* GPIO Port 0 pin 9 Handler */
Anna Bridge 169:a7c7b631e539 79 PORT0_10_IRQn = 26, /* GPIO Port 0 pin 10 Handler */
Anna Bridge 169:a7c7b631e539 80 PORT0_11_IRQn = 27, /* GPIO Port 0 pin 11 Handler */
Anna Bridge 169:a7c7b631e539 81 PORT0_12_IRQn = 28, /* GPIO Port 0 pin 12 Handler */
Anna Bridge 169:a7c7b631e539 82 PORT0_13_IRQn = 29, /* GPIO Port 0 pin 13 Handler */
Anna Bridge 169:a7c7b631e539 83 PORT0_14_IRQn = 30, /* GPIO Port 0 pin 14 Handler */
Anna Bridge 169:a7c7b631e539 84 PORT0_15_IRQn = 31, /* GPIO Port 0 pin 15 Handler */
Anna Bridge 169:a7c7b631e539 85 FLASH0_IRQn = 32, /* Reserved for Flash */
Anna Bridge 169:a7c7b631e539 86 FLASH1_IRQn = 33, /* Reserved for Flash */
Anna Bridge 169:a7c7b631e539 87 RESERVED1_IRQn = 34, /* Reserved for Cordio */
Anna Bridge 169:a7c7b631e539 88 RESERVED2_IRQn = 35, /* Reserved for Cordio */
Anna Bridge 169:a7c7b631e539 89 RESERVED3_IRQn = 36, /* Reserved for Cordio */
Anna Bridge 169:a7c7b631e539 90 RESERVED4_IRQn = 37, /* Reserved for Cordio */
Anna Bridge 169:a7c7b631e539 91 RESERVED5_IRQn = 38, /* Reserved for Cordio */
Anna Bridge 169:a7c7b631e539 92 RESERVED6_IRQn = 39, /* Reserved for Cordio */
Anna Bridge 169:a7c7b631e539 93 RESERVED7_IRQn = 40, /* Reserved for Cordio */
Anna Bridge 169:a7c7b631e539 94 RESERVED8_IRQn = 41, /* Reserved for Cordio */
Anna Bridge 169:a7c7b631e539 95 PORT2_ALL_IRQn = 42, /* GPIO Port 2 combined Interrupt */
Anna Bridge 169:a7c7b631e539 96 PORT3_ALL_IRQn = 43, /* GPIO Port 3 combined Interrupt */
Anna Bridge 169:a7c7b631e539 97 TRNG_IRQn = 44, /* Random number generator Interrupt */
Anna Bridge 169:a7c7b631e539 98 UART2_IRQn = 45, /* UART 2 RX and TX Combined Interrupt */
Anna Bridge 169:a7c7b631e539 99 UART3_IRQn = 46, /* UART 3 RX and TX Combined Interrupt */
Anna Bridge 169:a7c7b631e539 100 ETHERNET_IRQn = 47, /* Ethernet interrupt t.b.a. */
Anna Bridge 169:a7c7b631e539 101 I2S_IRQn = 48, /* I2S Interrupt */
Anna Bridge 169:a7c7b631e539 102 MPS2_SPI0_IRQn = 49, /* SPI Interrupt (spi header) */
Anna Bridge 169:a7c7b631e539 103 MPS2_SPI1_IRQn = 50, /* SPI Interrupt (clcd) */
Anna Bridge 169:a7c7b631e539 104 MPS2_SPI2_IRQn = 51, /* SPI Interrupt (spi 1 ADC replacement) */
Anna Bridge 169:a7c7b631e539 105 MPS2_SPI3_IRQn = 52, /* SPI Interrupt (shield 0) */
Anna Bridge 169:a7c7b631e539 106 MPS2_SPI4_IRQn = 53, /* SPI Interrupt (shield 1) */
Anna Bridge 169:a7c7b631e539 107 PORT4_ALL_IRQn = 54, /* GPIO Port 4 combined Interrupt */
Anna Bridge 169:a7c7b631e539 108 PORT5_ALL_IRQn = 55, /* GPIO Port 5 combined Interrupt */
Anna Bridge 169:a7c7b631e539 109 UART4_IRQn = 56 /* UART 4 RX and TX Combined Interrupt */
Anna Bridge 169:a7c7b631e539 110 } IRQn_Type;
Anna Bridge 169:a7c7b631e539 111
Anna Bridge 169:a7c7b631e539 112 /* ================================================================================ */
Anna Bridge 169:a7c7b631e539 113 /* ================ Processor and Core Peripheral Section ================ */
Anna Bridge 169:a7c7b631e539 114 /* ================================================================================ */
Anna Bridge 169:a7c7b631e539 115
Anna Bridge 169:a7c7b631e539 116 /* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */
Anna Bridge 169:a7c7b631e539 117 #define __CM3DS_REV 0x0201U /* Core revision r2p1 */
Anna Bridge 169:a7c7b631e539 118 #define __MPU_PRESENT 1 /* MPU present or not */
Anna Bridge 169:a7c7b631e539 119 #define __VTOR_PRESENT 1 /* VTOR present or not */
Anna Bridge 169:a7c7b631e539 120 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
Anna Bridge 169:a7c7b631e539 121 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
Anna Bridge 169:a7c7b631e539 122
Anna Bridge 169:a7c7b631e539 123 #include <core_cm3.h> /* Processor and core peripherals */
Anna Bridge 169:a7c7b631e539 124 #include "system_CMSDK_CM3DS.h" /* System Header */
Anna Bridge 169:a7c7b631e539 125
Anna Bridge 169:a7c7b631e539 126
Anna Bridge 169:a7c7b631e539 127 /* ================================================================================ */
Anna Bridge 169:a7c7b631e539 128 /* ================ Device Specific Peripheral Section ================ */
Anna Bridge 169:a7c7b631e539 129 /* ================================================================================ */
Anna Bridge 169:a7c7b631e539 130
Anna Bridge 169:a7c7b631e539 131 /* ------------------- Start of section using anonymous unions ------------------ */
Anna Bridge 169:a7c7b631e539 132 #if defined ( __CC_ARM )
Anna Bridge 169:a7c7b631e539 133 #pragma push
Anna Bridge 169:a7c7b631e539 134 #pragma anon_unions
Anna Bridge 169:a7c7b631e539 135 #elif defined(__ICCARM__)
Anna Bridge 169:a7c7b631e539 136 #pragma language=extended
Anna Bridge 169:a7c7b631e539 137 #elif defined(__GNUC__)
Anna Bridge 169:a7c7b631e539 138 /* anonymous unions are enabled by default */
Anna Bridge 169:a7c7b631e539 139 #elif defined(__TMS470__)
Anna Bridge 169:a7c7b631e539 140 /* anonymous unions are enabled by default */
Anna Bridge 169:a7c7b631e539 141 #elif defined(__TASKING__)
Anna Bridge 169:a7c7b631e539 142 #pragma warning 586
Anna Bridge 169:a7c7b631e539 143 #else
Anna Bridge 169:a7c7b631e539 144 #warning Not supported compiler type
Anna Bridge 169:a7c7b631e539 145 #endif
Anna Bridge 169:a7c7b631e539 146
Anna Bridge 169:a7c7b631e539 147 /*------------- System Control (SYSCON) --------------------------------------*/
Anna Bridge 169:a7c7b631e539 148 typedef struct
Anna Bridge 169:a7c7b631e539 149 {
Anna Bridge 169:a7c7b631e539 150 __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
Anna Bridge 169:a7c7b631e539 151 __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
Anna Bridge 169:a7c7b631e539 152 __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
Anna Bridge 169:a7c7b631e539 153 __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
Anna Bridge 169:a7c7b631e539 154 __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
Anna Bridge 169:a7c7b631e539 155 uint32_t RESERVED0[3];
Anna Bridge 169:a7c7b631e539 156 __IO uint32_t AHBPER0SET; /* Offset: 0x020 (R/W)AHB peripheral access control set */
Anna Bridge 169:a7c7b631e539 157 __IO uint32_t AHBPER0CLR; /* Offset: 0x024 (R/W)AHB peripheral access control clear */
Anna Bridge 169:a7c7b631e539 158 uint32_t RESERVED1[2];
Anna Bridge 169:a7c7b631e539 159 __IO uint32_t APBPER0SET; /* Offset: 0x030 (R/W)APB peripheral access control set */
Anna Bridge 169:a7c7b631e539 160 __IO uint32_t APBPER0CLR; /* Offset: 0x034 (R/W)APB peripheral access control clear */
Anna Bridge 169:a7c7b631e539 161 uint32_t RESERVED2[2];
Anna Bridge 169:a7c7b631e539 162 __IO uint32_t MAINCLK; /* Offset: 0x040 (R/W) Main Clock Control Register */
Anna Bridge 169:a7c7b631e539 163 __IO uint32_t AUXCLK; /* Offset: 0x044 (R/W) Auxiliary / RTC Control Register */
Anna Bridge 169:a7c7b631e539 164 __IO uint32_t PLLCTRL; /* Offset: 0x048 (R/W) PLL Control Register */
Anna Bridge 169:a7c7b631e539 165 __IO uint32_t PLLSTATUS; /* Offset: 0x04C (R/W) PLL Status Register */
Anna Bridge 169:a7c7b631e539 166 __IO uint32_t SLEEPCFG; /* Offset: 0x050 (R/W) Sleep Control Register */
Anna Bridge 169:a7c7b631e539 167 __IO uint32_t FLASHAUXCFG; /* Offset: 0x054 (R/W) Flash auxiliary settings Control Register */
Anna Bridge 169:a7c7b631e539 168 uint32_t RESERVED3[10];
Anna Bridge 169:a7c7b631e539 169 __IO uint32_t AHBCLKCFG0SET; /* Offset: 0x080 (R/W) AHB Peripheral Clock set in Active state */
Anna Bridge 169:a7c7b631e539 170 __IO uint32_t AHBCLKCFG0CLR; /* Offset: 0x084 (R/W) AHB Peripheral Clock clear in Active state */
Anna Bridge 169:a7c7b631e539 171 __IO uint32_t AHBCLKCFG1SET; /* Offset: 0x088 (R/W) AHB Peripheral Clock set in Sleep state */
Anna Bridge 169:a7c7b631e539 172 __IO uint32_t AHBCLKCFG1CLR; /* Offset: 0x08C (R/W) AHB Peripheral Clock clear in Sleep state */
Anna Bridge 169:a7c7b631e539 173 __IO uint32_t AHBCLKCFG2SET; /* Offset: 0x090 (R/W) AHB Peripheral Clock set in Deep Sleep state */
Anna Bridge 169:a7c7b631e539 174 __IO uint32_t AHBCLKCFG2CLR; /* Offset: 0x094 (R/W) AHB Peripheral Clock clear in Deep Sleep state */
Anna Bridge 169:a7c7b631e539 175 uint32_t RESERVED4[2];
Anna Bridge 169:a7c7b631e539 176 __IO uint32_t APBCLKCFG0SET; /* Offset: 0x0A0 (R/W) APB Peripheral Clock set in Active state */
Anna Bridge 169:a7c7b631e539 177 __IO uint32_t APBCLKCFG0CLR; /* Offset: 0x0A4 (R/W) APB Peripheral Clock clear in Active state */
Anna Bridge 169:a7c7b631e539 178 __IO uint32_t APBCLKCFG1SET; /* Offset: 0x0A8 (R/W) APB Peripheral Clock set in Sleep state */
Anna Bridge 169:a7c7b631e539 179 __IO uint32_t APBCLKCFG1CLR; /* Offset: 0x0AC (R/W) APB Peripheral Clock clear in Sleep state */
Anna Bridge 169:a7c7b631e539 180 __IO uint32_t APBCLKCFG2SET; /* Offset: 0x0B0 (R/W) APB Peripheral Clock set in Deep Sleep state */
Anna Bridge 169:a7c7b631e539 181 __IO uint32_t APBCLKCFG2CLR; /* Offset: 0x0B4 (R/W) APB Peripheral Clock clear in Deep Sleep state */
Anna Bridge 169:a7c7b631e539 182 uint32_t RESERVED5[2];
Anna Bridge 169:a7c7b631e539 183 __IO uint32_t AHBPRST0SET; /* Offset: 0x0C0 (R/W) AHB Peripheral reset select set */
Anna Bridge 169:a7c7b631e539 184 __IO uint32_t AHBPRST0CLR; /* Offset: 0x0C4 (R/W) AHB Peripheral reset select clear */
Anna Bridge 169:a7c7b631e539 185 __IO uint32_t APBPRST0SET; /* Offset: 0x0C8 (R/W) APB Peripheral reset select set */
Anna Bridge 169:a7c7b631e539 186 __IO uint32_t APBPRST0CLR; /* Offset: 0x0CC (R/W) APB Peripheral reset select clear */
Anna Bridge 169:a7c7b631e539 187 __IO uint32_t PWRDNCFG0SET; /* Offset: 0x0D0 (R/W) AHB Power down sleep wakeup source set */
Anna Bridge 169:a7c7b631e539 188 __IO uint32_t PWRDNCFG0CLR; /* Offset: 0x0D4 (R/W) AHB Power down sleep wakeup source clear */
Anna Bridge 169:a7c7b631e539 189 __IO uint32_t PWRDNCFG1SET; /* Offset: 0x0D8 (R/W) APB Power down sleep wakeup source set */
Anna Bridge 169:a7c7b631e539 190 __IO uint32_t PWRDNCFG1CLR; /* Offset: 0x0DC (R/W) APB Power down sleep wakeup source clear */
Anna Bridge 169:a7c7b631e539 191 __O uint32_t RTCRESET; /* Offset: 0x0E0 ( /W) RTC reset */
Anna Bridge 169:a7c7b631e539 192 __IO uint32_t EVENTCFG; /* Offset: 0x0E4 (R/W) Event interface Control Register */
Anna Bridge 169:a7c7b631e539 193 uint32_t RESERVED6[2];
Anna Bridge 169:a7c7b631e539 194 __IO uint32_t PWROVRIDE0; /* Offset: 0x0F0 (R/W) SRAM Power control overide */
Anna Bridge 169:a7c7b631e539 195 __IO uint32_t PWROVRIDE1; /* Offset: 0x0F4 (R/W) Embedded Flash Power control overide */
Anna Bridge 169:a7c7b631e539 196 __I uint32_t MEMORYSTATUS; /* Offset: 0x0F8 (R/ ) Memory Status Register */
Anna Bridge 169:a7c7b631e539 197 uint32_t RESERVED7[1];
Anna Bridge 169:a7c7b631e539 198 __IO uint32_t GPIOPADCFG0; /* Offset: 0x100 (R/W) IO pad settings */
Anna Bridge 169:a7c7b631e539 199 __IO uint32_t GPIOPADCFG1; /* Offset: 0x104 (R/W) IO pad settings */
Anna Bridge 169:a7c7b631e539 200 __IO uint32_t TESTMODECFG; /* Offset: 0x108 (R/W) Testmode boot bypass */
Anna Bridge 169:a7c7b631e539 201 } CMSDK_SYSCON_TypeDef;
Anna Bridge 169:a7c7b631e539 202
Anna Bridge 169:a7c7b631e539 203 #define CMSDK_SYSCON_REMAP_Pos 0
Anna Bridge 169:a7c7b631e539 204 #define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
Anna Bridge 169:a7c7b631e539 205
Anna Bridge 169:a7c7b631e539 206 #define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
Anna Bridge 169:a7c7b631e539 207 #define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
Anna Bridge 169:a7c7b631e539 208
Anna Bridge 169:a7c7b631e539 209 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
Anna Bridge 169:a7c7b631e539 210 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
Anna Bridge 169:a7c7b631e539 211
Anna Bridge 169:a7c7b631e539 212 #define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
Anna Bridge 169:a7c7b631e539 213 #define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
Anna Bridge 169:a7c7b631e539 214
Anna Bridge 169:a7c7b631e539 215 #define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
Anna Bridge 169:a7c7b631e539 216 #define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
Anna Bridge 169:a7c7b631e539 217
Anna Bridge 169:a7c7b631e539 218 #define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
Anna Bridge 169:a7c7b631e539 219 #define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
Anna Bridge 169:a7c7b631e539 220
Anna Bridge 169:a7c7b631e539 221 #define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
Anna Bridge 169:a7c7b631e539 222 #define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
Anna Bridge 169:a7c7b631e539 223
Anna Bridge 169:a7c7b631e539 224 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
Anna Bridge 169:a7c7b631e539 225 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
Anna Bridge 169:a7c7b631e539 226
Anna Bridge 169:a7c7b631e539 227 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
Anna Bridge 169:a7c7b631e539 228 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
Anna Bridge 169:a7c7b631e539 229
Anna Bridge 169:a7c7b631e539 230 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
Anna Bridge 169:a7c7b631e539 231 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
Anna Bridge 169:a7c7b631e539 232
Anna Bridge 169:a7c7b631e539 233 /*------------------------- Real Time Clock(RTC) ----------------------------------------------*/
Anna Bridge 169:a7c7b631e539 234 typedef struct
Anna Bridge 169:a7c7b631e539 235 {
Anna Bridge 169:a7c7b631e539 236 __I uint32_t RTCDR; /* 0x00 RO RTC Data Register */
Anna Bridge 169:a7c7b631e539 237 __IO uint32_t RTCMR; /* 0x04 RW RTC Match Register */
Anna Bridge 169:a7c7b631e539 238 __IO uint32_t RTCLR; /* 0x08 RW RTC Load Register */
Anna Bridge 169:a7c7b631e539 239 __IO uint32_t RTCCR; /* 0x0C RW RTC Control Register */
Anna Bridge 169:a7c7b631e539 240 __IO uint32_t RTCIMSC; /* 0x10 RW RTC Inerrupt Mask Set and Clear Register */
Anna Bridge 169:a7c7b631e539 241 __I uint32_t RTCRIS; /* 0x14 RO RTC Raw Inerrupt Status Register */
Anna Bridge 169:a7c7b631e539 242 __I uint32_t RTCMIS; /* 0x18 RO RTC Masked Inerrupt Status Register */
Anna Bridge 169:a7c7b631e539 243 __O uint32_t RTCICR; /* 0x1C WO RTC Interrupt Clear Register */
Anna Bridge 169:a7c7b631e539 244 } CMSDK_RTC_TypeDef;
Anna Bridge 169:a7c7b631e539 245
Anna Bridge 169:a7c7b631e539 246 #define CMSDK_RTC_ENABLE_Pos 0 /* CMSDK_RTC Enable: Real Time Clock Enable Position */
Anna Bridge 169:a7c7b631e539 247 #define CMSDK_RTC_ENABLE_Msk (0x1ul << CMSDK_RTC_ENABLE_Pos) /* CMSDK_RTC Enable: Real Time Clock Enable Mask */
Anna Bridge 169:a7c7b631e539 248
Anna Bridge 169:a7c7b631e539 249 /******************************************************************************/
Anna Bridge 169:a7c7b631e539 250 /* Audio and Touch Screen (I2C) Peripheral declaration */
Anna Bridge 169:a7c7b631e539 251 /******************************************************************************/
Anna Bridge 169:a7c7b631e539 252
Anna Bridge 169:a7c7b631e539 253 typedef struct
Anna Bridge 169:a7c7b631e539 254 {
Anna Bridge 169:a7c7b631e539 255 union {
Anna Bridge 169:a7c7b631e539 256 __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
Anna Bridge 169:a7c7b631e539 257 __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
Anna Bridge 169:a7c7b631e539 258 };
Anna Bridge 169:a7c7b631e539 259 __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
Anna Bridge 169:a7c7b631e539 260 } MPS2_I2C_TypeDef;
Anna Bridge 169:a7c7b631e539 261
Anna Bridge 169:a7c7b631e539 262 /******************************************************************************/
Anna Bridge 169:a7c7b631e539 263 /* SMSC9220 Register Definitions */
Anna Bridge 169:a7c7b631e539 264 /******************************************************************************/
Anna Bridge 169:a7c7b631e539 265
Anna Bridge 169:a7c7b631e539 266 typedef struct // SMSC LAN9220
Anna Bridge 169:a7c7b631e539 267 {
Anna Bridge 169:a7c7b631e539 268 __I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
Anna Bridge 169:a7c7b631e539 269 uint32_t RESERVED1[0x7];
Anna Bridge 169:a7c7b631e539 270 __O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
Anna Bridge 169:a7c7b631e539 271 uint32_t RESERVED2[0x7];
Anna Bridge 169:a7c7b631e539 272
Anna Bridge 169:a7c7b631e539 273 __I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
Anna Bridge 169:a7c7b631e539 274 __I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
Anna Bridge 169:a7c7b631e539 275 __I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
Anna Bridge 169:a7c7b631e539 276 __I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
Anna Bridge 169:a7c7b631e539 277
Anna Bridge 169:a7c7b631e539 278 __I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
Anna Bridge 169:a7c7b631e539 279 __IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
Anna Bridge 169:a7c7b631e539 280 __IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
Anna Bridge 169:a7c7b631e539 281 __IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
Anna Bridge 169:a7c7b631e539 282 uint32_t RESERVED3; // Reserved for future use (offset 0x60)
Anna Bridge 169:a7c7b631e539 283 __I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
Anna Bridge 169:a7c7b631e539 284 __IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
Anna Bridge 169:a7c7b631e539 285 __IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
Anna Bridge 169:a7c7b631e539 286 __IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
Anna Bridge 169:a7c7b631e539 287 __IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
Anna Bridge 169:a7c7b631e539 288 __IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
Anna Bridge 169:a7c7b631e539 289 __I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
Anna Bridge 169:a7c7b631e539 290 __I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
Anna Bridge 169:a7c7b631e539 291 __IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
Anna Bridge 169:a7c7b631e539 292 __IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
Anna Bridge 169:a7c7b631e539 293 __IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
Anna Bridge 169:a7c7b631e539 294 __I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
Anna Bridge 169:a7c7b631e539 295 uint32_t RESERVED4; // Reserved for future use (offset 0x94)
Anna Bridge 169:a7c7b631e539 296 __IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
Anna Bridge 169:a7c7b631e539 297 __I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
Anna Bridge 169:a7c7b631e539 298 __I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
Anna Bridge 169:a7c7b631e539 299 __IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
Anna Bridge 169:a7c7b631e539 300 __IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
Anna Bridge 169:a7c7b631e539 301 __IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
Anna Bridge 169:a7c7b631e539 302 __IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
Anna Bridge 169:a7c7b631e539 303 __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
Anna Bridge 169:a7c7b631e539 304
Anna Bridge 169:a7c7b631e539 305 } SMSC9220_TypeDef;
Anna Bridge 169:a7c7b631e539 306
Anna Bridge 169:a7c7b631e539 307 // SMSC9220 MAC Registers Indices
Anna Bridge 169:a7c7b631e539 308 #define SMSC9220_MAC_CR 0x1
Anna Bridge 169:a7c7b631e539 309 #define SMSC9220_MAC_ADDRH 0x2
Anna Bridge 169:a7c7b631e539 310 #define SMSC9220_MAC_ADDRL 0x3
Anna Bridge 169:a7c7b631e539 311 #define SMSC9220_MAC_HASHH 0x4
Anna Bridge 169:a7c7b631e539 312 #define SMSC9220_MAC_HASHL 0x5
Anna Bridge 169:a7c7b631e539 313 #define SMSC9220_MAC_MII_ACC 0x6
Anna Bridge 169:a7c7b631e539 314 #define SMSC9220_MAC_MII_DATA 0x7
Anna Bridge 169:a7c7b631e539 315 #define SMSC9220_MAC_FLOW 0x8
Anna Bridge 169:a7c7b631e539 316 #define SMSC9220_MAC_VLAN1 0x9
Anna Bridge 169:a7c7b631e539 317 #define SMSC9220_MAC_VLAN2 0xA
Anna Bridge 169:a7c7b631e539 318 #define SMSC9220_MAC_WUFF 0xB
Anna Bridge 169:a7c7b631e539 319 #define SMSC9220_MAC_WUCSR 0xC
Anna Bridge 169:a7c7b631e539 320
Anna Bridge 169:a7c7b631e539 321 // SMSC9220 PHY Registers Indices
Anna Bridge 169:a7c7b631e539 322 #define SMSC9220_PHY_BCONTROL 0x0
Anna Bridge 169:a7c7b631e539 323 #define SMSC9220_PHY_BSTATUS 0x1
Anna Bridge 169:a7c7b631e539 324 #define SMSC9220_PHY_ID1 0x2
Anna Bridge 169:a7c7b631e539 325 #define SMSC9220_PHY_ID2 0x3
Anna Bridge 169:a7c7b631e539 326 #define SMSC9220_PHY_ANEG_ADV 0x4
Anna Bridge 169:a7c7b631e539 327 #define SMSC9220_PHY_ANEG_LPA 0x5
Anna Bridge 169:a7c7b631e539 328 #define SMSC9220_PHY_ANEG_EXP 0x6
Anna Bridge 169:a7c7b631e539 329 #define SMSC9220_PHY_MCONTROL 0x17
Anna Bridge 169:a7c7b631e539 330 #define SMSC9220_PHY_MSTATUS 0x18
Anna Bridge 169:a7c7b631e539 331 #define SMSC9220_PHY_CSINDICATE 0x27
Anna Bridge 169:a7c7b631e539 332 #define SMSC9220_PHY_INTSRC 0x29
Anna Bridge 169:a7c7b631e539 333 #define SMSC9220_PHY_INTMASK 0x30
Anna Bridge 169:a7c7b631e539 334 #define SMSC9220_PHY_CS 0x31
Anna Bridge 169:a7c7b631e539 335
Anna Bridge 169:a7c7b631e539 336 /* -------------------- End of section using anonymous unions ------------------- */
Anna Bridge 169:a7c7b631e539 337 #if defined ( __CC_ARM )
Anna Bridge 169:a7c7b631e539 338 #pragma pop
Anna Bridge 169:a7c7b631e539 339 #elif defined(__ICCARM__)
Anna Bridge 169:a7c7b631e539 340 /* leave anonymous unions enabled */
Anna Bridge 169:a7c7b631e539 341 #elif defined(__GNUC__)
Anna Bridge 169:a7c7b631e539 342 /* anonymous unions are enabled by default */
Anna Bridge 169:a7c7b631e539 343 #elif defined(__TMS470__)
Anna Bridge 169:a7c7b631e539 344 /* anonymous unions are enabled by default */
Anna Bridge 169:a7c7b631e539 345 #elif defined(__TASKING__)
Anna Bridge 169:a7c7b631e539 346 #pragma warning restore
Anna Bridge 169:a7c7b631e539 347 #else
Anna Bridge 169:a7c7b631e539 348 #warning Not supported compiler type
Anna Bridge 169:a7c7b631e539 349 #endif
Anna Bridge 169:a7c7b631e539 350
Anna Bridge 169:a7c7b631e539 351 /* ================================================================================ */
Anna Bridge 169:a7c7b631e539 352 /* ================ Peripheral memory map ================ */
Anna Bridge 169:a7c7b631e539 353 /* ================================================================================ */
Anna Bridge 169:a7c7b631e539 354
Anna Bridge 169:a7c7b631e539 355 #define CMSDK_TIMER0_BASE 0x40000000UL
Anna Bridge 169:a7c7b631e539 356 #define CMSDK_TIMER1_BASE 0x40001000UL
Anna Bridge 169:a7c7b631e539 357 #define CMSDK_DUALTIMER_BASE 0x40002000UL
Anna Bridge 169:a7c7b631e539 358 #define CMSDK_DUALTIMER_1_BASE 0x40002000UL
Anna Bridge 169:a7c7b631e539 359 #define CMSDK_DUALTIMER_2_BASE 0x40002020UL
Anna Bridge 169:a7c7b631e539 360 #define CMSDK_UART0_BASE 0x40004000UL
Anna Bridge 169:a7c7b631e539 361 #define CMSDK_UART1_BASE 0x40005000UL
Anna Bridge 169:a7c7b631e539 362 #define CMSDK_RTC_BASE 0x40006000UL
Anna Bridge 169:a7c7b631e539 363 #define CMSDK_WATCHDOG_BASE 0x40008000UL
Anna Bridge 169:a7c7b631e539 364 #define TRNG_BASE 0x4000F000UL
Anna Bridge 169:a7c7b631e539 365 #define CMSDK_GPIO0_BASE 0x40010000UL
Anna Bridge 169:a7c7b631e539 366 #define CMSDK_GPIO1_BASE 0x40011000UL
Anna Bridge 169:a7c7b631e539 367 #define CMSDK_GPIO2_BASE 0x40012000UL
Anna Bridge 169:a7c7b631e539 368 #define CMSDK_GPIO3_BASE 0x40013000UL
Anna Bridge 169:a7c7b631e539 369 #define CMSDK_SYSCTRL_BASE 0x4001F000UL
Anna Bridge 169:a7c7b631e539 370 #define MPS2_SSP0_BASE 0x40020000UL /* User SSP Base Address */
Anna Bridge 169:a7c7b631e539 371 #define MPS2_SSP1_BASE 0x40021000UL /* CLCD SSP Base Address */
Anna Bridge 169:a7c7b631e539 372 #define MPS2_TSC_I2C_BASE 0x40022000UL /* Touch Screen I2C Base Address */
Anna Bridge 169:a7c7b631e539 373 #define MPS2_AAIC_I2C_BASE 0x40023000UL /* Audio Interface I2C Base Address */
Anna Bridge 169:a7c7b631e539 374 #define MPS2_AAIC_I2S_BASE 0x40024000UL /* Audio Interface I2S Base Address */
Anna Bridge 169:a7c7b631e539 375 #define MPS2_SSP2_BASE 0x40025000UL /* ADC SSP Base Address */
Anna Bridge 169:a7c7b631e539 376 #define MPS2_SSP3_BASE 0x40026000UL /* Shield 0 SSP Base Address */
Anna Bridge 169:a7c7b631e539 377 #define MPS2_SSP4_BASE 0x40027000UL /* Shield 1 SSP Base Address */
Anna Bridge 169:a7c7b631e539 378 #define MPS2_FPGAIO_BASE 0x40028000UL /* FPGAIO Base Address */
Anna Bridge 169:a7c7b631e539 379 #define MPS2_SHIELD0_I2C_BASE 0x40029000UL /* I2C shield 0 Base Address */
Anna Bridge 169:a7c7b631e539 380 #define MPS2_SHIELD1_I2C_BASE 0x4002A000UL /* I2C shield 1 Base Address */
Anna Bridge 169:a7c7b631e539 381 #define CMSDK_UART2_BASE 0x4002C000UL
Anna Bridge 169:a7c7b631e539 382 #define CMSDK_UART3_BASE 0x4002D000UL
Anna Bridge 169:a7c7b631e539 383 #define CMSDK_UART4_BASE 0x4002E000UL
Anna Bridge 169:a7c7b631e539 384 #define MPS2_SCC_BASE 0x4002F000UL /* SCC Base Address */
Anna Bridge 169:a7c7b631e539 385 #define CMSDK_GPIO4_BASE 0x40030000UL
Anna Bridge 169:a7c7b631e539 386 #define CMSDK_GPIO5_BASE 0x40031000UL
Anna Bridge 169:a7c7b631e539 387 #define SMSC9220_BASE 0x40200000UL /* Ethernet SMSC9220 Base Address */
Anna Bridge 169:a7c7b631e539 388 #define MPS2_VGA_TEXT_BUFFER 0x41000000UL /* VGA Text Buffer Address */
Anna Bridge 169:a7c7b631e539 389 #define MPS2_VGA_BUFFER 0x41100000UL /* VGA Buffer Base Address */
Anna Bridge 169:a7c7b631e539 390
Anna Bridge 169:a7c7b631e539 391 /* ================================================================================ */
Anna Bridge 169:a7c7b631e539 392 /* ================ Peripheral declaration ================ */
Anna Bridge 169:a7c7b631e539 393 /* ================================================================================ */
Anna Bridge 169:a7c7b631e539 394
Anna Bridge 169:a7c7b631e539 395 #define CMSDK_RTC ((CMSDK_RTC_TypeDef *) CMSDK_RTC_BASE )
Anna Bridge 169:a7c7b631e539 396 #define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
Anna Bridge 169:a7c7b631e539 397 #define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
Anna Bridge 169:a7c7b631e539 398
Anna Bridge 169:a7c7b631e539 399 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 400 }
Anna Bridge 169:a7c7b631e539 401 #endif
Anna Bridge 169:a7c7b631e539 402
Anna Bridge 169:a7c7b631e539 403 #endif /* CM3DS_H */