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TARGET_NUCLEO_F401RE/core_cm7.h@160:5571c4ff569f, 2018-01-17 (annotated)

Committer:: Anna Bridge
Date:: Wed Jan 17 16:13:02 2018 +0000
Revision:: 160:5571c4ff569f
Parent:: 156:ff21514d8981
Child:: 169:a7c7b631e539

mbed library. Release version 158

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	156:ff21514d8981	1	/************************************************************************//
AnnaBridge	156:ff21514d8981	2	* @file core_cm7.h
AnnaBridge	156:ff21514d8981	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
Anna Bridge	160:5571c4ff569f	4	* @version V5.0.3
Anna Bridge	160:5571c4ff569f	5	* @date 09. August 2017
AnnaBridge	156:ff21514d8981	6	******************************************************************************/
AnnaBridge	156:ff21514d8981	7	/*
AnnaBridge	156:ff21514d8981	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	156:ff21514d8981	9	*
AnnaBridge	156:ff21514d8981	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	156:ff21514d8981	11	*
AnnaBridge	156:ff21514d8981	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	156:ff21514d8981	13	* not use this file except in compliance with the License.
AnnaBridge	156:ff21514d8981	14	* You may obtain a copy of the License at
AnnaBridge	156:ff21514d8981	15	*
AnnaBridge	156:ff21514d8981	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	156:ff21514d8981	17	*
AnnaBridge	156:ff21514d8981	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	156:ff21514d8981	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	156:ff21514d8981	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	156:ff21514d8981	21	* See the License for the specific language governing permissions and
AnnaBridge	156:ff21514d8981	22	* limitations under the License.
AnnaBridge	156:ff21514d8981	23	*/
AnnaBridge	156:ff21514d8981	24
AnnaBridge	156:ff21514d8981	25	#if defined ( __ICCARM__ )
AnnaBridge	156:ff21514d8981	26	#pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge	156:ff21514d8981	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	156:ff21514d8981	28	#pragma clang system_header /* treat file as system include file */
AnnaBridge	156:ff21514d8981	29	#endif
AnnaBridge	156:ff21514d8981	30
AnnaBridge	156:ff21514d8981	31	#ifndef __CORE_CM7_H_GENERIC
AnnaBridge	156:ff21514d8981	32	#define __CORE_CM7_H_GENERIC
AnnaBridge	156:ff21514d8981	33
AnnaBridge	156:ff21514d8981	34	#include <stdint.h>
AnnaBridge	156:ff21514d8981	35
AnnaBridge	156:ff21514d8981	36	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	37	extern "C" {
AnnaBridge	156:ff21514d8981	38	#endif
AnnaBridge	156:ff21514d8981	39
AnnaBridge	156:ff21514d8981	40	/**
AnnaBridge	156:ff21514d8981	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge	156:ff21514d8981	42	CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge	156:ff21514d8981	43
AnnaBridge	156:ff21514d8981	44	\li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge	156:ff21514d8981	45	Function definitions in header files are used to allow 'inlining'.
AnnaBridge	156:ff21514d8981	46
AnnaBridge	156:ff21514d8981	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge	156:ff21514d8981	48	Unions are used for effective representation of core registers.
AnnaBridge	156:ff21514d8981	49
AnnaBridge	156:ff21514d8981	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge	156:ff21514d8981	51	Function-like macros are used to allow more efficient code.
AnnaBridge	156:ff21514d8981	52	*/
AnnaBridge	156:ff21514d8981	53
AnnaBridge	156:ff21514d8981	54
AnnaBridge	156:ff21514d8981	55	/*******************************************************************************
AnnaBridge	156:ff21514d8981	56	* CMSIS definitions
AnnaBridge	156:ff21514d8981	57	******************************************************************************/
AnnaBridge	156:ff21514d8981	58	/**
AnnaBridge	156:ff21514d8981	59	\ingroup Cortex_M7
AnnaBridge	156:ff21514d8981	60	@{
AnnaBridge	156:ff21514d8981	61	*/
AnnaBridge	156:ff21514d8981	62
Anna Bridge	160:5571c4ff569f	63	#include "cmsis_version.h"
Anna Bridge	160:5571c4ff569f	64
AnnaBridge	156:ff21514d8981	65	/* CMSIS CM7 definitions */
Anna Bridge	160:5571c4ff569f	66	#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
Anna Bridge	160:5571c4ff569f	67	#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
AnnaBridge	156:ff21514d8981	68	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) \| \
Anna Bridge	160:5571c4ff569f	69	__CM7_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
AnnaBridge	156:ff21514d8981	70
AnnaBridge	156:ff21514d8981	71	#define __CORTEX_M (7U) /!< Cortex-M Core /
AnnaBridge	156:ff21514d8981	72
AnnaBridge	156:ff21514d8981	73	/** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge	156:ff21514d8981	74	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
AnnaBridge	156:ff21514d8981	75	*/
AnnaBridge	156:ff21514d8981	76	#if defined ( __CC_ARM )
AnnaBridge	156:ff21514d8981	77	#if defined __TARGET_FPU_VFP
AnnaBridge	156:ff21514d8981	78	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	79	#define __FPU_USED 1U
AnnaBridge	156:ff21514d8981	80	#else
AnnaBridge	156:ff21514d8981	81	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	156:ff21514d8981	82	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	83	#endif
AnnaBridge	156:ff21514d8981	84	#else
AnnaBridge	156:ff21514d8981	85	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	86	#endif
AnnaBridge	156:ff21514d8981	87
AnnaBridge	156:ff21514d8981	88	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	156:ff21514d8981	89	#if defined __ARM_PCS_VFP
AnnaBridge	156:ff21514d8981	90	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	91	#define __FPU_USED 1U
AnnaBridge	156:ff21514d8981	92	#else
AnnaBridge	156:ff21514d8981	93	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	156:ff21514d8981	94	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	95	#endif
AnnaBridge	156:ff21514d8981	96	#else
AnnaBridge	156:ff21514d8981	97	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	98	#endif
AnnaBridge	156:ff21514d8981	99
AnnaBridge	156:ff21514d8981	100	#elif defined ( __GNUC__ )
AnnaBridge	156:ff21514d8981	101	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	156:ff21514d8981	102	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	103	#define __FPU_USED 1U
AnnaBridge	156:ff21514d8981	104	#else
AnnaBridge	156:ff21514d8981	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	156:ff21514d8981	106	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	107	#endif
AnnaBridge	156:ff21514d8981	108	#else
AnnaBridge	156:ff21514d8981	109	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	110	#endif
AnnaBridge	156:ff21514d8981	111
AnnaBridge	156:ff21514d8981	112	#elif defined ( __ICCARM__ )
AnnaBridge	156:ff21514d8981	113	#if defined __ARMVFP__
AnnaBridge	156:ff21514d8981	114	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	115	#define __FPU_USED 1U
AnnaBridge	156:ff21514d8981	116	#else
AnnaBridge	156:ff21514d8981	117	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	156:ff21514d8981	118	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	119	#endif
AnnaBridge	156:ff21514d8981	120	#else
AnnaBridge	156:ff21514d8981	121	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	122	#endif
AnnaBridge	156:ff21514d8981	123
AnnaBridge	156:ff21514d8981	124	#elif defined ( __TI_ARM__ )
AnnaBridge	156:ff21514d8981	125	#if defined __TI_VFP_SUPPORT__
AnnaBridge	156:ff21514d8981	126	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	127	#define __FPU_USED 1U
AnnaBridge	156:ff21514d8981	128	#else
AnnaBridge	156:ff21514d8981	129	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	156:ff21514d8981	130	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	131	#endif
AnnaBridge	156:ff21514d8981	132	#else
AnnaBridge	156:ff21514d8981	133	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	134	#endif
AnnaBridge	156:ff21514d8981	135
AnnaBridge	156:ff21514d8981	136	#elif defined ( __TASKING__ )
AnnaBridge	156:ff21514d8981	137	#if defined __FPU_VFP__
AnnaBridge	156:ff21514d8981	138	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	139	#define __FPU_USED 1U
AnnaBridge	156:ff21514d8981	140	#else
AnnaBridge	156:ff21514d8981	141	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	156:ff21514d8981	142	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	143	#endif
AnnaBridge	156:ff21514d8981	144	#else
AnnaBridge	156:ff21514d8981	145	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	146	#endif
AnnaBridge	156:ff21514d8981	147
AnnaBridge	156:ff21514d8981	148	#elif defined ( __CSMC__ )
AnnaBridge	156:ff21514d8981	149	#if ( __CSMC__ & 0x400U)
AnnaBridge	156:ff21514d8981	150	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	151	#define __FPU_USED 1U
AnnaBridge	156:ff21514d8981	152	#else
AnnaBridge	156:ff21514d8981	153	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	156:ff21514d8981	154	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	155	#endif
AnnaBridge	156:ff21514d8981	156	#else
AnnaBridge	156:ff21514d8981	157	#define __FPU_USED 0U
AnnaBridge	156:ff21514d8981	158	#endif
AnnaBridge	156:ff21514d8981	159
AnnaBridge	156:ff21514d8981	160	#endif
AnnaBridge	156:ff21514d8981	161
AnnaBridge	156:ff21514d8981	162	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	156:ff21514d8981	163
AnnaBridge	156:ff21514d8981	164
AnnaBridge	156:ff21514d8981	165	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	166	}
AnnaBridge	156:ff21514d8981	167	#endif
AnnaBridge	156:ff21514d8981	168
AnnaBridge	156:ff21514d8981	169	#endif /* __CORE_CM7_H_GENERIC */
AnnaBridge	156:ff21514d8981	170
AnnaBridge	156:ff21514d8981	171	#ifndef __CMSIS_GENERIC
AnnaBridge	156:ff21514d8981	172
AnnaBridge	156:ff21514d8981	173	#ifndef __CORE_CM7_H_DEPENDANT
AnnaBridge	156:ff21514d8981	174	#define __CORE_CM7_H_DEPENDANT
AnnaBridge	156:ff21514d8981	175
AnnaBridge	156:ff21514d8981	176	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	177	extern "C" {
AnnaBridge	156:ff21514d8981	178	#endif
AnnaBridge	156:ff21514d8981	179
AnnaBridge	156:ff21514d8981	180	/* check device defines and use defaults */
AnnaBridge	156:ff21514d8981	181	#if defined __CHECK_DEVICE_DEFINES
AnnaBridge	156:ff21514d8981	182	#ifndef __CM7_REV
AnnaBridge	156:ff21514d8981	183	#define __CM7_REV 0x0000U
AnnaBridge	156:ff21514d8981	184	#warning "__CM7_REV not defined in device header file; using default!"
AnnaBridge	156:ff21514d8981	185	#endif
AnnaBridge	156:ff21514d8981	186
AnnaBridge	156:ff21514d8981	187	#ifndef __FPU_PRESENT
AnnaBridge	156:ff21514d8981	188	#define __FPU_PRESENT 0U
AnnaBridge	156:ff21514d8981	189	#warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge	156:ff21514d8981	190	#endif
AnnaBridge	156:ff21514d8981	191
AnnaBridge	156:ff21514d8981	192	#ifndef __MPU_PRESENT
AnnaBridge	156:ff21514d8981	193	#define __MPU_PRESENT 0U
AnnaBridge	156:ff21514d8981	194	#warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge	156:ff21514d8981	195	#endif
AnnaBridge	156:ff21514d8981	196
AnnaBridge	156:ff21514d8981	197	#ifndef __ICACHE_PRESENT
AnnaBridge	156:ff21514d8981	198	#define __ICACHE_PRESENT 0U
AnnaBridge	156:ff21514d8981	199	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
AnnaBridge	156:ff21514d8981	200	#endif
AnnaBridge	156:ff21514d8981	201
AnnaBridge	156:ff21514d8981	202	#ifndef __DCACHE_PRESENT
AnnaBridge	156:ff21514d8981	203	#define __DCACHE_PRESENT 0U
AnnaBridge	156:ff21514d8981	204	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
AnnaBridge	156:ff21514d8981	205	#endif
AnnaBridge	156:ff21514d8981	206
AnnaBridge	156:ff21514d8981	207	#ifndef __DTCM_PRESENT
AnnaBridge	156:ff21514d8981	208	#define __DTCM_PRESENT 0U
AnnaBridge	156:ff21514d8981	209	#warning "__DTCM_PRESENT not defined in device header file; using default!"
AnnaBridge	156:ff21514d8981	210	#endif
AnnaBridge	156:ff21514d8981	211
AnnaBridge	156:ff21514d8981	212	#ifndef __NVIC_PRIO_BITS
AnnaBridge	156:ff21514d8981	213	#define __NVIC_PRIO_BITS 3U
AnnaBridge	156:ff21514d8981	214	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge	156:ff21514d8981	215	#endif
AnnaBridge	156:ff21514d8981	216
AnnaBridge	156:ff21514d8981	217	#ifndef __Vendor_SysTickConfig
AnnaBridge	156:ff21514d8981	218	#define __Vendor_SysTickConfig 0U
AnnaBridge	156:ff21514d8981	219	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge	156:ff21514d8981	220	#endif
AnnaBridge	156:ff21514d8981	221	#endif
AnnaBridge	156:ff21514d8981	222
AnnaBridge	156:ff21514d8981	223	/* IO definitions (access restrictions to peripheral registers) */
AnnaBridge	156:ff21514d8981	224	/**
AnnaBridge	156:ff21514d8981	225	\defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge	156:ff21514d8981	226
AnnaBridge	156:ff21514d8981	227	<strong>IO Type Qualifiers</strong> are used
AnnaBridge	156:ff21514d8981	228	\li to specify the access to peripheral variables.
AnnaBridge	156:ff21514d8981	229	\li for automatic generation of peripheral register debug information.
AnnaBridge	156:ff21514d8981	230	*/
AnnaBridge	156:ff21514d8981	231	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	232	#define __I volatile /!< Defines 'read only' permissions /
AnnaBridge	156:ff21514d8981	233	#else
AnnaBridge	156:ff21514d8981	234	#define __I volatile const /!< Defines 'read only' permissions /
AnnaBridge	156:ff21514d8981	235	#endif
AnnaBridge	156:ff21514d8981	236	#define __O volatile /!< Defines 'write only' permissions /
AnnaBridge	156:ff21514d8981	237	#define __IO volatile /!< Defines 'read / write' permissions /
AnnaBridge	156:ff21514d8981	238
AnnaBridge	156:ff21514d8981	239	/* following defines should be used for structure members */
AnnaBridge	156:ff21514d8981	240	#define __IM volatile const /! Defines 'read only' structure member permissions /
AnnaBridge	156:ff21514d8981	241	#define __OM volatile /! Defines 'write only' structure member permissions /
AnnaBridge	156:ff21514d8981	242	#define __IOM volatile /! Defines 'read / write' structure member permissions /
AnnaBridge	156:ff21514d8981	243
AnnaBridge	156:ff21514d8981	244	/@} end of group Cortex_M7 /
AnnaBridge	156:ff21514d8981	245
AnnaBridge	156:ff21514d8981	246
AnnaBridge	156:ff21514d8981	247
AnnaBridge	156:ff21514d8981	248	/*******************************************************************************
AnnaBridge	156:ff21514d8981	249	* Register Abstraction
AnnaBridge	156:ff21514d8981	250	Core Register contain:
AnnaBridge	156:ff21514d8981	251	- Core Register
AnnaBridge	156:ff21514d8981	252	- Core NVIC Register
AnnaBridge	156:ff21514d8981	253	- Core SCB Register
AnnaBridge	156:ff21514d8981	254	- Core SysTick Register
AnnaBridge	156:ff21514d8981	255	- Core Debug Register
AnnaBridge	156:ff21514d8981	256	- Core MPU Register
AnnaBridge	156:ff21514d8981	257	- Core FPU Register
AnnaBridge	156:ff21514d8981	258	******************************************************************************/
AnnaBridge	156:ff21514d8981	259	/**
AnnaBridge	156:ff21514d8981	260	\defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge	156:ff21514d8981	261	\brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge	156:ff21514d8981	262	*/
AnnaBridge	156:ff21514d8981	263
AnnaBridge	156:ff21514d8981	264	/**
AnnaBridge	156:ff21514d8981	265	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	266	\defgroup CMSIS_CORE Status and Control Registers
AnnaBridge	156:ff21514d8981	267	\brief Core Register type definitions.
AnnaBridge	156:ff21514d8981	268	@{
AnnaBridge	156:ff21514d8981	269	*/
AnnaBridge	156:ff21514d8981	270
AnnaBridge	156:ff21514d8981	271	/**
AnnaBridge	156:ff21514d8981	272	\brief Union type to access the Application Program Status Register (APSR).
AnnaBridge	156:ff21514d8981	273	*/
AnnaBridge	156:ff21514d8981	274	typedef union
AnnaBridge	156:ff21514d8981	275	{
AnnaBridge	156:ff21514d8981	276	struct
AnnaBridge	156:ff21514d8981	277	{
AnnaBridge	156:ff21514d8981	278	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
AnnaBridge	156:ff21514d8981	279	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	156:ff21514d8981	280	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
AnnaBridge	156:ff21514d8981	281	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	156:ff21514d8981	282	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	156:ff21514d8981	283	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	156:ff21514d8981	284	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	156:ff21514d8981	285	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	156:ff21514d8981	286	} b; /!< Structure used for bit access /
AnnaBridge	156:ff21514d8981	287	uint32_t w; /!< Type used for word access /
AnnaBridge	156:ff21514d8981	288	} APSR_Type;
AnnaBridge	156:ff21514d8981	289
AnnaBridge	156:ff21514d8981	290	/* APSR Register Definitions */
AnnaBridge	156:ff21514d8981	291	#define APSR_N_Pos 31U /!< APSR: N Position /
AnnaBridge	156:ff21514d8981	292	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
AnnaBridge	156:ff21514d8981	293
AnnaBridge	156:ff21514d8981	294	#define APSR_Z_Pos 30U /!< APSR: Z Position /
AnnaBridge	156:ff21514d8981	295	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
AnnaBridge	156:ff21514d8981	296
AnnaBridge	156:ff21514d8981	297	#define APSR_C_Pos 29U /!< APSR: C Position /
AnnaBridge	156:ff21514d8981	298	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
AnnaBridge	156:ff21514d8981	299
AnnaBridge	156:ff21514d8981	300	#define APSR_V_Pos 28U /!< APSR: V Position /
AnnaBridge	156:ff21514d8981	301	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
AnnaBridge	156:ff21514d8981	302
AnnaBridge	156:ff21514d8981	303	#define APSR_Q_Pos 27U /!< APSR: Q Position /
AnnaBridge	156:ff21514d8981	304	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
AnnaBridge	156:ff21514d8981	305
AnnaBridge	156:ff21514d8981	306	#define APSR_GE_Pos 16U /!< APSR: GE Position /
AnnaBridge	156:ff21514d8981	307	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
AnnaBridge	156:ff21514d8981	308
AnnaBridge	156:ff21514d8981	309
AnnaBridge	156:ff21514d8981	310	/**
AnnaBridge	156:ff21514d8981	311	\brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge	156:ff21514d8981	312	*/
AnnaBridge	156:ff21514d8981	313	typedef union
AnnaBridge	156:ff21514d8981	314	{
AnnaBridge	156:ff21514d8981	315	struct
AnnaBridge	156:ff21514d8981	316	{
AnnaBridge	156:ff21514d8981	317	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	156:ff21514d8981	318	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
AnnaBridge	156:ff21514d8981	319	} b; /!< Structure used for bit access /
AnnaBridge	156:ff21514d8981	320	uint32_t w; /!< Type used for word access /
AnnaBridge	156:ff21514d8981	321	} IPSR_Type;
AnnaBridge	156:ff21514d8981	322
AnnaBridge	156:ff21514d8981	323	/* IPSR Register Definitions */
AnnaBridge	156:ff21514d8981	324	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
AnnaBridge	156:ff21514d8981	325	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
AnnaBridge	156:ff21514d8981	326
AnnaBridge	156:ff21514d8981	327
AnnaBridge	156:ff21514d8981	328	/**
AnnaBridge	156:ff21514d8981	329	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge	156:ff21514d8981	330	*/
AnnaBridge	156:ff21514d8981	331	typedef union
AnnaBridge	156:ff21514d8981	332	{
AnnaBridge	156:ff21514d8981	333	struct
AnnaBridge	156:ff21514d8981	334	{
AnnaBridge	156:ff21514d8981	335	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	156:ff21514d8981	336	uint32_t _reserved0:1; /!< bit: 9 Reserved /
AnnaBridge	156:ff21514d8981	337	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
AnnaBridge	156:ff21514d8981	338	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
AnnaBridge	156:ff21514d8981	339	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
AnnaBridge	156:ff21514d8981	340	uint32_t T:1; /!< bit: 24 Thumb bit /
AnnaBridge	156:ff21514d8981	341	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
AnnaBridge	156:ff21514d8981	342	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	156:ff21514d8981	343	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	156:ff21514d8981	344	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	156:ff21514d8981	345	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	156:ff21514d8981	346	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	156:ff21514d8981	347	} b; /!< Structure used for bit access /
AnnaBridge	156:ff21514d8981	348	uint32_t w; /!< Type used for word access /
AnnaBridge	156:ff21514d8981	349	} xPSR_Type;
AnnaBridge	156:ff21514d8981	350
AnnaBridge	156:ff21514d8981	351	/* xPSR Register Definitions */
AnnaBridge	156:ff21514d8981	352	#define xPSR_N_Pos 31U /!< xPSR: N Position /
AnnaBridge	156:ff21514d8981	353	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
AnnaBridge	156:ff21514d8981	354
AnnaBridge	156:ff21514d8981	355	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
AnnaBridge	156:ff21514d8981	356	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
AnnaBridge	156:ff21514d8981	357
AnnaBridge	156:ff21514d8981	358	#define xPSR_C_Pos 29U /!< xPSR: C Position /
AnnaBridge	156:ff21514d8981	359	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
AnnaBridge	156:ff21514d8981	360
AnnaBridge	156:ff21514d8981	361	#define xPSR_V_Pos 28U /!< xPSR: V Position /
AnnaBridge	156:ff21514d8981	362	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
AnnaBridge	156:ff21514d8981	363
AnnaBridge	156:ff21514d8981	364	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
AnnaBridge	156:ff21514d8981	365	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
AnnaBridge	156:ff21514d8981	366
AnnaBridge	156:ff21514d8981	367	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
AnnaBridge	156:ff21514d8981	368	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
AnnaBridge	156:ff21514d8981	369
AnnaBridge	156:ff21514d8981	370	#define xPSR_T_Pos 24U /!< xPSR: T Position /
AnnaBridge	156:ff21514d8981	371	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
AnnaBridge	156:ff21514d8981	372
AnnaBridge	156:ff21514d8981	373	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
AnnaBridge	156:ff21514d8981	374	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
AnnaBridge	156:ff21514d8981	375
AnnaBridge	156:ff21514d8981	376	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
AnnaBridge	156:ff21514d8981	377	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
AnnaBridge	156:ff21514d8981	378
AnnaBridge	156:ff21514d8981	379	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
AnnaBridge	156:ff21514d8981	380	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
AnnaBridge	156:ff21514d8981	381
AnnaBridge	156:ff21514d8981	382
AnnaBridge	156:ff21514d8981	383	/**
AnnaBridge	156:ff21514d8981	384	\brief Union type to access the Control Registers (CONTROL).
AnnaBridge	156:ff21514d8981	385	*/
AnnaBridge	156:ff21514d8981	386	typedef union
AnnaBridge	156:ff21514d8981	387	{
AnnaBridge	156:ff21514d8981	388	struct
AnnaBridge	156:ff21514d8981	389	{
AnnaBridge	156:ff21514d8981	390	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
AnnaBridge	156:ff21514d8981	391	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
AnnaBridge	156:ff21514d8981	392	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
AnnaBridge	156:ff21514d8981	393	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
AnnaBridge	156:ff21514d8981	394	} b; /!< Structure used for bit access /
AnnaBridge	156:ff21514d8981	395	uint32_t w; /!< Type used for word access /
AnnaBridge	156:ff21514d8981	396	} CONTROL_Type;
AnnaBridge	156:ff21514d8981	397
AnnaBridge	156:ff21514d8981	398	/* CONTROL Register Definitions */
AnnaBridge	156:ff21514d8981	399	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
AnnaBridge	156:ff21514d8981	400	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
AnnaBridge	156:ff21514d8981	401
AnnaBridge	156:ff21514d8981	402	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
AnnaBridge	156:ff21514d8981	403	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
AnnaBridge	156:ff21514d8981	404
AnnaBridge	156:ff21514d8981	405	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
AnnaBridge	156:ff21514d8981	406	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
AnnaBridge	156:ff21514d8981	407
AnnaBridge	156:ff21514d8981	408	/@} end of group CMSIS_CORE /
AnnaBridge	156:ff21514d8981	409
AnnaBridge	156:ff21514d8981	410
AnnaBridge	156:ff21514d8981	411	/**
AnnaBridge	156:ff21514d8981	412	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	413	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge	156:ff21514d8981	414	\brief Type definitions for the NVIC Registers
AnnaBridge	156:ff21514d8981	415	@{
AnnaBridge	156:ff21514d8981	416	*/
AnnaBridge	156:ff21514d8981	417
AnnaBridge	156:ff21514d8981	418	/**
AnnaBridge	156:ff21514d8981	419	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge	156:ff21514d8981	420	*/
AnnaBridge	156:ff21514d8981	421	typedef struct
AnnaBridge	156:ff21514d8981	422	{
AnnaBridge	156:ff21514d8981	423	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
AnnaBridge	156:ff21514d8981	424	uint32_t RESERVED0[24U];
AnnaBridge	156:ff21514d8981	425	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
AnnaBridge	156:ff21514d8981	426	uint32_t RSERVED1[24U];
AnnaBridge	156:ff21514d8981	427	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
AnnaBridge	156:ff21514d8981	428	uint32_t RESERVED2[24U];
AnnaBridge	156:ff21514d8981	429	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
AnnaBridge	156:ff21514d8981	430	uint32_t RESERVED3[24U];
AnnaBridge	156:ff21514d8981	431	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
AnnaBridge	156:ff21514d8981	432	uint32_t RESERVED4[56U];
AnnaBridge	156:ff21514d8981	433	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
AnnaBridge	156:ff21514d8981	434	uint32_t RESERVED5[644U];
AnnaBridge	156:ff21514d8981	435	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
AnnaBridge	156:ff21514d8981	436	} NVIC_Type;
AnnaBridge	156:ff21514d8981	437
AnnaBridge	156:ff21514d8981	438	/* Software Triggered Interrupt Register Definitions */
AnnaBridge	156:ff21514d8981	439	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
AnnaBridge	156:ff21514d8981	440	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
AnnaBridge	156:ff21514d8981	441
AnnaBridge	156:ff21514d8981	442	/@} end of group CMSIS_NVIC /
AnnaBridge	156:ff21514d8981	443
AnnaBridge	156:ff21514d8981	444
AnnaBridge	156:ff21514d8981	445	/**
AnnaBridge	156:ff21514d8981	446	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	447	\defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge	156:ff21514d8981	448	\brief Type definitions for the System Control Block Registers
AnnaBridge	156:ff21514d8981	449	@{
AnnaBridge	156:ff21514d8981	450	*/
AnnaBridge	156:ff21514d8981	451
AnnaBridge	156:ff21514d8981	452	/**
AnnaBridge	156:ff21514d8981	453	\brief Structure type to access the System Control Block (SCB).
AnnaBridge	156:ff21514d8981	454	*/
AnnaBridge	156:ff21514d8981	455	typedef struct
AnnaBridge	156:ff21514d8981	456	{
AnnaBridge	156:ff21514d8981	457	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
AnnaBridge	156:ff21514d8981	458	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
AnnaBridge	156:ff21514d8981	459	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
AnnaBridge	156:ff21514d8981	460	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
AnnaBridge	156:ff21514d8981	461	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
AnnaBridge	156:ff21514d8981	462	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
AnnaBridge	156:ff21514d8981	463	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
AnnaBridge	156:ff21514d8981	464	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
AnnaBridge	156:ff21514d8981	465	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
AnnaBridge	156:ff21514d8981	466	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
AnnaBridge	156:ff21514d8981	467	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
AnnaBridge	156:ff21514d8981	468	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
AnnaBridge	156:ff21514d8981	469	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
AnnaBridge	156:ff21514d8981	470	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
AnnaBridge	156:ff21514d8981	471	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
AnnaBridge	156:ff21514d8981	472	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
AnnaBridge	156:ff21514d8981	473	__IM uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
AnnaBridge	156:ff21514d8981	474	__IM uint32_t ID_MFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
AnnaBridge	156:ff21514d8981	475	__IM uint32_t ID_ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
AnnaBridge	156:ff21514d8981	476	uint32_t RESERVED0[1U];
AnnaBridge	156:ff21514d8981	477	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
AnnaBridge	156:ff21514d8981	478	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
AnnaBridge	156:ff21514d8981	479	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
AnnaBridge	156:ff21514d8981	480	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
AnnaBridge	156:ff21514d8981	481	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
AnnaBridge	156:ff21514d8981	482	uint32_t RESERVED3[93U];
AnnaBridge	156:ff21514d8981	483	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
AnnaBridge	156:ff21514d8981	484	uint32_t RESERVED4[15U];
AnnaBridge	156:ff21514d8981	485	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
AnnaBridge	156:ff21514d8981	486	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
Anna Bridge	160:5571c4ff569f	487	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 /
AnnaBridge	156:ff21514d8981	488	uint32_t RESERVED5[1U];
AnnaBridge	156:ff21514d8981	489	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
AnnaBridge	156:ff21514d8981	490	uint32_t RESERVED6[1U];
AnnaBridge	156:ff21514d8981	491	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
AnnaBridge	156:ff21514d8981	492	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
AnnaBridge	156:ff21514d8981	493	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
AnnaBridge	156:ff21514d8981	494	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
AnnaBridge	156:ff21514d8981	495	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
AnnaBridge	156:ff21514d8981	496	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
AnnaBridge	156:ff21514d8981	497	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
AnnaBridge	156:ff21514d8981	498	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
AnnaBridge	156:ff21514d8981	499	uint32_t RESERVED7[6U];
AnnaBridge	156:ff21514d8981	500	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
AnnaBridge	156:ff21514d8981	501	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
AnnaBridge	156:ff21514d8981	502	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
AnnaBridge	156:ff21514d8981	503	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
AnnaBridge	156:ff21514d8981	504	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
AnnaBridge	156:ff21514d8981	505	uint32_t RESERVED8[1U];
AnnaBridge	156:ff21514d8981	506	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
AnnaBridge	156:ff21514d8981	507	} SCB_Type;
AnnaBridge	156:ff21514d8981	508
AnnaBridge	156:ff21514d8981	509	/* SCB CPUID Register Definitions */
AnnaBridge	156:ff21514d8981	510	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
AnnaBridge	156:ff21514d8981	511	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
AnnaBridge	156:ff21514d8981	512
AnnaBridge	156:ff21514d8981	513	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
AnnaBridge	156:ff21514d8981	514	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
AnnaBridge	156:ff21514d8981	515
AnnaBridge	156:ff21514d8981	516	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
AnnaBridge	156:ff21514d8981	517	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
AnnaBridge	156:ff21514d8981	518
AnnaBridge	156:ff21514d8981	519	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
AnnaBridge	156:ff21514d8981	520	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
AnnaBridge	156:ff21514d8981	521
AnnaBridge	156:ff21514d8981	522	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
AnnaBridge	156:ff21514d8981	523	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
AnnaBridge	156:ff21514d8981	524
AnnaBridge	156:ff21514d8981	525	/* SCB Interrupt Control State Register Definitions */
AnnaBridge	156:ff21514d8981	526	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
AnnaBridge	156:ff21514d8981	527	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
AnnaBridge	156:ff21514d8981	528
AnnaBridge	156:ff21514d8981	529	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
AnnaBridge	156:ff21514d8981	530	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
AnnaBridge	156:ff21514d8981	531
AnnaBridge	156:ff21514d8981	532	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
AnnaBridge	156:ff21514d8981	533	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
AnnaBridge	156:ff21514d8981	534
AnnaBridge	156:ff21514d8981	535	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
AnnaBridge	156:ff21514d8981	536	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
AnnaBridge	156:ff21514d8981	537
AnnaBridge	156:ff21514d8981	538	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
AnnaBridge	156:ff21514d8981	539	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
AnnaBridge	156:ff21514d8981	540
AnnaBridge	156:ff21514d8981	541	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
AnnaBridge	156:ff21514d8981	542	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
AnnaBridge	156:ff21514d8981	543
AnnaBridge	156:ff21514d8981	544	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
AnnaBridge	156:ff21514d8981	545	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
AnnaBridge	156:ff21514d8981	546
AnnaBridge	156:ff21514d8981	547	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
AnnaBridge	156:ff21514d8981	548	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
AnnaBridge	156:ff21514d8981	549
AnnaBridge	156:ff21514d8981	550	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
AnnaBridge	156:ff21514d8981	551	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
AnnaBridge	156:ff21514d8981	552
AnnaBridge	156:ff21514d8981	553	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
AnnaBridge	156:ff21514d8981	554	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
AnnaBridge	156:ff21514d8981	555
AnnaBridge	156:ff21514d8981	556	/* SCB Vector Table Offset Register Definitions */
AnnaBridge	156:ff21514d8981	557	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
AnnaBridge	156:ff21514d8981	558	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
AnnaBridge	156:ff21514d8981	559
AnnaBridge	156:ff21514d8981	560	/* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge	156:ff21514d8981	561	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
AnnaBridge	156:ff21514d8981	562	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
AnnaBridge	156:ff21514d8981	563
AnnaBridge	156:ff21514d8981	564	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
AnnaBridge	156:ff21514d8981	565	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
AnnaBridge	156:ff21514d8981	566
AnnaBridge	156:ff21514d8981	567	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
AnnaBridge	156:ff21514d8981	568	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
AnnaBridge	156:ff21514d8981	569
AnnaBridge	156:ff21514d8981	570	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
AnnaBridge	156:ff21514d8981	571	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
AnnaBridge	156:ff21514d8981	572
AnnaBridge	156:ff21514d8981	573	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
AnnaBridge	156:ff21514d8981	574	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
AnnaBridge	156:ff21514d8981	575
AnnaBridge	156:ff21514d8981	576	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
AnnaBridge	156:ff21514d8981	577	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
AnnaBridge	156:ff21514d8981	578
AnnaBridge	156:ff21514d8981	579	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
AnnaBridge	156:ff21514d8981	580	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
AnnaBridge	156:ff21514d8981	581
AnnaBridge	156:ff21514d8981	582	/* SCB System Control Register Definitions */
AnnaBridge	156:ff21514d8981	583	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
AnnaBridge	156:ff21514d8981	584	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
AnnaBridge	156:ff21514d8981	585
AnnaBridge	156:ff21514d8981	586	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
AnnaBridge	156:ff21514d8981	587	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
AnnaBridge	156:ff21514d8981	588
AnnaBridge	156:ff21514d8981	589	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
AnnaBridge	156:ff21514d8981	590	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
AnnaBridge	156:ff21514d8981	591
AnnaBridge	156:ff21514d8981	592	/* SCB Configuration Control Register Definitions */
AnnaBridge	156:ff21514d8981	593	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: Branch prediction enable bit Position /
AnnaBridge	156:ff21514d8981	594	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
AnnaBridge	156:ff21514d8981	595
AnnaBridge	156:ff21514d8981	596	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: Instruction cache enable bit Position /
AnnaBridge	156:ff21514d8981	597	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
AnnaBridge	156:ff21514d8981	598
AnnaBridge	156:ff21514d8981	599	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: Cache enable bit Position /
AnnaBridge	156:ff21514d8981	600	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
AnnaBridge	156:ff21514d8981	601
AnnaBridge	156:ff21514d8981	602	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
AnnaBridge	156:ff21514d8981	603	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
AnnaBridge	156:ff21514d8981	604
AnnaBridge	156:ff21514d8981	605	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
AnnaBridge	156:ff21514d8981	606	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
AnnaBridge	156:ff21514d8981	607
AnnaBridge	156:ff21514d8981	608	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
AnnaBridge	156:ff21514d8981	609	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
AnnaBridge	156:ff21514d8981	610
AnnaBridge	156:ff21514d8981	611	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
AnnaBridge	156:ff21514d8981	612	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
AnnaBridge	156:ff21514d8981	613
AnnaBridge	156:ff21514d8981	614	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
AnnaBridge	156:ff21514d8981	615	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
AnnaBridge	156:ff21514d8981	616
AnnaBridge	156:ff21514d8981	617	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
AnnaBridge	156:ff21514d8981	618	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
AnnaBridge	156:ff21514d8981	619
AnnaBridge	156:ff21514d8981	620	/* SCB System Handler Control and State Register Definitions */
AnnaBridge	156:ff21514d8981	621	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
AnnaBridge	156:ff21514d8981	622	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
AnnaBridge	156:ff21514d8981	623
AnnaBridge	156:ff21514d8981	624	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
AnnaBridge	156:ff21514d8981	625	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
AnnaBridge	156:ff21514d8981	626
AnnaBridge	156:ff21514d8981	627	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
AnnaBridge	156:ff21514d8981	628	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
AnnaBridge	156:ff21514d8981	629
AnnaBridge	156:ff21514d8981	630	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
AnnaBridge	156:ff21514d8981	631	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
AnnaBridge	156:ff21514d8981	632
AnnaBridge	156:ff21514d8981	633	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
AnnaBridge	156:ff21514d8981	634	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
AnnaBridge	156:ff21514d8981	635
AnnaBridge	156:ff21514d8981	636	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
AnnaBridge	156:ff21514d8981	637	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
AnnaBridge	156:ff21514d8981	638
AnnaBridge	156:ff21514d8981	639	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
AnnaBridge	156:ff21514d8981	640	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
AnnaBridge	156:ff21514d8981	641
AnnaBridge	156:ff21514d8981	642	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
AnnaBridge	156:ff21514d8981	643	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
AnnaBridge	156:ff21514d8981	644
AnnaBridge	156:ff21514d8981	645	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
AnnaBridge	156:ff21514d8981	646	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
AnnaBridge	156:ff21514d8981	647
AnnaBridge	156:ff21514d8981	648	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
AnnaBridge	156:ff21514d8981	649	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
AnnaBridge	156:ff21514d8981	650
AnnaBridge	156:ff21514d8981	651	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
AnnaBridge	156:ff21514d8981	652	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
AnnaBridge	156:ff21514d8981	653
AnnaBridge	156:ff21514d8981	654	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
AnnaBridge	156:ff21514d8981	655	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
AnnaBridge	156:ff21514d8981	656
AnnaBridge	156:ff21514d8981	657	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
AnnaBridge	156:ff21514d8981	658	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
AnnaBridge	156:ff21514d8981	659
AnnaBridge	156:ff21514d8981	660	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
AnnaBridge	156:ff21514d8981	661	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
AnnaBridge	156:ff21514d8981	662
AnnaBridge	156:ff21514d8981	663	/* SCB Configurable Fault Status Register Definitions */
AnnaBridge	156:ff21514d8981	664	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
AnnaBridge	156:ff21514d8981	665	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
AnnaBridge	156:ff21514d8981	666
AnnaBridge	156:ff21514d8981	667	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
AnnaBridge	156:ff21514d8981	668	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
AnnaBridge	156:ff21514d8981	669
AnnaBridge	156:ff21514d8981	670	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
AnnaBridge	156:ff21514d8981	671	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
AnnaBridge	156:ff21514d8981	672
AnnaBridge	156:ff21514d8981	673	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	156:ff21514d8981	674	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
AnnaBridge	156:ff21514d8981	675	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
AnnaBridge	156:ff21514d8981	676
AnnaBridge	156:ff21514d8981	677	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
AnnaBridge	156:ff21514d8981	678	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
AnnaBridge	156:ff21514d8981	679
AnnaBridge	156:ff21514d8981	680	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
AnnaBridge	156:ff21514d8981	681	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
AnnaBridge	156:ff21514d8981	682
AnnaBridge	156:ff21514d8981	683	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
AnnaBridge	156:ff21514d8981	684	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
AnnaBridge	156:ff21514d8981	685
AnnaBridge	156:ff21514d8981	686	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
AnnaBridge	156:ff21514d8981	687	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
AnnaBridge	156:ff21514d8981	688
AnnaBridge	156:ff21514d8981	689	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
AnnaBridge	156:ff21514d8981	690	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
AnnaBridge	156:ff21514d8981	691
AnnaBridge	156:ff21514d8981	692	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	156:ff21514d8981	693	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
AnnaBridge	156:ff21514d8981	694	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
AnnaBridge	156:ff21514d8981	695
AnnaBridge	156:ff21514d8981	696	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
AnnaBridge	156:ff21514d8981	697	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
AnnaBridge	156:ff21514d8981	698
AnnaBridge	156:ff21514d8981	699	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
AnnaBridge	156:ff21514d8981	700	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
AnnaBridge	156:ff21514d8981	701
AnnaBridge	156:ff21514d8981	702	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
AnnaBridge	156:ff21514d8981	703	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
AnnaBridge	156:ff21514d8981	704
AnnaBridge	156:ff21514d8981	705	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
AnnaBridge	156:ff21514d8981	706	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
AnnaBridge	156:ff21514d8981	707
AnnaBridge	156:ff21514d8981	708	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
AnnaBridge	156:ff21514d8981	709	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
AnnaBridge	156:ff21514d8981	710
AnnaBridge	156:ff21514d8981	711	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
AnnaBridge	156:ff21514d8981	712	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
AnnaBridge	156:ff21514d8981	713
AnnaBridge	156:ff21514d8981	714	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	156:ff21514d8981	715	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
AnnaBridge	156:ff21514d8981	716	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
AnnaBridge	156:ff21514d8981	717
AnnaBridge	156:ff21514d8981	718	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
AnnaBridge	156:ff21514d8981	719	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
AnnaBridge	156:ff21514d8981	720
AnnaBridge	156:ff21514d8981	721	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
AnnaBridge	156:ff21514d8981	722	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
AnnaBridge	156:ff21514d8981	723
AnnaBridge	156:ff21514d8981	724	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
AnnaBridge	156:ff21514d8981	725	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
AnnaBridge	156:ff21514d8981	726
AnnaBridge	156:ff21514d8981	727	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
AnnaBridge	156:ff21514d8981	728	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
AnnaBridge	156:ff21514d8981	729
AnnaBridge	156:ff21514d8981	730	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
AnnaBridge	156:ff21514d8981	731	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
AnnaBridge	156:ff21514d8981	732
AnnaBridge	156:ff21514d8981	733	/* SCB Hard Fault Status Register Definitions */
AnnaBridge	156:ff21514d8981	734	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
AnnaBridge	156:ff21514d8981	735	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
AnnaBridge	156:ff21514d8981	736
AnnaBridge	156:ff21514d8981	737	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
AnnaBridge	156:ff21514d8981	738	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
AnnaBridge	156:ff21514d8981	739
AnnaBridge	156:ff21514d8981	740	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
AnnaBridge	156:ff21514d8981	741	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
AnnaBridge	156:ff21514d8981	742
AnnaBridge	156:ff21514d8981	743	/* SCB Debug Fault Status Register Definitions */
AnnaBridge	156:ff21514d8981	744	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
AnnaBridge	156:ff21514d8981	745	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
AnnaBridge	156:ff21514d8981	746
AnnaBridge	156:ff21514d8981	747	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
AnnaBridge	156:ff21514d8981	748	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
AnnaBridge	156:ff21514d8981	749
AnnaBridge	156:ff21514d8981	750	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
AnnaBridge	156:ff21514d8981	751	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
AnnaBridge	156:ff21514d8981	752
AnnaBridge	156:ff21514d8981	753	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
AnnaBridge	156:ff21514d8981	754	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
AnnaBridge	156:ff21514d8981	755
AnnaBridge	156:ff21514d8981	756	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
AnnaBridge	156:ff21514d8981	757	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
AnnaBridge	156:ff21514d8981	758
AnnaBridge	156:ff21514d8981	759	/* SCB Cache Level ID Register Definitions */
AnnaBridge	156:ff21514d8981	760	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
AnnaBridge	156:ff21514d8981	761	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
AnnaBridge	156:ff21514d8981	762
AnnaBridge	156:ff21514d8981	763	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
AnnaBridge	156:ff21514d8981	764	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
AnnaBridge	156:ff21514d8981	765
AnnaBridge	156:ff21514d8981	766	/* SCB Cache Type Register Definitions */
AnnaBridge	156:ff21514d8981	767	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
AnnaBridge	156:ff21514d8981	768	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
AnnaBridge	156:ff21514d8981	769
AnnaBridge	156:ff21514d8981	770	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
AnnaBridge	156:ff21514d8981	771	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
AnnaBridge	156:ff21514d8981	772
AnnaBridge	156:ff21514d8981	773	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
AnnaBridge	156:ff21514d8981	774	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
AnnaBridge	156:ff21514d8981	775
AnnaBridge	156:ff21514d8981	776	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
AnnaBridge	156:ff21514d8981	777	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
AnnaBridge	156:ff21514d8981	778
AnnaBridge	156:ff21514d8981	779	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
AnnaBridge	156:ff21514d8981	780	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
AnnaBridge	156:ff21514d8981	781
AnnaBridge	156:ff21514d8981	782	/* SCB Cache Size ID Register Definitions */
AnnaBridge	156:ff21514d8981	783	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
AnnaBridge	156:ff21514d8981	784	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
AnnaBridge	156:ff21514d8981	785
AnnaBridge	156:ff21514d8981	786	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
AnnaBridge	156:ff21514d8981	787	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
AnnaBridge	156:ff21514d8981	788
AnnaBridge	156:ff21514d8981	789	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
AnnaBridge	156:ff21514d8981	790	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
AnnaBridge	156:ff21514d8981	791
AnnaBridge	156:ff21514d8981	792	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
AnnaBridge	156:ff21514d8981	793	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
AnnaBridge	156:ff21514d8981	794
AnnaBridge	156:ff21514d8981	795	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
AnnaBridge	156:ff21514d8981	796	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
AnnaBridge	156:ff21514d8981	797
AnnaBridge	156:ff21514d8981	798	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
AnnaBridge	156:ff21514d8981	799	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
AnnaBridge	156:ff21514d8981	800
AnnaBridge	156:ff21514d8981	801	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
AnnaBridge	156:ff21514d8981	802	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
AnnaBridge	156:ff21514d8981	803
AnnaBridge	156:ff21514d8981	804	/* SCB Cache Size Selection Register Definitions */
AnnaBridge	156:ff21514d8981	805	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
AnnaBridge	156:ff21514d8981	806	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
AnnaBridge	156:ff21514d8981	807
AnnaBridge	156:ff21514d8981	808	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
AnnaBridge	156:ff21514d8981	809	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
AnnaBridge	156:ff21514d8981	810
AnnaBridge	156:ff21514d8981	811	/* SCB Software Triggered Interrupt Register Definitions */
AnnaBridge	156:ff21514d8981	812	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
AnnaBridge	156:ff21514d8981	813	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
AnnaBridge	156:ff21514d8981	814
AnnaBridge	156:ff21514d8981	815	/* SCB D-Cache Invalidate by Set-way Register Definitions */
AnnaBridge	156:ff21514d8981	816	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
AnnaBridge	156:ff21514d8981	817	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
AnnaBridge	156:ff21514d8981	818
AnnaBridge	156:ff21514d8981	819	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
AnnaBridge	156:ff21514d8981	820	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
AnnaBridge	156:ff21514d8981	821
AnnaBridge	156:ff21514d8981	822	/* SCB D-Cache Clean by Set-way Register Definitions */
AnnaBridge	156:ff21514d8981	823	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
AnnaBridge	156:ff21514d8981	824	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
AnnaBridge	156:ff21514d8981	825
AnnaBridge	156:ff21514d8981	826	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
AnnaBridge	156:ff21514d8981	827	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
AnnaBridge	156:ff21514d8981	828
AnnaBridge	156:ff21514d8981	829	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
AnnaBridge	156:ff21514d8981	830	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
AnnaBridge	156:ff21514d8981	831	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
AnnaBridge	156:ff21514d8981	832
AnnaBridge	156:ff21514d8981	833	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
AnnaBridge	156:ff21514d8981	834	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
AnnaBridge	156:ff21514d8981	835
AnnaBridge	156:ff21514d8981	836	/* Instruction Tightly-Coupled Memory Control Register Definitions */
AnnaBridge	156:ff21514d8981	837	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
AnnaBridge	156:ff21514d8981	838	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
AnnaBridge	156:ff21514d8981	839
AnnaBridge	156:ff21514d8981	840	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
AnnaBridge	156:ff21514d8981	841	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
AnnaBridge	156:ff21514d8981	842
AnnaBridge	156:ff21514d8981	843	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
AnnaBridge	156:ff21514d8981	844	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
AnnaBridge	156:ff21514d8981	845
AnnaBridge	156:ff21514d8981	846	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
AnnaBridge	156:ff21514d8981	847	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
AnnaBridge	156:ff21514d8981	848
AnnaBridge	156:ff21514d8981	849	/* Data Tightly-Coupled Memory Control Register Definitions */
AnnaBridge	156:ff21514d8981	850	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
AnnaBridge	156:ff21514d8981	851	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
AnnaBridge	156:ff21514d8981	852
AnnaBridge	156:ff21514d8981	853	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
AnnaBridge	156:ff21514d8981	854	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
AnnaBridge	156:ff21514d8981	855
AnnaBridge	156:ff21514d8981	856	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
AnnaBridge	156:ff21514d8981	857	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
AnnaBridge	156:ff21514d8981	858
AnnaBridge	156:ff21514d8981	859	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
AnnaBridge	156:ff21514d8981	860	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
AnnaBridge	156:ff21514d8981	861
AnnaBridge	156:ff21514d8981	862	/* AHBP Control Register Definitions */
AnnaBridge	156:ff21514d8981	863	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
AnnaBridge	156:ff21514d8981	864	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
AnnaBridge	156:ff21514d8981	865
AnnaBridge	156:ff21514d8981	866	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
AnnaBridge	156:ff21514d8981	867	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
AnnaBridge	156:ff21514d8981	868
AnnaBridge	156:ff21514d8981	869	/* L1 Cache Control Register Definitions */
AnnaBridge	156:ff21514d8981	870	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
AnnaBridge	156:ff21514d8981	871	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
AnnaBridge	156:ff21514d8981	872
AnnaBridge	156:ff21514d8981	873	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
AnnaBridge	156:ff21514d8981	874	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
AnnaBridge	156:ff21514d8981	875
AnnaBridge	156:ff21514d8981	876	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
AnnaBridge	156:ff21514d8981	877	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
AnnaBridge	156:ff21514d8981	878
AnnaBridge	156:ff21514d8981	879	/* AHBS Control Register Definitions */
AnnaBridge	156:ff21514d8981	880	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
AnnaBridge	156:ff21514d8981	881	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
AnnaBridge	156:ff21514d8981	882
AnnaBridge	156:ff21514d8981	883	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
AnnaBridge	156:ff21514d8981	884	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
AnnaBridge	156:ff21514d8981	885
AnnaBridge	156:ff21514d8981	886	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
AnnaBridge	156:ff21514d8981	887	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
AnnaBridge	156:ff21514d8981	888
AnnaBridge	156:ff21514d8981	889	/* Auxiliary Bus Fault Status Register Definitions */
AnnaBridge	156:ff21514d8981	890	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
AnnaBridge	156:ff21514d8981	891	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
AnnaBridge	156:ff21514d8981	892
AnnaBridge	156:ff21514d8981	893	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
AnnaBridge	156:ff21514d8981	894	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
AnnaBridge	156:ff21514d8981	895
AnnaBridge	156:ff21514d8981	896	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
AnnaBridge	156:ff21514d8981	897	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
AnnaBridge	156:ff21514d8981	898
AnnaBridge	156:ff21514d8981	899	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
AnnaBridge	156:ff21514d8981	900	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
AnnaBridge	156:ff21514d8981	901
AnnaBridge	156:ff21514d8981	902	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
AnnaBridge	156:ff21514d8981	903	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
AnnaBridge	156:ff21514d8981	904
AnnaBridge	156:ff21514d8981	905	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
AnnaBridge	156:ff21514d8981	906	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
AnnaBridge	156:ff21514d8981	907
AnnaBridge	156:ff21514d8981	908	/@} end of group CMSIS_SCB /
AnnaBridge	156:ff21514d8981	909
AnnaBridge	156:ff21514d8981	910
AnnaBridge	156:ff21514d8981	911	/**
AnnaBridge	156:ff21514d8981	912	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	913	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge	156:ff21514d8981	914	\brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge	156:ff21514d8981	915	@{
AnnaBridge	156:ff21514d8981	916	*/
AnnaBridge	156:ff21514d8981	917
AnnaBridge	156:ff21514d8981	918	/**
AnnaBridge	156:ff21514d8981	919	\brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge	156:ff21514d8981	920	*/
AnnaBridge	156:ff21514d8981	921	typedef struct
AnnaBridge	156:ff21514d8981	922	{
AnnaBridge	156:ff21514d8981	923	uint32_t RESERVED0[1U];
AnnaBridge	156:ff21514d8981	924	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
AnnaBridge	156:ff21514d8981	925	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
AnnaBridge	156:ff21514d8981	926	} SCnSCB_Type;
AnnaBridge	156:ff21514d8981	927
AnnaBridge	156:ff21514d8981	928	/* Interrupt Controller Type Register Definitions */
AnnaBridge	156:ff21514d8981	929	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
AnnaBridge	156:ff21514d8981	930	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
AnnaBridge	156:ff21514d8981	931
AnnaBridge	156:ff21514d8981	932	/* Auxiliary Control Register Definitions */
AnnaBridge	156:ff21514d8981	933	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /!< ACTLR: DISITMATBFLUSH Position /
AnnaBridge	156:ff21514d8981	934	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
AnnaBridge	156:ff21514d8981	935
AnnaBridge	156:ff21514d8981	936	#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /!< ACTLR: DISRAMODE Position /
AnnaBridge	156:ff21514d8981	937	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
AnnaBridge	156:ff21514d8981	938
AnnaBridge	156:ff21514d8981	939	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /!< ACTLR: FPEXCODIS Position /
AnnaBridge	156:ff21514d8981	940	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
AnnaBridge	156:ff21514d8981	941
AnnaBridge	156:ff21514d8981	942	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
AnnaBridge	156:ff21514d8981	943	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
AnnaBridge	156:ff21514d8981	944
AnnaBridge	156:ff21514d8981	945	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
AnnaBridge	156:ff21514d8981	946	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
AnnaBridge	156:ff21514d8981	947
AnnaBridge	156:ff21514d8981	948	/@} end of group CMSIS_SCnotSCB /
AnnaBridge	156:ff21514d8981	949
AnnaBridge	156:ff21514d8981	950
AnnaBridge	156:ff21514d8981	951	/**
AnnaBridge	156:ff21514d8981	952	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	953	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge	156:ff21514d8981	954	\brief Type definitions for the System Timer Registers.
AnnaBridge	156:ff21514d8981	955	@{
AnnaBridge	156:ff21514d8981	956	*/
AnnaBridge	156:ff21514d8981	957
AnnaBridge	156:ff21514d8981	958	/**
AnnaBridge	156:ff21514d8981	959	\brief Structure type to access the System Timer (SysTick).
AnnaBridge	156:ff21514d8981	960	*/
AnnaBridge	156:ff21514d8981	961	typedef struct
AnnaBridge	156:ff21514d8981	962	{
AnnaBridge	156:ff21514d8981	963	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
AnnaBridge	156:ff21514d8981	964	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
AnnaBridge	156:ff21514d8981	965	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
AnnaBridge	156:ff21514d8981	966	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
AnnaBridge	156:ff21514d8981	967	} SysTick_Type;
AnnaBridge	156:ff21514d8981	968
AnnaBridge	156:ff21514d8981	969	/* SysTick Control / Status Register Definitions */
AnnaBridge	156:ff21514d8981	970	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
AnnaBridge	156:ff21514d8981	971	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
AnnaBridge	156:ff21514d8981	972
AnnaBridge	156:ff21514d8981	973	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
AnnaBridge	156:ff21514d8981	974	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
AnnaBridge	156:ff21514d8981	975
AnnaBridge	156:ff21514d8981	976	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
AnnaBridge	156:ff21514d8981	977	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
AnnaBridge	156:ff21514d8981	978
AnnaBridge	156:ff21514d8981	979	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
AnnaBridge	156:ff21514d8981	980	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
AnnaBridge	156:ff21514d8981	981
AnnaBridge	156:ff21514d8981	982	/* SysTick Reload Register Definitions */
AnnaBridge	156:ff21514d8981	983	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
AnnaBridge	156:ff21514d8981	984	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
AnnaBridge	156:ff21514d8981	985
AnnaBridge	156:ff21514d8981	986	/* SysTick Current Register Definitions */
AnnaBridge	156:ff21514d8981	987	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
AnnaBridge	156:ff21514d8981	988	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
AnnaBridge	156:ff21514d8981	989
AnnaBridge	156:ff21514d8981	990	/* SysTick Calibration Register Definitions */
AnnaBridge	156:ff21514d8981	991	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
AnnaBridge	156:ff21514d8981	992	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
AnnaBridge	156:ff21514d8981	993
AnnaBridge	156:ff21514d8981	994	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
AnnaBridge	156:ff21514d8981	995	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
AnnaBridge	156:ff21514d8981	996
AnnaBridge	156:ff21514d8981	997	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
AnnaBridge	156:ff21514d8981	998	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
AnnaBridge	156:ff21514d8981	999
AnnaBridge	156:ff21514d8981	1000	/@} end of group CMSIS_SysTick /
AnnaBridge	156:ff21514d8981	1001
AnnaBridge	156:ff21514d8981	1002
AnnaBridge	156:ff21514d8981	1003	/**
AnnaBridge	156:ff21514d8981	1004	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	1005	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge	156:ff21514d8981	1006	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge	156:ff21514d8981	1007	@{
AnnaBridge	156:ff21514d8981	1008	*/
AnnaBridge	156:ff21514d8981	1009
AnnaBridge	156:ff21514d8981	1010	/**
AnnaBridge	156:ff21514d8981	1011	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge	156:ff21514d8981	1012	*/
AnnaBridge	156:ff21514d8981	1013	typedef struct
AnnaBridge	156:ff21514d8981	1014	{
AnnaBridge	156:ff21514d8981	1015	__OM union
AnnaBridge	156:ff21514d8981	1016	{
AnnaBridge	156:ff21514d8981	1017	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
AnnaBridge	156:ff21514d8981	1018	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
AnnaBridge	156:ff21514d8981	1019	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
AnnaBridge	156:ff21514d8981	1020	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
AnnaBridge	156:ff21514d8981	1021	uint32_t RESERVED0[864U];
AnnaBridge	156:ff21514d8981	1022	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
AnnaBridge	156:ff21514d8981	1023	uint32_t RESERVED1[15U];
AnnaBridge	156:ff21514d8981	1024	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
AnnaBridge	156:ff21514d8981	1025	uint32_t RESERVED2[15U];
AnnaBridge	156:ff21514d8981	1026	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
AnnaBridge	156:ff21514d8981	1027	uint32_t RESERVED3[29U];
AnnaBridge	156:ff21514d8981	1028	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
AnnaBridge	156:ff21514d8981	1029	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
AnnaBridge	156:ff21514d8981	1030	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
AnnaBridge	156:ff21514d8981	1031	uint32_t RESERVED4[43U];
AnnaBridge	156:ff21514d8981	1032	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
AnnaBridge	156:ff21514d8981	1033	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
AnnaBridge	156:ff21514d8981	1034	uint32_t RESERVED5[6U];
AnnaBridge	156:ff21514d8981	1035	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
AnnaBridge	156:ff21514d8981	1036	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
AnnaBridge	156:ff21514d8981	1037	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
AnnaBridge	156:ff21514d8981	1038	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
AnnaBridge	156:ff21514d8981	1039	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
AnnaBridge	156:ff21514d8981	1040	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
AnnaBridge	156:ff21514d8981	1041	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
AnnaBridge	156:ff21514d8981	1042	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
AnnaBridge	156:ff21514d8981	1043	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
AnnaBridge	156:ff21514d8981	1044	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
AnnaBridge	156:ff21514d8981	1045	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
AnnaBridge	156:ff21514d8981	1046	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
AnnaBridge	156:ff21514d8981	1047	} ITM_Type;
AnnaBridge	156:ff21514d8981	1048
AnnaBridge	156:ff21514d8981	1049	/* ITM Trace Privilege Register Definitions */
AnnaBridge	156:ff21514d8981	1050	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
AnnaBridge	156:ff21514d8981	1051	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
AnnaBridge	156:ff21514d8981	1052
AnnaBridge	156:ff21514d8981	1053	/* ITM Trace Control Register Definitions */
AnnaBridge	156:ff21514d8981	1054	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
AnnaBridge	156:ff21514d8981	1055	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
AnnaBridge	156:ff21514d8981	1056
AnnaBridge	156:ff21514d8981	1057	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
AnnaBridge	156:ff21514d8981	1058	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
AnnaBridge	156:ff21514d8981	1059
AnnaBridge	156:ff21514d8981	1060	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
AnnaBridge	156:ff21514d8981	1061	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
AnnaBridge	156:ff21514d8981	1062
AnnaBridge	156:ff21514d8981	1063	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
AnnaBridge	156:ff21514d8981	1064	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
AnnaBridge	156:ff21514d8981	1065
AnnaBridge	156:ff21514d8981	1066	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
AnnaBridge	156:ff21514d8981	1067	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
AnnaBridge	156:ff21514d8981	1068
AnnaBridge	156:ff21514d8981	1069	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
AnnaBridge	156:ff21514d8981	1070	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
AnnaBridge	156:ff21514d8981	1071
AnnaBridge	156:ff21514d8981	1072	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
AnnaBridge	156:ff21514d8981	1073	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
AnnaBridge	156:ff21514d8981	1074
AnnaBridge	156:ff21514d8981	1075	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
AnnaBridge	156:ff21514d8981	1076	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
AnnaBridge	156:ff21514d8981	1077
AnnaBridge	156:ff21514d8981	1078	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
AnnaBridge	156:ff21514d8981	1079	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
AnnaBridge	156:ff21514d8981	1080
AnnaBridge	156:ff21514d8981	1081	/* ITM Integration Write Register Definitions */
AnnaBridge	156:ff21514d8981	1082	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
AnnaBridge	156:ff21514d8981	1083	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
AnnaBridge	156:ff21514d8981	1084
AnnaBridge	156:ff21514d8981	1085	/* ITM Integration Read Register Definitions */
AnnaBridge	156:ff21514d8981	1086	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
AnnaBridge	156:ff21514d8981	1087	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
AnnaBridge	156:ff21514d8981	1088
AnnaBridge	156:ff21514d8981	1089	/* ITM Integration Mode Control Register Definitions */
AnnaBridge	156:ff21514d8981	1090	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
AnnaBridge	156:ff21514d8981	1091	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
AnnaBridge	156:ff21514d8981	1092
AnnaBridge	156:ff21514d8981	1093	/* ITM Lock Status Register Definitions */
AnnaBridge	156:ff21514d8981	1094	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
AnnaBridge	156:ff21514d8981	1095	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
AnnaBridge	156:ff21514d8981	1096
AnnaBridge	156:ff21514d8981	1097	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
AnnaBridge	156:ff21514d8981	1098	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
AnnaBridge	156:ff21514d8981	1099
AnnaBridge	156:ff21514d8981	1100	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
AnnaBridge	156:ff21514d8981	1101	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
AnnaBridge	156:ff21514d8981	1102
AnnaBridge	156:ff21514d8981	1103	/@}/ /* end of group CMSIS_ITM */
AnnaBridge	156:ff21514d8981	1104
AnnaBridge	156:ff21514d8981	1105
AnnaBridge	156:ff21514d8981	1106	/**
AnnaBridge	156:ff21514d8981	1107	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	1108	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge	156:ff21514d8981	1109	\brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge	156:ff21514d8981	1110	@{
AnnaBridge	156:ff21514d8981	1111	*/
AnnaBridge	156:ff21514d8981	1112
AnnaBridge	156:ff21514d8981	1113	/**
AnnaBridge	156:ff21514d8981	1114	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge	156:ff21514d8981	1115	*/
AnnaBridge	156:ff21514d8981	1116	typedef struct
AnnaBridge	156:ff21514d8981	1117	{
AnnaBridge	156:ff21514d8981	1118	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
AnnaBridge	156:ff21514d8981	1119	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
AnnaBridge	156:ff21514d8981	1120	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
AnnaBridge	156:ff21514d8981	1121	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
AnnaBridge	156:ff21514d8981	1122	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
AnnaBridge	156:ff21514d8981	1123	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
AnnaBridge	156:ff21514d8981	1124	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
AnnaBridge	156:ff21514d8981	1125	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
AnnaBridge	156:ff21514d8981	1126	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
AnnaBridge	156:ff21514d8981	1127	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
AnnaBridge	156:ff21514d8981	1128	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
AnnaBridge	156:ff21514d8981	1129	uint32_t RESERVED0[1U];
AnnaBridge	156:ff21514d8981	1130	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
AnnaBridge	156:ff21514d8981	1131	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
AnnaBridge	156:ff21514d8981	1132	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
AnnaBridge	156:ff21514d8981	1133	uint32_t RESERVED1[1U];
AnnaBridge	156:ff21514d8981	1134	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
AnnaBridge	156:ff21514d8981	1135	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
AnnaBridge	156:ff21514d8981	1136	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
AnnaBridge	156:ff21514d8981	1137	uint32_t RESERVED2[1U];
AnnaBridge	156:ff21514d8981	1138	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
AnnaBridge	156:ff21514d8981	1139	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
AnnaBridge	156:ff21514d8981	1140	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
AnnaBridge	156:ff21514d8981	1141	uint32_t RESERVED3[981U];
AnnaBridge	156:ff21514d8981	1142	__OM uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
AnnaBridge	156:ff21514d8981	1143	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
AnnaBridge	156:ff21514d8981	1144	} DWT_Type;
AnnaBridge	156:ff21514d8981	1145
AnnaBridge	156:ff21514d8981	1146	/* DWT Control Register Definitions */
AnnaBridge	156:ff21514d8981	1147	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
AnnaBridge	156:ff21514d8981	1148	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
AnnaBridge	156:ff21514d8981	1149
AnnaBridge	156:ff21514d8981	1150	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
AnnaBridge	156:ff21514d8981	1151	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
AnnaBridge	156:ff21514d8981	1152
AnnaBridge	156:ff21514d8981	1153	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
AnnaBridge	156:ff21514d8981	1154	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
AnnaBridge	156:ff21514d8981	1155
AnnaBridge	156:ff21514d8981	1156	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
AnnaBridge	156:ff21514d8981	1157	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
AnnaBridge	156:ff21514d8981	1158
AnnaBridge	156:ff21514d8981	1159	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
AnnaBridge	156:ff21514d8981	1160	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
AnnaBridge	156:ff21514d8981	1161
AnnaBridge	156:ff21514d8981	1162	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
AnnaBridge	156:ff21514d8981	1163	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
AnnaBridge	156:ff21514d8981	1164
AnnaBridge	156:ff21514d8981	1165	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
AnnaBridge	156:ff21514d8981	1166	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
AnnaBridge	156:ff21514d8981	1167
AnnaBridge	156:ff21514d8981	1168	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
AnnaBridge	156:ff21514d8981	1169	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
AnnaBridge	156:ff21514d8981	1170
AnnaBridge	156:ff21514d8981	1171	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
AnnaBridge	156:ff21514d8981	1172	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
AnnaBridge	156:ff21514d8981	1173
AnnaBridge	156:ff21514d8981	1174	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
AnnaBridge	156:ff21514d8981	1175	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
AnnaBridge	156:ff21514d8981	1176
AnnaBridge	156:ff21514d8981	1177	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
AnnaBridge	156:ff21514d8981	1178	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
AnnaBridge	156:ff21514d8981	1179
AnnaBridge	156:ff21514d8981	1180	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
AnnaBridge	156:ff21514d8981	1181	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
AnnaBridge	156:ff21514d8981	1182
AnnaBridge	156:ff21514d8981	1183	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
AnnaBridge	156:ff21514d8981	1184	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
AnnaBridge	156:ff21514d8981	1185
AnnaBridge	156:ff21514d8981	1186	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
AnnaBridge	156:ff21514d8981	1187	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
AnnaBridge	156:ff21514d8981	1188
AnnaBridge	156:ff21514d8981	1189	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
AnnaBridge	156:ff21514d8981	1190	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
AnnaBridge	156:ff21514d8981	1191
AnnaBridge	156:ff21514d8981	1192	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
AnnaBridge	156:ff21514d8981	1193	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
AnnaBridge	156:ff21514d8981	1194
AnnaBridge	156:ff21514d8981	1195	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
AnnaBridge	156:ff21514d8981	1196	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
AnnaBridge	156:ff21514d8981	1197
AnnaBridge	156:ff21514d8981	1198	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
AnnaBridge	156:ff21514d8981	1199	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
AnnaBridge	156:ff21514d8981	1200
AnnaBridge	156:ff21514d8981	1201	/* DWT CPI Count Register Definitions */
AnnaBridge	156:ff21514d8981	1202	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
AnnaBridge	156:ff21514d8981	1203	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
AnnaBridge	156:ff21514d8981	1204
AnnaBridge	156:ff21514d8981	1205	/* DWT Exception Overhead Count Register Definitions */
AnnaBridge	156:ff21514d8981	1206	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
AnnaBridge	156:ff21514d8981	1207	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
AnnaBridge	156:ff21514d8981	1208
AnnaBridge	156:ff21514d8981	1209	/* DWT Sleep Count Register Definitions */
AnnaBridge	156:ff21514d8981	1210	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
AnnaBridge	156:ff21514d8981	1211	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
AnnaBridge	156:ff21514d8981	1212
AnnaBridge	156:ff21514d8981	1213	/* DWT LSU Count Register Definitions */
AnnaBridge	156:ff21514d8981	1214	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
AnnaBridge	156:ff21514d8981	1215	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
AnnaBridge	156:ff21514d8981	1216
AnnaBridge	156:ff21514d8981	1217	/* DWT Folded-instruction Count Register Definitions */
AnnaBridge	156:ff21514d8981	1218	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
AnnaBridge	156:ff21514d8981	1219	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
AnnaBridge	156:ff21514d8981	1220
AnnaBridge	156:ff21514d8981	1221	/* DWT Comparator Mask Register Definitions */
AnnaBridge	156:ff21514d8981	1222	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
AnnaBridge	156:ff21514d8981	1223	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
AnnaBridge	156:ff21514d8981	1224
AnnaBridge	156:ff21514d8981	1225	/* DWT Comparator Function Register Definitions */
AnnaBridge	156:ff21514d8981	1226	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
AnnaBridge	156:ff21514d8981	1227	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
AnnaBridge	156:ff21514d8981	1228
AnnaBridge	156:ff21514d8981	1229	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
AnnaBridge	156:ff21514d8981	1230	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
AnnaBridge	156:ff21514d8981	1231
AnnaBridge	156:ff21514d8981	1232	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
AnnaBridge	156:ff21514d8981	1233	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
AnnaBridge	156:ff21514d8981	1234
AnnaBridge	156:ff21514d8981	1235	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
AnnaBridge	156:ff21514d8981	1236	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
AnnaBridge	156:ff21514d8981	1237
AnnaBridge	156:ff21514d8981	1238	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
AnnaBridge	156:ff21514d8981	1239	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
AnnaBridge	156:ff21514d8981	1240
AnnaBridge	156:ff21514d8981	1241	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
AnnaBridge	156:ff21514d8981	1242	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
AnnaBridge	156:ff21514d8981	1243
AnnaBridge	156:ff21514d8981	1244	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
AnnaBridge	156:ff21514d8981	1245	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
AnnaBridge	156:ff21514d8981	1246
AnnaBridge	156:ff21514d8981	1247	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
AnnaBridge	156:ff21514d8981	1248	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
AnnaBridge	156:ff21514d8981	1249
AnnaBridge	156:ff21514d8981	1250	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
AnnaBridge	156:ff21514d8981	1251	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
AnnaBridge	156:ff21514d8981	1252
AnnaBridge	156:ff21514d8981	1253	/@}/ /* end of group CMSIS_DWT */
AnnaBridge	156:ff21514d8981	1254
AnnaBridge	156:ff21514d8981	1255
AnnaBridge	156:ff21514d8981	1256	/**
AnnaBridge	156:ff21514d8981	1257	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	1258	\defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge	156:ff21514d8981	1259	\brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge	156:ff21514d8981	1260	@{
AnnaBridge	156:ff21514d8981	1261	*/
AnnaBridge	156:ff21514d8981	1262
AnnaBridge	156:ff21514d8981	1263	/**
AnnaBridge	156:ff21514d8981	1264	\brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge	156:ff21514d8981	1265	*/
AnnaBridge	156:ff21514d8981	1266	typedef struct
AnnaBridge	156:ff21514d8981	1267	{
AnnaBridge	156:ff21514d8981	1268	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
AnnaBridge	156:ff21514d8981	1269	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
AnnaBridge	156:ff21514d8981	1270	uint32_t RESERVED0[2U];
AnnaBridge	156:ff21514d8981	1271	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
AnnaBridge	156:ff21514d8981	1272	uint32_t RESERVED1[55U];
AnnaBridge	156:ff21514d8981	1273	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
AnnaBridge	156:ff21514d8981	1274	uint32_t RESERVED2[131U];
AnnaBridge	156:ff21514d8981	1275	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
AnnaBridge	156:ff21514d8981	1276	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	156:ff21514d8981	1277	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
AnnaBridge	156:ff21514d8981	1278	uint32_t RESERVED3[759U];
AnnaBridge	156:ff21514d8981	1279	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
AnnaBridge	156:ff21514d8981	1280	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
AnnaBridge	156:ff21514d8981	1281	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
AnnaBridge	156:ff21514d8981	1282	uint32_t RESERVED4[1U];
AnnaBridge	156:ff21514d8981	1283	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
AnnaBridge	156:ff21514d8981	1284	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
AnnaBridge	156:ff21514d8981	1285	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
AnnaBridge	156:ff21514d8981	1286	uint32_t RESERVED5[39U];
AnnaBridge	156:ff21514d8981	1287	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
AnnaBridge	156:ff21514d8981	1288	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
AnnaBridge	156:ff21514d8981	1289	uint32_t RESERVED7[8U];
AnnaBridge	156:ff21514d8981	1290	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
AnnaBridge	156:ff21514d8981	1291	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
AnnaBridge	156:ff21514d8981	1292	} TPI_Type;
AnnaBridge	156:ff21514d8981	1293
AnnaBridge	156:ff21514d8981	1294	/* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge	156:ff21514d8981	1295	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
AnnaBridge	156:ff21514d8981	1296	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
AnnaBridge	156:ff21514d8981	1297
AnnaBridge	156:ff21514d8981	1298	/* TPI Selected Pin Protocol Register Definitions */
AnnaBridge	156:ff21514d8981	1299	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
AnnaBridge	156:ff21514d8981	1300	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
AnnaBridge	156:ff21514d8981	1301
AnnaBridge	156:ff21514d8981	1302	/* TPI Formatter and Flush Status Register Definitions */
AnnaBridge	156:ff21514d8981	1303	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
AnnaBridge	156:ff21514d8981	1304	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
AnnaBridge	156:ff21514d8981	1305
AnnaBridge	156:ff21514d8981	1306	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
AnnaBridge	156:ff21514d8981	1307	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
AnnaBridge	156:ff21514d8981	1308
AnnaBridge	156:ff21514d8981	1309	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
AnnaBridge	156:ff21514d8981	1310	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
AnnaBridge	156:ff21514d8981	1311
AnnaBridge	156:ff21514d8981	1312	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
AnnaBridge	156:ff21514d8981	1313	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
AnnaBridge	156:ff21514d8981	1314
AnnaBridge	156:ff21514d8981	1315	/* TPI Formatter and Flush Control Register Definitions */
AnnaBridge	156:ff21514d8981	1316	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
AnnaBridge	156:ff21514d8981	1317	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
AnnaBridge	156:ff21514d8981	1318
AnnaBridge	156:ff21514d8981	1319	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
AnnaBridge	156:ff21514d8981	1320	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
AnnaBridge	156:ff21514d8981	1321
AnnaBridge	156:ff21514d8981	1322	/* TPI TRIGGER Register Definitions */
AnnaBridge	156:ff21514d8981	1323	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
AnnaBridge	156:ff21514d8981	1324	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
AnnaBridge	156:ff21514d8981	1325
AnnaBridge	156:ff21514d8981	1326	/* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge	156:ff21514d8981	1327	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
AnnaBridge	156:ff21514d8981	1328	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
AnnaBridge	156:ff21514d8981	1329
AnnaBridge	156:ff21514d8981	1330	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
AnnaBridge	156:ff21514d8981	1331	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
AnnaBridge	156:ff21514d8981	1332
AnnaBridge	156:ff21514d8981	1333	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
AnnaBridge	156:ff21514d8981	1334	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
AnnaBridge	156:ff21514d8981	1335
AnnaBridge	156:ff21514d8981	1336	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
AnnaBridge	156:ff21514d8981	1337	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
AnnaBridge	156:ff21514d8981	1338
AnnaBridge	156:ff21514d8981	1339	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
AnnaBridge	156:ff21514d8981	1340	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
AnnaBridge	156:ff21514d8981	1341
AnnaBridge	156:ff21514d8981	1342	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
AnnaBridge	156:ff21514d8981	1343	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
AnnaBridge	156:ff21514d8981	1344
AnnaBridge	156:ff21514d8981	1345	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
AnnaBridge	156:ff21514d8981	1346	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
AnnaBridge	156:ff21514d8981	1347
AnnaBridge	156:ff21514d8981	1348	/* TPI ITATBCTR2 Register Definitions */
AnnaBridge	156:ff21514d8981	1349	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
AnnaBridge	156:ff21514d8981	1350	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
AnnaBridge	156:ff21514d8981	1351
AnnaBridge	156:ff21514d8981	1352	/* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge	156:ff21514d8981	1353	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
AnnaBridge	156:ff21514d8981	1354	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
AnnaBridge	156:ff21514d8981	1355
AnnaBridge	156:ff21514d8981	1356	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
AnnaBridge	156:ff21514d8981	1357	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
AnnaBridge	156:ff21514d8981	1358
AnnaBridge	156:ff21514d8981	1359	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
AnnaBridge	156:ff21514d8981	1360	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
AnnaBridge	156:ff21514d8981	1361
AnnaBridge	156:ff21514d8981	1362	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
AnnaBridge	156:ff21514d8981	1363	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
AnnaBridge	156:ff21514d8981	1364
AnnaBridge	156:ff21514d8981	1365	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
AnnaBridge	156:ff21514d8981	1366	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
AnnaBridge	156:ff21514d8981	1367
AnnaBridge	156:ff21514d8981	1368	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
AnnaBridge	156:ff21514d8981	1369	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
AnnaBridge	156:ff21514d8981	1370
AnnaBridge	156:ff21514d8981	1371	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
AnnaBridge	156:ff21514d8981	1372	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
AnnaBridge	156:ff21514d8981	1373
AnnaBridge	156:ff21514d8981	1374	/* TPI ITATBCTR0 Register Definitions */
AnnaBridge	156:ff21514d8981	1375	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
AnnaBridge	156:ff21514d8981	1376	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
AnnaBridge	156:ff21514d8981	1377
AnnaBridge	156:ff21514d8981	1378	/* TPI Integration Mode Control Register Definitions */
AnnaBridge	156:ff21514d8981	1379	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
AnnaBridge	156:ff21514d8981	1380	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
AnnaBridge	156:ff21514d8981	1381
AnnaBridge	156:ff21514d8981	1382	/* TPI DEVID Register Definitions */
AnnaBridge	156:ff21514d8981	1383	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
AnnaBridge	156:ff21514d8981	1384	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
AnnaBridge	156:ff21514d8981	1385
AnnaBridge	156:ff21514d8981	1386	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
AnnaBridge	156:ff21514d8981	1387	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
AnnaBridge	156:ff21514d8981	1388
AnnaBridge	156:ff21514d8981	1389	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
AnnaBridge	156:ff21514d8981	1390	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
AnnaBridge	156:ff21514d8981	1391
AnnaBridge	156:ff21514d8981	1392	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
AnnaBridge	156:ff21514d8981	1393	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
AnnaBridge	156:ff21514d8981	1394
AnnaBridge	156:ff21514d8981	1395	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
AnnaBridge	156:ff21514d8981	1396	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
AnnaBridge	156:ff21514d8981	1397
AnnaBridge	156:ff21514d8981	1398	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
AnnaBridge	156:ff21514d8981	1399	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
AnnaBridge	156:ff21514d8981	1400
AnnaBridge	156:ff21514d8981	1401	/* TPI DEVTYPE Register Definitions */
AnnaBridge	156:ff21514d8981	1402	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
AnnaBridge	156:ff21514d8981	1403	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
AnnaBridge	156:ff21514d8981	1404
AnnaBridge	156:ff21514d8981	1405	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
AnnaBridge	156:ff21514d8981	1406	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
AnnaBridge	156:ff21514d8981	1407
AnnaBridge	156:ff21514d8981	1408	/@}/ /* end of group CMSIS_TPI */
AnnaBridge	156:ff21514d8981	1409
AnnaBridge	156:ff21514d8981	1410
AnnaBridge	156:ff21514d8981	1411	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	1412	/**
AnnaBridge	156:ff21514d8981	1413	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	1414	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge	156:ff21514d8981	1415	\brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge	156:ff21514d8981	1416	@{
AnnaBridge	156:ff21514d8981	1417	*/
AnnaBridge	156:ff21514d8981	1418
AnnaBridge	156:ff21514d8981	1419	/**
AnnaBridge	156:ff21514d8981	1420	\brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge	156:ff21514d8981	1421	*/
AnnaBridge	156:ff21514d8981	1422	typedef struct
AnnaBridge	156:ff21514d8981	1423	{
AnnaBridge	156:ff21514d8981	1424	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
AnnaBridge	156:ff21514d8981	1425	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
AnnaBridge	156:ff21514d8981	1426	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
AnnaBridge	156:ff21514d8981	1427	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
AnnaBridge	156:ff21514d8981	1428	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
AnnaBridge	156:ff21514d8981	1429	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
AnnaBridge	156:ff21514d8981	1430	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
AnnaBridge	156:ff21514d8981	1431	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
AnnaBridge	156:ff21514d8981	1432	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
AnnaBridge	156:ff21514d8981	1433	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
AnnaBridge	156:ff21514d8981	1434	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
AnnaBridge	156:ff21514d8981	1435	} MPU_Type;
AnnaBridge	156:ff21514d8981	1436
Anna Bridge	160:5571c4ff569f	1437	#define MPU_TYPE_RALIASES 4U
Anna Bridge	160:5571c4ff569f	1438
AnnaBridge	156:ff21514d8981	1439	/* MPU Type Register Definitions */
AnnaBridge	156:ff21514d8981	1440	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
AnnaBridge	156:ff21514d8981	1441	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
AnnaBridge	156:ff21514d8981	1442
AnnaBridge	156:ff21514d8981	1443	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
AnnaBridge	156:ff21514d8981	1444	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
AnnaBridge	156:ff21514d8981	1445
AnnaBridge	156:ff21514d8981	1446	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
AnnaBridge	156:ff21514d8981	1447	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
AnnaBridge	156:ff21514d8981	1448
AnnaBridge	156:ff21514d8981	1449	/* MPU Control Register Definitions */
AnnaBridge	156:ff21514d8981	1450	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
AnnaBridge	156:ff21514d8981	1451	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
AnnaBridge	156:ff21514d8981	1452
AnnaBridge	156:ff21514d8981	1453	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
AnnaBridge	156:ff21514d8981	1454	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
AnnaBridge	156:ff21514d8981	1455
AnnaBridge	156:ff21514d8981	1456	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
AnnaBridge	156:ff21514d8981	1457	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
AnnaBridge	156:ff21514d8981	1458
AnnaBridge	156:ff21514d8981	1459	/* MPU Region Number Register Definitions */
AnnaBridge	156:ff21514d8981	1460	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
AnnaBridge	156:ff21514d8981	1461	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
AnnaBridge	156:ff21514d8981	1462
AnnaBridge	156:ff21514d8981	1463	/* MPU Region Base Address Register Definitions */
AnnaBridge	156:ff21514d8981	1464	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
AnnaBridge	156:ff21514d8981	1465	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
AnnaBridge	156:ff21514d8981	1466
AnnaBridge	156:ff21514d8981	1467	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
AnnaBridge	156:ff21514d8981	1468	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
AnnaBridge	156:ff21514d8981	1469
AnnaBridge	156:ff21514d8981	1470	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
AnnaBridge	156:ff21514d8981	1471	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
AnnaBridge	156:ff21514d8981	1472
AnnaBridge	156:ff21514d8981	1473	/* MPU Region Attribute and Size Register Definitions */
AnnaBridge	156:ff21514d8981	1474	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
AnnaBridge	156:ff21514d8981	1475	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
AnnaBridge	156:ff21514d8981	1476
AnnaBridge	156:ff21514d8981	1477	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
AnnaBridge	156:ff21514d8981	1478	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
AnnaBridge	156:ff21514d8981	1479
AnnaBridge	156:ff21514d8981	1480	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
AnnaBridge	156:ff21514d8981	1481	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
AnnaBridge	156:ff21514d8981	1482
AnnaBridge	156:ff21514d8981	1483	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
AnnaBridge	156:ff21514d8981	1484	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
AnnaBridge	156:ff21514d8981	1485
AnnaBridge	156:ff21514d8981	1486	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
AnnaBridge	156:ff21514d8981	1487	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
AnnaBridge	156:ff21514d8981	1488
AnnaBridge	156:ff21514d8981	1489	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
AnnaBridge	156:ff21514d8981	1490	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
AnnaBridge	156:ff21514d8981	1491
AnnaBridge	156:ff21514d8981	1492	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
AnnaBridge	156:ff21514d8981	1493	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
AnnaBridge	156:ff21514d8981	1494
AnnaBridge	156:ff21514d8981	1495	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
AnnaBridge	156:ff21514d8981	1496	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
AnnaBridge	156:ff21514d8981	1497
AnnaBridge	156:ff21514d8981	1498	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
AnnaBridge	156:ff21514d8981	1499	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
AnnaBridge	156:ff21514d8981	1500
AnnaBridge	156:ff21514d8981	1501	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
AnnaBridge	156:ff21514d8981	1502	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
AnnaBridge	156:ff21514d8981	1503
AnnaBridge	156:ff21514d8981	1504	/@} end of group CMSIS_MPU /
AnnaBridge	156:ff21514d8981	1505	#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
AnnaBridge	156:ff21514d8981	1506
AnnaBridge	156:ff21514d8981	1507
AnnaBridge	156:ff21514d8981	1508	/**
AnnaBridge	156:ff21514d8981	1509	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	1510	\defgroup CMSIS_FPU Floating Point Unit (FPU)
AnnaBridge	156:ff21514d8981	1511	\brief Type definitions for the Floating Point Unit (FPU)
AnnaBridge	156:ff21514d8981	1512	@{
AnnaBridge	156:ff21514d8981	1513	*/
AnnaBridge	156:ff21514d8981	1514
AnnaBridge	156:ff21514d8981	1515	/**
AnnaBridge	156:ff21514d8981	1516	\brief Structure type to access the Floating Point Unit (FPU).
AnnaBridge	156:ff21514d8981	1517	*/
AnnaBridge	156:ff21514d8981	1518	typedef struct
AnnaBridge	156:ff21514d8981	1519	{
AnnaBridge	156:ff21514d8981	1520	uint32_t RESERVED0[1U];
AnnaBridge	156:ff21514d8981	1521	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
AnnaBridge	156:ff21514d8981	1522	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
AnnaBridge	156:ff21514d8981	1523	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
AnnaBridge	156:ff21514d8981	1524	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
AnnaBridge	156:ff21514d8981	1525	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
AnnaBridge	156:ff21514d8981	1526	__IM uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
AnnaBridge	156:ff21514d8981	1527	} FPU_Type;
AnnaBridge	156:ff21514d8981	1528
AnnaBridge	156:ff21514d8981	1529	/* Floating-Point Context Control Register Definitions */
AnnaBridge	156:ff21514d8981	1530	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
AnnaBridge	156:ff21514d8981	1531	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
AnnaBridge	156:ff21514d8981	1532
AnnaBridge	156:ff21514d8981	1533	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
AnnaBridge	156:ff21514d8981	1534	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
AnnaBridge	156:ff21514d8981	1535
AnnaBridge	156:ff21514d8981	1536	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
AnnaBridge	156:ff21514d8981	1537	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
AnnaBridge	156:ff21514d8981	1538
AnnaBridge	156:ff21514d8981	1539	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
AnnaBridge	156:ff21514d8981	1540	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
AnnaBridge	156:ff21514d8981	1541
AnnaBridge	156:ff21514d8981	1542	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
AnnaBridge	156:ff21514d8981	1543	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
AnnaBridge	156:ff21514d8981	1544
AnnaBridge	156:ff21514d8981	1545	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
AnnaBridge	156:ff21514d8981	1546	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
AnnaBridge	156:ff21514d8981	1547
AnnaBridge	156:ff21514d8981	1548	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
AnnaBridge	156:ff21514d8981	1549	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
AnnaBridge	156:ff21514d8981	1550
AnnaBridge	156:ff21514d8981	1551	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
AnnaBridge	156:ff21514d8981	1552	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
AnnaBridge	156:ff21514d8981	1553
AnnaBridge	156:ff21514d8981	1554	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
AnnaBridge	156:ff21514d8981	1555	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
AnnaBridge	156:ff21514d8981	1556
AnnaBridge	156:ff21514d8981	1557	/* Floating-Point Context Address Register Definitions */
AnnaBridge	156:ff21514d8981	1558	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
AnnaBridge	156:ff21514d8981	1559	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
AnnaBridge	156:ff21514d8981	1560
AnnaBridge	156:ff21514d8981	1561	/* Floating-Point Default Status Control Register Definitions */
AnnaBridge	156:ff21514d8981	1562	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
AnnaBridge	156:ff21514d8981	1563	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
AnnaBridge	156:ff21514d8981	1564
AnnaBridge	156:ff21514d8981	1565	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
AnnaBridge	156:ff21514d8981	1566	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
AnnaBridge	156:ff21514d8981	1567
AnnaBridge	156:ff21514d8981	1568	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
AnnaBridge	156:ff21514d8981	1569	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
AnnaBridge	156:ff21514d8981	1570
AnnaBridge	156:ff21514d8981	1571	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
AnnaBridge	156:ff21514d8981	1572	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
AnnaBridge	156:ff21514d8981	1573
AnnaBridge	156:ff21514d8981	1574	/* Media and FP Feature Register 0 Definitions */
AnnaBridge	156:ff21514d8981	1575	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
AnnaBridge	156:ff21514d8981	1576	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
AnnaBridge	156:ff21514d8981	1577
AnnaBridge	156:ff21514d8981	1578	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
AnnaBridge	156:ff21514d8981	1579	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
AnnaBridge	156:ff21514d8981	1580
AnnaBridge	156:ff21514d8981	1581	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
AnnaBridge	156:ff21514d8981	1582	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
AnnaBridge	156:ff21514d8981	1583
AnnaBridge	156:ff21514d8981	1584	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
AnnaBridge	156:ff21514d8981	1585	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
AnnaBridge	156:ff21514d8981	1586
AnnaBridge	156:ff21514d8981	1587	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
AnnaBridge	156:ff21514d8981	1588	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
AnnaBridge	156:ff21514d8981	1589
AnnaBridge	156:ff21514d8981	1590	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
AnnaBridge	156:ff21514d8981	1591	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
AnnaBridge	156:ff21514d8981	1592
AnnaBridge	156:ff21514d8981	1593	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
AnnaBridge	156:ff21514d8981	1594	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
AnnaBridge	156:ff21514d8981	1595
AnnaBridge	156:ff21514d8981	1596	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
AnnaBridge	156:ff21514d8981	1597	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
AnnaBridge	156:ff21514d8981	1598
AnnaBridge	156:ff21514d8981	1599	/* Media and FP Feature Register 1 Definitions */
AnnaBridge	156:ff21514d8981	1600	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
AnnaBridge	156:ff21514d8981	1601	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
AnnaBridge	156:ff21514d8981	1602
AnnaBridge	156:ff21514d8981	1603	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
AnnaBridge	156:ff21514d8981	1604	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
AnnaBridge	156:ff21514d8981	1605
AnnaBridge	156:ff21514d8981	1606	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
AnnaBridge	156:ff21514d8981	1607	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
AnnaBridge	156:ff21514d8981	1608
AnnaBridge	156:ff21514d8981	1609	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
AnnaBridge	156:ff21514d8981	1610	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
AnnaBridge	156:ff21514d8981	1611
AnnaBridge	156:ff21514d8981	1612	/* Media and FP Feature Register 2 Definitions */
AnnaBridge	156:ff21514d8981	1613
AnnaBridge	156:ff21514d8981	1614	/@} end of group CMSIS_FPU /
AnnaBridge	156:ff21514d8981	1615
AnnaBridge	156:ff21514d8981	1616
AnnaBridge	156:ff21514d8981	1617	/**
AnnaBridge	156:ff21514d8981	1618	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	1619	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge	156:ff21514d8981	1620	\brief Type definitions for the Core Debug Registers
AnnaBridge	156:ff21514d8981	1621	@{
AnnaBridge	156:ff21514d8981	1622	*/
AnnaBridge	156:ff21514d8981	1623
AnnaBridge	156:ff21514d8981	1624	/**
AnnaBridge	156:ff21514d8981	1625	\brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge	156:ff21514d8981	1626	*/
AnnaBridge	156:ff21514d8981	1627	typedef struct
AnnaBridge	156:ff21514d8981	1628	{
AnnaBridge	156:ff21514d8981	1629	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
AnnaBridge	156:ff21514d8981	1630	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
AnnaBridge	156:ff21514d8981	1631	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
AnnaBridge	156:ff21514d8981	1632	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
AnnaBridge	156:ff21514d8981	1633	} CoreDebug_Type;
AnnaBridge	156:ff21514d8981	1634
AnnaBridge	156:ff21514d8981	1635	/* Debug Halting Control and Status Register Definitions */
AnnaBridge	156:ff21514d8981	1636	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
AnnaBridge	156:ff21514d8981	1637	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
AnnaBridge	156:ff21514d8981	1638
AnnaBridge	156:ff21514d8981	1639	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
AnnaBridge	156:ff21514d8981	1640	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
AnnaBridge	156:ff21514d8981	1641
AnnaBridge	156:ff21514d8981	1642	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
AnnaBridge	156:ff21514d8981	1643	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
AnnaBridge	156:ff21514d8981	1644
AnnaBridge	156:ff21514d8981	1645	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
AnnaBridge	156:ff21514d8981	1646	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
AnnaBridge	156:ff21514d8981	1647
AnnaBridge	156:ff21514d8981	1648	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
AnnaBridge	156:ff21514d8981	1649	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
AnnaBridge	156:ff21514d8981	1650
AnnaBridge	156:ff21514d8981	1651	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
AnnaBridge	156:ff21514d8981	1652	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
AnnaBridge	156:ff21514d8981	1653
AnnaBridge	156:ff21514d8981	1654	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
AnnaBridge	156:ff21514d8981	1655	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
AnnaBridge	156:ff21514d8981	1656
AnnaBridge	156:ff21514d8981	1657	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
AnnaBridge	156:ff21514d8981	1658	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
AnnaBridge	156:ff21514d8981	1659
AnnaBridge	156:ff21514d8981	1660	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
AnnaBridge	156:ff21514d8981	1661	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
AnnaBridge	156:ff21514d8981	1662
AnnaBridge	156:ff21514d8981	1663	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
AnnaBridge	156:ff21514d8981	1664	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
AnnaBridge	156:ff21514d8981	1665
AnnaBridge	156:ff21514d8981	1666	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
AnnaBridge	156:ff21514d8981	1667	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
AnnaBridge	156:ff21514d8981	1668
AnnaBridge	156:ff21514d8981	1669	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
AnnaBridge	156:ff21514d8981	1670	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
AnnaBridge	156:ff21514d8981	1671
AnnaBridge	156:ff21514d8981	1672	/* Debug Core Register Selector Register Definitions */
AnnaBridge	156:ff21514d8981	1673	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
AnnaBridge	156:ff21514d8981	1674	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
AnnaBridge	156:ff21514d8981	1675
AnnaBridge	156:ff21514d8981	1676	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
AnnaBridge	156:ff21514d8981	1677	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
AnnaBridge	156:ff21514d8981	1678
AnnaBridge	156:ff21514d8981	1679	/* Debug Exception and Monitor Control Register Definitions */
AnnaBridge	156:ff21514d8981	1680	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
AnnaBridge	156:ff21514d8981	1681	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
AnnaBridge	156:ff21514d8981	1682
AnnaBridge	156:ff21514d8981	1683	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
AnnaBridge	156:ff21514d8981	1684	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
AnnaBridge	156:ff21514d8981	1685
AnnaBridge	156:ff21514d8981	1686	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
AnnaBridge	156:ff21514d8981	1687	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
AnnaBridge	156:ff21514d8981	1688
AnnaBridge	156:ff21514d8981	1689	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
AnnaBridge	156:ff21514d8981	1690	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
AnnaBridge	156:ff21514d8981	1691
AnnaBridge	156:ff21514d8981	1692	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
AnnaBridge	156:ff21514d8981	1693	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
AnnaBridge	156:ff21514d8981	1694
AnnaBridge	156:ff21514d8981	1695	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
AnnaBridge	156:ff21514d8981	1696	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
AnnaBridge	156:ff21514d8981	1697
AnnaBridge	156:ff21514d8981	1698	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
AnnaBridge	156:ff21514d8981	1699	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
AnnaBridge	156:ff21514d8981	1700
AnnaBridge	156:ff21514d8981	1701	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
AnnaBridge	156:ff21514d8981	1702	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
AnnaBridge	156:ff21514d8981	1703
AnnaBridge	156:ff21514d8981	1704	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
AnnaBridge	156:ff21514d8981	1705	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
AnnaBridge	156:ff21514d8981	1706
AnnaBridge	156:ff21514d8981	1707	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
AnnaBridge	156:ff21514d8981	1708	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
AnnaBridge	156:ff21514d8981	1709
AnnaBridge	156:ff21514d8981	1710	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
AnnaBridge	156:ff21514d8981	1711	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
AnnaBridge	156:ff21514d8981	1712
AnnaBridge	156:ff21514d8981	1713	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
AnnaBridge	156:ff21514d8981	1714	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
AnnaBridge	156:ff21514d8981	1715
AnnaBridge	156:ff21514d8981	1716	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
AnnaBridge	156:ff21514d8981	1717	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
AnnaBridge	156:ff21514d8981	1718
AnnaBridge	156:ff21514d8981	1719	/@} end of group CMSIS_CoreDebug /
AnnaBridge	156:ff21514d8981	1720
AnnaBridge	156:ff21514d8981	1721
AnnaBridge	156:ff21514d8981	1722	/**
AnnaBridge	156:ff21514d8981	1723	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	1724	\defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge	156:ff21514d8981	1725	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge	156:ff21514d8981	1726	@{
AnnaBridge	156:ff21514d8981	1727	*/
AnnaBridge	156:ff21514d8981	1728
AnnaBridge	156:ff21514d8981	1729	/**
AnnaBridge	156:ff21514d8981	1730	\brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge	156:ff21514d8981	1731	\param[in] field Name of the register bit field.
AnnaBridge	156:ff21514d8981	1732	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge	156:ff21514d8981	1733	\return Masked and shifted value.
AnnaBridge	156:ff21514d8981	1734	*/
AnnaBridge	156:ff21514d8981	1735	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge	156:ff21514d8981	1736
AnnaBridge	156:ff21514d8981	1737	/**
AnnaBridge	156:ff21514d8981	1738	\brief Mask and shift a register value to extract a bit filed value.
AnnaBridge	156:ff21514d8981	1739	\param[in] field Name of the register bit field.
AnnaBridge	156:ff21514d8981	1740	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge	156:ff21514d8981	1741	\return Masked and shifted bit field value.
AnnaBridge	156:ff21514d8981	1742	*/
AnnaBridge	156:ff21514d8981	1743	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge	156:ff21514d8981	1744
AnnaBridge	156:ff21514d8981	1745	/@} end of group CMSIS_core_bitfield /
AnnaBridge	156:ff21514d8981	1746
AnnaBridge	156:ff21514d8981	1747
AnnaBridge	156:ff21514d8981	1748	/**
AnnaBridge	156:ff21514d8981	1749	\ingroup CMSIS_core_register
AnnaBridge	156:ff21514d8981	1750	\defgroup CMSIS_core_base Core Definitions
AnnaBridge	156:ff21514d8981	1751	\brief Definitions for base addresses, unions, and structures.
AnnaBridge	156:ff21514d8981	1752	@{
AnnaBridge	156:ff21514d8981	1753	*/
AnnaBridge	156:ff21514d8981	1754
AnnaBridge	156:ff21514d8981	1755	/* Memory mapping of Core Hardware */
AnnaBridge	156:ff21514d8981	1756	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
AnnaBridge	156:ff21514d8981	1757	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
AnnaBridge	156:ff21514d8981	1758	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
AnnaBridge	156:ff21514d8981	1759	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
AnnaBridge	156:ff21514d8981	1760	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
AnnaBridge	156:ff21514d8981	1761	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
AnnaBridge	156:ff21514d8981	1762	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
AnnaBridge	156:ff21514d8981	1763	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
AnnaBridge	156:ff21514d8981	1764
AnnaBridge	156:ff21514d8981	1765	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
AnnaBridge	156:ff21514d8981	1766	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
AnnaBridge	156:ff21514d8981	1767	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
AnnaBridge	156:ff21514d8981	1768	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
AnnaBridge	156:ff21514d8981	1769	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
AnnaBridge	156:ff21514d8981	1770	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
AnnaBridge	156:ff21514d8981	1771	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
AnnaBridge	156:ff21514d8981	1772	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
AnnaBridge	156:ff21514d8981	1773
AnnaBridge	156:ff21514d8981	1774	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	1775	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
AnnaBridge	156:ff21514d8981	1776	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
AnnaBridge	156:ff21514d8981	1777	#endif
AnnaBridge	156:ff21514d8981	1778
AnnaBridge	156:ff21514d8981	1779	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
AnnaBridge	156:ff21514d8981	1780	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
AnnaBridge	156:ff21514d8981	1781
AnnaBridge	156:ff21514d8981	1782	/@} /
AnnaBridge	156:ff21514d8981	1783
AnnaBridge	156:ff21514d8981	1784
AnnaBridge	156:ff21514d8981	1785
AnnaBridge	156:ff21514d8981	1786	/*******************************************************************************
AnnaBridge	156:ff21514d8981	1787	* Hardware Abstraction Layer
AnnaBridge	156:ff21514d8981	1788	Core Function Interface contains:
AnnaBridge	156:ff21514d8981	1789	- Core NVIC Functions
AnnaBridge	156:ff21514d8981	1790	- Core SysTick Functions
AnnaBridge	156:ff21514d8981	1791	- Core Debug Functions
AnnaBridge	156:ff21514d8981	1792	- Core Register Access Functions
AnnaBridge	156:ff21514d8981	1793	******************************************************************************/
AnnaBridge	156:ff21514d8981	1794	/**
AnnaBridge	156:ff21514d8981	1795	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge	156:ff21514d8981	1796	*/
AnnaBridge	156:ff21514d8981	1797
AnnaBridge	156:ff21514d8981	1798
AnnaBridge	156:ff21514d8981	1799
AnnaBridge	156:ff21514d8981	1800	/* ########################## NVIC functions #################################### */
AnnaBridge	156:ff21514d8981	1801	/**
AnnaBridge	156:ff21514d8981	1802	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	156:ff21514d8981	1803	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge	156:ff21514d8981	1804	\brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge	156:ff21514d8981	1805	@{
AnnaBridge	156:ff21514d8981	1806	*/
AnnaBridge	156:ff21514d8981	1807
AnnaBridge	156:ff21514d8981	1808	#ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge	156:ff21514d8981	1809	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	156:ff21514d8981	1810	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge	156:ff21514d8981	1811	#endif
AnnaBridge	156:ff21514d8981	1812	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	156:ff21514d8981	1813	#else
AnnaBridge	156:ff21514d8981	1814	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge	156:ff21514d8981	1815	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge	156:ff21514d8981	1816	#define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge	156:ff21514d8981	1817	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge	156:ff21514d8981	1818	#define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge	156:ff21514d8981	1819	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge	156:ff21514d8981	1820	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge	156:ff21514d8981	1821	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge	156:ff21514d8981	1822	#define NVIC_GetActive __NVIC_GetActive
AnnaBridge	156:ff21514d8981	1823	#define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge	156:ff21514d8981	1824	#define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge	156:ff21514d8981	1825	#define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge	156:ff21514d8981	1826	#endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge	156:ff21514d8981	1827
AnnaBridge	156:ff21514d8981	1828	#ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge	156:ff21514d8981	1829	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	156:ff21514d8981	1830	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge	156:ff21514d8981	1831	#endif
AnnaBridge	156:ff21514d8981	1832	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	156:ff21514d8981	1833	#else
AnnaBridge	156:ff21514d8981	1834	#define NVIC_SetVector __NVIC_SetVector
AnnaBridge	156:ff21514d8981	1835	#define NVIC_GetVector __NVIC_GetVector
AnnaBridge	156:ff21514d8981	1836	#endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge	156:ff21514d8981	1837
AnnaBridge	156:ff21514d8981	1838	#define NVIC_USER_IRQ_OFFSET 16
AnnaBridge	156:ff21514d8981	1839
AnnaBridge	156:ff21514d8981	1840
AnnaBridge	156:ff21514d8981	1841
AnnaBridge	156:ff21514d8981	1842	/**
AnnaBridge	156:ff21514d8981	1843	\brief Set Priority Grouping
AnnaBridge	156:ff21514d8981	1844	\details Sets the priority grouping field using the required unlock sequence.
AnnaBridge	156:ff21514d8981	1845	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge	156:ff21514d8981	1846	Only values from 0..7 are used.
AnnaBridge	156:ff21514d8981	1847	In case of a conflict between priority grouping and available
AnnaBridge	156:ff21514d8981	1848	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	156:ff21514d8981	1849	\param [in] PriorityGroup Priority grouping field.
AnnaBridge	156:ff21514d8981	1850	*/
AnnaBridge	156:ff21514d8981	1851	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge	156:ff21514d8981	1852	{
AnnaBridge	156:ff21514d8981	1853	uint32_t reg_value;
AnnaBridge	156:ff21514d8981	1854	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	156:ff21514d8981	1855
AnnaBridge	156:ff21514d8981	1856	reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge	156:ff21514d8981	1857	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge	156:ff21514d8981	1858	reg_value = (reg_value \|
AnnaBridge	156:ff21514d8981	1859	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	156:ff21514d8981	1860	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
AnnaBridge	156:ff21514d8981	1861	SCB->AIRCR = reg_value;
AnnaBridge	156:ff21514d8981	1862	}
AnnaBridge	156:ff21514d8981	1863
AnnaBridge	156:ff21514d8981	1864
AnnaBridge	156:ff21514d8981	1865	/**
AnnaBridge	156:ff21514d8981	1866	\brief Get Priority Grouping
AnnaBridge	156:ff21514d8981	1867	\details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge	156:ff21514d8981	1868	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge	156:ff21514d8981	1869	*/
AnnaBridge	156:ff21514d8981	1870	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
AnnaBridge	156:ff21514d8981	1871	{
AnnaBridge	156:ff21514d8981	1872	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge	156:ff21514d8981	1873	}
AnnaBridge	156:ff21514d8981	1874
AnnaBridge	156:ff21514d8981	1875
AnnaBridge	156:ff21514d8981	1876	/**
AnnaBridge	156:ff21514d8981	1877	\brief Enable Interrupt
AnnaBridge	156:ff21514d8981	1878	\details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	156:ff21514d8981	1879	\param [in] IRQn Device specific interrupt number.
AnnaBridge	156:ff21514d8981	1880	\note IRQn must not be negative.
AnnaBridge	156:ff21514d8981	1881	*/
AnnaBridge	156:ff21514d8981	1882	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge	156:ff21514d8981	1883	{
AnnaBridge	156:ff21514d8981	1884	if ((int32_t)(IRQn) >= 0)
AnnaBridge	156:ff21514d8981	1885	{
AnnaBridge	156:ff21514d8981	1886	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	156:ff21514d8981	1887	}
AnnaBridge	156:ff21514d8981	1888	}
AnnaBridge	156:ff21514d8981	1889
AnnaBridge	156:ff21514d8981	1890
AnnaBridge	156:ff21514d8981	1891	/**
AnnaBridge	156:ff21514d8981	1892	\brief Get Interrupt Enable status
AnnaBridge	156:ff21514d8981	1893	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge	156:ff21514d8981	1894	\param [in] IRQn Device specific interrupt number.
AnnaBridge	156:ff21514d8981	1895	\return 0 Interrupt is not enabled.
AnnaBridge	156:ff21514d8981	1896	\return 1 Interrupt is enabled.
AnnaBridge	156:ff21514d8981	1897	\note IRQn must not be negative.
AnnaBridge	156:ff21514d8981	1898	*/
AnnaBridge	156:ff21514d8981	1899	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge	156:ff21514d8981	1900	{
AnnaBridge	156:ff21514d8981	1901	if ((int32_t)(IRQn) >= 0)
AnnaBridge	156:ff21514d8981	1902	{
AnnaBridge	156:ff21514d8981	1903	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	156:ff21514d8981	1904	}
AnnaBridge	156:ff21514d8981	1905	else
AnnaBridge	156:ff21514d8981	1906	{
AnnaBridge	156:ff21514d8981	1907	return(0U);
AnnaBridge	156:ff21514d8981	1908	}
AnnaBridge	156:ff21514d8981	1909	}
AnnaBridge	156:ff21514d8981	1910
AnnaBridge	156:ff21514d8981	1911
AnnaBridge	156:ff21514d8981	1912	/**
AnnaBridge	156:ff21514d8981	1913	\brief Disable Interrupt
AnnaBridge	156:ff21514d8981	1914	\details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	156:ff21514d8981	1915	\param [in] IRQn Device specific interrupt number.
AnnaBridge	156:ff21514d8981	1916	\note IRQn must not be negative.
AnnaBridge	156:ff21514d8981	1917	*/
AnnaBridge	156:ff21514d8981	1918	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge	156:ff21514d8981	1919	{
AnnaBridge	156:ff21514d8981	1920	if ((int32_t)(IRQn) >= 0)
AnnaBridge	156:ff21514d8981	1921	{
AnnaBridge	156:ff21514d8981	1922	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	156:ff21514d8981	1923	__DSB();
AnnaBridge	156:ff21514d8981	1924	__ISB();
AnnaBridge	156:ff21514d8981	1925	}
AnnaBridge	156:ff21514d8981	1926	}
AnnaBridge	156:ff21514d8981	1927
AnnaBridge	156:ff21514d8981	1928
AnnaBridge	156:ff21514d8981	1929	/**
AnnaBridge	156:ff21514d8981	1930	\brief Get Pending Interrupt
AnnaBridge	156:ff21514d8981	1931	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge	156:ff21514d8981	1932	\param [in] IRQn Device specific interrupt number.
AnnaBridge	156:ff21514d8981	1933	\return 0 Interrupt status is not pending.
AnnaBridge	156:ff21514d8981	1934	\return 1 Interrupt status is pending.
AnnaBridge	156:ff21514d8981	1935	\note IRQn must not be negative.
AnnaBridge	156:ff21514d8981	1936	*/
AnnaBridge	156:ff21514d8981	1937	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	156:ff21514d8981	1938	{
AnnaBridge	156:ff21514d8981	1939	if ((int32_t)(IRQn) >= 0)
AnnaBridge	156:ff21514d8981	1940	{
AnnaBridge	156:ff21514d8981	1941	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	156:ff21514d8981	1942	}
AnnaBridge	156:ff21514d8981	1943	else
AnnaBridge	156:ff21514d8981	1944	{
AnnaBridge	156:ff21514d8981	1945	return(0U);
AnnaBridge	156:ff21514d8981	1946	}
AnnaBridge	156:ff21514d8981	1947	}
AnnaBridge	156:ff21514d8981	1948
AnnaBridge	156:ff21514d8981	1949
AnnaBridge	156:ff21514d8981	1950	/**
AnnaBridge	156:ff21514d8981	1951	\brief Set Pending Interrupt
AnnaBridge	156:ff21514d8981	1952	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	156:ff21514d8981	1953	\param [in] IRQn Device specific interrupt number.
AnnaBridge	156:ff21514d8981	1954	\note IRQn must not be negative.
AnnaBridge	156:ff21514d8981	1955	*/
AnnaBridge	156:ff21514d8981	1956	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	156:ff21514d8981	1957	{
AnnaBridge	156:ff21514d8981	1958	if ((int32_t)(IRQn) >= 0)
AnnaBridge	156:ff21514d8981	1959	{
AnnaBridge	156:ff21514d8981	1960	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	156:ff21514d8981	1961	}
AnnaBridge	156:ff21514d8981	1962	}
AnnaBridge	156:ff21514d8981	1963
AnnaBridge	156:ff21514d8981	1964
AnnaBridge	156:ff21514d8981	1965	/**
AnnaBridge	156:ff21514d8981	1966	\brief Clear Pending Interrupt
AnnaBridge	156:ff21514d8981	1967	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	156:ff21514d8981	1968	\param [in] IRQn Device specific interrupt number.
AnnaBridge	156:ff21514d8981	1969	\note IRQn must not be negative.
AnnaBridge	156:ff21514d8981	1970	*/
AnnaBridge	156:ff21514d8981	1971	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	156:ff21514d8981	1972	{
AnnaBridge	156:ff21514d8981	1973	if ((int32_t)(IRQn) >= 0)
AnnaBridge	156:ff21514d8981	1974	{
AnnaBridge	156:ff21514d8981	1975	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	156:ff21514d8981	1976	}
AnnaBridge	156:ff21514d8981	1977	}
AnnaBridge	156:ff21514d8981	1978
AnnaBridge	156:ff21514d8981	1979
AnnaBridge	156:ff21514d8981	1980	/**
AnnaBridge	156:ff21514d8981	1981	\brief Get Active Interrupt
AnnaBridge	156:ff21514d8981	1982	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge	156:ff21514d8981	1983	\param [in] IRQn Device specific interrupt number.
AnnaBridge	156:ff21514d8981	1984	\return 0 Interrupt status is not active.
AnnaBridge	156:ff21514d8981	1985	\return 1 Interrupt status is active.
AnnaBridge	156:ff21514d8981	1986	\note IRQn must not be negative.
AnnaBridge	156:ff21514d8981	1987	*/
AnnaBridge	156:ff21514d8981	1988	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge	156:ff21514d8981	1989	{
AnnaBridge	156:ff21514d8981	1990	if ((int32_t)(IRQn) >= 0)
AnnaBridge	156:ff21514d8981	1991	{
AnnaBridge	156:ff21514d8981	1992	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	156:ff21514d8981	1993	}
AnnaBridge	156:ff21514d8981	1994	else
AnnaBridge	156:ff21514d8981	1995	{
AnnaBridge	156:ff21514d8981	1996	return(0U);
AnnaBridge	156:ff21514d8981	1997	}
AnnaBridge	156:ff21514d8981	1998	}
AnnaBridge	156:ff21514d8981	1999
AnnaBridge	156:ff21514d8981	2000
AnnaBridge	156:ff21514d8981	2001	/**
AnnaBridge	156:ff21514d8981	2002	\brief Set Interrupt Priority
AnnaBridge	156:ff21514d8981	2003	\details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge	156:ff21514d8981	2004	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	156:ff21514d8981	2005	or negative to specify a processor exception.
AnnaBridge	156:ff21514d8981	2006	\param [in] IRQn Interrupt number.
AnnaBridge	156:ff21514d8981	2007	\param [in] priority Priority to set.
AnnaBridge	156:ff21514d8981	2008	\note The priority cannot be set for every processor exception.
AnnaBridge	156:ff21514d8981	2009	*/
AnnaBridge	156:ff21514d8981	2010	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	156:ff21514d8981	2011	{
AnnaBridge	156:ff21514d8981	2012	if ((int32_t)(IRQn) >= 0)
AnnaBridge	156:ff21514d8981	2013	{
AnnaBridge	156:ff21514d8981	2014	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	156:ff21514d8981	2015	}
AnnaBridge	156:ff21514d8981	2016	else
AnnaBridge	156:ff21514d8981	2017	{
AnnaBridge	156:ff21514d8981	2018	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	156:ff21514d8981	2019	}
AnnaBridge	156:ff21514d8981	2020	}
AnnaBridge	156:ff21514d8981	2021
AnnaBridge	156:ff21514d8981	2022
AnnaBridge	156:ff21514d8981	2023	/**
AnnaBridge	156:ff21514d8981	2024	\brief Get Interrupt Priority
AnnaBridge	156:ff21514d8981	2025	\details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge	156:ff21514d8981	2026	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	156:ff21514d8981	2027	or negative to specify a processor exception.
AnnaBridge	156:ff21514d8981	2028	\param [in] IRQn Interrupt number.
AnnaBridge	156:ff21514d8981	2029	\return Interrupt Priority.
AnnaBridge	156:ff21514d8981	2030	Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	156:ff21514d8981	2031	*/
AnnaBridge	156:ff21514d8981	2032	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	156:ff21514d8981	2033	{
AnnaBridge	156:ff21514d8981	2034
AnnaBridge	156:ff21514d8981	2035	if ((int32_t)(IRQn) >= 0)
AnnaBridge	156:ff21514d8981	2036	{
AnnaBridge	156:ff21514d8981	2037	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	156:ff21514d8981	2038	}
AnnaBridge	156:ff21514d8981	2039	else
AnnaBridge	156:ff21514d8981	2040	{
AnnaBridge	156:ff21514d8981	2041	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	156:ff21514d8981	2042	}
AnnaBridge	156:ff21514d8981	2043	}
AnnaBridge	156:ff21514d8981	2044
AnnaBridge	156:ff21514d8981	2045
AnnaBridge	156:ff21514d8981	2046	/**
AnnaBridge	156:ff21514d8981	2047	\brief Encode Priority
AnnaBridge	156:ff21514d8981	2048	\details Encodes the priority for an interrupt with the given priority group,
AnnaBridge	156:ff21514d8981	2049	preemptive priority value, and subpriority value.
AnnaBridge	156:ff21514d8981	2050	In case of a conflict between priority grouping and available
AnnaBridge	156:ff21514d8981	2051	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	156:ff21514d8981	2052	\param [in] PriorityGroup Used priority group.
AnnaBridge	156:ff21514d8981	2053	\param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	156:ff21514d8981	2054	\param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge	156:ff21514d8981	2055	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge	156:ff21514d8981	2056	*/
AnnaBridge	156:ff21514d8981	2057	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge	156:ff21514d8981	2058	{
AnnaBridge	156:ff21514d8981	2059	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	156:ff21514d8981	2060	uint32_t PreemptPriorityBits;
AnnaBridge	156:ff21514d8981	2061	uint32_t SubPriorityBits;
AnnaBridge	156:ff21514d8981	2062
AnnaBridge	156:ff21514d8981	2063	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	156:ff21514d8981	2064	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	156:ff21514d8981	2065
AnnaBridge	156:ff21514d8981	2066	return (
AnnaBridge	156:ff21514d8981	2067	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
AnnaBridge	156:ff21514d8981	2068	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge	156:ff21514d8981	2069	);
AnnaBridge	156:ff21514d8981	2070	}
AnnaBridge	156:ff21514d8981	2071
AnnaBridge	156:ff21514d8981	2072
AnnaBridge	156:ff21514d8981	2073	/**
AnnaBridge	156:ff21514d8981	2074	\brief Decode Priority
AnnaBridge	156:ff21514d8981	2075	\details Decodes an interrupt priority value with a given priority group to
AnnaBridge	156:ff21514d8981	2076	preemptive priority value and subpriority value.
AnnaBridge	156:ff21514d8981	2077	In case of a conflict between priority grouping and available
AnnaBridge	156:ff21514d8981	2078	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge	156:ff21514d8981	2079	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge	156:ff21514d8981	2080	\param [in] PriorityGroup Used priority group.
AnnaBridge	156:ff21514d8981	2081	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	156:ff21514d8981	2082	\param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge	156:ff21514d8981	2083	*/
AnnaBridge	156:ff21514d8981	2084	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge	156:ff21514d8981	2085	{
AnnaBridge	156:ff21514d8981	2086	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	156:ff21514d8981	2087	uint32_t PreemptPriorityBits;
AnnaBridge	156:ff21514d8981	2088	uint32_t SubPriorityBits;
AnnaBridge	156:ff21514d8981	2089
AnnaBridge	156:ff21514d8981	2090	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	156:ff21514d8981	2091	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	156:ff21514d8981	2092
AnnaBridge	156:ff21514d8981	2093	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge	156:ff21514d8981	2094	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge	156:ff21514d8981	2095	}
AnnaBridge	156:ff21514d8981	2096
AnnaBridge	156:ff21514d8981	2097
AnnaBridge	156:ff21514d8981	2098	/**
AnnaBridge	156:ff21514d8981	2099	\brief Set Interrupt Vector
AnnaBridge	156:ff21514d8981	2100	\details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge	156:ff21514d8981	2101	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	156:ff21514d8981	2102	or negative to specify a processor exception.
AnnaBridge	156:ff21514d8981	2103	VTOR must been relocated to SRAM before.
AnnaBridge	156:ff21514d8981	2104	\param [in] IRQn Interrupt number
AnnaBridge	156:ff21514d8981	2105	\param [in] vector Address of interrupt handler function
AnnaBridge	156:ff21514d8981	2106	*/
AnnaBridge	156:ff21514d8981	2107	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge	156:ff21514d8981	2108	{
AnnaBridge	156:ff21514d8981	2109	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	156:ff21514d8981	2110	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge	156:ff21514d8981	2111	}
AnnaBridge	156:ff21514d8981	2112
AnnaBridge	156:ff21514d8981	2113
AnnaBridge	156:ff21514d8981	2114	/**
AnnaBridge	156:ff21514d8981	2115	\brief Get Interrupt Vector
AnnaBridge	156:ff21514d8981	2116	\details Reads an interrupt vector from interrupt vector table.
AnnaBridge	156:ff21514d8981	2117	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	156:ff21514d8981	2118	or negative to specify a processor exception.
AnnaBridge	156:ff21514d8981	2119	\param [in] IRQn Interrupt number.
AnnaBridge	156:ff21514d8981	2120	\return Address of interrupt handler function
AnnaBridge	156:ff21514d8981	2121	*/
AnnaBridge	156:ff21514d8981	2122	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge	156:ff21514d8981	2123	{
AnnaBridge	156:ff21514d8981	2124	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	156:ff21514d8981	2125	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge	156:ff21514d8981	2126	}
AnnaBridge	156:ff21514d8981	2127
AnnaBridge	156:ff21514d8981	2128
AnnaBridge	156:ff21514d8981	2129	/**
AnnaBridge	156:ff21514d8981	2130	\brief System Reset
AnnaBridge	156:ff21514d8981	2131	\details Initiates a system reset request to reset the MCU.
AnnaBridge	156:ff21514d8981	2132	*/
AnnaBridge	156:ff21514d8981	2133	__STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge	156:ff21514d8981	2134	{
AnnaBridge	156:ff21514d8981	2135	__DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge	156:ff21514d8981	2136	buffered write are completed before reset */
AnnaBridge	156:ff21514d8981	2137	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	156:ff21514d8981	2138	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
AnnaBridge	156:ff21514d8981	2139	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge	156:ff21514d8981	2140	__DSB(); /* Ensure completion of memory access */
AnnaBridge	156:ff21514d8981	2141
AnnaBridge	156:ff21514d8981	2142	for(;;) /* wait until reset */
AnnaBridge	156:ff21514d8981	2143	{
AnnaBridge	156:ff21514d8981	2144	__NOP();
AnnaBridge	156:ff21514d8981	2145	}
AnnaBridge	156:ff21514d8981	2146	}
AnnaBridge	156:ff21514d8981	2147
AnnaBridge	156:ff21514d8981	2148	/@} end of CMSIS_Core_NVICFunctions /
AnnaBridge	156:ff21514d8981	2149
Anna Bridge	160:5571c4ff569f	2150	/* ########################## MPU functions #################################### */
Anna Bridge	160:5571c4ff569f	2151
Anna Bridge	160:5571c4ff569f	2152	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge	160:5571c4ff569f	2153
Anna Bridge	160:5571c4ff569f	2154	#include "mpu_armv7.h"
Anna Bridge	160:5571c4ff569f	2155
Anna Bridge	160:5571c4ff569f	2156	#endif
AnnaBridge	156:ff21514d8981	2157
AnnaBridge	156:ff21514d8981	2158	/* ########################## FPU functions #################################### */
AnnaBridge	156:ff21514d8981	2159	/**
AnnaBridge	156:ff21514d8981	2160	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	156:ff21514d8981	2161	\defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge	156:ff21514d8981	2162	\brief Function that provides FPU type.
AnnaBridge	156:ff21514d8981	2163	@{
AnnaBridge	156:ff21514d8981	2164	*/
AnnaBridge	156:ff21514d8981	2165
AnnaBridge	156:ff21514d8981	2166	/**
AnnaBridge	156:ff21514d8981	2167	\brief get FPU type
AnnaBridge	156:ff21514d8981	2168	\details returns the FPU type
AnnaBridge	156:ff21514d8981	2169	\returns
AnnaBridge	156:ff21514d8981	2170	- \b 0: No FPU
AnnaBridge	156:ff21514d8981	2171	- \b 1: Single precision FPU
AnnaBridge	156:ff21514d8981	2172	- \b 2: Double + Single precision FPU
AnnaBridge	156:ff21514d8981	2173	*/
AnnaBridge	156:ff21514d8981	2174	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge	156:ff21514d8981	2175	{
AnnaBridge	156:ff21514d8981	2176	uint32_t mvfr0;
AnnaBridge	156:ff21514d8981	2177
AnnaBridge	156:ff21514d8981	2178	mvfr0 = SCB->MVFR0;
AnnaBridge	156:ff21514d8981	2179	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
AnnaBridge	156:ff21514d8981	2180	{
AnnaBridge	156:ff21514d8981	2181	return 2U; /* Double + Single precision FPU */
AnnaBridge	156:ff21514d8981	2182	}
AnnaBridge	156:ff21514d8981	2183	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
AnnaBridge	156:ff21514d8981	2184	{
AnnaBridge	156:ff21514d8981	2185	return 1U; /* Single precision FPU */
AnnaBridge	156:ff21514d8981	2186	}
AnnaBridge	156:ff21514d8981	2187	else
AnnaBridge	156:ff21514d8981	2188	{
AnnaBridge	156:ff21514d8981	2189	return 0U; /* No FPU */
AnnaBridge	156:ff21514d8981	2190	}
AnnaBridge	156:ff21514d8981	2191	}
AnnaBridge	156:ff21514d8981	2192
AnnaBridge	156:ff21514d8981	2193
AnnaBridge	156:ff21514d8981	2194	/@} end of CMSIS_Core_FpuFunctions /
AnnaBridge	156:ff21514d8981	2195
AnnaBridge	156:ff21514d8981	2196
AnnaBridge	156:ff21514d8981	2197
AnnaBridge	156:ff21514d8981	2198	/* ########################## Cache functions #################################### */
AnnaBridge	156:ff21514d8981	2199	/**
AnnaBridge	156:ff21514d8981	2200	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	156:ff21514d8981	2201	\defgroup CMSIS_Core_CacheFunctions Cache Functions
AnnaBridge	156:ff21514d8981	2202	\brief Functions that configure Instruction and Data cache.
AnnaBridge	156:ff21514d8981	2203	@{
AnnaBridge	156:ff21514d8981	2204	*/
AnnaBridge	156:ff21514d8981	2205
AnnaBridge	156:ff21514d8981	2206	/* Cache Size ID Register Macros */
AnnaBridge	156:ff21514d8981	2207	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
AnnaBridge	156:ff21514d8981	2208	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
AnnaBridge	156:ff21514d8981	2209
AnnaBridge	156:ff21514d8981	2210
AnnaBridge	156:ff21514d8981	2211	/**
AnnaBridge	156:ff21514d8981	2212	\brief Enable I-Cache
AnnaBridge	156:ff21514d8981	2213	\details Turns on I-Cache
AnnaBridge	156:ff21514d8981	2214	*/
AnnaBridge	156:ff21514d8981	2215	__STATIC_INLINE void SCB_EnableICache (void)
AnnaBridge	156:ff21514d8981	2216	{
AnnaBridge	156:ff21514d8981	2217	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	2218	__DSB();
AnnaBridge	156:ff21514d8981	2219	__ISB();
AnnaBridge	156:ff21514d8981	2220	SCB->ICIALLU = 0UL; /* invalidate I-Cache */
AnnaBridge	156:ff21514d8981	2221	__DSB();
AnnaBridge	156:ff21514d8981	2222	__ISB();
AnnaBridge	156:ff21514d8981	2223	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
AnnaBridge	156:ff21514d8981	2224	__DSB();
AnnaBridge	156:ff21514d8981	2225	__ISB();
AnnaBridge	156:ff21514d8981	2226	#endif
AnnaBridge	156:ff21514d8981	2227	}
AnnaBridge	156:ff21514d8981	2228
AnnaBridge	156:ff21514d8981	2229
AnnaBridge	156:ff21514d8981	2230	/**
AnnaBridge	156:ff21514d8981	2231	\brief Disable I-Cache
AnnaBridge	156:ff21514d8981	2232	\details Turns off I-Cache
AnnaBridge	156:ff21514d8981	2233	*/
AnnaBridge	156:ff21514d8981	2234	__STATIC_INLINE void SCB_DisableICache (void)
AnnaBridge	156:ff21514d8981	2235	{
AnnaBridge	156:ff21514d8981	2236	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	2237	__DSB();
AnnaBridge	156:ff21514d8981	2238	__ISB();
AnnaBridge	156:ff21514d8981	2239	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
AnnaBridge	156:ff21514d8981	2240	SCB->ICIALLU = 0UL; /* invalidate I-Cache */
AnnaBridge	156:ff21514d8981	2241	__DSB();
AnnaBridge	156:ff21514d8981	2242	__ISB();
AnnaBridge	156:ff21514d8981	2243	#endif
AnnaBridge	156:ff21514d8981	2244	}
AnnaBridge	156:ff21514d8981	2245
AnnaBridge	156:ff21514d8981	2246
AnnaBridge	156:ff21514d8981	2247	/**
AnnaBridge	156:ff21514d8981	2248	\brief Invalidate I-Cache
AnnaBridge	156:ff21514d8981	2249	\details Invalidates I-Cache
AnnaBridge	156:ff21514d8981	2250	*/
AnnaBridge	156:ff21514d8981	2251	__STATIC_INLINE void SCB_InvalidateICache (void)
AnnaBridge	156:ff21514d8981	2252	{
AnnaBridge	156:ff21514d8981	2253	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	2254	__DSB();
AnnaBridge	156:ff21514d8981	2255	__ISB();
AnnaBridge	156:ff21514d8981	2256	SCB->ICIALLU = 0UL;
AnnaBridge	156:ff21514d8981	2257	__DSB();
AnnaBridge	156:ff21514d8981	2258	__ISB();
AnnaBridge	156:ff21514d8981	2259	#endif
AnnaBridge	156:ff21514d8981	2260	}
AnnaBridge	156:ff21514d8981	2261
AnnaBridge	156:ff21514d8981	2262
AnnaBridge	156:ff21514d8981	2263	/**
AnnaBridge	156:ff21514d8981	2264	\brief Enable D-Cache
AnnaBridge	156:ff21514d8981	2265	\details Turns on D-Cache
AnnaBridge	156:ff21514d8981	2266	*/
AnnaBridge	156:ff21514d8981	2267	__STATIC_INLINE void SCB_EnableDCache (void)
AnnaBridge	156:ff21514d8981	2268	{
AnnaBridge	156:ff21514d8981	2269	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	2270	uint32_t ccsidr;
AnnaBridge	156:ff21514d8981	2271	uint32_t sets;
AnnaBridge	156:ff21514d8981	2272	uint32_t ways;
AnnaBridge	156:ff21514d8981	2273
AnnaBridge	156:ff21514d8981	2274	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	156:ff21514d8981	2275	__DSB();
AnnaBridge	156:ff21514d8981	2276
AnnaBridge	156:ff21514d8981	2277	ccsidr = SCB->CCSIDR;
AnnaBridge	156:ff21514d8981	2278
AnnaBridge	156:ff21514d8981	2279	/* invalidate D-Cache */
AnnaBridge	156:ff21514d8981	2280	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	156:ff21514d8981	2281	do {
AnnaBridge	156:ff21514d8981	2282	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	156:ff21514d8981	2283	do {
AnnaBridge	156:ff21514d8981	2284	SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) \|
AnnaBridge	156:ff21514d8981	2285	((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
AnnaBridge	156:ff21514d8981	2286	#if defined ( __CC_ARM )
AnnaBridge	156:ff21514d8981	2287	__schedule_barrier();
AnnaBridge	156:ff21514d8981	2288	#endif
AnnaBridge	156:ff21514d8981	2289	} while (ways-- != 0U);
AnnaBridge	156:ff21514d8981	2290	} while(sets-- != 0U);
AnnaBridge	156:ff21514d8981	2291	__DSB();
AnnaBridge	156:ff21514d8981	2292
AnnaBridge	156:ff21514d8981	2293	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
AnnaBridge	156:ff21514d8981	2294
AnnaBridge	156:ff21514d8981	2295	__DSB();
AnnaBridge	156:ff21514d8981	2296	__ISB();
AnnaBridge	156:ff21514d8981	2297	#endif
AnnaBridge	156:ff21514d8981	2298	}
AnnaBridge	156:ff21514d8981	2299
AnnaBridge	156:ff21514d8981	2300
AnnaBridge	156:ff21514d8981	2301	/**
AnnaBridge	156:ff21514d8981	2302	\brief Disable D-Cache
AnnaBridge	156:ff21514d8981	2303	\details Turns off D-Cache
AnnaBridge	156:ff21514d8981	2304	*/
AnnaBridge	156:ff21514d8981	2305	__STATIC_INLINE void SCB_DisableDCache (void)
AnnaBridge	156:ff21514d8981	2306	{
AnnaBridge	156:ff21514d8981	2307	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	2308	register uint32_t ccsidr;
AnnaBridge	156:ff21514d8981	2309	register uint32_t sets;
AnnaBridge	156:ff21514d8981	2310	register uint32_t ways;
AnnaBridge	156:ff21514d8981	2311
AnnaBridge	156:ff21514d8981	2312	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	156:ff21514d8981	2313	__DSB();
AnnaBridge	156:ff21514d8981	2314
AnnaBridge	156:ff21514d8981	2315	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
AnnaBridge	156:ff21514d8981	2316	__DSB();
AnnaBridge	156:ff21514d8981	2317
AnnaBridge	156:ff21514d8981	2318	ccsidr = SCB->CCSIDR;
AnnaBridge	156:ff21514d8981	2319
AnnaBridge	156:ff21514d8981	2320	/* clean & invalidate D-Cache */
AnnaBridge	156:ff21514d8981	2321	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	156:ff21514d8981	2322	do {
AnnaBridge	156:ff21514d8981	2323	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	156:ff21514d8981	2324	do {
AnnaBridge	156:ff21514d8981	2325	SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) \|
AnnaBridge	156:ff21514d8981	2326	((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
AnnaBridge	156:ff21514d8981	2327	#if defined ( __CC_ARM )
AnnaBridge	156:ff21514d8981	2328	__schedule_barrier();
AnnaBridge	156:ff21514d8981	2329	#endif
AnnaBridge	156:ff21514d8981	2330	} while (ways-- != 0U);
AnnaBridge	156:ff21514d8981	2331	} while(sets-- != 0U);
AnnaBridge	156:ff21514d8981	2332
AnnaBridge	156:ff21514d8981	2333	__DSB();
AnnaBridge	156:ff21514d8981	2334	__ISB();
AnnaBridge	156:ff21514d8981	2335	#endif
AnnaBridge	156:ff21514d8981	2336	}
AnnaBridge	156:ff21514d8981	2337
AnnaBridge	156:ff21514d8981	2338
AnnaBridge	156:ff21514d8981	2339	/**
AnnaBridge	156:ff21514d8981	2340	\brief Invalidate D-Cache
AnnaBridge	156:ff21514d8981	2341	\details Invalidates D-Cache
AnnaBridge	156:ff21514d8981	2342	*/
AnnaBridge	156:ff21514d8981	2343	__STATIC_INLINE void SCB_InvalidateDCache (void)
AnnaBridge	156:ff21514d8981	2344	{
AnnaBridge	156:ff21514d8981	2345	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	2346	uint32_t ccsidr;
AnnaBridge	156:ff21514d8981	2347	uint32_t sets;
AnnaBridge	156:ff21514d8981	2348	uint32_t ways;
AnnaBridge	156:ff21514d8981	2349
AnnaBridge	156:ff21514d8981	2350	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	156:ff21514d8981	2351	__DSB();
AnnaBridge	156:ff21514d8981	2352
AnnaBridge	156:ff21514d8981	2353	ccsidr = SCB->CCSIDR;
AnnaBridge	156:ff21514d8981	2354
AnnaBridge	156:ff21514d8981	2355	/* invalidate D-Cache */
AnnaBridge	156:ff21514d8981	2356	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	156:ff21514d8981	2357	do {
AnnaBridge	156:ff21514d8981	2358	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	156:ff21514d8981	2359	do {
AnnaBridge	156:ff21514d8981	2360	SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) \|
AnnaBridge	156:ff21514d8981	2361	((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
AnnaBridge	156:ff21514d8981	2362	#if defined ( __CC_ARM )
AnnaBridge	156:ff21514d8981	2363	__schedule_barrier();
AnnaBridge	156:ff21514d8981	2364	#endif
AnnaBridge	156:ff21514d8981	2365	} while (ways-- != 0U);
AnnaBridge	156:ff21514d8981	2366	} while(sets-- != 0U);
AnnaBridge	156:ff21514d8981	2367
AnnaBridge	156:ff21514d8981	2368	__DSB();
AnnaBridge	156:ff21514d8981	2369	__ISB();
AnnaBridge	156:ff21514d8981	2370	#endif
AnnaBridge	156:ff21514d8981	2371	}
AnnaBridge	156:ff21514d8981	2372
AnnaBridge	156:ff21514d8981	2373
AnnaBridge	156:ff21514d8981	2374	/**
AnnaBridge	156:ff21514d8981	2375	\brief Clean D-Cache
AnnaBridge	156:ff21514d8981	2376	\details Cleans D-Cache
AnnaBridge	156:ff21514d8981	2377	*/
AnnaBridge	156:ff21514d8981	2378	__STATIC_INLINE void SCB_CleanDCache (void)
AnnaBridge	156:ff21514d8981	2379	{
AnnaBridge	156:ff21514d8981	2380	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	2381	uint32_t ccsidr;
AnnaBridge	156:ff21514d8981	2382	uint32_t sets;
AnnaBridge	156:ff21514d8981	2383	uint32_t ways;
AnnaBridge	156:ff21514d8981	2384
AnnaBridge	156:ff21514d8981	2385	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	156:ff21514d8981	2386	__DSB();
AnnaBridge	156:ff21514d8981	2387
AnnaBridge	156:ff21514d8981	2388	ccsidr = SCB->CCSIDR;
AnnaBridge	156:ff21514d8981	2389
AnnaBridge	156:ff21514d8981	2390	/* clean D-Cache */
AnnaBridge	156:ff21514d8981	2391	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	156:ff21514d8981	2392	do {
AnnaBridge	156:ff21514d8981	2393	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	156:ff21514d8981	2394	do {
AnnaBridge	156:ff21514d8981	2395	SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) \|
AnnaBridge	156:ff21514d8981	2396	((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
AnnaBridge	156:ff21514d8981	2397	#if defined ( __CC_ARM )
AnnaBridge	156:ff21514d8981	2398	__schedule_barrier();
AnnaBridge	156:ff21514d8981	2399	#endif
AnnaBridge	156:ff21514d8981	2400	} while (ways-- != 0U);
AnnaBridge	156:ff21514d8981	2401	} while(sets-- != 0U);
AnnaBridge	156:ff21514d8981	2402
AnnaBridge	156:ff21514d8981	2403	__DSB();
AnnaBridge	156:ff21514d8981	2404	__ISB();
AnnaBridge	156:ff21514d8981	2405	#endif
AnnaBridge	156:ff21514d8981	2406	}
AnnaBridge	156:ff21514d8981	2407
AnnaBridge	156:ff21514d8981	2408
AnnaBridge	156:ff21514d8981	2409	/**
AnnaBridge	156:ff21514d8981	2410	\brief Clean & Invalidate D-Cache
AnnaBridge	156:ff21514d8981	2411	\details Cleans and Invalidates D-Cache
AnnaBridge	156:ff21514d8981	2412	*/
AnnaBridge	156:ff21514d8981	2413	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
AnnaBridge	156:ff21514d8981	2414	{
AnnaBridge	156:ff21514d8981	2415	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	2416	uint32_t ccsidr;
AnnaBridge	156:ff21514d8981	2417	uint32_t sets;
AnnaBridge	156:ff21514d8981	2418	uint32_t ways;
AnnaBridge	156:ff21514d8981	2419
AnnaBridge	156:ff21514d8981	2420	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
AnnaBridge	156:ff21514d8981	2421	__DSB();
AnnaBridge	156:ff21514d8981	2422
AnnaBridge	156:ff21514d8981	2423	ccsidr = SCB->CCSIDR;
AnnaBridge	156:ff21514d8981	2424
AnnaBridge	156:ff21514d8981	2425	/* clean & invalidate D-Cache */
AnnaBridge	156:ff21514d8981	2426	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
AnnaBridge	156:ff21514d8981	2427	do {
AnnaBridge	156:ff21514d8981	2428	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
AnnaBridge	156:ff21514d8981	2429	do {
AnnaBridge	156:ff21514d8981	2430	SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) \|
AnnaBridge	156:ff21514d8981	2431	((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
AnnaBridge	156:ff21514d8981	2432	#if defined ( __CC_ARM )
AnnaBridge	156:ff21514d8981	2433	__schedule_barrier();
AnnaBridge	156:ff21514d8981	2434	#endif
AnnaBridge	156:ff21514d8981	2435	} while (ways-- != 0U);
AnnaBridge	156:ff21514d8981	2436	} while(sets-- != 0U);
AnnaBridge	156:ff21514d8981	2437
AnnaBridge	156:ff21514d8981	2438	__DSB();
AnnaBridge	156:ff21514d8981	2439	__ISB();
AnnaBridge	156:ff21514d8981	2440	#endif
AnnaBridge	156:ff21514d8981	2441	}
AnnaBridge	156:ff21514d8981	2442
AnnaBridge	156:ff21514d8981	2443
AnnaBridge	156:ff21514d8981	2444	/**
AnnaBridge	156:ff21514d8981	2445	\brief D-Cache Invalidate by address
AnnaBridge	156:ff21514d8981	2446	\details Invalidates D-Cache for the given address
AnnaBridge	156:ff21514d8981	2447	\param[in] addr address (aligned to 32-byte boundary)
AnnaBridge	156:ff21514d8981	2448	\param[in] dsize size of memory block (in number of bytes)
AnnaBridge	156:ff21514d8981	2449	*/
AnnaBridge	156:ff21514d8981	2450	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
AnnaBridge	156:ff21514d8981	2451	{
AnnaBridge	156:ff21514d8981	2452	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	2453	int32_t op_size = dsize;
AnnaBridge	156:ff21514d8981	2454	uint32_t op_addr = (uint32_t)addr;
AnnaBridge	156:ff21514d8981	2455	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
AnnaBridge	156:ff21514d8981	2456
AnnaBridge	156:ff21514d8981	2457	__DSB();
AnnaBridge	156:ff21514d8981	2458
AnnaBridge	156:ff21514d8981	2459	while (op_size > 0) {
AnnaBridge	156:ff21514d8981	2460	SCB->DCIMVAC = op_addr;
AnnaBridge	156:ff21514d8981	2461	op_addr += (uint32_t)linesize;
AnnaBridge	156:ff21514d8981	2462	op_size -= linesize;
AnnaBridge	156:ff21514d8981	2463	}
AnnaBridge	156:ff21514d8981	2464
AnnaBridge	156:ff21514d8981	2465	__DSB();
AnnaBridge	156:ff21514d8981	2466	__ISB();
AnnaBridge	156:ff21514d8981	2467	#endif
AnnaBridge	156:ff21514d8981	2468	}
AnnaBridge	156:ff21514d8981	2469
AnnaBridge	156:ff21514d8981	2470
AnnaBridge	156:ff21514d8981	2471	/**
AnnaBridge	156:ff21514d8981	2472	\brief D-Cache Clean by address
AnnaBridge	156:ff21514d8981	2473	\details Cleans D-Cache for the given address
AnnaBridge	156:ff21514d8981	2474	\param[in] addr address (aligned to 32-byte boundary)
AnnaBridge	156:ff21514d8981	2475	\param[in] dsize size of memory block (in number of bytes)
AnnaBridge	156:ff21514d8981	2476	*/
AnnaBridge	156:ff21514d8981	2477	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
AnnaBridge	156:ff21514d8981	2478	{
AnnaBridge	156:ff21514d8981	2479	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	2480	int32_t op_size = dsize;
AnnaBridge	156:ff21514d8981	2481	uint32_t op_addr = (uint32_t) addr;
AnnaBridge	156:ff21514d8981	2482	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
AnnaBridge	156:ff21514d8981	2483
AnnaBridge	156:ff21514d8981	2484	__DSB();
AnnaBridge	156:ff21514d8981	2485
AnnaBridge	156:ff21514d8981	2486	while (op_size > 0) {
AnnaBridge	156:ff21514d8981	2487	SCB->DCCMVAC = op_addr;
AnnaBridge	156:ff21514d8981	2488	op_addr += (uint32_t)linesize;
AnnaBridge	156:ff21514d8981	2489	op_size -= linesize;
AnnaBridge	156:ff21514d8981	2490	}
AnnaBridge	156:ff21514d8981	2491
AnnaBridge	156:ff21514d8981	2492	__DSB();
AnnaBridge	156:ff21514d8981	2493	__ISB();
AnnaBridge	156:ff21514d8981	2494	#endif
AnnaBridge	156:ff21514d8981	2495	}
AnnaBridge	156:ff21514d8981	2496
AnnaBridge	156:ff21514d8981	2497
AnnaBridge	156:ff21514d8981	2498	/**
AnnaBridge	156:ff21514d8981	2499	\brief D-Cache Clean and Invalidate by address
AnnaBridge	156:ff21514d8981	2500	\details Cleans and invalidates D_Cache for the given address
AnnaBridge	156:ff21514d8981	2501	\param[in] addr address (aligned to 32-byte boundary)
AnnaBridge	156:ff21514d8981	2502	\param[in] dsize size of memory block (in number of bytes)
AnnaBridge	156:ff21514d8981	2503	*/
AnnaBridge	156:ff21514d8981	2504	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
AnnaBridge	156:ff21514d8981	2505	{
AnnaBridge	156:ff21514d8981	2506	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
AnnaBridge	156:ff21514d8981	2507	int32_t op_size = dsize;
AnnaBridge	156:ff21514d8981	2508	uint32_t op_addr = (uint32_t) addr;
AnnaBridge	156:ff21514d8981	2509	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
AnnaBridge	156:ff21514d8981	2510
AnnaBridge	156:ff21514d8981	2511	__DSB();
AnnaBridge	156:ff21514d8981	2512
AnnaBridge	156:ff21514d8981	2513	while (op_size > 0) {
AnnaBridge	156:ff21514d8981	2514	SCB->DCCIMVAC = op_addr;
AnnaBridge	156:ff21514d8981	2515	op_addr += (uint32_t)linesize;
AnnaBridge	156:ff21514d8981	2516	op_size -= linesize;
AnnaBridge	156:ff21514d8981	2517	}
AnnaBridge	156:ff21514d8981	2518
AnnaBridge	156:ff21514d8981	2519	__DSB();
AnnaBridge	156:ff21514d8981	2520	__ISB();
AnnaBridge	156:ff21514d8981	2521	#endif
AnnaBridge	156:ff21514d8981	2522	}
AnnaBridge	156:ff21514d8981	2523
AnnaBridge	156:ff21514d8981	2524
AnnaBridge	156:ff21514d8981	2525	/@} end of CMSIS_Core_CacheFunctions /
AnnaBridge	156:ff21514d8981	2526
AnnaBridge	156:ff21514d8981	2527
AnnaBridge	156:ff21514d8981	2528
AnnaBridge	156:ff21514d8981	2529	/* ################################## SysTick function ############################################ */
AnnaBridge	156:ff21514d8981	2530	/**
AnnaBridge	156:ff21514d8981	2531	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	156:ff21514d8981	2532	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge	156:ff21514d8981	2533	\brief Functions that configure the System.
AnnaBridge	156:ff21514d8981	2534	@{
AnnaBridge	156:ff21514d8981	2535	*/
AnnaBridge	156:ff21514d8981	2536
AnnaBridge	156:ff21514d8981	2537	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge	156:ff21514d8981	2538
AnnaBridge	156:ff21514d8981	2539	/**
AnnaBridge	156:ff21514d8981	2540	\brief System Tick Configuration
AnnaBridge	156:ff21514d8981	2541	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge	156:ff21514d8981	2542	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	156:ff21514d8981	2543	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	156:ff21514d8981	2544	\return 0 Function succeeded.
AnnaBridge	156:ff21514d8981	2545	\return 1 Function failed.
AnnaBridge	156:ff21514d8981	2546	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	156:ff21514d8981	2547	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	156:ff21514d8981	2548	must contain a vendor-specific implementation of this function.
AnnaBridge	156:ff21514d8981	2549	*/
AnnaBridge	156:ff21514d8981	2550	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge	156:ff21514d8981	2551	{
AnnaBridge	156:ff21514d8981	2552	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	156:ff21514d8981	2553	{
AnnaBridge	156:ff21514d8981	2554	return (1UL); /* Reload value impossible */
AnnaBridge	156:ff21514d8981	2555	}
AnnaBridge	156:ff21514d8981	2556
AnnaBridge	156:ff21514d8981	2557	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	156:ff21514d8981	2558	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	156:ff21514d8981	2559	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	156:ff21514d8981	2560	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	156:ff21514d8981	2561	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	156:ff21514d8981	2562	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	156:ff21514d8981	2563	return (0UL); /* Function successful */
AnnaBridge	156:ff21514d8981	2564	}
AnnaBridge	156:ff21514d8981	2565
AnnaBridge	156:ff21514d8981	2566	#endif
AnnaBridge	156:ff21514d8981	2567
AnnaBridge	156:ff21514d8981	2568	/@} end of CMSIS_Core_SysTickFunctions /
AnnaBridge	156:ff21514d8981	2569
AnnaBridge	156:ff21514d8981	2570
AnnaBridge	156:ff21514d8981	2571
AnnaBridge	156:ff21514d8981	2572	/* ##################################### Debug In/Output function ########################################### */
AnnaBridge	156:ff21514d8981	2573	/**
AnnaBridge	156:ff21514d8981	2574	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	156:ff21514d8981	2575	\defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge	156:ff21514d8981	2576	\brief Functions that access the ITM debug interface.
AnnaBridge	156:ff21514d8981	2577	@{
AnnaBridge	156:ff21514d8981	2578	*/
AnnaBridge	156:ff21514d8981	2579
AnnaBridge	156:ff21514d8981	2580	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
AnnaBridge	156:ff21514d8981	2581	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
AnnaBridge	156:ff21514d8981	2582
AnnaBridge	156:ff21514d8981	2583
AnnaBridge	156:ff21514d8981	2584	/**
AnnaBridge	156:ff21514d8981	2585	\brief ITM Send Character
AnnaBridge	156:ff21514d8981	2586	\details Transmits a character via the ITM channel 0, and
AnnaBridge	156:ff21514d8981	2587	\li Just returns when no debugger is connected that has booked the output.
AnnaBridge	156:ff21514d8981	2588	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge	156:ff21514d8981	2589	\param [in] ch Character to transmit.
AnnaBridge	156:ff21514d8981	2590	\returns Character to transmit.
AnnaBridge	156:ff21514d8981	2591	*/
AnnaBridge	156:ff21514d8981	2592	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge	156:ff21514d8981	2593	{
AnnaBridge	156:ff21514d8981	2594	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge	156:ff21514d8981	2595	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge	156:ff21514d8981	2596	{
AnnaBridge	156:ff21514d8981	2597	while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge	156:ff21514d8981	2598	{
AnnaBridge	156:ff21514d8981	2599	__NOP();
AnnaBridge	156:ff21514d8981	2600	}
AnnaBridge	156:ff21514d8981	2601	ITM->PORT[0U].u8 = (uint8_t)ch;
AnnaBridge	156:ff21514d8981	2602	}
AnnaBridge	156:ff21514d8981	2603	return (ch);
AnnaBridge	156:ff21514d8981	2604	}
AnnaBridge	156:ff21514d8981	2605
AnnaBridge	156:ff21514d8981	2606
AnnaBridge	156:ff21514d8981	2607	/**
AnnaBridge	156:ff21514d8981	2608	\brief ITM Receive Character
AnnaBridge	156:ff21514d8981	2609	\details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge	156:ff21514d8981	2610	\return Received character.
AnnaBridge	156:ff21514d8981	2611	\return -1 No character pending.
AnnaBridge	156:ff21514d8981	2612	*/
AnnaBridge	156:ff21514d8981	2613	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge	156:ff21514d8981	2614	{
AnnaBridge	156:ff21514d8981	2615	int32_t ch = -1; /* no character available */
AnnaBridge	156:ff21514d8981	2616
AnnaBridge	156:ff21514d8981	2617	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge	156:ff21514d8981	2618	{
AnnaBridge	156:ff21514d8981	2619	ch = ITM_RxBuffer;
AnnaBridge	156:ff21514d8981	2620	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge	156:ff21514d8981	2621	}
AnnaBridge	156:ff21514d8981	2622
AnnaBridge	156:ff21514d8981	2623	return (ch);
AnnaBridge	156:ff21514d8981	2624	}
AnnaBridge	156:ff21514d8981	2625
AnnaBridge	156:ff21514d8981	2626
AnnaBridge	156:ff21514d8981	2627	/**
AnnaBridge	156:ff21514d8981	2628	\brief ITM Check Character
AnnaBridge	156:ff21514d8981	2629	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge	156:ff21514d8981	2630	\return 0 No character available.
AnnaBridge	156:ff21514d8981	2631	\return 1 Character available.
AnnaBridge	156:ff21514d8981	2632	*/
AnnaBridge	156:ff21514d8981	2633	__STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge	156:ff21514d8981	2634	{
AnnaBridge	156:ff21514d8981	2635
AnnaBridge	156:ff21514d8981	2636	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge	156:ff21514d8981	2637	{
AnnaBridge	156:ff21514d8981	2638	return (0); /* no character available */
AnnaBridge	156:ff21514d8981	2639	}
AnnaBridge	156:ff21514d8981	2640	else
AnnaBridge	156:ff21514d8981	2641	{
AnnaBridge	156:ff21514d8981	2642	return (1); /* character available */
AnnaBridge	156:ff21514d8981	2643	}
AnnaBridge	156:ff21514d8981	2644	}
AnnaBridge	156:ff21514d8981	2645
AnnaBridge	156:ff21514d8981	2646	/@} end of CMSIS_core_DebugFunctions /
AnnaBridge	156:ff21514d8981	2647
AnnaBridge	156:ff21514d8981	2648
AnnaBridge	156:ff21514d8981	2649
AnnaBridge	156:ff21514d8981	2650
AnnaBridge	156:ff21514d8981	2651	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	2652	}
AnnaBridge	156:ff21514d8981	2653	#endif
AnnaBridge	156:ff21514d8981	2654
AnnaBridge	156:ff21514d8981	2655	#endif /* __CORE_CM7_H_DEPENDANT */
AnnaBridge	156:ff21514d8981	2656
AnnaBridge	156:ff21514d8981	2657	#endif /* __CMSIS_GENERIC */