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TARGET_NUCLEO_F401RE/cmsis_gcc.h@160:5571c4ff569f, 2018-01-17 (annotated)

Committer:: Anna Bridge
Date:: Wed Jan 17 16:13:02 2018 +0000
Revision:: 160:5571c4ff569f
Parent:: 145:64910690c574
Child:: 169:a7c7b631e539

mbed library. Release version 158

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	145:64910690c574	1	/************************************************************************//
AnnaBridge	145:64910690c574	2	* @file cmsis_gcc.h
AnnaBridge	145:64910690c574	3	* @brief CMSIS compiler GCC header file
AnnaBridge	145:64910690c574	4	* @version V5.0.2
AnnaBridge	145:64910690c574	5	* @date 13. February 2017
AnnaBridge	145:64910690c574	6	******************************************************************************/
AnnaBridge	145:64910690c574	7	/*
AnnaBridge	145:64910690c574	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	145:64910690c574	9	*
AnnaBridge	145:64910690c574	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	145:64910690c574	11	*
AnnaBridge	145:64910690c574	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	145:64910690c574	13	* not use this file except in compliance with the License.
AnnaBridge	145:64910690c574	14	* You may obtain a copy of the License at
AnnaBridge	145:64910690c574	15	*
AnnaBridge	145:64910690c574	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	145:64910690c574	17	*
AnnaBridge	145:64910690c574	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	145:64910690c574	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	145:64910690c574	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	145:64910690c574	21	* See the License for the specific language governing permissions and
AnnaBridge	145:64910690c574	22	* limitations under the License.
AnnaBridge	145:64910690c574	23	*/
AnnaBridge	145:64910690c574	24
AnnaBridge	145:64910690c574	25	#ifndef __CMSIS_GCC_H
AnnaBridge	145:64910690c574	26	#define __CMSIS_GCC_H
AnnaBridge	145:64910690c574	27
AnnaBridge	145:64910690c574	28	/* ignore some GCC warnings */
AnnaBridge	145:64910690c574	29	#pragma GCC diagnostic push
AnnaBridge	145:64910690c574	30	#pragma GCC diagnostic ignored "-Wsign-conversion"
AnnaBridge	145:64910690c574	31	#pragma GCC diagnostic ignored "-Wconversion"
AnnaBridge	145:64910690c574	32	#pragma GCC diagnostic ignored "-Wunused-parameter"
AnnaBridge	145:64910690c574	33
Anna Bridge	160:5571c4ff569f	34	/* Fallback for __has_builtin */
Anna Bridge	160:5571c4ff569f	35	#ifndef __has_builtin
Anna Bridge	160:5571c4ff569f	36	#define __has_builtin(x) (0)
Anna Bridge	160:5571c4ff569f	37	#endif
Anna Bridge	160:5571c4ff569f	38
AnnaBridge	145:64910690c574	39	/* CMSIS compiler specific defines */
AnnaBridge	145:64910690c574	40	#ifndef __ASM
AnnaBridge	145:64910690c574	41	#define __ASM __asm
AnnaBridge	145:64910690c574	42	#endif
AnnaBridge	145:64910690c574	43	#ifndef __INLINE
AnnaBridge	145:64910690c574	44	#define __INLINE inline
AnnaBridge	145:64910690c574	45	#endif
AnnaBridge	145:64910690c574	46	#ifndef __STATIC_INLINE
AnnaBridge	145:64910690c574	47	#define __STATIC_INLINE static inline
AnnaBridge	145:64910690c574	48	#endif
AnnaBridge	145:64910690c574	49	#ifndef __NO_RETURN
AnnaBridge	145:64910690c574	50	#define __NO_RETURN __attribute__((noreturn))
AnnaBridge	145:64910690c574	51	#endif
AnnaBridge	145:64910690c574	52	#ifndef __USED
AnnaBridge	145:64910690c574	53	#define __USED __attribute__((used))
AnnaBridge	145:64910690c574	54	#endif
AnnaBridge	145:64910690c574	55	#ifndef __WEAK
AnnaBridge	145:64910690c574	56	#define __WEAK __attribute__((weak))
AnnaBridge	145:64910690c574	57	#endif
AnnaBridge	145:64910690c574	58	#ifndef __PACKED
AnnaBridge	145:64910690c574	59	#define __PACKED __attribute__((packed, aligned(1)))
AnnaBridge	145:64910690c574	60	#endif
AnnaBridge	145:64910690c574	61	#ifndef __PACKED_STRUCT
AnnaBridge	145:64910690c574	62	#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
AnnaBridge	145:64910690c574	63	#endif
Anna Bridge	160:5571c4ff569f	64	#ifndef __PACKED_UNION
Anna Bridge	160:5571c4ff569f	65	#define __PACKED_UNION union __attribute__((packed, aligned(1)))
Anna Bridge	160:5571c4ff569f	66	#endif
AnnaBridge	145:64910690c574	67	#ifndef __UNALIGNED_UINT32 /* deprecated */
AnnaBridge	145:64910690c574	68	#pragma GCC diagnostic push
AnnaBridge	145:64910690c574	69	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	145:64910690c574	70	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	145:64910690c574	71	struct __attribute__((packed)) T_UINT32 { uint32_t v; };
AnnaBridge	145:64910690c574	72	#pragma GCC diagnostic pop
AnnaBridge	145:64910690c574	73	#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
AnnaBridge	145:64910690c574	74	#endif
AnnaBridge	145:64910690c574	75	#ifndef __UNALIGNED_UINT16_WRITE
AnnaBridge	145:64910690c574	76	#pragma GCC diagnostic push
AnnaBridge	145:64910690c574	77	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	145:64910690c574	78	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	145:64910690c574	79	__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
AnnaBridge	145:64910690c574	80	#pragma GCC diagnostic pop
AnnaBridge	145:64910690c574	81	#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE )(void )(addr))->v) = (val))
AnnaBridge	145:64910690c574	82	#endif
AnnaBridge	145:64910690c574	83	#ifndef __UNALIGNED_UINT16_READ
AnnaBridge	145:64910690c574	84	#pragma GCC diagnostic push
AnnaBridge	145:64910690c574	85	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	145:64910690c574	86	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	145:64910690c574	87	__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
AnnaBridge	145:64910690c574	88	#pragma GCC diagnostic pop
AnnaBridge	145:64910690c574	89	#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ )(const void )(addr))->v)
AnnaBridge	145:64910690c574	90	#endif
AnnaBridge	145:64910690c574	91	#ifndef __UNALIGNED_UINT32_WRITE
AnnaBridge	145:64910690c574	92	#pragma GCC diagnostic push
AnnaBridge	145:64910690c574	93	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	145:64910690c574	94	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	145:64910690c574	95	__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
AnnaBridge	145:64910690c574	96	#pragma GCC diagnostic pop
AnnaBridge	145:64910690c574	97	#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE )(void )(addr))->v) = (val))
AnnaBridge	145:64910690c574	98	#endif
AnnaBridge	145:64910690c574	99	#ifndef __UNALIGNED_UINT32_READ
AnnaBridge	145:64910690c574	100	#pragma GCC diagnostic push
AnnaBridge	145:64910690c574	101	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	145:64910690c574	102	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	145:64910690c574	103	__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
AnnaBridge	145:64910690c574	104	#pragma GCC diagnostic pop
AnnaBridge	145:64910690c574	105	#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ )(const void )(addr))->v)
AnnaBridge	145:64910690c574	106	#endif
AnnaBridge	145:64910690c574	107	#ifndef __ALIGNED
AnnaBridge	145:64910690c574	108	#define __ALIGNED(x) __attribute__((aligned(x)))
AnnaBridge	145:64910690c574	109	#endif
Anna Bridge	160:5571c4ff569f	110	#ifndef __RESTRICT
Anna Bridge	160:5571c4ff569f	111	#define __RESTRICT __restrict
Anna Bridge	160:5571c4ff569f	112	#endif
AnnaBridge	145:64910690c574	113
AnnaBridge	145:64910690c574	114
AnnaBridge	145:64910690c574	115	/* ########################### Core Function Access ########################### */
AnnaBridge	145:64910690c574	116	/** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge	145:64910690c574	117	\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
AnnaBridge	145:64910690c574	118	@{
AnnaBridge	145:64910690c574	119	*/
AnnaBridge	145:64910690c574	120
AnnaBridge	145:64910690c574	121	/**
AnnaBridge	145:64910690c574	122	\brief Enable IRQ Interrupts
AnnaBridge	145:64910690c574	123	\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
AnnaBridge	145:64910690c574	124	Can only be executed in Privileged modes.
AnnaBridge	145:64910690c574	125	*/
AnnaBridge	145:64910690c574	126	__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
AnnaBridge	145:64910690c574	127	{
AnnaBridge	145:64910690c574	128	__ASM volatile ("cpsie i" : : : "memory");
AnnaBridge	145:64910690c574	129	}
AnnaBridge	145:64910690c574	130
AnnaBridge	145:64910690c574	131
AnnaBridge	145:64910690c574	132	/**
AnnaBridge	145:64910690c574	133	\brief Disable IRQ Interrupts
AnnaBridge	145:64910690c574	134	\details Disables IRQ interrupts by setting the I-bit in the CPSR.
AnnaBridge	145:64910690c574	135	Can only be executed in Privileged modes.
AnnaBridge	145:64910690c574	136	*/
AnnaBridge	145:64910690c574	137	__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
AnnaBridge	145:64910690c574	138	{
AnnaBridge	145:64910690c574	139	__ASM volatile ("cpsid i" : : : "memory");
AnnaBridge	145:64910690c574	140	}
AnnaBridge	145:64910690c574	141
AnnaBridge	145:64910690c574	142
AnnaBridge	145:64910690c574	143	/**
AnnaBridge	145:64910690c574	144	\brief Get Control Register
AnnaBridge	145:64910690c574	145	\details Returns the content of the Control Register.
AnnaBridge	145:64910690c574	146	\return Control Register value
AnnaBridge	145:64910690c574	147	*/
AnnaBridge	145:64910690c574	148	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
AnnaBridge	145:64910690c574	149	{
AnnaBridge	145:64910690c574	150	uint32_t result;
AnnaBridge	145:64910690c574	151
AnnaBridge	145:64910690c574	152	__ASM volatile ("MRS %0, control" : "=r" (result) );
AnnaBridge	145:64910690c574	153	return(result);
AnnaBridge	145:64910690c574	154	}
AnnaBridge	145:64910690c574	155
AnnaBridge	145:64910690c574	156
AnnaBridge	145:64910690c574	157	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	158	/**
AnnaBridge	145:64910690c574	159	\brief Get Control Register (non-secure)
AnnaBridge	145:64910690c574	160	\details Returns the content of the non-secure Control Register when in secure mode.
AnnaBridge	145:64910690c574	161	\return non-secure Control Register value
AnnaBridge	145:64910690c574	162	*/
AnnaBridge	145:64910690c574	163	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
AnnaBridge	145:64910690c574	164	{
AnnaBridge	145:64910690c574	165	uint32_t result;
AnnaBridge	145:64910690c574	166
AnnaBridge	145:64910690c574	167	__ASM volatile ("MRS %0, control_ns" : "=r" (result) );
AnnaBridge	145:64910690c574	168	return(result);
AnnaBridge	145:64910690c574	169	}
AnnaBridge	145:64910690c574	170	#endif
AnnaBridge	145:64910690c574	171
AnnaBridge	145:64910690c574	172
AnnaBridge	145:64910690c574	173	/**
AnnaBridge	145:64910690c574	174	\brief Set Control Register
AnnaBridge	145:64910690c574	175	\details Writes the given value to the Control Register.
AnnaBridge	145:64910690c574	176	\param [in] control Control Register value to set
AnnaBridge	145:64910690c574	177	*/
AnnaBridge	145:64910690c574	178	__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
AnnaBridge	145:64910690c574	179	{
AnnaBridge	145:64910690c574	180	__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
AnnaBridge	145:64910690c574	181	}
AnnaBridge	145:64910690c574	182
AnnaBridge	145:64910690c574	183
AnnaBridge	145:64910690c574	184	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	185	/**
AnnaBridge	145:64910690c574	186	\brief Set Control Register (non-secure)
AnnaBridge	145:64910690c574	187	\details Writes the given value to the non-secure Control Register when in secure state.
AnnaBridge	145:64910690c574	188	\param [in] control Control Register value to set
AnnaBridge	145:64910690c574	189	*/
AnnaBridge	145:64910690c574	190	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
AnnaBridge	145:64910690c574	191	{
AnnaBridge	145:64910690c574	192	__ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
AnnaBridge	145:64910690c574	193	}
AnnaBridge	145:64910690c574	194	#endif
AnnaBridge	145:64910690c574	195
AnnaBridge	145:64910690c574	196
AnnaBridge	145:64910690c574	197	/**
AnnaBridge	145:64910690c574	198	\brief Get IPSR Register
AnnaBridge	145:64910690c574	199	\details Returns the content of the IPSR Register.
AnnaBridge	145:64910690c574	200	\return IPSR Register value
AnnaBridge	145:64910690c574	201	*/
AnnaBridge	145:64910690c574	202	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
AnnaBridge	145:64910690c574	203	{
AnnaBridge	145:64910690c574	204	uint32_t result;
AnnaBridge	145:64910690c574	205
AnnaBridge	145:64910690c574	206	__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
AnnaBridge	145:64910690c574	207	return(result);
AnnaBridge	145:64910690c574	208	}
AnnaBridge	145:64910690c574	209
AnnaBridge	145:64910690c574	210
AnnaBridge	145:64910690c574	211	/**
AnnaBridge	145:64910690c574	212	\brief Get APSR Register
AnnaBridge	145:64910690c574	213	\details Returns the content of the APSR Register.
AnnaBridge	145:64910690c574	214	\return APSR Register value
AnnaBridge	145:64910690c574	215	*/
AnnaBridge	145:64910690c574	216	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
AnnaBridge	145:64910690c574	217	{
AnnaBridge	145:64910690c574	218	uint32_t result;
AnnaBridge	145:64910690c574	219
AnnaBridge	145:64910690c574	220	__ASM volatile ("MRS %0, apsr" : "=r" (result) );
AnnaBridge	145:64910690c574	221	return(result);
AnnaBridge	145:64910690c574	222	}
AnnaBridge	145:64910690c574	223
AnnaBridge	145:64910690c574	224
AnnaBridge	145:64910690c574	225	/**
AnnaBridge	145:64910690c574	226	\brief Get xPSR Register
AnnaBridge	145:64910690c574	227	\details Returns the content of the xPSR Register.
AnnaBridge	145:64910690c574	228	\return xPSR Register value
AnnaBridge	145:64910690c574	229	*/
AnnaBridge	145:64910690c574	230	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
AnnaBridge	145:64910690c574	231	{
AnnaBridge	145:64910690c574	232	uint32_t result;
AnnaBridge	145:64910690c574	233
AnnaBridge	145:64910690c574	234	__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
AnnaBridge	145:64910690c574	235	return(result);
AnnaBridge	145:64910690c574	236	}
AnnaBridge	145:64910690c574	237
AnnaBridge	145:64910690c574	238
AnnaBridge	145:64910690c574	239	/**
AnnaBridge	145:64910690c574	240	\brief Get Process Stack Pointer
AnnaBridge	145:64910690c574	241	\details Returns the current value of the Process Stack Pointer (PSP).
AnnaBridge	145:64910690c574	242	\return PSP Register value
AnnaBridge	145:64910690c574	243	*/
AnnaBridge	145:64910690c574	244	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
AnnaBridge	145:64910690c574	245	{
AnnaBridge	145:64910690c574	246	register uint32_t result;
AnnaBridge	145:64910690c574	247
AnnaBridge	145:64910690c574	248	__ASM volatile ("MRS %0, psp" : "=r" (result) );
AnnaBridge	145:64910690c574	249	return(result);
AnnaBridge	145:64910690c574	250	}
AnnaBridge	145:64910690c574	251
AnnaBridge	145:64910690c574	252
AnnaBridge	145:64910690c574	253	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	254	/**
AnnaBridge	145:64910690c574	255	\brief Get Process Stack Pointer (non-secure)
AnnaBridge	145:64910690c574	256	\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge	145:64910690c574	257	\return PSP Register value
AnnaBridge	145:64910690c574	258	*/
AnnaBridge	145:64910690c574	259	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
AnnaBridge	145:64910690c574	260	{
AnnaBridge	145:64910690c574	261	register uint32_t result;
AnnaBridge	145:64910690c574	262
AnnaBridge	145:64910690c574	263	__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
AnnaBridge	145:64910690c574	264	return(result);
AnnaBridge	145:64910690c574	265	}
AnnaBridge	145:64910690c574	266	#endif
AnnaBridge	145:64910690c574	267
AnnaBridge	145:64910690c574	268
AnnaBridge	145:64910690c574	269	/**
AnnaBridge	145:64910690c574	270	\brief Set Process Stack Pointer
AnnaBridge	145:64910690c574	271	\details Assigns the given value to the Process Stack Pointer (PSP).
AnnaBridge	145:64910690c574	272	\param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge	145:64910690c574	273	*/
AnnaBridge	145:64910690c574	274	__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
AnnaBridge	145:64910690c574	275	{
AnnaBridge	145:64910690c574	276	__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
AnnaBridge	145:64910690c574	277	}
AnnaBridge	145:64910690c574	278
AnnaBridge	145:64910690c574	279
AnnaBridge	145:64910690c574	280	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	281	/**
AnnaBridge	145:64910690c574	282	\brief Set Process Stack Pointer (non-secure)
AnnaBridge	145:64910690c574	283	\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge	145:64910690c574	284	\param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge	145:64910690c574	285	*/
AnnaBridge	145:64910690c574	286	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
AnnaBridge	145:64910690c574	287	{
AnnaBridge	145:64910690c574	288	__ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
AnnaBridge	145:64910690c574	289	}
AnnaBridge	145:64910690c574	290	#endif
AnnaBridge	145:64910690c574	291
AnnaBridge	145:64910690c574	292
AnnaBridge	145:64910690c574	293	/**
AnnaBridge	145:64910690c574	294	\brief Get Main Stack Pointer
AnnaBridge	145:64910690c574	295	\details Returns the current value of the Main Stack Pointer (MSP).
AnnaBridge	145:64910690c574	296	\return MSP Register value
AnnaBridge	145:64910690c574	297	*/
AnnaBridge	145:64910690c574	298	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
AnnaBridge	145:64910690c574	299	{
AnnaBridge	145:64910690c574	300	register uint32_t result;
AnnaBridge	145:64910690c574	301
AnnaBridge	145:64910690c574	302	__ASM volatile ("MRS %0, msp" : "=r" (result) );
AnnaBridge	145:64910690c574	303	return(result);
AnnaBridge	145:64910690c574	304	}
AnnaBridge	145:64910690c574	305
AnnaBridge	145:64910690c574	306
AnnaBridge	145:64910690c574	307	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	308	/**
AnnaBridge	145:64910690c574	309	\brief Get Main Stack Pointer (non-secure)
AnnaBridge	145:64910690c574	310	\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge	145:64910690c574	311	\return MSP Register value
AnnaBridge	145:64910690c574	312	*/
AnnaBridge	145:64910690c574	313	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
AnnaBridge	145:64910690c574	314	{
AnnaBridge	145:64910690c574	315	register uint32_t result;
AnnaBridge	145:64910690c574	316
AnnaBridge	145:64910690c574	317	__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
AnnaBridge	145:64910690c574	318	return(result);
AnnaBridge	145:64910690c574	319	}
AnnaBridge	145:64910690c574	320	#endif
AnnaBridge	145:64910690c574	321
AnnaBridge	145:64910690c574	322
AnnaBridge	145:64910690c574	323	/**
AnnaBridge	145:64910690c574	324	\brief Set Main Stack Pointer
AnnaBridge	145:64910690c574	325	\details Assigns the given value to the Main Stack Pointer (MSP).
AnnaBridge	145:64910690c574	326	\param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge	145:64910690c574	327	*/
AnnaBridge	145:64910690c574	328	__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
AnnaBridge	145:64910690c574	329	{
AnnaBridge	145:64910690c574	330	__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
AnnaBridge	145:64910690c574	331	}
AnnaBridge	145:64910690c574	332
AnnaBridge	145:64910690c574	333
AnnaBridge	145:64910690c574	334	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	335	/**
AnnaBridge	145:64910690c574	336	\brief Set Main Stack Pointer (non-secure)
AnnaBridge	145:64910690c574	337	\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge	145:64910690c574	338	\param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge	145:64910690c574	339	*/
AnnaBridge	145:64910690c574	340	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
AnnaBridge	145:64910690c574	341	{
AnnaBridge	145:64910690c574	342	__ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
AnnaBridge	145:64910690c574	343	}
AnnaBridge	145:64910690c574	344	#endif
AnnaBridge	145:64910690c574	345
AnnaBridge	145:64910690c574	346
AnnaBridge	145:64910690c574	347	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	348	/**
AnnaBridge	145:64910690c574	349	\brief Get Stack Pointer (non-secure)
AnnaBridge	145:64910690c574	350	\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge	145:64910690c574	351	\return SP Register value
AnnaBridge	145:64910690c574	352	*/
AnnaBridge	145:64910690c574	353	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
AnnaBridge	145:64910690c574	354	{
AnnaBridge	145:64910690c574	355	register uint32_t result;
AnnaBridge	145:64910690c574	356
AnnaBridge	145:64910690c574	357	__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
AnnaBridge	145:64910690c574	358	return(result);
AnnaBridge	145:64910690c574	359	}
AnnaBridge	145:64910690c574	360
AnnaBridge	145:64910690c574	361
AnnaBridge	145:64910690c574	362	/**
AnnaBridge	145:64910690c574	363	\brief Set Stack Pointer (non-secure)
AnnaBridge	145:64910690c574	364	\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge	145:64910690c574	365	\param [in] topOfStack Stack Pointer value to set
AnnaBridge	145:64910690c574	366	*/
AnnaBridge	145:64910690c574	367	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
AnnaBridge	145:64910690c574	368	{
AnnaBridge	145:64910690c574	369	__ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
AnnaBridge	145:64910690c574	370	}
AnnaBridge	145:64910690c574	371	#endif
AnnaBridge	145:64910690c574	372
AnnaBridge	145:64910690c574	373
AnnaBridge	145:64910690c574	374	/**
AnnaBridge	145:64910690c574	375	\brief Get Priority Mask
AnnaBridge	145:64910690c574	376	\details Returns the current state of the priority mask bit from the Priority Mask Register.
AnnaBridge	145:64910690c574	377	\return Priority Mask value
AnnaBridge	145:64910690c574	378	*/
AnnaBridge	145:64910690c574	379	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
AnnaBridge	145:64910690c574	380	{
AnnaBridge	145:64910690c574	381	uint32_t result;
AnnaBridge	145:64910690c574	382
AnnaBridge	145:64910690c574	383	__ASM volatile ("MRS %0, primask" : "=r" (result) );
AnnaBridge	145:64910690c574	384	return(result);
AnnaBridge	145:64910690c574	385	}
AnnaBridge	145:64910690c574	386
AnnaBridge	145:64910690c574	387
AnnaBridge	145:64910690c574	388	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	389	/**
AnnaBridge	145:64910690c574	390	\brief Get Priority Mask (non-secure)
AnnaBridge	145:64910690c574	391	\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
AnnaBridge	145:64910690c574	392	\return Priority Mask value
AnnaBridge	145:64910690c574	393	*/
AnnaBridge	145:64910690c574	394	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
AnnaBridge	145:64910690c574	395	{
AnnaBridge	145:64910690c574	396	uint32_t result;
AnnaBridge	145:64910690c574	397
AnnaBridge	145:64910690c574	398	__ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
AnnaBridge	145:64910690c574	399	return(result);
AnnaBridge	145:64910690c574	400	}
AnnaBridge	145:64910690c574	401	#endif
AnnaBridge	145:64910690c574	402
AnnaBridge	145:64910690c574	403
AnnaBridge	145:64910690c574	404	/**
AnnaBridge	145:64910690c574	405	\brief Set Priority Mask
AnnaBridge	145:64910690c574	406	\details Assigns the given value to the Priority Mask Register.
AnnaBridge	145:64910690c574	407	\param [in] priMask Priority Mask
AnnaBridge	145:64910690c574	408	*/
AnnaBridge	145:64910690c574	409	__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
AnnaBridge	145:64910690c574	410	{
AnnaBridge	145:64910690c574	411	__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
AnnaBridge	145:64910690c574	412	}
AnnaBridge	145:64910690c574	413
AnnaBridge	145:64910690c574	414
AnnaBridge	145:64910690c574	415	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	416	/**
AnnaBridge	145:64910690c574	417	\brief Set Priority Mask (non-secure)
AnnaBridge	145:64910690c574	418	\details Assigns the given value to the non-secure Priority Mask Register when in secure state.
AnnaBridge	145:64910690c574	419	\param [in] priMask Priority Mask
AnnaBridge	145:64910690c574	420	*/
AnnaBridge	145:64910690c574	421	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
AnnaBridge	145:64910690c574	422	{
AnnaBridge	145:64910690c574	423	__ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
AnnaBridge	145:64910690c574	424	}
AnnaBridge	145:64910690c574	425	#endif
AnnaBridge	145:64910690c574	426
AnnaBridge	145:64910690c574	427
AnnaBridge	145:64910690c574	428	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	145:64910690c574	429	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	145:64910690c574	430	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	145:64910690c574	431	/**
AnnaBridge	145:64910690c574	432	\brief Enable FIQ
AnnaBridge	145:64910690c574	433	\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge	145:64910690c574	434	Can only be executed in Privileged modes.
AnnaBridge	145:64910690c574	435	*/
AnnaBridge	145:64910690c574	436	__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
AnnaBridge	145:64910690c574	437	{
AnnaBridge	145:64910690c574	438	__ASM volatile ("cpsie f" : : : "memory");
AnnaBridge	145:64910690c574	439	}
AnnaBridge	145:64910690c574	440
AnnaBridge	145:64910690c574	441
AnnaBridge	145:64910690c574	442	/**
AnnaBridge	145:64910690c574	443	\brief Disable FIQ
AnnaBridge	145:64910690c574	444	\details Disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge	145:64910690c574	445	Can only be executed in Privileged modes.
AnnaBridge	145:64910690c574	446	*/
AnnaBridge	145:64910690c574	447	__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
AnnaBridge	145:64910690c574	448	{
AnnaBridge	145:64910690c574	449	__ASM volatile ("cpsid f" : : : "memory");
AnnaBridge	145:64910690c574	450	}
AnnaBridge	145:64910690c574	451
AnnaBridge	145:64910690c574	452
AnnaBridge	145:64910690c574	453	/**
AnnaBridge	145:64910690c574	454	\brief Get Base Priority
AnnaBridge	145:64910690c574	455	\details Returns the current value of the Base Priority register.
AnnaBridge	145:64910690c574	456	\return Base Priority register value
AnnaBridge	145:64910690c574	457	*/
AnnaBridge	145:64910690c574	458	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
AnnaBridge	145:64910690c574	459	{
AnnaBridge	145:64910690c574	460	uint32_t result;
AnnaBridge	145:64910690c574	461
AnnaBridge	145:64910690c574	462	__ASM volatile ("MRS %0, basepri" : "=r" (result) );
AnnaBridge	145:64910690c574	463	return(result);
AnnaBridge	145:64910690c574	464	}
AnnaBridge	145:64910690c574	465
AnnaBridge	145:64910690c574	466
AnnaBridge	145:64910690c574	467	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	468	/**
AnnaBridge	145:64910690c574	469	\brief Get Base Priority (non-secure)
AnnaBridge	145:64910690c574	470	\details Returns the current value of the non-secure Base Priority register when in secure state.
AnnaBridge	145:64910690c574	471	\return Base Priority register value
AnnaBridge	145:64910690c574	472	*/
AnnaBridge	145:64910690c574	473	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
AnnaBridge	145:64910690c574	474	{
AnnaBridge	145:64910690c574	475	uint32_t result;
AnnaBridge	145:64910690c574	476
AnnaBridge	145:64910690c574	477	__ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
AnnaBridge	145:64910690c574	478	return(result);
AnnaBridge	145:64910690c574	479	}
AnnaBridge	145:64910690c574	480	#endif
AnnaBridge	145:64910690c574	481
AnnaBridge	145:64910690c574	482
AnnaBridge	145:64910690c574	483	/**
AnnaBridge	145:64910690c574	484	\brief Set Base Priority
AnnaBridge	145:64910690c574	485	\details Assigns the given value to the Base Priority register.
AnnaBridge	145:64910690c574	486	\param [in] basePri Base Priority value to set
AnnaBridge	145:64910690c574	487	*/
AnnaBridge	145:64910690c574	488	__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
AnnaBridge	145:64910690c574	489	{
AnnaBridge	145:64910690c574	490	__ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
AnnaBridge	145:64910690c574	491	}
AnnaBridge	145:64910690c574	492
AnnaBridge	145:64910690c574	493
AnnaBridge	145:64910690c574	494	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	495	/**
AnnaBridge	145:64910690c574	496	\brief Set Base Priority (non-secure)
AnnaBridge	145:64910690c574	497	\details Assigns the given value to the non-secure Base Priority register when in secure state.
AnnaBridge	145:64910690c574	498	\param [in] basePri Base Priority value to set
AnnaBridge	145:64910690c574	499	*/
AnnaBridge	145:64910690c574	500	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
AnnaBridge	145:64910690c574	501	{
AnnaBridge	145:64910690c574	502	__ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
AnnaBridge	145:64910690c574	503	}
AnnaBridge	145:64910690c574	504	#endif
AnnaBridge	145:64910690c574	505
AnnaBridge	145:64910690c574	506
AnnaBridge	145:64910690c574	507	/**
AnnaBridge	145:64910690c574	508	\brief Set Base Priority with condition
AnnaBridge	145:64910690c574	509	\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
AnnaBridge	145:64910690c574	510	or the new value increases the BASEPRI priority level.
AnnaBridge	145:64910690c574	511	\param [in] basePri Base Priority value to set
AnnaBridge	145:64910690c574	512	*/
AnnaBridge	145:64910690c574	513	__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
AnnaBridge	145:64910690c574	514	{
AnnaBridge	145:64910690c574	515	__ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
AnnaBridge	145:64910690c574	516	}
AnnaBridge	145:64910690c574	517
AnnaBridge	145:64910690c574	518
AnnaBridge	145:64910690c574	519	/**
AnnaBridge	145:64910690c574	520	\brief Get Fault Mask
AnnaBridge	145:64910690c574	521	\details Returns the current value of the Fault Mask register.
AnnaBridge	145:64910690c574	522	\return Fault Mask register value
AnnaBridge	145:64910690c574	523	*/
AnnaBridge	145:64910690c574	524	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
AnnaBridge	145:64910690c574	525	{
AnnaBridge	145:64910690c574	526	uint32_t result;
AnnaBridge	145:64910690c574	527
AnnaBridge	145:64910690c574	528	__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
AnnaBridge	145:64910690c574	529	return(result);
AnnaBridge	145:64910690c574	530	}
AnnaBridge	145:64910690c574	531
AnnaBridge	145:64910690c574	532
AnnaBridge	145:64910690c574	533	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	534	/**
AnnaBridge	145:64910690c574	535	\brief Get Fault Mask (non-secure)
AnnaBridge	145:64910690c574	536	\details Returns the current value of the non-secure Fault Mask register when in secure state.
AnnaBridge	145:64910690c574	537	\return Fault Mask register value
AnnaBridge	145:64910690c574	538	*/
AnnaBridge	145:64910690c574	539	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
AnnaBridge	145:64910690c574	540	{
AnnaBridge	145:64910690c574	541	uint32_t result;
AnnaBridge	145:64910690c574	542
AnnaBridge	145:64910690c574	543	__ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
AnnaBridge	145:64910690c574	544	return(result);
AnnaBridge	145:64910690c574	545	}
AnnaBridge	145:64910690c574	546	#endif
AnnaBridge	145:64910690c574	547
AnnaBridge	145:64910690c574	548
AnnaBridge	145:64910690c574	549	/**
AnnaBridge	145:64910690c574	550	\brief Set Fault Mask
AnnaBridge	145:64910690c574	551	\details Assigns the given value to the Fault Mask register.
AnnaBridge	145:64910690c574	552	\param [in] faultMask Fault Mask value to set
AnnaBridge	145:64910690c574	553	*/
AnnaBridge	145:64910690c574	554	__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
AnnaBridge	145:64910690c574	555	{
AnnaBridge	145:64910690c574	556	__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
AnnaBridge	145:64910690c574	557	}
AnnaBridge	145:64910690c574	558
AnnaBridge	145:64910690c574	559
AnnaBridge	145:64910690c574	560	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	145:64910690c574	561	/**
AnnaBridge	145:64910690c574	562	\brief Set Fault Mask (non-secure)
AnnaBridge	145:64910690c574	563	\details Assigns the given value to the non-secure Fault Mask register when in secure state.
AnnaBridge	145:64910690c574	564	\param [in] faultMask Fault Mask value to set
AnnaBridge	145:64910690c574	565	*/
AnnaBridge	145:64910690c574	566	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
AnnaBridge	145:64910690c574	567	{
AnnaBridge	145:64910690c574	568	__ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
AnnaBridge	145:64910690c574	569	}
AnnaBridge	145:64910690c574	570	#endif
AnnaBridge	145:64910690c574	571
AnnaBridge	145:64910690c574	572	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	145:64910690c574	573	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	145:64910690c574	574	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	145:64910690c574	575
AnnaBridge	145:64910690c574	576
AnnaBridge	145:64910690c574	577	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	145:64910690c574	578	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge	145:64910690c574	579
AnnaBridge	145:64910690c574	580	/**
AnnaBridge	145:64910690c574	581	\brief Get Process Stack Pointer Limit
AnnaBridge	145:64910690c574	582	\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
AnnaBridge	145:64910690c574	583	\return PSPLIM Register value
AnnaBridge	145:64910690c574	584	*/
AnnaBridge	145:64910690c574	585	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
AnnaBridge	145:64910690c574	586	{
AnnaBridge	145:64910690c574	587	register uint32_t result;
AnnaBridge	145:64910690c574	588
AnnaBridge	145:64910690c574	589	__ASM volatile ("MRS %0, psplim" : "=r" (result) );
AnnaBridge	145:64910690c574	590	return(result);
AnnaBridge	145:64910690c574	591	}
AnnaBridge	145:64910690c574	592
AnnaBridge	145:64910690c574	593
AnnaBridge	145:64910690c574	594	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge	145:64910690c574	595	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	145:64910690c574	596	/**
AnnaBridge	145:64910690c574	597	\brief Get Process Stack Pointer Limit (non-secure)
AnnaBridge	145:64910690c574	598	\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge	145:64910690c574	599	\return PSPLIM Register value
AnnaBridge	145:64910690c574	600	*/
AnnaBridge	145:64910690c574	601	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
AnnaBridge	145:64910690c574	602	{
AnnaBridge	145:64910690c574	603	register uint32_t result;
AnnaBridge	145:64910690c574	604
AnnaBridge	145:64910690c574	605	__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
AnnaBridge	145:64910690c574	606	return(result);
AnnaBridge	145:64910690c574	607	}
AnnaBridge	145:64910690c574	608	#endif
AnnaBridge	145:64910690c574	609
AnnaBridge	145:64910690c574	610
AnnaBridge	145:64910690c574	611	/**
AnnaBridge	145:64910690c574	612	\brief Set Process Stack Pointer Limit
AnnaBridge	145:64910690c574	613	\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
AnnaBridge	145:64910690c574	614	\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge	145:64910690c574	615	*/
AnnaBridge	145:64910690c574	616	__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
AnnaBridge	145:64910690c574	617	{
AnnaBridge	145:64910690c574	618	__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
AnnaBridge	145:64910690c574	619	}
AnnaBridge	145:64910690c574	620
AnnaBridge	145:64910690c574	621
AnnaBridge	145:64910690c574	622	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge	145:64910690c574	623	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	145:64910690c574	624	/**
AnnaBridge	145:64910690c574	625	\brief Set Process Stack Pointer (non-secure)
AnnaBridge	145:64910690c574	626	\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge	145:64910690c574	627	\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge	145:64910690c574	628	*/
AnnaBridge	145:64910690c574	629	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
AnnaBridge	145:64910690c574	630	{
AnnaBridge	145:64910690c574	631	__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
AnnaBridge	145:64910690c574	632	}
AnnaBridge	145:64910690c574	633	#endif
AnnaBridge	145:64910690c574	634
AnnaBridge	145:64910690c574	635
AnnaBridge	145:64910690c574	636	/**
AnnaBridge	145:64910690c574	637	\brief Get Main Stack Pointer Limit
AnnaBridge	145:64910690c574	638	\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
AnnaBridge	145:64910690c574	639	\return MSPLIM Register value
AnnaBridge	145:64910690c574	640	*/
AnnaBridge	145:64910690c574	641	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
AnnaBridge	145:64910690c574	642	{
AnnaBridge	145:64910690c574	643	register uint32_t result;
AnnaBridge	145:64910690c574	644
AnnaBridge	145:64910690c574	645	__ASM volatile ("MRS %0, msplim" : "=r" (result) );
AnnaBridge	145:64910690c574	646
AnnaBridge	145:64910690c574	647	return(result);
AnnaBridge	145:64910690c574	648	}
AnnaBridge	145:64910690c574	649
AnnaBridge	145:64910690c574	650
AnnaBridge	145:64910690c574	651	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge	145:64910690c574	652	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	145:64910690c574	653	/**
AnnaBridge	145:64910690c574	654	\brief Get Main Stack Pointer Limit (non-secure)
AnnaBridge	145:64910690c574	655	\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
AnnaBridge	145:64910690c574	656	\return MSPLIM Register value
AnnaBridge	145:64910690c574	657	*/
AnnaBridge	145:64910690c574	658	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
AnnaBridge	145:64910690c574	659	{
AnnaBridge	145:64910690c574	660	register uint32_t result;
AnnaBridge	145:64910690c574	661
AnnaBridge	145:64910690c574	662	__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
AnnaBridge	145:64910690c574	663	return(result);
AnnaBridge	145:64910690c574	664	}
AnnaBridge	145:64910690c574	665	#endif
AnnaBridge	145:64910690c574	666
AnnaBridge	145:64910690c574	667
AnnaBridge	145:64910690c574	668	/**
AnnaBridge	145:64910690c574	669	\brief Set Main Stack Pointer Limit
AnnaBridge	145:64910690c574	670	\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
AnnaBridge	145:64910690c574	671	\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
AnnaBridge	145:64910690c574	672	*/
AnnaBridge	145:64910690c574	673	__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
AnnaBridge	145:64910690c574	674	{
AnnaBridge	145:64910690c574	675	__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
AnnaBridge	145:64910690c574	676	}
AnnaBridge	145:64910690c574	677
AnnaBridge	145:64910690c574	678
AnnaBridge	145:64910690c574	679	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge	145:64910690c574	680	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	145:64910690c574	681	/**
AnnaBridge	145:64910690c574	682	\brief Set Main Stack Pointer Limit (non-secure)
AnnaBridge	145:64910690c574	683	\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
AnnaBridge	145:64910690c574	684	\param [in] MainStackPtrLimit Main Stack Pointer value to set
AnnaBridge	145:64910690c574	685	*/
AnnaBridge	145:64910690c574	686	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
AnnaBridge	145:64910690c574	687	{
AnnaBridge	145:64910690c574	688	__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
AnnaBridge	145:64910690c574	689	}
AnnaBridge	145:64910690c574	690	#endif
AnnaBridge	145:64910690c574	691
AnnaBridge	145:64910690c574	692	#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	145:64910690c574	693	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge	145:64910690c574	694
AnnaBridge	145:64910690c574	695
AnnaBridge	145:64910690c574	696	#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	145:64910690c574	697	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	145:64910690c574	698
AnnaBridge	145:64910690c574	699	/**
AnnaBridge	145:64910690c574	700	\brief Get FPSCR
AnnaBridge	145:64910690c574	701	\details Returns the current value of the Floating Point Status/Control register.
AnnaBridge	145:64910690c574	702	\return Floating Point Status/Control register value
AnnaBridge	145:64910690c574	703	*/
AnnaBridge	145:64910690c574	704	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
AnnaBridge	145:64910690c574	705	{
AnnaBridge	145:64910690c574	706	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge	145:64910690c574	707	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
Anna Bridge	160:5571c4ff569f	708	#if __has_builtin(__builtin_arm_get_fpscr) \|\| (__GNUC__ > 7) \|\| (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
Anna Bridge	160:5571c4ff569f	709	/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
Anna Bridge	160:5571c4ff569f	710	return __builtin_arm_get_fpscr();
Anna Bridge	160:5571c4ff569f	711	#else
AnnaBridge	145:64910690c574	712	uint32_t result;
AnnaBridge	145:64910690c574	713
AnnaBridge	145:64910690c574	714	__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
AnnaBridge	145:64910690c574	715	return(result);
Anna Bridge	160:5571c4ff569f	716	#endif
AnnaBridge	145:64910690c574	717	#else
Anna Bridge	160:5571c4ff569f	718	return(0U);
AnnaBridge	145:64910690c574	719	#endif
AnnaBridge	145:64910690c574	720	}
AnnaBridge	145:64910690c574	721
AnnaBridge	145:64910690c574	722
AnnaBridge	145:64910690c574	723	/**
AnnaBridge	145:64910690c574	724	\brief Set FPSCR
AnnaBridge	145:64910690c574	725	\details Assigns the given value to the Floating Point Status/Control register.
AnnaBridge	145:64910690c574	726	\param [in] fpscr Floating Point Status/Control value to set
AnnaBridge	145:64910690c574	727	*/
AnnaBridge	145:64910690c574	728	__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge	145:64910690c574	729	{
AnnaBridge	145:64910690c574	730	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge	145:64910690c574	731	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
Anna Bridge	160:5571c4ff569f	732	#if __has_builtin(__builtin_arm_set_fpscr) \|\| (__GNUC__ > 7) \|\| (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
Anna Bridge	160:5571c4ff569f	733	/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
Anna Bridge	160:5571c4ff569f	734	__builtin_arm_set_fpscr(fpscr);
Anna Bridge	160:5571c4ff569f	735	#else
AnnaBridge	145:64910690c574	736	__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
Anna Bridge	160:5571c4ff569f	737	#endif
AnnaBridge	145:64910690c574	738	#else
AnnaBridge	145:64910690c574	739	(void)fpscr;
AnnaBridge	145:64910690c574	740	#endif
AnnaBridge	145:64910690c574	741	}
AnnaBridge	145:64910690c574	742
AnnaBridge	145:64910690c574	743	#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	145:64910690c574	744	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	145:64910690c574	745
AnnaBridge	145:64910690c574	746
AnnaBridge	145:64910690c574	747
AnnaBridge	145:64910690c574	748	/@} end of CMSIS_Core_RegAccFunctions /
AnnaBridge	145:64910690c574	749
AnnaBridge	145:64910690c574	750
AnnaBridge	145:64910690c574	751	/* ########################## Core Instruction Access ######################### */
AnnaBridge	145:64910690c574	752	/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
AnnaBridge	145:64910690c574	753	Access to dedicated instructions
AnnaBridge	145:64910690c574	754	@{
AnnaBridge	145:64910690c574	755	*/
AnnaBridge	145:64910690c574	756
AnnaBridge	145:64910690c574	757	/* Define macros for porting to both thumb1 and thumb2.
AnnaBridge	145:64910690c574	758	* For thumb1, use low register (r0-r7), specified by constraint "l"
AnnaBridge	145:64910690c574	759	* Otherwise, use general registers, specified by constraint "r" */
AnnaBridge	145:64910690c574	760	#if defined (__thumb__) && !defined (__thumb2__)
AnnaBridge	145:64910690c574	761	#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
AnnaBridge	145:64910690c574	762	#define __CMSIS_GCC_RW_REG(r) "+l" (r)
AnnaBridge	145:64910690c574	763	#define __CMSIS_GCC_USE_REG(r) "l" (r)
AnnaBridge	145:64910690c574	764	#else
AnnaBridge	145:64910690c574	765	#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
AnnaBridge	145:64910690c574	766	#define __CMSIS_GCC_RW_REG(r) "+r" (r)
AnnaBridge	145:64910690c574	767	#define __CMSIS_GCC_USE_REG(r) "r" (r)
AnnaBridge	145:64910690c574	768	#endif
AnnaBridge	145:64910690c574	769
AnnaBridge	145:64910690c574	770	/**
AnnaBridge	145:64910690c574	771	\brief No Operation
AnnaBridge	145:64910690c574	772	\details No Operation does nothing. This instruction can be used for code alignment purposes.
AnnaBridge	145:64910690c574	773	*/
AnnaBridge	145:64910690c574	774	//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
AnnaBridge	145:64910690c574	775	//{
AnnaBridge	145:64910690c574	776	// __ASM volatile ("nop");
AnnaBridge	145:64910690c574	777	//}
AnnaBridge	145:64910690c574	778	#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */
AnnaBridge	145:64910690c574	779
AnnaBridge	145:64910690c574	780	/**
AnnaBridge	145:64910690c574	781	\brief Wait For Interrupt
AnnaBridge	145:64910690c574	782	\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
AnnaBridge	145:64910690c574	783	*/
AnnaBridge	145:64910690c574	784	//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
AnnaBridge	145:64910690c574	785	//{
AnnaBridge	145:64910690c574	786	// __ASM volatile ("wfi");
AnnaBridge	145:64910690c574	787	//}
AnnaBridge	145:64910690c574	788	#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */
AnnaBridge	145:64910690c574	789
AnnaBridge	145:64910690c574	790
AnnaBridge	145:64910690c574	791	/**
AnnaBridge	145:64910690c574	792	\brief Wait For Event
AnnaBridge	145:64910690c574	793	\details Wait For Event is a hint instruction that permits the processor to enter
AnnaBridge	145:64910690c574	794	a low-power state until one of a number of events occurs.
AnnaBridge	145:64910690c574	795	*/
AnnaBridge	145:64910690c574	796	//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
AnnaBridge	145:64910690c574	797	//{
AnnaBridge	145:64910690c574	798	// __ASM volatile ("wfe");
AnnaBridge	145:64910690c574	799	//}
AnnaBridge	145:64910690c574	800	#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */
AnnaBridge	145:64910690c574	801
AnnaBridge	145:64910690c574	802
AnnaBridge	145:64910690c574	803	/**
AnnaBridge	145:64910690c574	804	\brief Send Event
AnnaBridge	145:64910690c574	805	\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
AnnaBridge	145:64910690c574	806	*/
AnnaBridge	145:64910690c574	807	//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
AnnaBridge	145:64910690c574	808	//{
AnnaBridge	145:64910690c574	809	// __ASM volatile ("sev");
AnnaBridge	145:64910690c574	810	//}
AnnaBridge	145:64910690c574	811	#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */
AnnaBridge	145:64910690c574	812
AnnaBridge	145:64910690c574	813
AnnaBridge	145:64910690c574	814	/**
AnnaBridge	145:64910690c574	815	\brief Instruction Synchronization Barrier
AnnaBridge	145:64910690c574	816	\details Instruction Synchronization Barrier flushes the pipeline in the processor,
AnnaBridge	145:64910690c574	817	so that all instructions following the ISB are fetched from cache or memory,
AnnaBridge	145:64910690c574	818	after the instruction has been completed.
AnnaBridge	145:64910690c574	819	*/
AnnaBridge	145:64910690c574	820	__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
AnnaBridge	145:64910690c574	821	{
AnnaBridge	145:64910690c574	822	__ASM volatile ("isb 0xF":::"memory");
AnnaBridge	145:64910690c574	823	}
AnnaBridge	145:64910690c574	824
AnnaBridge	145:64910690c574	825
AnnaBridge	145:64910690c574	826	/**
AnnaBridge	145:64910690c574	827	\brief Data Synchronization Barrier
AnnaBridge	145:64910690c574	828	\details Acts as a special kind of Data Memory Barrier.
AnnaBridge	145:64910690c574	829	It completes when all explicit memory accesses before this instruction complete.
AnnaBridge	145:64910690c574	830	*/
AnnaBridge	145:64910690c574	831	__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
AnnaBridge	145:64910690c574	832	{
AnnaBridge	145:64910690c574	833	__ASM volatile ("dsb 0xF":::"memory");
AnnaBridge	145:64910690c574	834	}
AnnaBridge	145:64910690c574	835
AnnaBridge	145:64910690c574	836
AnnaBridge	145:64910690c574	837	/**
AnnaBridge	145:64910690c574	838	\brief Data Memory Barrier
AnnaBridge	145:64910690c574	839	\details Ensures the apparent order of the explicit memory operations before
AnnaBridge	145:64910690c574	840	and after the instruction, without ensuring their completion.
AnnaBridge	145:64910690c574	841	*/
AnnaBridge	145:64910690c574	842	__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
AnnaBridge	145:64910690c574	843	{
AnnaBridge	145:64910690c574	844	__ASM volatile ("dmb 0xF":::"memory");
AnnaBridge	145:64910690c574	845	}
AnnaBridge	145:64910690c574	846
AnnaBridge	145:64910690c574	847
AnnaBridge	145:64910690c574	848	/**
AnnaBridge	145:64910690c574	849	\brief Reverse byte order (32 bit)
Anna Bridge	160:5571c4ff569f	850	\details Reverses the byte order in unsigned integer value.
AnnaBridge	145:64910690c574	851	\param [in] value Value to reverse
AnnaBridge	145:64910690c574	852	\return Reversed value
AnnaBridge	145:64910690c574	853	*/
AnnaBridge	145:64910690c574	854	__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
AnnaBridge	145:64910690c574	855	{
AnnaBridge	145:64910690c574	856	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
AnnaBridge	145:64910690c574	857	return __builtin_bswap32(value);
AnnaBridge	145:64910690c574	858	#else
AnnaBridge	145:64910690c574	859	uint32_t result;
AnnaBridge	145:64910690c574	860
AnnaBridge	145:64910690c574	861	__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	145:64910690c574	862	return(result);
AnnaBridge	145:64910690c574	863	#endif
AnnaBridge	145:64910690c574	864	}
AnnaBridge	145:64910690c574	865
AnnaBridge	145:64910690c574	866
AnnaBridge	145:64910690c574	867	/**
AnnaBridge	145:64910690c574	868	\brief Reverse byte order (16 bit)
Anna Bridge	160:5571c4ff569f	869	\details Reverses the byte order in unsigned short value.
AnnaBridge	145:64910690c574	870	\param [in] value Value to reverse
AnnaBridge	145:64910690c574	871	\return Reversed value
AnnaBridge	145:64910690c574	872	*/
Anna Bridge	160:5571c4ff569f	873	__attribute__((always_inline)) __STATIC_INLINE uint16_t __REV16(uint16_t value)
AnnaBridge	145:64910690c574	874	{
Anna Bridge	160:5571c4ff569f	875	uint16_t result;
AnnaBridge	145:64910690c574	876
AnnaBridge	145:64910690c574	877	__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	145:64910690c574	878	return(result);
AnnaBridge	145:64910690c574	879	}
AnnaBridge	145:64910690c574	880
AnnaBridge	145:64910690c574	881
AnnaBridge	145:64910690c574	882	/**
AnnaBridge	145:64910690c574	883	\brief Reverse byte order in signed short value
AnnaBridge	145:64910690c574	884	\details Reverses the byte order in a signed short value with sign extension to integer.
AnnaBridge	145:64910690c574	885	\param [in] value Value to reverse
AnnaBridge	145:64910690c574	886	\return Reversed value
AnnaBridge	145:64910690c574	887	*/
Anna Bridge	160:5571c4ff569f	888	__attribute__((always_inline)) __STATIC_INLINE int16_t __REVSH(int16_t value)
AnnaBridge	145:64910690c574	889	{
AnnaBridge	145:64910690c574	890	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
Anna Bridge	160:5571c4ff569f	891	return (int16_t)__builtin_bswap16(value);
AnnaBridge	145:64910690c574	892	#else
Anna Bridge	160:5571c4ff569f	893	int16_t result;
AnnaBridge	145:64910690c574	894
AnnaBridge	145:64910690c574	895	__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
Anna Bridge	160:5571c4ff569f	896	return result;
AnnaBridge	145:64910690c574	897	#endif
AnnaBridge	145:64910690c574	898	}
AnnaBridge	145:64910690c574	899
AnnaBridge	145:64910690c574	900
AnnaBridge	145:64910690c574	901	/**
AnnaBridge	145:64910690c574	902	\brief Rotate Right in unsigned value (32 bit)
AnnaBridge	145:64910690c574	903	\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
AnnaBridge	145:64910690c574	904	\param [in] op1 Value to rotate
AnnaBridge	145:64910690c574	905	\param [in] op2 Number of Bits to rotate
AnnaBridge	145:64910690c574	906	\return Rotated value
AnnaBridge	145:64910690c574	907	*/
AnnaBridge	145:64910690c574	908	__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	909	{
AnnaBridge	145:64910690c574	910	return (op1 >> op2) \| (op1 << (32U - op2));
AnnaBridge	145:64910690c574	911	}
AnnaBridge	145:64910690c574	912
AnnaBridge	145:64910690c574	913
AnnaBridge	145:64910690c574	914	/**
AnnaBridge	145:64910690c574	915	\brief Breakpoint
AnnaBridge	145:64910690c574	916	\details Causes the processor to enter Debug state.
AnnaBridge	145:64910690c574	917	Debug tools can use this to investigate system state when the instruction at a particular address is reached.
AnnaBridge	145:64910690c574	918	\param [in] value is ignored by the processor.
AnnaBridge	145:64910690c574	919	If required, a debugger can use it to store additional information about the breakpoint.
AnnaBridge	145:64910690c574	920	*/
AnnaBridge	145:64910690c574	921	#define __BKPT(value) __ASM volatile ("bkpt "#value)
AnnaBridge	145:64910690c574	922
AnnaBridge	145:64910690c574	923
AnnaBridge	145:64910690c574	924	/**
AnnaBridge	145:64910690c574	925	\brief Reverse bit order of value
AnnaBridge	145:64910690c574	926	\details Reverses the bit order of the given value.
AnnaBridge	145:64910690c574	927	\param [in] value Value to reverse
AnnaBridge	145:64910690c574	928	\return Reversed value
AnnaBridge	145:64910690c574	929	*/
AnnaBridge	145:64910690c574	930	__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
AnnaBridge	145:64910690c574	931	{
AnnaBridge	145:64910690c574	932	uint32_t result;
AnnaBridge	145:64910690c574	933
AnnaBridge	145:64910690c574	934	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	145:64910690c574	935	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	145:64910690c574	936	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	145:64910690c574	937	__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
AnnaBridge	145:64910690c574	938	#else
Anna Bridge	160:5571c4ff569f	939	uint32_t s = (4U /sizeof(v)/ * 8U) - 1U; /* extra shift needed at end */
AnnaBridge	145:64910690c574	940
AnnaBridge	145:64910690c574	941	result = value; /* r will be reversed bits of v; first get LSB of v */
Anna Bridge	160:5571c4ff569f	942	for (value >>= 1U; value != 0U; value >>= 1U)
AnnaBridge	145:64910690c574	943	{
AnnaBridge	145:64910690c574	944	result <<= 1U;
AnnaBridge	145:64910690c574	945	result \|= value & 1U;
AnnaBridge	145:64910690c574	946	s--;
AnnaBridge	145:64910690c574	947	}
AnnaBridge	145:64910690c574	948	result <<= s; /* shift when v's highest bits are zero */
AnnaBridge	145:64910690c574	949	#endif
Anna Bridge	160:5571c4ff569f	950	return result;
AnnaBridge	145:64910690c574	951	}
AnnaBridge	145:64910690c574	952
AnnaBridge	145:64910690c574	953
AnnaBridge	145:64910690c574	954	/**
AnnaBridge	145:64910690c574	955	\brief Count leading zeros
AnnaBridge	145:64910690c574	956	\details Counts the number of leading zeros of a data value.
AnnaBridge	145:64910690c574	957	\param [in] value Value to count the leading zeros
AnnaBridge	145:64910690c574	958	\return number of leading zeros in value
AnnaBridge	145:64910690c574	959	*/
AnnaBridge	145:64910690c574	960	#define __CLZ __builtin_clz
AnnaBridge	145:64910690c574	961
AnnaBridge	145:64910690c574	962
AnnaBridge	145:64910690c574	963	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	145:64910690c574	964	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	145:64910690c574	965	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	145:64910690c574	966	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge	145:64910690c574	967	/**
AnnaBridge	145:64910690c574	968	\brief LDR Exclusive (8 bit)
AnnaBridge	145:64910690c574	969	\details Executes a exclusive LDR instruction for 8 bit value.
AnnaBridge	145:64910690c574	970	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	971	\return value of type uint8_t at (*ptr)
AnnaBridge	145:64910690c574	972	*/
AnnaBridge	145:64910690c574	973	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
AnnaBridge	145:64910690c574	974	{
AnnaBridge	145:64910690c574	975	uint32_t result;
AnnaBridge	145:64910690c574	976
AnnaBridge	145:64910690c574	977	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	145:64910690c574	978	__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge	145:64910690c574	979	#else
AnnaBridge	145:64910690c574	980	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	145:64910690c574	981	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	145:64910690c574	982	*/
AnnaBridge	145:64910690c574	983	__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
AnnaBridge	145:64910690c574	984	#endif
AnnaBridge	145:64910690c574	985	return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge	145:64910690c574	986	}
AnnaBridge	145:64910690c574	987
AnnaBridge	145:64910690c574	988
AnnaBridge	145:64910690c574	989	/**
AnnaBridge	145:64910690c574	990	\brief LDR Exclusive (16 bit)
AnnaBridge	145:64910690c574	991	\details Executes a exclusive LDR instruction for 16 bit values.
AnnaBridge	145:64910690c574	992	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	993	\return value of type uint16_t at (*ptr)
AnnaBridge	145:64910690c574	994	*/
AnnaBridge	145:64910690c574	995	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
AnnaBridge	145:64910690c574	996	{
AnnaBridge	145:64910690c574	997	uint32_t result;
AnnaBridge	145:64910690c574	998
AnnaBridge	145:64910690c574	999	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	145:64910690c574	1000	__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge	145:64910690c574	1001	#else
AnnaBridge	145:64910690c574	1002	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	145:64910690c574	1003	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	145:64910690c574	1004	*/
AnnaBridge	145:64910690c574	1005	__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
AnnaBridge	145:64910690c574	1006	#endif
AnnaBridge	145:64910690c574	1007	return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge	145:64910690c574	1008	}
AnnaBridge	145:64910690c574	1009
AnnaBridge	145:64910690c574	1010
AnnaBridge	145:64910690c574	1011	/**
AnnaBridge	145:64910690c574	1012	\brief LDR Exclusive (32 bit)
AnnaBridge	145:64910690c574	1013	\details Executes a exclusive LDR instruction for 32 bit values.
AnnaBridge	145:64910690c574	1014	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1015	\return value of type uint32_t at (*ptr)
AnnaBridge	145:64910690c574	1016	*/
AnnaBridge	145:64910690c574	1017	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
AnnaBridge	145:64910690c574	1018	{
AnnaBridge	145:64910690c574	1019	uint32_t result;
AnnaBridge	145:64910690c574	1020
AnnaBridge	145:64910690c574	1021	__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge	145:64910690c574	1022	return(result);
AnnaBridge	145:64910690c574	1023	}
AnnaBridge	145:64910690c574	1024
AnnaBridge	145:64910690c574	1025
AnnaBridge	145:64910690c574	1026	/**
AnnaBridge	145:64910690c574	1027	\brief STR Exclusive (8 bit)
AnnaBridge	145:64910690c574	1028	\details Executes a exclusive STR instruction for 8 bit values.
AnnaBridge	145:64910690c574	1029	\param [in] value Value to store
AnnaBridge	145:64910690c574	1030	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1031	\return 0 Function succeeded
AnnaBridge	145:64910690c574	1032	\return 1 Function failed
AnnaBridge	145:64910690c574	1033	*/
AnnaBridge	145:64910690c574	1034	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
AnnaBridge	145:64910690c574	1035	{
AnnaBridge	145:64910690c574	1036	uint32_t result;
AnnaBridge	145:64910690c574	1037
AnnaBridge	145:64910690c574	1038	__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1039	return(result);
AnnaBridge	145:64910690c574	1040	}
AnnaBridge	145:64910690c574	1041
AnnaBridge	145:64910690c574	1042
AnnaBridge	145:64910690c574	1043	/**
AnnaBridge	145:64910690c574	1044	\brief STR Exclusive (16 bit)
AnnaBridge	145:64910690c574	1045	\details Executes a exclusive STR instruction for 16 bit values.
AnnaBridge	145:64910690c574	1046	\param [in] value Value to store
AnnaBridge	145:64910690c574	1047	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1048	\return 0 Function succeeded
AnnaBridge	145:64910690c574	1049	\return 1 Function failed
AnnaBridge	145:64910690c574	1050	*/
AnnaBridge	145:64910690c574	1051	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
AnnaBridge	145:64910690c574	1052	{
AnnaBridge	145:64910690c574	1053	uint32_t result;
AnnaBridge	145:64910690c574	1054
AnnaBridge	145:64910690c574	1055	__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1056	return(result);
AnnaBridge	145:64910690c574	1057	}
AnnaBridge	145:64910690c574	1058
AnnaBridge	145:64910690c574	1059
AnnaBridge	145:64910690c574	1060	/**
AnnaBridge	145:64910690c574	1061	\brief STR Exclusive (32 bit)
AnnaBridge	145:64910690c574	1062	\details Executes a exclusive STR instruction for 32 bit values.
AnnaBridge	145:64910690c574	1063	\param [in] value Value to store
AnnaBridge	145:64910690c574	1064	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1065	\return 0 Function succeeded
AnnaBridge	145:64910690c574	1066	\return 1 Function failed
AnnaBridge	145:64910690c574	1067	*/
AnnaBridge	145:64910690c574	1068	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
AnnaBridge	145:64910690c574	1069	{
AnnaBridge	145:64910690c574	1070	uint32_t result;
AnnaBridge	145:64910690c574	1071
AnnaBridge	145:64910690c574	1072	__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
AnnaBridge	145:64910690c574	1073	return(result);
AnnaBridge	145:64910690c574	1074	}
AnnaBridge	145:64910690c574	1075
AnnaBridge	145:64910690c574	1076
AnnaBridge	145:64910690c574	1077	/**
AnnaBridge	145:64910690c574	1078	\brief Remove the exclusive lock
AnnaBridge	145:64910690c574	1079	\details Removes the exclusive lock which is created by LDREX.
AnnaBridge	145:64910690c574	1080	*/
AnnaBridge	145:64910690c574	1081	__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
AnnaBridge	145:64910690c574	1082	{
AnnaBridge	145:64910690c574	1083	__ASM volatile ("clrex" ::: "memory");
AnnaBridge	145:64910690c574	1084	}
AnnaBridge	145:64910690c574	1085
AnnaBridge	145:64910690c574	1086	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	145:64910690c574	1087	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	145:64910690c574	1088	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	145:64910690c574	1089	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge	145:64910690c574	1090
AnnaBridge	145:64910690c574	1091
AnnaBridge	145:64910690c574	1092	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	145:64910690c574	1093	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	145:64910690c574	1094	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	145:64910690c574	1095	/**
AnnaBridge	145:64910690c574	1096	\brief Signed Saturate
AnnaBridge	145:64910690c574	1097	\details Saturates a signed value.
Anna Bridge	160:5571c4ff569f	1098	\param [in] ARG1 Value to be saturated
Anna Bridge	160:5571c4ff569f	1099	\param [in] ARG2 Bit position to saturate to (1..32)
AnnaBridge	145:64910690c574	1100	\return Saturated value
AnnaBridge	145:64910690c574	1101	*/
AnnaBridge	145:64910690c574	1102	#define __SSAT(ARG1,ARG2) \
Anna Bridge	160:5571c4ff569f	1103	__extension__ \
AnnaBridge	145:64910690c574	1104	({ \
AnnaBridge	145:64910690c574	1105	int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	145:64910690c574	1106	__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	145:64910690c574	1107	__RES; \
AnnaBridge	145:64910690c574	1108	})
AnnaBridge	145:64910690c574	1109
AnnaBridge	145:64910690c574	1110
AnnaBridge	145:64910690c574	1111	/**
AnnaBridge	145:64910690c574	1112	\brief Unsigned Saturate
AnnaBridge	145:64910690c574	1113	\details Saturates an unsigned value.
Anna Bridge	160:5571c4ff569f	1114	\param [in] ARG1 Value to be saturated
Anna Bridge	160:5571c4ff569f	1115	\param [in] ARG2 Bit position to saturate to (0..31)
AnnaBridge	145:64910690c574	1116	\return Saturated value
AnnaBridge	145:64910690c574	1117	*/
AnnaBridge	145:64910690c574	1118	#define __USAT(ARG1,ARG2) \
Anna Bridge	160:5571c4ff569f	1119	__extension__ \
AnnaBridge	145:64910690c574	1120	({ \
AnnaBridge	145:64910690c574	1121	uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	145:64910690c574	1122	__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	145:64910690c574	1123	__RES; \
AnnaBridge	145:64910690c574	1124	})
AnnaBridge	145:64910690c574	1125
AnnaBridge	145:64910690c574	1126
AnnaBridge	145:64910690c574	1127	/**
AnnaBridge	145:64910690c574	1128	\brief Rotate Right with Extend (32 bit)
AnnaBridge	145:64910690c574	1129	\details Moves each bit of a bitstring right by one bit.
AnnaBridge	145:64910690c574	1130	The carry input is shifted in at the left end of the bitstring.
AnnaBridge	145:64910690c574	1131	\param [in] value Value to rotate
AnnaBridge	145:64910690c574	1132	\return Rotated value
AnnaBridge	145:64910690c574	1133	*/
AnnaBridge	145:64910690c574	1134	__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
AnnaBridge	145:64910690c574	1135	{
AnnaBridge	145:64910690c574	1136	uint32_t result;
AnnaBridge	145:64910690c574	1137
AnnaBridge	145:64910690c574	1138	__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	145:64910690c574	1139	return(result);
AnnaBridge	145:64910690c574	1140	}
AnnaBridge	145:64910690c574	1141
AnnaBridge	145:64910690c574	1142
AnnaBridge	145:64910690c574	1143	/**
AnnaBridge	145:64910690c574	1144	\brief LDRT Unprivileged (8 bit)
AnnaBridge	145:64910690c574	1145	\details Executes a Unprivileged LDRT instruction for 8 bit value.
AnnaBridge	145:64910690c574	1146	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1147	\return value of type uint8_t at (*ptr)
AnnaBridge	145:64910690c574	1148	*/
AnnaBridge	145:64910690c574	1149	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
AnnaBridge	145:64910690c574	1150	{
AnnaBridge	145:64910690c574	1151	uint32_t result;
AnnaBridge	145:64910690c574	1152
AnnaBridge	145:64910690c574	1153	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	145:64910690c574	1154	__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	145:64910690c574	1155	#else
AnnaBridge	145:64910690c574	1156	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	145:64910690c574	1157	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	145:64910690c574	1158	*/
AnnaBridge	145:64910690c574	1159	__ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
AnnaBridge	145:64910690c574	1160	#endif
AnnaBridge	145:64910690c574	1161	return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge	145:64910690c574	1162	}
AnnaBridge	145:64910690c574	1163
AnnaBridge	145:64910690c574	1164
AnnaBridge	145:64910690c574	1165	/**
AnnaBridge	145:64910690c574	1166	\brief LDRT Unprivileged (16 bit)
AnnaBridge	145:64910690c574	1167	\details Executes a Unprivileged LDRT instruction for 16 bit values.
AnnaBridge	145:64910690c574	1168	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1169	\return value of type uint16_t at (*ptr)
AnnaBridge	145:64910690c574	1170	*/
AnnaBridge	145:64910690c574	1171	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
AnnaBridge	145:64910690c574	1172	{
AnnaBridge	145:64910690c574	1173	uint32_t result;
AnnaBridge	145:64910690c574	1174
AnnaBridge	145:64910690c574	1175	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	145:64910690c574	1176	__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	145:64910690c574	1177	#else
AnnaBridge	145:64910690c574	1178	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	145:64910690c574	1179	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	145:64910690c574	1180	*/
AnnaBridge	145:64910690c574	1181	__ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
AnnaBridge	145:64910690c574	1182	#endif
AnnaBridge	145:64910690c574	1183	return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge	145:64910690c574	1184	}
AnnaBridge	145:64910690c574	1185
AnnaBridge	145:64910690c574	1186
AnnaBridge	145:64910690c574	1187	/**
AnnaBridge	145:64910690c574	1188	\brief LDRT Unprivileged (32 bit)
AnnaBridge	145:64910690c574	1189	\details Executes a Unprivileged LDRT instruction for 32 bit values.
AnnaBridge	145:64910690c574	1190	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1191	\return value of type uint32_t at (*ptr)
AnnaBridge	145:64910690c574	1192	*/
AnnaBridge	145:64910690c574	1193	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
AnnaBridge	145:64910690c574	1194	{
AnnaBridge	145:64910690c574	1195	uint32_t result;
AnnaBridge	145:64910690c574	1196
AnnaBridge	145:64910690c574	1197	__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	145:64910690c574	1198	return(result);
AnnaBridge	145:64910690c574	1199	}
AnnaBridge	145:64910690c574	1200
AnnaBridge	145:64910690c574	1201
AnnaBridge	145:64910690c574	1202	/**
AnnaBridge	145:64910690c574	1203	\brief STRT Unprivileged (8 bit)
AnnaBridge	145:64910690c574	1204	\details Executes a Unprivileged STRT instruction for 8 bit values.
AnnaBridge	145:64910690c574	1205	\param [in] value Value to store
AnnaBridge	145:64910690c574	1206	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1207	*/
AnnaBridge	145:64910690c574	1208	__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
AnnaBridge	145:64910690c574	1209	{
AnnaBridge	145:64910690c574	1210	__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1211	}
AnnaBridge	145:64910690c574	1212
AnnaBridge	145:64910690c574	1213
AnnaBridge	145:64910690c574	1214	/**
AnnaBridge	145:64910690c574	1215	\brief STRT Unprivileged (16 bit)
AnnaBridge	145:64910690c574	1216	\details Executes a Unprivileged STRT instruction for 16 bit values.
AnnaBridge	145:64910690c574	1217	\param [in] value Value to store
AnnaBridge	145:64910690c574	1218	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1219	*/
AnnaBridge	145:64910690c574	1220	__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
AnnaBridge	145:64910690c574	1221	{
AnnaBridge	145:64910690c574	1222	__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1223	}
AnnaBridge	145:64910690c574	1224
AnnaBridge	145:64910690c574	1225
AnnaBridge	145:64910690c574	1226	/**
AnnaBridge	145:64910690c574	1227	\brief STRT Unprivileged (32 bit)
AnnaBridge	145:64910690c574	1228	\details Executes a Unprivileged STRT instruction for 32 bit values.
AnnaBridge	145:64910690c574	1229	\param [in] value Value to store
AnnaBridge	145:64910690c574	1230	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1231	*/
AnnaBridge	145:64910690c574	1232	__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
AnnaBridge	145:64910690c574	1233	{
AnnaBridge	145:64910690c574	1234	__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
AnnaBridge	145:64910690c574	1235	}
AnnaBridge	145:64910690c574	1236
Anna Bridge	160:5571c4ff569f	1237	#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
Anna Bridge	160:5571c4ff569f	1238	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
Anna Bridge	160:5571c4ff569f	1239	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
Anna Bridge	160:5571c4ff569f	1240
Anna Bridge	160:5571c4ff569f	1241	/**
Anna Bridge	160:5571c4ff569f	1242	\brief Signed Saturate
Anna Bridge	160:5571c4ff569f	1243	\details Saturates a signed value.
Anna Bridge	160:5571c4ff569f	1244	\param [in] value Value to be saturated
Anna Bridge	160:5571c4ff569f	1245	\param [in] sat Bit position to saturate to (1..32)
Anna Bridge	160:5571c4ff569f	1246	\return Saturated value
Anna Bridge	160:5571c4ff569f	1247	*/
Anna Bridge	160:5571c4ff569f	1248	__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
Anna Bridge	160:5571c4ff569f	1249	{
Anna Bridge	160:5571c4ff569f	1250	if ((sat >= 1U) && (sat <= 32U)) {
Anna Bridge	160:5571c4ff569f	1251	const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
Anna Bridge	160:5571c4ff569f	1252	const int32_t min = -1 - max ;
Anna Bridge	160:5571c4ff569f	1253	if (val > max) {
Anna Bridge	160:5571c4ff569f	1254	return max;
Anna Bridge	160:5571c4ff569f	1255	} else if (val < min) {
Anna Bridge	160:5571c4ff569f	1256	return min;
Anna Bridge	160:5571c4ff569f	1257	}
Anna Bridge	160:5571c4ff569f	1258	}
Anna Bridge	160:5571c4ff569f	1259	return val;
Anna Bridge	160:5571c4ff569f	1260	}
Anna Bridge	160:5571c4ff569f	1261
Anna Bridge	160:5571c4ff569f	1262	/**
Anna Bridge	160:5571c4ff569f	1263	\brief Unsigned Saturate
Anna Bridge	160:5571c4ff569f	1264	\details Saturates an unsigned value.
Anna Bridge	160:5571c4ff569f	1265	\param [in] value Value to be saturated
Anna Bridge	160:5571c4ff569f	1266	\param [in] sat Bit position to saturate to (0..31)
Anna Bridge	160:5571c4ff569f	1267	\return Saturated value
Anna Bridge	160:5571c4ff569f	1268	*/
Anna Bridge	160:5571c4ff569f	1269	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
Anna Bridge	160:5571c4ff569f	1270	{
Anna Bridge	160:5571c4ff569f	1271	if (sat <= 31U) {
Anna Bridge	160:5571c4ff569f	1272	const uint32_t max = ((1U << sat) - 1U);
Anna Bridge	160:5571c4ff569f	1273	if (val > (int32_t)max) {
Anna Bridge	160:5571c4ff569f	1274	return max;
Anna Bridge	160:5571c4ff569f	1275	} else if (val < 0) {
Anna Bridge	160:5571c4ff569f	1276	return 0U;
Anna Bridge	160:5571c4ff569f	1277	}
Anna Bridge	160:5571c4ff569f	1278	}
Anna Bridge	160:5571c4ff569f	1279	return (uint32_t)val;
Anna Bridge	160:5571c4ff569f	1280	}
Anna Bridge	160:5571c4ff569f	1281
AnnaBridge	145:64910690c574	1282	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	145:64910690c574	1283	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	145:64910690c574	1284	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	145:64910690c574	1285
AnnaBridge	145:64910690c574	1286
AnnaBridge	145:64910690c574	1287	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	145:64910690c574	1288	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge	145:64910690c574	1289	/**
AnnaBridge	145:64910690c574	1290	\brief Load-Acquire (8 bit)
AnnaBridge	145:64910690c574	1291	\details Executes a LDAB instruction for 8 bit value.
AnnaBridge	145:64910690c574	1292	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1293	\return value of type uint8_t at (*ptr)
AnnaBridge	145:64910690c574	1294	*/
AnnaBridge	145:64910690c574	1295	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
AnnaBridge	145:64910690c574	1296	{
AnnaBridge	145:64910690c574	1297	uint32_t result;
AnnaBridge	145:64910690c574	1298
AnnaBridge	145:64910690c574	1299	__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	145:64910690c574	1300	return ((uint8_t) result);
AnnaBridge	145:64910690c574	1301	}
AnnaBridge	145:64910690c574	1302
AnnaBridge	145:64910690c574	1303
AnnaBridge	145:64910690c574	1304	/**
AnnaBridge	145:64910690c574	1305	\brief Load-Acquire (16 bit)
AnnaBridge	145:64910690c574	1306	\details Executes a LDAH instruction for 16 bit values.
AnnaBridge	145:64910690c574	1307	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1308	\return value of type uint16_t at (*ptr)
AnnaBridge	145:64910690c574	1309	*/
AnnaBridge	145:64910690c574	1310	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
AnnaBridge	145:64910690c574	1311	{
AnnaBridge	145:64910690c574	1312	uint32_t result;
AnnaBridge	145:64910690c574	1313
AnnaBridge	145:64910690c574	1314	__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	145:64910690c574	1315	return ((uint16_t) result);
AnnaBridge	145:64910690c574	1316	}
AnnaBridge	145:64910690c574	1317
AnnaBridge	145:64910690c574	1318
AnnaBridge	145:64910690c574	1319	/**
AnnaBridge	145:64910690c574	1320	\brief Load-Acquire (32 bit)
AnnaBridge	145:64910690c574	1321	\details Executes a LDA instruction for 32 bit values.
AnnaBridge	145:64910690c574	1322	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1323	\return value of type uint32_t at (*ptr)
AnnaBridge	145:64910690c574	1324	*/
AnnaBridge	145:64910690c574	1325	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
AnnaBridge	145:64910690c574	1326	{
AnnaBridge	145:64910690c574	1327	uint32_t result;
AnnaBridge	145:64910690c574	1328
AnnaBridge	145:64910690c574	1329	__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	145:64910690c574	1330	return(result);
AnnaBridge	145:64910690c574	1331	}
AnnaBridge	145:64910690c574	1332
AnnaBridge	145:64910690c574	1333
AnnaBridge	145:64910690c574	1334	/**
AnnaBridge	145:64910690c574	1335	\brief Store-Release (8 bit)
AnnaBridge	145:64910690c574	1336	\details Executes a STLB instruction for 8 bit values.
AnnaBridge	145:64910690c574	1337	\param [in] value Value to store
AnnaBridge	145:64910690c574	1338	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1339	*/
AnnaBridge	145:64910690c574	1340	__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
AnnaBridge	145:64910690c574	1341	{
AnnaBridge	145:64910690c574	1342	__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1343	}
AnnaBridge	145:64910690c574	1344
AnnaBridge	145:64910690c574	1345
AnnaBridge	145:64910690c574	1346	/**
AnnaBridge	145:64910690c574	1347	\brief Store-Release (16 bit)
AnnaBridge	145:64910690c574	1348	\details Executes a STLH instruction for 16 bit values.
AnnaBridge	145:64910690c574	1349	\param [in] value Value to store
AnnaBridge	145:64910690c574	1350	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1351	*/
AnnaBridge	145:64910690c574	1352	__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
AnnaBridge	145:64910690c574	1353	{
AnnaBridge	145:64910690c574	1354	__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1355	}
AnnaBridge	145:64910690c574	1356
AnnaBridge	145:64910690c574	1357
AnnaBridge	145:64910690c574	1358	/**
AnnaBridge	145:64910690c574	1359	\brief Store-Release (32 bit)
AnnaBridge	145:64910690c574	1360	\details Executes a STL instruction for 32 bit values.
AnnaBridge	145:64910690c574	1361	\param [in] value Value to store
AnnaBridge	145:64910690c574	1362	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1363	*/
AnnaBridge	145:64910690c574	1364	__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
AnnaBridge	145:64910690c574	1365	{
AnnaBridge	145:64910690c574	1366	__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1367	}
AnnaBridge	145:64910690c574	1368
AnnaBridge	145:64910690c574	1369
AnnaBridge	145:64910690c574	1370	/**
AnnaBridge	145:64910690c574	1371	\brief Load-Acquire Exclusive (8 bit)
AnnaBridge	145:64910690c574	1372	\details Executes a LDAB exclusive instruction for 8 bit value.
AnnaBridge	145:64910690c574	1373	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1374	\return value of type uint8_t at (*ptr)
AnnaBridge	145:64910690c574	1375	*/
AnnaBridge	145:64910690c574	1376	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
AnnaBridge	145:64910690c574	1377	{
AnnaBridge	145:64910690c574	1378	uint32_t result;
AnnaBridge	145:64910690c574	1379
AnnaBridge	145:64910690c574	1380	__ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	145:64910690c574	1381	return ((uint8_t) result);
AnnaBridge	145:64910690c574	1382	}
AnnaBridge	145:64910690c574	1383
AnnaBridge	145:64910690c574	1384
AnnaBridge	145:64910690c574	1385	/**
AnnaBridge	145:64910690c574	1386	\brief Load-Acquire Exclusive (16 bit)
AnnaBridge	145:64910690c574	1387	\details Executes a LDAH exclusive instruction for 16 bit values.
AnnaBridge	145:64910690c574	1388	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1389	\return value of type uint16_t at (*ptr)
AnnaBridge	145:64910690c574	1390	*/
AnnaBridge	145:64910690c574	1391	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
AnnaBridge	145:64910690c574	1392	{
AnnaBridge	145:64910690c574	1393	uint32_t result;
AnnaBridge	145:64910690c574	1394
AnnaBridge	145:64910690c574	1395	__ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	145:64910690c574	1396	return ((uint16_t) result);
AnnaBridge	145:64910690c574	1397	}
AnnaBridge	145:64910690c574	1398
AnnaBridge	145:64910690c574	1399
AnnaBridge	145:64910690c574	1400	/**
AnnaBridge	145:64910690c574	1401	\brief Load-Acquire Exclusive (32 bit)
AnnaBridge	145:64910690c574	1402	\details Executes a LDA exclusive instruction for 32 bit values.
AnnaBridge	145:64910690c574	1403	\param [in] ptr Pointer to data
AnnaBridge	145:64910690c574	1404	\return value of type uint32_t at (*ptr)
AnnaBridge	145:64910690c574	1405	*/
AnnaBridge	145:64910690c574	1406	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr)
AnnaBridge	145:64910690c574	1407	{
AnnaBridge	145:64910690c574	1408	uint32_t result;
AnnaBridge	145:64910690c574	1409
AnnaBridge	145:64910690c574	1410	__ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	145:64910690c574	1411	return(result);
AnnaBridge	145:64910690c574	1412	}
AnnaBridge	145:64910690c574	1413
AnnaBridge	145:64910690c574	1414
AnnaBridge	145:64910690c574	1415	/**
AnnaBridge	145:64910690c574	1416	\brief Store-Release Exclusive (8 bit)
AnnaBridge	145:64910690c574	1417	\details Executes a STLB exclusive instruction for 8 bit values.
AnnaBridge	145:64910690c574	1418	\param [in] value Value to store
AnnaBridge	145:64910690c574	1419	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1420	\return 0 Function succeeded
AnnaBridge	145:64910690c574	1421	\return 1 Function failed
AnnaBridge	145:64910690c574	1422	*/
AnnaBridge	145:64910690c574	1423	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
AnnaBridge	145:64910690c574	1424	{
AnnaBridge	145:64910690c574	1425	uint32_t result;
AnnaBridge	145:64910690c574	1426
AnnaBridge	145:64910690c574	1427	__ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1428	return(result);
AnnaBridge	145:64910690c574	1429	}
AnnaBridge	145:64910690c574	1430
AnnaBridge	145:64910690c574	1431
AnnaBridge	145:64910690c574	1432	/**
AnnaBridge	145:64910690c574	1433	\brief Store-Release Exclusive (16 bit)
AnnaBridge	145:64910690c574	1434	\details Executes a STLH exclusive instruction for 16 bit values.
AnnaBridge	145:64910690c574	1435	\param [in] value Value to store
AnnaBridge	145:64910690c574	1436	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1437	\return 0 Function succeeded
AnnaBridge	145:64910690c574	1438	\return 1 Function failed
AnnaBridge	145:64910690c574	1439	*/
AnnaBridge	145:64910690c574	1440	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
AnnaBridge	145:64910690c574	1441	{
AnnaBridge	145:64910690c574	1442	uint32_t result;
AnnaBridge	145:64910690c574	1443
AnnaBridge	145:64910690c574	1444	__ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1445	return(result);
AnnaBridge	145:64910690c574	1446	}
AnnaBridge	145:64910690c574	1447
AnnaBridge	145:64910690c574	1448
AnnaBridge	145:64910690c574	1449	/**
AnnaBridge	145:64910690c574	1450	\brief Store-Release Exclusive (32 bit)
AnnaBridge	145:64910690c574	1451	\details Executes a STL exclusive instruction for 32 bit values.
AnnaBridge	145:64910690c574	1452	\param [in] value Value to store
AnnaBridge	145:64910690c574	1453	\param [in] ptr Pointer to location
AnnaBridge	145:64910690c574	1454	\return 0 Function succeeded
AnnaBridge	145:64910690c574	1455	\return 1 Function failed
AnnaBridge	145:64910690c574	1456	*/
AnnaBridge	145:64910690c574	1457	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
AnnaBridge	145:64910690c574	1458	{
AnnaBridge	145:64910690c574	1459	uint32_t result;
AnnaBridge	145:64910690c574	1460
AnnaBridge	145:64910690c574	1461	__ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	145:64910690c574	1462	return(result);
AnnaBridge	145:64910690c574	1463	}
AnnaBridge	145:64910690c574	1464
AnnaBridge	145:64910690c574	1465	#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	145:64910690c574	1466	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge	145:64910690c574	1467
AnnaBridge	145:64910690c574	1468	/@}/ /* end of group CMSIS_Core_InstructionInterface */
AnnaBridge	145:64910690c574	1469
AnnaBridge	145:64910690c574	1470
AnnaBridge	145:64910690c574	1471	/* ################### Compiler specific Intrinsics ########################### */
AnnaBridge	145:64910690c574	1472	/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
AnnaBridge	145:64910690c574	1473	Access to dedicated SIMD instructions
AnnaBridge	145:64910690c574	1474	@{
AnnaBridge	145:64910690c574	1475	*/
AnnaBridge	145:64910690c574	1476
AnnaBridge	145:64910690c574	1477	#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
AnnaBridge	145:64910690c574	1478
AnnaBridge	145:64910690c574	1479	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1480	{
AnnaBridge	145:64910690c574	1481	uint32_t result;
AnnaBridge	145:64910690c574	1482
AnnaBridge	145:64910690c574	1483	__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1484	return(result);
AnnaBridge	145:64910690c574	1485	}
AnnaBridge	145:64910690c574	1486
AnnaBridge	145:64910690c574	1487	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1488	{
AnnaBridge	145:64910690c574	1489	uint32_t result;
AnnaBridge	145:64910690c574	1490
AnnaBridge	145:64910690c574	1491	__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1492	return(result);
AnnaBridge	145:64910690c574	1493	}
AnnaBridge	145:64910690c574	1494
AnnaBridge	145:64910690c574	1495	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1496	{
AnnaBridge	145:64910690c574	1497	uint32_t result;
AnnaBridge	145:64910690c574	1498
AnnaBridge	145:64910690c574	1499	__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1500	return(result);
AnnaBridge	145:64910690c574	1501	}
AnnaBridge	145:64910690c574	1502
AnnaBridge	145:64910690c574	1503	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1504	{
AnnaBridge	145:64910690c574	1505	uint32_t result;
AnnaBridge	145:64910690c574	1506
AnnaBridge	145:64910690c574	1507	__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1508	return(result);
AnnaBridge	145:64910690c574	1509	}
AnnaBridge	145:64910690c574	1510
AnnaBridge	145:64910690c574	1511	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1512	{
AnnaBridge	145:64910690c574	1513	uint32_t result;
AnnaBridge	145:64910690c574	1514
AnnaBridge	145:64910690c574	1515	__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1516	return(result);
AnnaBridge	145:64910690c574	1517	}
AnnaBridge	145:64910690c574	1518
AnnaBridge	145:64910690c574	1519	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1520	{
AnnaBridge	145:64910690c574	1521	uint32_t result;
AnnaBridge	145:64910690c574	1522
AnnaBridge	145:64910690c574	1523	__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1524	return(result);
AnnaBridge	145:64910690c574	1525	}
AnnaBridge	145:64910690c574	1526
AnnaBridge	145:64910690c574	1527
AnnaBridge	145:64910690c574	1528	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1529	{
AnnaBridge	145:64910690c574	1530	uint32_t result;
AnnaBridge	145:64910690c574	1531
AnnaBridge	145:64910690c574	1532	__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1533	return(result);
AnnaBridge	145:64910690c574	1534	}
AnnaBridge	145:64910690c574	1535
AnnaBridge	145:64910690c574	1536	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1537	{
AnnaBridge	145:64910690c574	1538	uint32_t result;
AnnaBridge	145:64910690c574	1539
AnnaBridge	145:64910690c574	1540	__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1541	return(result);
AnnaBridge	145:64910690c574	1542	}
AnnaBridge	145:64910690c574	1543
AnnaBridge	145:64910690c574	1544	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1545	{
AnnaBridge	145:64910690c574	1546	uint32_t result;
AnnaBridge	145:64910690c574	1547
AnnaBridge	145:64910690c574	1548	__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1549	return(result);
AnnaBridge	145:64910690c574	1550	}
AnnaBridge	145:64910690c574	1551
AnnaBridge	145:64910690c574	1552	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1553	{
AnnaBridge	145:64910690c574	1554	uint32_t result;
AnnaBridge	145:64910690c574	1555
AnnaBridge	145:64910690c574	1556	__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1557	return(result);
AnnaBridge	145:64910690c574	1558	}
AnnaBridge	145:64910690c574	1559
AnnaBridge	145:64910690c574	1560	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1561	{
AnnaBridge	145:64910690c574	1562	uint32_t result;
AnnaBridge	145:64910690c574	1563
AnnaBridge	145:64910690c574	1564	__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1565	return(result);
AnnaBridge	145:64910690c574	1566	}
AnnaBridge	145:64910690c574	1567
AnnaBridge	145:64910690c574	1568	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1569	{
AnnaBridge	145:64910690c574	1570	uint32_t result;
AnnaBridge	145:64910690c574	1571
AnnaBridge	145:64910690c574	1572	__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1573	return(result);
AnnaBridge	145:64910690c574	1574	}
AnnaBridge	145:64910690c574	1575
AnnaBridge	145:64910690c574	1576
AnnaBridge	145:64910690c574	1577	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1578	{
AnnaBridge	145:64910690c574	1579	uint32_t result;
AnnaBridge	145:64910690c574	1580
AnnaBridge	145:64910690c574	1581	__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1582	return(result);
AnnaBridge	145:64910690c574	1583	}
AnnaBridge	145:64910690c574	1584
AnnaBridge	145:64910690c574	1585	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1586	{
AnnaBridge	145:64910690c574	1587	uint32_t result;
AnnaBridge	145:64910690c574	1588
AnnaBridge	145:64910690c574	1589	__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1590	return(result);
AnnaBridge	145:64910690c574	1591	}
AnnaBridge	145:64910690c574	1592
AnnaBridge	145:64910690c574	1593	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1594	{
AnnaBridge	145:64910690c574	1595	uint32_t result;
AnnaBridge	145:64910690c574	1596
AnnaBridge	145:64910690c574	1597	__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1598	return(result);
AnnaBridge	145:64910690c574	1599	}
AnnaBridge	145:64910690c574	1600
AnnaBridge	145:64910690c574	1601	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1602	{
AnnaBridge	145:64910690c574	1603	uint32_t result;
AnnaBridge	145:64910690c574	1604
AnnaBridge	145:64910690c574	1605	__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1606	return(result);
AnnaBridge	145:64910690c574	1607	}
AnnaBridge	145:64910690c574	1608
AnnaBridge	145:64910690c574	1609	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1610	{
AnnaBridge	145:64910690c574	1611	uint32_t result;
AnnaBridge	145:64910690c574	1612
AnnaBridge	145:64910690c574	1613	__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1614	return(result);
AnnaBridge	145:64910690c574	1615	}
AnnaBridge	145:64910690c574	1616
AnnaBridge	145:64910690c574	1617	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1618	{
AnnaBridge	145:64910690c574	1619	uint32_t result;
AnnaBridge	145:64910690c574	1620
AnnaBridge	145:64910690c574	1621	__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1622	return(result);
AnnaBridge	145:64910690c574	1623	}
AnnaBridge	145:64910690c574	1624
AnnaBridge	145:64910690c574	1625	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1626	{
AnnaBridge	145:64910690c574	1627	uint32_t result;
AnnaBridge	145:64910690c574	1628
AnnaBridge	145:64910690c574	1629	__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1630	return(result);
AnnaBridge	145:64910690c574	1631	}
AnnaBridge	145:64910690c574	1632
AnnaBridge	145:64910690c574	1633	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1634	{
AnnaBridge	145:64910690c574	1635	uint32_t result;
AnnaBridge	145:64910690c574	1636
AnnaBridge	145:64910690c574	1637	__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1638	return(result);
AnnaBridge	145:64910690c574	1639	}
AnnaBridge	145:64910690c574	1640
AnnaBridge	145:64910690c574	1641	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1642	{
AnnaBridge	145:64910690c574	1643	uint32_t result;
AnnaBridge	145:64910690c574	1644
AnnaBridge	145:64910690c574	1645	__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1646	return(result);
AnnaBridge	145:64910690c574	1647	}
AnnaBridge	145:64910690c574	1648
AnnaBridge	145:64910690c574	1649	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1650	{
AnnaBridge	145:64910690c574	1651	uint32_t result;
AnnaBridge	145:64910690c574	1652
AnnaBridge	145:64910690c574	1653	__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1654	return(result);
AnnaBridge	145:64910690c574	1655	}
AnnaBridge	145:64910690c574	1656
AnnaBridge	145:64910690c574	1657	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1658	{
AnnaBridge	145:64910690c574	1659	uint32_t result;
AnnaBridge	145:64910690c574	1660
AnnaBridge	145:64910690c574	1661	__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1662	return(result);
AnnaBridge	145:64910690c574	1663	}
AnnaBridge	145:64910690c574	1664
AnnaBridge	145:64910690c574	1665	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1666	{
AnnaBridge	145:64910690c574	1667	uint32_t result;
AnnaBridge	145:64910690c574	1668
AnnaBridge	145:64910690c574	1669	__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1670	return(result);
AnnaBridge	145:64910690c574	1671	}
AnnaBridge	145:64910690c574	1672
AnnaBridge	145:64910690c574	1673	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1674	{
AnnaBridge	145:64910690c574	1675	uint32_t result;
AnnaBridge	145:64910690c574	1676
AnnaBridge	145:64910690c574	1677	__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1678	return(result);
AnnaBridge	145:64910690c574	1679	}
AnnaBridge	145:64910690c574	1680
AnnaBridge	145:64910690c574	1681	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1682	{
AnnaBridge	145:64910690c574	1683	uint32_t result;
AnnaBridge	145:64910690c574	1684
AnnaBridge	145:64910690c574	1685	__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1686	return(result);
AnnaBridge	145:64910690c574	1687	}
AnnaBridge	145:64910690c574	1688
AnnaBridge	145:64910690c574	1689	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1690	{
AnnaBridge	145:64910690c574	1691	uint32_t result;
AnnaBridge	145:64910690c574	1692
AnnaBridge	145:64910690c574	1693	__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1694	return(result);
AnnaBridge	145:64910690c574	1695	}
AnnaBridge	145:64910690c574	1696
AnnaBridge	145:64910690c574	1697	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1698	{
AnnaBridge	145:64910690c574	1699	uint32_t result;
AnnaBridge	145:64910690c574	1700
AnnaBridge	145:64910690c574	1701	__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1702	return(result);
AnnaBridge	145:64910690c574	1703	}
AnnaBridge	145:64910690c574	1704
AnnaBridge	145:64910690c574	1705	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1706	{
AnnaBridge	145:64910690c574	1707	uint32_t result;
AnnaBridge	145:64910690c574	1708
AnnaBridge	145:64910690c574	1709	__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1710	return(result);
AnnaBridge	145:64910690c574	1711	}
AnnaBridge	145:64910690c574	1712
AnnaBridge	145:64910690c574	1713	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1714	{
AnnaBridge	145:64910690c574	1715	uint32_t result;
AnnaBridge	145:64910690c574	1716
AnnaBridge	145:64910690c574	1717	__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1718	return(result);
AnnaBridge	145:64910690c574	1719	}
AnnaBridge	145:64910690c574	1720
AnnaBridge	145:64910690c574	1721	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1722	{
AnnaBridge	145:64910690c574	1723	uint32_t result;
AnnaBridge	145:64910690c574	1724
AnnaBridge	145:64910690c574	1725	__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1726	return(result);
AnnaBridge	145:64910690c574	1727	}
AnnaBridge	145:64910690c574	1728
AnnaBridge	145:64910690c574	1729	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1730	{
AnnaBridge	145:64910690c574	1731	uint32_t result;
AnnaBridge	145:64910690c574	1732
AnnaBridge	145:64910690c574	1733	__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1734	return(result);
AnnaBridge	145:64910690c574	1735	}
AnnaBridge	145:64910690c574	1736
AnnaBridge	145:64910690c574	1737	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1738	{
AnnaBridge	145:64910690c574	1739	uint32_t result;
AnnaBridge	145:64910690c574	1740
AnnaBridge	145:64910690c574	1741	__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1742	return(result);
AnnaBridge	145:64910690c574	1743	}
AnnaBridge	145:64910690c574	1744
AnnaBridge	145:64910690c574	1745	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1746	{
AnnaBridge	145:64910690c574	1747	uint32_t result;
AnnaBridge	145:64910690c574	1748
AnnaBridge	145:64910690c574	1749	__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1750	return(result);
AnnaBridge	145:64910690c574	1751	}
AnnaBridge	145:64910690c574	1752
AnnaBridge	145:64910690c574	1753	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1754	{
AnnaBridge	145:64910690c574	1755	uint32_t result;
AnnaBridge	145:64910690c574	1756
AnnaBridge	145:64910690c574	1757	__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1758	return(result);
AnnaBridge	145:64910690c574	1759	}
AnnaBridge	145:64910690c574	1760
AnnaBridge	145:64910690c574	1761	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1762	{
AnnaBridge	145:64910690c574	1763	uint32_t result;
AnnaBridge	145:64910690c574	1764
AnnaBridge	145:64910690c574	1765	__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1766	return(result);
AnnaBridge	145:64910690c574	1767	}
AnnaBridge	145:64910690c574	1768
AnnaBridge	145:64910690c574	1769	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1770	{
AnnaBridge	145:64910690c574	1771	uint32_t result;
AnnaBridge	145:64910690c574	1772
AnnaBridge	145:64910690c574	1773	__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1774	return(result);
AnnaBridge	145:64910690c574	1775	}
AnnaBridge	145:64910690c574	1776
AnnaBridge	145:64910690c574	1777	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	145:64910690c574	1778	{
AnnaBridge	145:64910690c574	1779	uint32_t result;
AnnaBridge	145:64910690c574	1780
AnnaBridge	145:64910690c574	1781	__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	145:64910690c574	1782	return(result);
AnnaBridge	145:64910690c574	1783	}
AnnaBridge	145:64910690c574	1784
AnnaBridge	145:64910690c574	1785	#define __SSAT16(ARG1,ARG2) \
AnnaBridge	145:64910690c574	1786	({ \
AnnaBridge	145:64910690c574	1787	int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	145:64910690c574	1788	__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	145:64910690c574	1789	__RES; \
AnnaBridge	145:64910690c574	1790	})
AnnaBridge	145:64910690c574	1791
AnnaBridge	145:64910690c574	1792	#define __USAT16(ARG1,ARG2) \
AnnaBridge	145:64910690c574	1793	({ \
AnnaBridge	145:64910690c574	1794	uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	145:64910690c574	1795	__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	145:64910690c574	1796	__RES; \
AnnaBridge	145:64910690c574	1797	})
AnnaBridge	145:64910690c574	1798
AnnaBridge	145:64910690c574	1799	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
AnnaBridge	145:64910690c574	1800	{
AnnaBridge	145:64910690c574	1801	uint32_t result;
AnnaBridge	145:64910690c574	1802
AnnaBridge	145:64910690c574	1803	__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge	145:64910690c574	1804	return(result);
AnnaBridge	145:64910690c574	1805	}
AnnaBridge	145:64910690c574	1806
AnnaBridge	145:64910690c574	1807	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1808	{
AnnaBridge	145:64910690c574	1809	uint32_t result;
AnnaBridge	145:64910690c574	1810
AnnaBridge	145:64910690c574	1811	__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1812	return(result);
AnnaBridge	145:64910690c574	1813	}
AnnaBridge	145:64910690c574	1814
AnnaBridge	145:64910690c574	1815	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
AnnaBridge	145:64910690c574	1816	{
AnnaBridge	145:64910690c574	1817	uint32_t result;
AnnaBridge	145:64910690c574	1818
AnnaBridge	145:64910690c574	1819	__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge	145:64910690c574	1820	return(result);
AnnaBridge	145:64910690c574	1821	}
AnnaBridge	145:64910690c574	1822
AnnaBridge	145:64910690c574	1823	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1824	{
AnnaBridge	145:64910690c574	1825	uint32_t result;
AnnaBridge	145:64910690c574	1826
AnnaBridge	145:64910690c574	1827	__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1828	return(result);
AnnaBridge	145:64910690c574	1829	}
AnnaBridge	145:64910690c574	1830
AnnaBridge	145:64910690c574	1831	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1832	{
AnnaBridge	145:64910690c574	1833	uint32_t result;
AnnaBridge	145:64910690c574	1834
AnnaBridge	145:64910690c574	1835	__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1836	return(result);
AnnaBridge	145:64910690c574	1837	}
AnnaBridge	145:64910690c574	1838
AnnaBridge	145:64910690c574	1839	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1840	{
AnnaBridge	145:64910690c574	1841	uint32_t result;
AnnaBridge	145:64910690c574	1842
AnnaBridge	145:64910690c574	1843	__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1844	return(result);
AnnaBridge	145:64910690c574	1845	}
AnnaBridge	145:64910690c574	1846
AnnaBridge	145:64910690c574	1847	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	145:64910690c574	1848	{
AnnaBridge	145:64910690c574	1849	uint32_t result;
AnnaBridge	145:64910690c574	1850
AnnaBridge	145:64910690c574	1851	__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	145:64910690c574	1852	return(result);
AnnaBridge	145:64910690c574	1853	}
AnnaBridge	145:64910690c574	1854
AnnaBridge	145:64910690c574	1855	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	145:64910690c574	1856	{
AnnaBridge	145:64910690c574	1857	uint32_t result;
AnnaBridge	145:64910690c574	1858
AnnaBridge	145:64910690c574	1859	__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	145:64910690c574	1860	return(result);
AnnaBridge	145:64910690c574	1861	}
AnnaBridge	145:64910690c574	1862
AnnaBridge	145:64910690c574	1863	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	145:64910690c574	1864	{
AnnaBridge	145:64910690c574	1865	union llreg_u{
AnnaBridge	145:64910690c574	1866	uint32_t w32[2];
AnnaBridge	145:64910690c574	1867	uint64_t w64;
AnnaBridge	145:64910690c574	1868	} llr;
AnnaBridge	145:64910690c574	1869	llr.w64 = acc;
AnnaBridge	145:64910690c574	1870
AnnaBridge	145:64910690c574	1871	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	145:64910690c574	1872	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	145:64910690c574	1873	#else /* Big endian */
AnnaBridge	145:64910690c574	1874	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	145:64910690c574	1875	#endif
AnnaBridge	145:64910690c574	1876
AnnaBridge	145:64910690c574	1877	return(llr.w64);
AnnaBridge	145:64910690c574	1878	}
AnnaBridge	145:64910690c574	1879
AnnaBridge	145:64910690c574	1880	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	145:64910690c574	1881	{
AnnaBridge	145:64910690c574	1882	union llreg_u{
AnnaBridge	145:64910690c574	1883	uint32_t w32[2];
AnnaBridge	145:64910690c574	1884	uint64_t w64;
AnnaBridge	145:64910690c574	1885	} llr;
AnnaBridge	145:64910690c574	1886	llr.w64 = acc;
AnnaBridge	145:64910690c574	1887
AnnaBridge	145:64910690c574	1888	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	145:64910690c574	1889	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	145:64910690c574	1890	#else /* Big endian */
AnnaBridge	145:64910690c574	1891	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	145:64910690c574	1892	#endif
AnnaBridge	145:64910690c574	1893
AnnaBridge	145:64910690c574	1894	return(llr.w64);
AnnaBridge	145:64910690c574	1895	}
AnnaBridge	145:64910690c574	1896
AnnaBridge	145:64910690c574	1897	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1898	{
AnnaBridge	145:64910690c574	1899	uint32_t result;
AnnaBridge	145:64910690c574	1900
AnnaBridge	145:64910690c574	1901	__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1902	return(result);
AnnaBridge	145:64910690c574	1903	}
AnnaBridge	145:64910690c574	1904
AnnaBridge	145:64910690c574	1905	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1906	{
AnnaBridge	145:64910690c574	1907	uint32_t result;
AnnaBridge	145:64910690c574	1908
AnnaBridge	145:64910690c574	1909	__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1910	return(result);
AnnaBridge	145:64910690c574	1911	}
AnnaBridge	145:64910690c574	1912
AnnaBridge	145:64910690c574	1913	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	145:64910690c574	1914	{
AnnaBridge	145:64910690c574	1915	uint32_t result;
AnnaBridge	145:64910690c574	1916
AnnaBridge	145:64910690c574	1917	__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	145:64910690c574	1918	return(result);
AnnaBridge	145:64910690c574	1919	}
AnnaBridge	145:64910690c574	1920
AnnaBridge	145:64910690c574	1921	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	145:64910690c574	1922	{
AnnaBridge	145:64910690c574	1923	uint32_t result;
AnnaBridge	145:64910690c574	1924
AnnaBridge	145:64910690c574	1925	__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	145:64910690c574	1926	return(result);
AnnaBridge	145:64910690c574	1927	}
AnnaBridge	145:64910690c574	1928
AnnaBridge	145:64910690c574	1929	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	145:64910690c574	1930	{
AnnaBridge	145:64910690c574	1931	union llreg_u{
AnnaBridge	145:64910690c574	1932	uint32_t w32[2];
AnnaBridge	145:64910690c574	1933	uint64_t w64;
AnnaBridge	145:64910690c574	1934	} llr;
AnnaBridge	145:64910690c574	1935	llr.w64 = acc;
AnnaBridge	145:64910690c574	1936
AnnaBridge	145:64910690c574	1937	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	145:64910690c574	1938	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	145:64910690c574	1939	#else /* Big endian */
AnnaBridge	145:64910690c574	1940	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	145:64910690c574	1941	#endif
AnnaBridge	145:64910690c574	1942
AnnaBridge	145:64910690c574	1943	return(llr.w64);
AnnaBridge	145:64910690c574	1944	}
AnnaBridge	145:64910690c574	1945
AnnaBridge	145:64910690c574	1946	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	145:64910690c574	1947	{
AnnaBridge	145:64910690c574	1948	union llreg_u{
AnnaBridge	145:64910690c574	1949	uint32_t w32[2];
AnnaBridge	145:64910690c574	1950	uint64_t w64;
AnnaBridge	145:64910690c574	1951	} llr;
AnnaBridge	145:64910690c574	1952	llr.w64 = acc;
AnnaBridge	145:64910690c574	1953
AnnaBridge	145:64910690c574	1954	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	145:64910690c574	1955	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	145:64910690c574	1956	#else /* Big endian */
AnnaBridge	145:64910690c574	1957	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	145:64910690c574	1958	#endif
AnnaBridge	145:64910690c574	1959
AnnaBridge	145:64910690c574	1960	return(llr.w64);
AnnaBridge	145:64910690c574	1961	}
AnnaBridge	145:64910690c574	1962
AnnaBridge	145:64910690c574	1963	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
AnnaBridge	145:64910690c574	1964	{
AnnaBridge	145:64910690c574	1965	uint32_t result;
AnnaBridge	145:64910690c574	1966
AnnaBridge	145:64910690c574	1967	__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1968	return(result);
AnnaBridge	145:64910690c574	1969	}
AnnaBridge	145:64910690c574	1970
AnnaBridge	145:64910690c574	1971	__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
AnnaBridge	145:64910690c574	1972	{
AnnaBridge	145:64910690c574	1973	int32_t result;
AnnaBridge	145:64910690c574	1974
AnnaBridge	145:64910690c574	1975	__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1976	return(result);
AnnaBridge	145:64910690c574	1977	}
AnnaBridge	145:64910690c574	1978
AnnaBridge	145:64910690c574	1979	__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
AnnaBridge	145:64910690c574	1980	{
AnnaBridge	145:64910690c574	1981	int32_t result;
AnnaBridge	145:64910690c574	1982
AnnaBridge	145:64910690c574	1983	__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	145:64910690c574	1984	return(result);
AnnaBridge	145:64910690c574	1985	}
AnnaBridge	145:64910690c574	1986
AnnaBridge	145:64910690c574	1987	#if 0
AnnaBridge	145:64910690c574	1988	#define __PKHBT(ARG1,ARG2,ARG3) \
AnnaBridge	145:64910690c574	1989	({ \
AnnaBridge	145:64910690c574	1990	uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge	145:64910690c574	1991	__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge	145:64910690c574	1992	__RES; \
AnnaBridge	145:64910690c574	1993	})
AnnaBridge	145:64910690c574	1994
AnnaBridge	145:64910690c574	1995	#define __PKHTB(ARG1,ARG2,ARG3) \
AnnaBridge	145:64910690c574	1996	({ \
AnnaBridge	145:64910690c574	1997	uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge	145:64910690c574	1998	if (ARG3 == 0) \
AnnaBridge	145:64910690c574	1999	__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
AnnaBridge	145:64910690c574	2000	else \
AnnaBridge	145:64910690c574	2001	__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge	145:64910690c574	2002	__RES; \
AnnaBridge	145:64910690c574	2003	})
AnnaBridge	145:64910690c574	2004	#endif
AnnaBridge	145:64910690c574	2005
AnnaBridge	145:64910690c574	2006	#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) \| \
AnnaBridge	145:64910690c574	2007	((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
AnnaBridge	145:64910690c574	2008
AnnaBridge	145:64910690c574	2009	#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) \| \
AnnaBridge	145:64910690c574	2010	((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
AnnaBridge	145:64910690c574	2011
AnnaBridge	145:64910690c574	2012	__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
AnnaBridge	145:64910690c574	2013	{
AnnaBridge	145:64910690c574	2014	int32_t result;
AnnaBridge	145:64910690c574	2015
AnnaBridge	145:64910690c574	2016	__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	145:64910690c574	2017	return(result);
AnnaBridge	145:64910690c574	2018	}
AnnaBridge	145:64910690c574	2019
AnnaBridge	145:64910690c574	2020	#endif /* (__ARM_FEATURE_DSP == 1) */
AnnaBridge	145:64910690c574	2021	/@} end of group CMSIS_SIMD_intrinsics /
AnnaBridge	145:64910690c574	2022
AnnaBridge	145:64910690c574	2023
AnnaBridge	145:64910690c574	2024	#pragma GCC diagnostic pop
AnnaBridge	145:64910690c574	2025
AnnaBridge	145:64910690c574	2026	#endif /* __CMSIS_GCC_H */