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TARGET_TB_SENSE_12/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/efr32mg12p_rmu.h@142:4eea097334d6, 2017-05-10 (annotated)
- Committer:
- Anna Bridge
- Date:
- Wed May 10 11:31:27 2017 +0100
- Revision:
- 142:4eea097334d6
Release 142 of the mbed library
Ports for Upcoming Targets
Fixes and Changes
4059: [Silicon Labs] Rename targets https://github.com/ARMmbed/mbed-os/pull/4059
4187: [NCS36510] Reduce default heap size allocated by IAR to 1/4 of RAM https://github.com/ARMmbed/mbed-os/pull/4187
4225: fixed missing device_name for xDot and removed progen https://github.com/ARMmbed/mbed-os/pull/4225
4251: Fix C++11 build error w/ u-blox EVK-ODIN-W2 https://github.com/ARMmbed/mbed-os/pull/4251
4236: STM32 Fixed warning related to __packed redefinition https://github.com/ARMmbed/mbed-os/pull/4236
4190: LPC4088: Enable LWIP feature https://github.com/ARMmbed/mbed-os/pull/4190
4260: Inherit Xadow M0 target from LPC11U35_501 https://github.com/ARMmbed/mbed-os/pull/4260
4249: Add consistent button names across targets https://github.com/ARMmbed/mbed-os/pull/4249
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Anna Bridge |
142:4eea097334d6 | 1 | /**************************************************************************//** |
Anna Bridge |
142:4eea097334d6 | 2 | * @file efr32mg12p_rmu.h |
Anna Bridge |
142:4eea097334d6 | 3 | * @brief EFR32MG12P_RMU register and bit field definitions |
Anna Bridge |
142:4eea097334d6 | 4 | * @version 5.1.2 |
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142:4eea097334d6 | 5 | ****************************************************************************** |
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142:4eea097334d6 | 6 | * @section License |
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142:4eea097334d6 | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
Anna Bridge |
142:4eea097334d6 | 8 | ****************************************************************************** |
Anna Bridge |
142:4eea097334d6 | 9 | * |
Anna Bridge |
142:4eea097334d6 | 10 | * Permission is granted to anyone to use this software for any purpose, |
Anna Bridge |
142:4eea097334d6 | 11 | * including commercial applications, and to alter it and redistribute it |
Anna Bridge |
142:4eea097334d6 | 12 | * freely, subject to the following restrictions: |
Anna Bridge |
142:4eea097334d6 | 13 | * |
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142:4eea097334d6 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
Anna Bridge |
142:4eea097334d6 | 15 | * claim that you wrote the original software.@n |
Anna Bridge |
142:4eea097334d6 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
Anna Bridge |
142:4eea097334d6 | 17 | * misrepresented as being the original software.@n |
Anna Bridge |
142:4eea097334d6 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
Anna Bridge |
142:4eea097334d6 | 19 | * |
Anna Bridge |
142:4eea097334d6 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
Anna Bridge |
142:4eea097334d6 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
Anna Bridge |
142:4eea097334d6 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
Anna Bridge |
142:4eea097334d6 | 23 | * kind, including, but not limited to, any implied warranties of |
Anna Bridge |
142:4eea097334d6 | 24 | * merchantability or fitness for any particular purpose or warranties against |
Anna Bridge |
142:4eea097334d6 | 25 | * infringement of any proprietary rights of a third party. |
Anna Bridge |
142:4eea097334d6 | 26 | * |
Anna Bridge |
142:4eea097334d6 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
Anna Bridge |
142:4eea097334d6 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
Anna Bridge |
142:4eea097334d6 | 29 | * any third party, arising from your use of this Software. |
Anna Bridge |
142:4eea097334d6 | 30 | * |
Anna Bridge |
142:4eea097334d6 | 31 | *****************************************************************************/ |
Anna Bridge |
142:4eea097334d6 | 32 | /**************************************************************************//** |
Anna Bridge |
142:4eea097334d6 | 33 | * @addtogroup Parts |
Anna Bridge |
142:4eea097334d6 | 34 | * @{ |
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142:4eea097334d6 | 35 | ******************************************************************************/ |
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142:4eea097334d6 | 36 | /**************************************************************************//** |
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142:4eea097334d6 | 37 | * @defgroup EFR32MG12P_RMU |
Anna Bridge |
142:4eea097334d6 | 38 | * @{ |
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142:4eea097334d6 | 39 | * @brief EFR32MG12P_RMU Register Declaration |
Anna Bridge |
142:4eea097334d6 | 40 | *****************************************************************************/ |
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142:4eea097334d6 | 41 | typedef struct |
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142:4eea097334d6 | 42 | { |
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142:4eea097334d6 | 43 | __IOM uint32_t CTRL; /**< Control Register */ |
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142:4eea097334d6 | 44 | __IM uint32_t RSTCAUSE; /**< Reset Cause Register */ |
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142:4eea097334d6 | 45 | __IOM uint32_t CMD; /**< Command Register */ |
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142:4eea097334d6 | 46 | __IOM uint32_t RST; /**< Reset Control Register */ |
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142:4eea097334d6 | 47 | __IOM uint32_t LOCK; /**< Configuration Lock Register */ |
Anna Bridge |
142:4eea097334d6 | 48 | } RMU_TypeDef; /** @} */ |
Anna Bridge |
142:4eea097334d6 | 49 | |
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142:4eea097334d6 | 50 | /**************************************************************************//** |
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142:4eea097334d6 | 51 | * @defgroup EFR32MG12P_RMU_BitFields |
Anna Bridge |
142:4eea097334d6 | 52 | * @{ |
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142:4eea097334d6 | 53 | *****************************************************************************/ |
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142:4eea097334d6 | 54 | |
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142:4eea097334d6 | 55 | /* Bit fields for RMU CTRL */ |
Anna Bridge |
142:4eea097334d6 | 56 | #define _RMU_CTRL_RESETVALUE 0x00004204UL /**< Default value for RMU_CTRL */ |
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142:4eea097334d6 | 57 | #define _RMU_CTRL_MASK 0x03007777UL /**< Mask for RMU_CTRL */ |
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142:4eea097334d6 | 58 | #define _RMU_CTRL_WDOGRMODE_SHIFT 0 /**< Shift value for RMU_WDOGRMODE */ |
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142:4eea097334d6 | 59 | #define _RMU_CTRL_WDOGRMODE_MASK 0x7UL /**< Bit mask for RMU_WDOGRMODE */ |
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142:4eea097334d6 | 60 | #define _RMU_CTRL_WDOGRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ |
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142:4eea097334d6 | 61 | #define _RMU_CTRL_WDOGRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ |
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142:4eea097334d6 | 62 | #define _RMU_CTRL_WDOGRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ |
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142:4eea097334d6 | 63 | #define _RMU_CTRL_WDOGRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */ |
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142:4eea097334d6 | 64 | #define _RMU_CTRL_WDOGRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ |
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142:4eea097334d6 | 65 | #define RMU_CTRL_WDOGRMODE_DISABLED (_RMU_CTRL_WDOGRMODE_DISABLED << 0) /**< Shifted mode DISABLED for RMU_CTRL */ |
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142:4eea097334d6 | 66 | #define RMU_CTRL_WDOGRMODE_LIMITED (_RMU_CTRL_WDOGRMODE_LIMITED << 0) /**< Shifted mode LIMITED for RMU_CTRL */ |
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142:4eea097334d6 | 67 | #define RMU_CTRL_WDOGRMODE_EXTENDED (_RMU_CTRL_WDOGRMODE_EXTENDED << 0) /**< Shifted mode EXTENDED for RMU_CTRL */ |
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142:4eea097334d6 | 68 | #define RMU_CTRL_WDOGRMODE_DEFAULT (_RMU_CTRL_WDOGRMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */ |
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142:4eea097334d6 | 69 | #define RMU_CTRL_WDOGRMODE_FULL (_RMU_CTRL_WDOGRMODE_FULL << 0) /**< Shifted mode FULL for RMU_CTRL */ |
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142:4eea097334d6 | 70 | #define _RMU_CTRL_LOCKUPRMODE_SHIFT 4 /**< Shift value for RMU_LOCKUPRMODE */ |
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142:4eea097334d6 | 71 | #define _RMU_CTRL_LOCKUPRMODE_MASK 0x70UL /**< Bit mask for RMU_LOCKUPRMODE */ |
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142:4eea097334d6 | 72 | #define _RMU_CTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */ |
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142:4eea097334d6 | 73 | #define _RMU_CTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ |
Anna Bridge |
142:4eea097334d6 | 74 | #define _RMU_CTRL_LOCKUPRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ |
Anna Bridge |
142:4eea097334d6 | 75 | #define _RMU_CTRL_LOCKUPRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ |
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142:4eea097334d6 | 76 | #define _RMU_CTRL_LOCKUPRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ |
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142:4eea097334d6 | 77 | #define RMU_CTRL_LOCKUPRMODE_DEFAULT (_RMU_CTRL_LOCKUPRMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_CTRL */ |
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142:4eea097334d6 | 78 | #define RMU_CTRL_LOCKUPRMODE_DISABLED (_RMU_CTRL_LOCKUPRMODE_DISABLED << 4) /**< Shifted mode DISABLED for RMU_CTRL */ |
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142:4eea097334d6 | 79 | #define RMU_CTRL_LOCKUPRMODE_LIMITED (_RMU_CTRL_LOCKUPRMODE_LIMITED << 4) /**< Shifted mode LIMITED for RMU_CTRL */ |
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142:4eea097334d6 | 80 | #define RMU_CTRL_LOCKUPRMODE_EXTENDED (_RMU_CTRL_LOCKUPRMODE_EXTENDED << 4) /**< Shifted mode EXTENDED for RMU_CTRL */ |
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142:4eea097334d6 | 81 | #define RMU_CTRL_LOCKUPRMODE_FULL (_RMU_CTRL_LOCKUPRMODE_FULL << 4) /**< Shifted mode FULL for RMU_CTRL */ |
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142:4eea097334d6 | 82 | #define _RMU_CTRL_SYSRMODE_SHIFT 8 /**< Shift value for RMU_SYSRMODE */ |
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142:4eea097334d6 | 83 | #define _RMU_CTRL_SYSRMODE_MASK 0x700UL /**< Bit mask for RMU_SYSRMODE */ |
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142:4eea097334d6 | 84 | #define _RMU_CTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ |
Anna Bridge |
142:4eea097334d6 | 85 | #define _RMU_CTRL_SYSRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ |
Anna Bridge |
142:4eea097334d6 | 86 | #define _RMU_CTRL_SYSRMODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for RMU_CTRL */ |
Anna Bridge |
142:4eea097334d6 | 87 | #define _RMU_CTRL_SYSRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ |
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142:4eea097334d6 | 88 | #define _RMU_CTRL_SYSRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ |
Anna Bridge |
142:4eea097334d6 | 89 | #define RMU_CTRL_SYSRMODE_DISABLED (_RMU_CTRL_SYSRMODE_DISABLED << 8) /**< Shifted mode DISABLED for RMU_CTRL */ |
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142:4eea097334d6 | 90 | #define RMU_CTRL_SYSRMODE_LIMITED (_RMU_CTRL_SYSRMODE_LIMITED << 8) /**< Shifted mode LIMITED for RMU_CTRL */ |
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142:4eea097334d6 | 91 | #define RMU_CTRL_SYSRMODE_DEFAULT (_RMU_CTRL_SYSRMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_CTRL */ |
Anna Bridge |
142:4eea097334d6 | 92 | #define RMU_CTRL_SYSRMODE_EXTENDED (_RMU_CTRL_SYSRMODE_EXTENDED << 8) /**< Shifted mode EXTENDED for RMU_CTRL */ |
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142:4eea097334d6 | 93 | #define RMU_CTRL_SYSRMODE_FULL (_RMU_CTRL_SYSRMODE_FULL << 8) /**< Shifted mode FULL for RMU_CTRL */ |
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142:4eea097334d6 | 94 | #define _RMU_CTRL_PINRMODE_SHIFT 12 /**< Shift value for RMU_PINRMODE */ |
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142:4eea097334d6 | 95 | #define _RMU_CTRL_PINRMODE_MASK 0x7000UL /**< Bit mask for RMU_PINRMODE */ |
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142:4eea097334d6 | 96 | #define _RMU_CTRL_PINRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */ |
Anna Bridge |
142:4eea097334d6 | 97 | #define _RMU_CTRL_PINRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */ |
Anna Bridge |
142:4eea097334d6 | 98 | #define _RMU_CTRL_PINRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */ |
Anna Bridge |
142:4eea097334d6 | 99 | #define _RMU_CTRL_PINRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */ |
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142:4eea097334d6 | 100 | #define _RMU_CTRL_PINRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */ |
Anna Bridge |
142:4eea097334d6 | 101 | #define RMU_CTRL_PINRMODE_DISABLED (_RMU_CTRL_PINRMODE_DISABLED << 12) /**< Shifted mode DISABLED for RMU_CTRL */ |
Anna Bridge |
142:4eea097334d6 | 102 | #define RMU_CTRL_PINRMODE_LIMITED (_RMU_CTRL_PINRMODE_LIMITED << 12) /**< Shifted mode LIMITED for RMU_CTRL */ |
Anna Bridge |
142:4eea097334d6 | 103 | #define RMU_CTRL_PINRMODE_EXTENDED (_RMU_CTRL_PINRMODE_EXTENDED << 12) /**< Shifted mode EXTENDED for RMU_CTRL */ |
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142:4eea097334d6 | 104 | #define RMU_CTRL_PINRMODE_DEFAULT (_RMU_CTRL_PINRMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_CTRL */ |
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142:4eea097334d6 | 105 | #define RMU_CTRL_PINRMODE_FULL (_RMU_CTRL_PINRMODE_FULL << 12) /**< Shifted mode FULL for RMU_CTRL */ |
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142:4eea097334d6 | 106 | #define _RMU_CTRL_RESETSTATE_SHIFT 24 /**< Shift value for RMU_RESETSTATE */ |
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142:4eea097334d6 | 107 | #define _RMU_CTRL_RESETSTATE_MASK 0x3000000UL /**< Bit mask for RMU_RESETSTATE */ |
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142:4eea097334d6 | 108 | #define _RMU_CTRL_RESETSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */ |
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142:4eea097334d6 | 109 | #define RMU_CTRL_RESETSTATE_DEFAULT (_RMU_CTRL_RESETSTATE_DEFAULT << 24) /**< Shifted mode DEFAULT for RMU_CTRL */ |
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142:4eea097334d6 | 110 | |
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142:4eea097334d6 | 111 | /* Bit fields for RMU RSTCAUSE */ |
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142:4eea097334d6 | 112 | #define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 113 | #define _RMU_RSTCAUSE_MASK 0x00010F1DUL /**< Mask for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 114 | #define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */ |
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142:4eea097334d6 | 115 | #define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */ |
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142:4eea097334d6 | 116 | #define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */ |
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142:4eea097334d6 | 117 | #define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 118 | #define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 119 | #define RMU_RSTCAUSE_AVDDBOD (0x1UL << 2) /**< Brown Out Detector AVDD Reset */ |
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142:4eea097334d6 | 120 | #define _RMU_RSTCAUSE_AVDDBOD_SHIFT 2 /**< Shift value for RMU_AVDDBOD */ |
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142:4eea097334d6 | 121 | #define _RMU_RSTCAUSE_AVDDBOD_MASK 0x4UL /**< Bit mask for RMU_AVDDBOD */ |
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142:4eea097334d6 | 122 | #define _RMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 123 | #define RMU_RSTCAUSE_AVDDBOD_DEFAULT (_RMU_RSTCAUSE_AVDDBOD_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 124 | #define RMU_RSTCAUSE_DVDDBOD (0x1UL << 3) /**< Brown Out Detector DVDD Reset */ |
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142:4eea097334d6 | 125 | #define _RMU_RSTCAUSE_DVDDBOD_SHIFT 3 /**< Shift value for RMU_DVDDBOD */ |
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142:4eea097334d6 | 126 | #define _RMU_RSTCAUSE_DVDDBOD_MASK 0x8UL /**< Bit mask for RMU_DVDDBOD */ |
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142:4eea097334d6 | 127 | #define _RMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 128 | #define RMU_RSTCAUSE_DVDDBOD_DEFAULT (_RMU_RSTCAUSE_DVDDBOD_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 129 | #define RMU_RSTCAUSE_DECBOD (0x1UL << 4) /**< Brown Out Detector Decouple Domain Reset */ |
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142:4eea097334d6 | 130 | #define _RMU_RSTCAUSE_DECBOD_SHIFT 4 /**< Shift value for RMU_DECBOD */ |
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142:4eea097334d6 | 131 | #define _RMU_RSTCAUSE_DECBOD_MASK 0x10UL /**< Bit mask for RMU_DECBOD */ |
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142:4eea097334d6 | 132 | #define _RMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 133 | #define RMU_RSTCAUSE_DECBOD_DEFAULT (_RMU_RSTCAUSE_DECBOD_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 134 | #define RMU_RSTCAUSE_EXTRST (0x1UL << 8) /**< External Pin Reset */ |
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142:4eea097334d6 | 135 | #define _RMU_RSTCAUSE_EXTRST_SHIFT 8 /**< Shift value for RMU_EXTRST */ |
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142:4eea097334d6 | 136 | #define _RMU_RSTCAUSE_EXTRST_MASK 0x100UL /**< Bit mask for RMU_EXTRST */ |
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142:4eea097334d6 | 137 | #define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 138 | #define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 139 | #define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 9) /**< LOCKUP Reset */ |
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142:4eea097334d6 | 140 | #define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 9 /**< Shift value for RMU_LOCKUPRST */ |
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142:4eea097334d6 | 141 | #define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x200UL /**< Bit mask for RMU_LOCKUPRST */ |
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142:4eea097334d6 | 142 | #define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 143 | #define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 144 | #define RMU_RSTCAUSE_SYSREQRST (0x1UL << 10) /**< System Request Reset */ |
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142:4eea097334d6 | 145 | #define _RMU_RSTCAUSE_SYSREQRST_SHIFT 10 /**< Shift value for RMU_SYSREQRST */ |
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142:4eea097334d6 | 146 | #define _RMU_RSTCAUSE_SYSREQRST_MASK 0x400UL /**< Bit mask for RMU_SYSREQRST */ |
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142:4eea097334d6 | 147 | #define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 148 | #define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 149 | #define RMU_RSTCAUSE_WDOGRST (0x1UL << 11) /**< Watchdog Reset */ |
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142:4eea097334d6 | 150 | #define _RMU_RSTCAUSE_WDOGRST_SHIFT 11 /**< Shift value for RMU_WDOGRST */ |
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142:4eea097334d6 | 151 | #define _RMU_RSTCAUSE_WDOGRST_MASK 0x800UL /**< Bit mask for RMU_WDOGRST */ |
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142:4eea097334d6 | 152 | #define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 153 | #define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 154 | #define RMU_RSTCAUSE_EM4RST (0x1UL << 16) /**< EM4 Reset */ |
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142:4eea097334d6 | 155 | #define _RMU_RSTCAUSE_EM4RST_SHIFT 16 /**< Shift value for RMU_EM4RST */ |
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142:4eea097334d6 | 156 | #define _RMU_RSTCAUSE_EM4RST_MASK 0x10000UL /**< Bit mask for RMU_EM4RST */ |
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142:4eea097334d6 | 157 | #define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 158 | #define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 16) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */ |
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142:4eea097334d6 | 159 | |
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142:4eea097334d6 | 160 | /* Bit fields for RMU CMD */ |
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142:4eea097334d6 | 161 | #define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */ |
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142:4eea097334d6 | 162 | #define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */ |
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142:4eea097334d6 | 163 | #define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */ |
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142:4eea097334d6 | 164 | #define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */ |
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142:4eea097334d6 | 165 | #define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */ |
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142:4eea097334d6 | 166 | #define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */ |
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142:4eea097334d6 | 167 | #define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */ |
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142:4eea097334d6 | 168 | |
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142:4eea097334d6 | 169 | /* Bit fields for RMU RST */ |
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142:4eea097334d6 | 170 | #define _RMU_RST_RESETVALUE 0x00000000UL /**< Default value for RMU_RST */ |
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142:4eea097334d6 | 171 | #define _RMU_RST_MASK 0x00000000UL /**< Mask for RMU_RST */ |
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142:4eea097334d6 | 172 | |
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142:4eea097334d6 | 173 | /* Bit fields for RMU LOCK */ |
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142:4eea097334d6 | 174 | #define _RMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for RMU_LOCK */ |
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142:4eea097334d6 | 175 | #define _RMU_LOCK_MASK 0x0000FFFFUL /**< Mask for RMU_LOCK */ |
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142:4eea097334d6 | 176 | #define _RMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RMU_LOCKKEY */ |
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142:4eea097334d6 | 177 | #define _RMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RMU_LOCKKEY */ |
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142:4eea097334d6 | 178 | #define _RMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_LOCK */ |
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142:4eea097334d6 | 179 | #define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */ |
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142:4eea097334d6 | 180 | #define _RMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RMU_LOCK */ |
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142:4eea097334d6 | 181 | #define _RMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RMU_LOCK */ |
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142:4eea097334d6 | 182 | #define _RMU_LOCK_LOCKKEY_UNLOCK 0x0000E084UL /**< Mode UNLOCK for RMU_LOCK */ |
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142:4eea097334d6 | 183 | #define RMU_LOCK_LOCKKEY_DEFAULT (_RMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_LOCK */ |
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142:4eea097334d6 | 184 | #define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */ |
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142:4eea097334d6 | 185 | #define RMU_LOCK_LOCKKEY_UNLOCKED (_RMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RMU_LOCK */ |
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142:4eea097334d6 | 186 | #define RMU_LOCK_LOCKKEY_LOCKED (_RMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RMU_LOCK */ |
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142:4eea097334d6 | 187 | #define RMU_LOCK_LOCKKEY_UNLOCK (_RMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RMU_LOCK */ |
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142:4eea097334d6 | 188 | |
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142:4eea097334d6 | 189 | /** @} End of group EFR32MG12P_RMU */ |
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142:4eea097334d6 | 190 | /** @} End of group Parts */ |
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142:4eea097334d6 | 191 |