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TARGET_NUCLEO_F429ZI/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_dfsdm.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_DISCO_F407VG/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.h@163:e59c8e839560
mbed library. Release version 164
Who changed what in which revision?
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AnnaBridge | 161:aa5281ff4a02 | 1 | /** |
AnnaBridge | 161:aa5281ff4a02 | 2 | ****************************************************************************** |
AnnaBridge | 161:aa5281ff4a02 | 3 | * @file stm32f4xx_hal_dfsdm.h |
AnnaBridge | 161:aa5281ff4a02 | 4 | * @author MCD Application Team |
AnnaBridge | 161:aa5281ff4a02 | 5 | * @brief Header file of DFSDM HAL module. |
AnnaBridge | 161:aa5281ff4a02 | 6 | ****************************************************************************** |
AnnaBridge | 161:aa5281ff4a02 | 7 | * @attention |
AnnaBridge | 161:aa5281ff4a02 | 8 | * |
AnnaBridge | 161:aa5281ff4a02 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
AnnaBridge | 161:aa5281ff4a02 | 10 | * |
AnnaBridge | 161:aa5281ff4a02 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 161:aa5281ff4a02 | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 161:aa5281ff4a02 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 161:aa5281ff4a02 | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 161:aa5281ff4a02 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 161:aa5281ff4a02 | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 161:aa5281ff4a02 | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 161:aa5281ff4a02 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 161:aa5281ff4a02 | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 161:aa5281ff4a02 | 20 | * without specific prior written permission. |
AnnaBridge | 161:aa5281ff4a02 | 21 | * |
AnnaBridge | 161:aa5281ff4a02 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 161:aa5281ff4a02 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 161:aa5281ff4a02 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 161:aa5281ff4a02 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 161:aa5281ff4a02 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 161:aa5281ff4a02 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 161:aa5281ff4a02 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 161:aa5281ff4a02 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 161:aa5281ff4a02 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 161:aa5281ff4a02 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 161:aa5281ff4a02 | 32 | * |
AnnaBridge | 161:aa5281ff4a02 | 33 | ****************************************************************************** |
AnnaBridge | 161:aa5281ff4a02 | 34 | */ |
AnnaBridge | 161:aa5281ff4a02 | 35 | |
AnnaBridge | 161:aa5281ff4a02 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 37 | #ifndef __STM32F4xx_HAL_DFSDM_H |
AnnaBridge | 161:aa5281ff4a02 | 38 | #define __STM32F4xx_HAL_DFSDM_H |
AnnaBridge | 161:aa5281ff4a02 | 39 | |
AnnaBridge | 161:aa5281ff4a02 | 40 | #ifdef __cplusplus |
AnnaBridge | 161:aa5281ff4a02 | 41 | extern "C" { |
AnnaBridge | 161:aa5281ff4a02 | 42 | #endif |
AnnaBridge | 161:aa5281ff4a02 | 43 | |
AnnaBridge | 161:aa5281ff4a02 | 44 | #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) |
AnnaBridge | 161:aa5281ff4a02 | 45 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 46 | #include "stm32f4xx_hal_def.h" |
AnnaBridge | 161:aa5281ff4a02 | 47 | |
AnnaBridge | 161:aa5281ff4a02 | 48 | /** @addtogroup STM32F4xx_HAL_Driver |
AnnaBridge | 161:aa5281ff4a02 | 49 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 50 | */ |
AnnaBridge | 161:aa5281ff4a02 | 51 | |
AnnaBridge | 161:aa5281ff4a02 | 52 | /** @addtogroup DFSDM |
AnnaBridge | 161:aa5281ff4a02 | 53 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 54 | */ |
AnnaBridge | 161:aa5281ff4a02 | 55 | |
AnnaBridge | 161:aa5281ff4a02 | 56 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 57 | /** @defgroup DFSDM_Exported_Types DFSDM Exported Types |
AnnaBridge | 161:aa5281ff4a02 | 58 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 59 | */ |
AnnaBridge | 161:aa5281ff4a02 | 60 | |
AnnaBridge | 161:aa5281ff4a02 | 61 | /** |
AnnaBridge | 161:aa5281ff4a02 | 62 | * @brief HAL DFSDM Channel states definition |
AnnaBridge | 161:aa5281ff4a02 | 63 | */ |
AnnaBridge | 161:aa5281ff4a02 | 64 | typedef enum |
AnnaBridge | 161:aa5281ff4a02 | 65 | { |
AnnaBridge | 161:aa5281ff4a02 | 66 | HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ |
AnnaBridge | 161:aa5281ff4a02 | 67 | HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */ |
AnnaBridge | 161:aa5281ff4a02 | 68 | HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ |
AnnaBridge | 161:aa5281ff4a02 | 69 | }HAL_DFSDM_Channel_StateTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 70 | |
AnnaBridge | 161:aa5281ff4a02 | 71 | /** |
AnnaBridge | 161:aa5281ff4a02 | 72 | * @brief DFSDM channel output clock structure definition |
AnnaBridge | 161:aa5281ff4a02 | 73 | */ |
AnnaBridge | 161:aa5281ff4a02 | 74 | typedef struct |
AnnaBridge | 161:aa5281ff4a02 | 75 | { |
AnnaBridge | 161:aa5281ff4a02 | 76 | FunctionalState Activation; /*!< Output clock enable/disable */ |
AnnaBridge | 161:aa5281ff4a02 | 77 | uint32_t Selection; /*!< Output clock is system clock or audio clock. |
AnnaBridge | 161:aa5281ff4a02 | 78 | This parameter can be a value of @ref DFSDM_Channel_OuputClock */ |
AnnaBridge | 161:aa5281ff4a02 | 79 | uint32_t Divider; /*!< Output clock divider. |
AnnaBridge | 161:aa5281ff4a02 | 80 | This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ |
AnnaBridge | 161:aa5281ff4a02 | 81 | }DFSDM_Channel_OutputClockTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 82 | |
AnnaBridge | 161:aa5281ff4a02 | 83 | /** |
AnnaBridge | 161:aa5281ff4a02 | 84 | * @brief DFSDM channel input structure definition |
AnnaBridge | 161:aa5281ff4a02 | 85 | */ |
AnnaBridge | 161:aa5281ff4a02 | 86 | typedef struct |
AnnaBridge | 161:aa5281ff4a02 | 87 | { |
AnnaBridge | 161:aa5281ff4a02 | 88 | uint32_t Multiplexer; /*!< Input is external serial inputs or internal register. |
AnnaBridge | 161:aa5281ff4a02 | 89 | This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ |
AnnaBridge | 161:aa5281ff4a02 | 90 | uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. |
AnnaBridge | 161:aa5281ff4a02 | 91 | This parameter can be a value of @ref DFSDM_Channel_DataPacking */ |
AnnaBridge | 161:aa5281ff4a02 | 92 | uint32_t Pins; /*!< Input pins are taken from same or following channel. |
AnnaBridge | 161:aa5281ff4a02 | 93 | This parameter can be a value of @ref DFSDM_Channel_InputPins */ |
AnnaBridge | 161:aa5281ff4a02 | 94 | }DFSDM_Channel_InputTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 95 | |
AnnaBridge | 161:aa5281ff4a02 | 96 | /** |
AnnaBridge | 161:aa5281ff4a02 | 97 | * @brief DFSDM channel serial interface structure definition |
AnnaBridge | 161:aa5281ff4a02 | 98 | */ |
AnnaBridge | 161:aa5281ff4a02 | 99 | typedef struct |
AnnaBridge | 161:aa5281ff4a02 | 100 | { |
AnnaBridge | 161:aa5281ff4a02 | 101 | uint32_t Type; /*!< SPI or Manchester modes. |
AnnaBridge | 161:aa5281ff4a02 | 102 | This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ |
AnnaBridge | 161:aa5281ff4a02 | 103 | uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). |
AnnaBridge | 161:aa5281ff4a02 | 104 | This parameter can be a value of @ref DFSDM_Channel_SpiClock */ |
AnnaBridge | 161:aa5281ff4a02 | 105 | }DFSDM_Channel_SerialInterfaceTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 106 | |
AnnaBridge | 161:aa5281ff4a02 | 107 | /** |
AnnaBridge | 161:aa5281ff4a02 | 108 | * @brief DFSDM channel analog watchdog structure definition |
AnnaBridge | 161:aa5281ff4a02 | 109 | */ |
AnnaBridge | 161:aa5281ff4a02 | 110 | typedef struct |
AnnaBridge | 161:aa5281ff4a02 | 111 | { |
AnnaBridge | 161:aa5281ff4a02 | 112 | uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. |
AnnaBridge | 161:aa5281ff4a02 | 113 | This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ |
AnnaBridge | 161:aa5281ff4a02 | 114 | uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. |
AnnaBridge | 161:aa5281ff4a02 | 115 | This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ |
AnnaBridge | 161:aa5281ff4a02 | 116 | }DFSDM_Channel_AwdTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 117 | |
AnnaBridge | 161:aa5281ff4a02 | 118 | /** |
AnnaBridge | 161:aa5281ff4a02 | 119 | * @brief DFSDM channel init structure definition |
AnnaBridge | 161:aa5281ff4a02 | 120 | */ |
AnnaBridge | 161:aa5281ff4a02 | 121 | typedef struct |
AnnaBridge | 161:aa5281ff4a02 | 122 | { |
AnnaBridge | 161:aa5281ff4a02 | 123 | DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ |
AnnaBridge | 161:aa5281ff4a02 | 124 | DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */ |
AnnaBridge | 161:aa5281ff4a02 | 125 | DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */ |
AnnaBridge | 161:aa5281ff4a02 | 126 | DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */ |
AnnaBridge | 161:aa5281ff4a02 | 127 | int32_t Offset; /*!< DFSDM channel offset. |
AnnaBridge | 161:aa5281ff4a02 | 128 | This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ |
AnnaBridge | 161:aa5281ff4a02 | 129 | uint32_t RightBitShift; /*!< DFSDM channel right bit shift. |
AnnaBridge | 161:aa5281ff4a02 | 130 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
AnnaBridge | 161:aa5281ff4a02 | 131 | }DFSDM_Channel_InitTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 132 | |
AnnaBridge | 161:aa5281ff4a02 | 133 | /** |
AnnaBridge | 161:aa5281ff4a02 | 134 | * @brief DFSDM channel handle structure definition |
AnnaBridge | 161:aa5281ff4a02 | 135 | */ |
AnnaBridge | 161:aa5281ff4a02 | 136 | typedef struct |
AnnaBridge | 161:aa5281ff4a02 | 137 | { |
AnnaBridge | 161:aa5281ff4a02 | 138 | DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ |
AnnaBridge | 161:aa5281ff4a02 | 139 | DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ |
AnnaBridge | 161:aa5281ff4a02 | 140 | HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ |
AnnaBridge | 161:aa5281ff4a02 | 141 | }DFSDM_Channel_HandleTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 142 | |
AnnaBridge | 161:aa5281ff4a02 | 143 | /** |
AnnaBridge | 161:aa5281ff4a02 | 144 | * @brief HAL DFSDM Filter states definition |
AnnaBridge | 161:aa5281ff4a02 | 145 | */ |
AnnaBridge | 161:aa5281ff4a02 | 146 | typedef enum |
AnnaBridge | 161:aa5281ff4a02 | 147 | { |
AnnaBridge | 161:aa5281ff4a02 | 148 | HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ |
AnnaBridge | 161:aa5281ff4a02 | 149 | HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */ |
AnnaBridge | 161:aa5281ff4a02 | 150 | HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */ |
AnnaBridge | 161:aa5281ff4a02 | 151 | HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */ |
AnnaBridge | 161:aa5281ff4a02 | 152 | HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */ |
AnnaBridge | 161:aa5281ff4a02 | 153 | HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ |
AnnaBridge | 161:aa5281ff4a02 | 154 | }HAL_DFSDM_Filter_StateTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 155 | |
AnnaBridge | 161:aa5281ff4a02 | 156 | /** |
AnnaBridge | 161:aa5281ff4a02 | 157 | * @brief DFSDM filter regular conversion parameters structure definition |
AnnaBridge | 161:aa5281ff4a02 | 158 | */ |
AnnaBridge | 161:aa5281ff4a02 | 159 | typedef struct |
AnnaBridge | 161:aa5281ff4a02 | 160 | { |
AnnaBridge | 161:aa5281ff4a02 | 161 | uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. |
AnnaBridge | 161:aa5281ff4a02 | 162 | This parameter can be a value of @ref DFSDM_Filter_Trigger */ |
AnnaBridge | 161:aa5281ff4a02 | 163 | FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ |
AnnaBridge | 161:aa5281ff4a02 | 164 | FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ |
AnnaBridge | 161:aa5281ff4a02 | 165 | }DFSDM_Filter_RegularParamTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 166 | |
AnnaBridge | 161:aa5281ff4a02 | 167 | /** |
AnnaBridge | 161:aa5281ff4a02 | 168 | * @brief DFSDM filter injected conversion parameters structure definition |
AnnaBridge | 161:aa5281ff4a02 | 169 | */ |
AnnaBridge | 161:aa5281ff4a02 | 170 | typedef struct |
AnnaBridge | 161:aa5281ff4a02 | 171 | { |
AnnaBridge | 161:aa5281ff4a02 | 172 | uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. |
AnnaBridge | 161:aa5281ff4a02 | 173 | This parameter can be a value of @ref DFSDM_Filter_Trigger */ |
AnnaBridge | 161:aa5281ff4a02 | 174 | FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */ |
AnnaBridge | 161:aa5281ff4a02 | 175 | FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */ |
AnnaBridge | 161:aa5281ff4a02 | 176 | uint32_t ExtTrigger; /*!< External trigger. |
AnnaBridge | 161:aa5281ff4a02 | 177 | This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ |
AnnaBridge | 161:aa5281ff4a02 | 178 | uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. |
AnnaBridge | 161:aa5281ff4a02 | 179 | This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ |
AnnaBridge | 161:aa5281ff4a02 | 180 | }DFSDM_Filter_InjectedParamTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 181 | |
AnnaBridge | 161:aa5281ff4a02 | 182 | /** |
AnnaBridge | 161:aa5281ff4a02 | 183 | * @brief DFSDM filter parameters structure definition |
AnnaBridge | 161:aa5281ff4a02 | 184 | */ |
AnnaBridge | 161:aa5281ff4a02 | 185 | typedef struct |
AnnaBridge | 161:aa5281ff4a02 | 186 | { |
AnnaBridge | 161:aa5281ff4a02 | 187 | uint32_t SincOrder; /*!< Sinc filter order. |
AnnaBridge | 161:aa5281ff4a02 | 188 | This parameter can be a value of @ref DFSDM_Filter_SincOrder */ |
AnnaBridge | 161:aa5281ff4a02 | 189 | uint32_t Oversampling; /*!< Filter oversampling ratio. |
AnnaBridge | 161:aa5281ff4a02 | 190 | This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ |
AnnaBridge | 161:aa5281ff4a02 | 191 | uint32_t IntOversampling; /*!< Integrator oversampling ratio. |
AnnaBridge | 161:aa5281ff4a02 | 192 | This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ |
AnnaBridge | 161:aa5281ff4a02 | 193 | }DFSDM_Filter_FilterParamTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 194 | |
AnnaBridge | 161:aa5281ff4a02 | 195 | /** |
AnnaBridge | 161:aa5281ff4a02 | 196 | * @brief DFSDM filter init structure definition |
AnnaBridge | 161:aa5281ff4a02 | 197 | */ |
AnnaBridge | 161:aa5281ff4a02 | 198 | typedef struct |
AnnaBridge | 161:aa5281ff4a02 | 199 | { |
AnnaBridge | 161:aa5281ff4a02 | 200 | DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ |
AnnaBridge | 161:aa5281ff4a02 | 201 | DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ |
AnnaBridge | 161:aa5281ff4a02 | 202 | DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ |
AnnaBridge | 161:aa5281ff4a02 | 203 | }DFSDM_Filter_InitTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 204 | |
AnnaBridge | 161:aa5281ff4a02 | 205 | /** |
AnnaBridge | 161:aa5281ff4a02 | 206 | * @brief DFSDM filter handle structure definition |
AnnaBridge | 161:aa5281ff4a02 | 207 | */ |
AnnaBridge | 161:aa5281ff4a02 | 208 | typedef struct |
AnnaBridge | 161:aa5281ff4a02 | 209 | { |
AnnaBridge | 161:aa5281ff4a02 | 210 | DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ |
AnnaBridge | 161:aa5281ff4a02 | 211 | DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ |
AnnaBridge | 161:aa5281ff4a02 | 212 | DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */ |
AnnaBridge | 161:aa5281ff4a02 | 213 | DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */ |
AnnaBridge | 161:aa5281ff4a02 | 214 | uint32_t RegularContMode; /*!< Regular conversion continuous mode */ |
AnnaBridge | 161:aa5281ff4a02 | 215 | uint32_t RegularTrigger; /*!< Trigger used for regular conversion */ |
AnnaBridge | 161:aa5281ff4a02 | 216 | uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */ |
AnnaBridge | 161:aa5281ff4a02 | 217 | uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ |
AnnaBridge | 161:aa5281ff4a02 | 218 | FunctionalState InjectedScanMode; /*!< Injected scanning mode */ |
AnnaBridge | 161:aa5281ff4a02 | 219 | uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ |
AnnaBridge | 161:aa5281ff4a02 | 220 | uint32_t InjConvRemaining; /*!< Injected conversions remaining */ |
AnnaBridge | 161:aa5281ff4a02 | 221 | HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ |
AnnaBridge | 161:aa5281ff4a02 | 222 | uint32_t ErrorCode; /*!< DFSDM filter error code */ |
AnnaBridge | 161:aa5281ff4a02 | 223 | }DFSDM_Filter_HandleTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 224 | |
AnnaBridge | 161:aa5281ff4a02 | 225 | /** |
AnnaBridge | 161:aa5281ff4a02 | 226 | * @brief DFSDM filter analog watchdog parameters structure definition |
AnnaBridge | 161:aa5281ff4a02 | 227 | */ |
AnnaBridge | 161:aa5281ff4a02 | 228 | typedef struct |
AnnaBridge | 161:aa5281ff4a02 | 229 | { |
AnnaBridge | 161:aa5281ff4a02 | 230 | uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. |
AnnaBridge | 161:aa5281ff4a02 | 231 | This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */ |
AnnaBridge | 161:aa5281ff4a02 | 232 | uint32_t Channel; /*!< Analog watchdog channel selection. |
AnnaBridge | 161:aa5281ff4a02 | 233 | This parameter can be a values combination of @ref DFSDM_Channel_Selection */ |
AnnaBridge | 161:aa5281ff4a02 | 234 | int32_t HighThreshold; /*!< High threshold for the analog watchdog. |
AnnaBridge | 161:aa5281ff4a02 | 235 | This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ |
AnnaBridge | 161:aa5281ff4a02 | 236 | int32_t LowThreshold; /*!< Low threshold for the analog watchdog. |
AnnaBridge | 161:aa5281ff4a02 | 237 | This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ |
AnnaBridge | 161:aa5281ff4a02 | 238 | uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event. |
AnnaBridge | 161:aa5281ff4a02 | 239 | This parameter can be a values combination of @ref DFSDM_BreakSignals */ |
AnnaBridge | 161:aa5281ff4a02 | 240 | uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. |
AnnaBridge | 161:aa5281ff4a02 | 241 | This parameter can be a values combination of @ref DFSDM_BreakSignals */ |
AnnaBridge | 161:aa5281ff4a02 | 242 | }DFSDM_Filter_AwdParamTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 243 | |
AnnaBridge | 161:aa5281ff4a02 | 244 | /** |
AnnaBridge | 161:aa5281ff4a02 | 245 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 246 | */ |
AnnaBridge | 161:aa5281ff4a02 | 247 | #if defined(SYSCFG_MCHDLYCR_BSCKSEL) |
AnnaBridge | 161:aa5281ff4a02 | 248 | /** |
AnnaBridge | 161:aa5281ff4a02 | 249 | * @brief Synchronization parameters structure definition for STM32F413xx/STM32F423xx devices |
AnnaBridge | 161:aa5281ff4a02 | 250 | */ |
AnnaBridge | 161:aa5281ff4a02 | 251 | typedef struct |
AnnaBridge | 161:aa5281ff4a02 | 252 | { |
AnnaBridge | 161:aa5281ff4a02 | 253 | uint32_t DFSDM1ClockIn; /*!< Source selection for DFSDM1_Ckin. |
AnnaBridge | 161:aa5281ff4a02 | 254 | This parameter can be a value of @ref DFSDM_1_CLOCKIN_SELECTION*/ |
AnnaBridge | 161:aa5281ff4a02 | 255 | uint32_t DFSDM2ClockIn; /*!< Source selection for DFSDM2_Ckin. |
AnnaBridge | 161:aa5281ff4a02 | 256 | This parameter can be a value of @ref DFSDM_2_CLOCKIN_SELECTION*/ |
AnnaBridge | 161:aa5281ff4a02 | 257 | uint32_t DFSDM1ClockOut; /*!< Source selection for DFSDM1_Ckout. |
AnnaBridge | 161:aa5281ff4a02 | 258 | This parameter can be a value of @ref DFSDM_1_CLOCKOUT_SELECTION*/ |
AnnaBridge | 161:aa5281ff4a02 | 259 | uint32_t DFSDM2ClockOut; /*!< Source selection for DFSDM2_Ckout. |
AnnaBridge | 161:aa5281ff4a02 | 260 | This parameter can be a value of @ref DFSDM_2_CLOCKOUT_SELECTION*/ |
AnnaBridge | 161:aa5281ff4a02 | 261 | uint32_t DFSDM1BitClkDistribution; /*!< Distribution of the DFSDM1 bitstream clock gated by TIM4 OC1 or TIM4 OC2. |
AnnaBridge | 161:aa5281ff4a02 | 262 | This parameter can be a value of @ref DFSDM_1_BIT_STREAM_DISTRIBUTION |
AnnaBridge | 161:aa5281ff4a02 | 263 | @note The DFSDM2 audio gated by TIM4 OC2 can be injected on CKIN0 or CKIN2 |
AnnaBridge | 161:aa5281ff4a02 | 264 | @note The DFSDM2 audio gated by TIM4 OC1 can be injected on CKIN1 or CKIN3 */ |
AnnaBridge | 161:aa5281ff4a02 | 265 | uint32_t DFSDM2BitClkDistribution; /*!< Distribution of the DFSDM2 bitstream clock gated by TIM3 OC1 or TIM3 OC2 or TIM3 OC3 or TIM3 OC4. |
AnnaBridge | 161:aa5281ff4a02 | 266 | This parameter can be a value of @ref DFSDM_2_BIT_STREAM_DISTRIBUTION |
AnnaBridge | 161:aa5281ff4a02 | 267 | @note The DFSDM2 audio gated by TIM3 OC4 can be injected on CKIN0 or CKIN4 |
AnnaBridge | 161:aa5281ff4a02 | 268 | @note The DFSDM2 audio gated by TIM3 OC3 can be injected on CKIN1 or CKIN5 |
AnnaBridge | 161:aa5281ff4a02 | 269 | @note The DFSDM2 audio gated by TIM3 OC2 can be injected on CKIN2 or CKIN6 |
AnnaBridge | 161:aa5281ff4a02 | 270 | @note The DFSDM2 audio gated by TIM3 OC1 can be injected on CKIN3 or CKIN7 */ |
AnnaBridge | 161:aa5281ff4a02 | 271 | uint32_t DFSDM1DataDistribution; /*!< Source selection for DatIn0 and DatIn2 of DFSDM1. |
AnnaBridge | 161:aa5281ff4a02 | 272 | This parameter can be a value of @ref DFSDM_1_DATA_DISTRIBUTION */ |
AnnaBridge | 161:aa5281ff4a02 | 273 | uint32_t DFSDM2DataDistribution; /*!< Source selection for DatIn0, DatIn2, DatIn4 and DatIn6 of DFSDM2. |
AnnaBridge | 161:aa5281ff4a02 | 274 | This parameter can be a value of @ref DFSDM_2_DATA_DISTRIBUTION */ |
AnnaBridge | 161:aa5281ff4a02 | 275 | }DFSDM_MultiChannelConfigTypeDef; |
AnnaBridge | 161:aa5281ff4a02 | 276 | #endif /* SYSCFG_MCHDLYCR_BSCKSEL */ |
AnnaBridge | 161:aa5281ff4a02 | 277 | /** |
AnnaBridge | 161:aa5281ff4a02 | 278 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 279 | */ |
AnnaBridge | 161:aa5281ff4a02 | 280 | |
AnnaBridge | 161:aa5281ff4a02 | 281 | /* End of exported types -----------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 282 | |
AnnaBridge | 161:aa5281ff4a02 | 283 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 284 | /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants |
AnnaBridge | 161:aa5281ff4a02 | 285 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 286 | */ |
AnnaBridge | 161:aa5281ff4a02 | 287 | |
AnnaBridge | 161:aa5281ff4a02 | 288 | /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection |
AnnaBridge | 161:aa5281ff4a02 | 289 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 290 | */ |
AnnaBridge | 161:aa5281ff4a02 | 291 | #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */ |
AnnaBridge | 161:aa5281ff4a02 | 292 | #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ |
AnnaBridge | 161:aa5281ff4a02 | 293 | /** |
AnnaBridge | 161:aa5281ff4a02 | 294 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 295 | */ |
AnnaBridge | 161:aa5281ff4a02 | 296 | |
AnnaBridge | 161:aa5281ff4a02 | 297 | /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer |
AnnaBridge | 161:aa5281ff4a02 | 298 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 299 | */ |
AnnaBridge | 161:aa5281ff4a02 | 300 | #define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U /*!< Data are taken from external inputs */ |
AnnaBridge | 161:aa5281ff4a02 | 301 | #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ |
AnnaBridge | 161:aa5281ff4a02 | 302 | /** |
AnnaBridge | 161:aa5281ff4a02 | 303 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 304 | */ |
AnnaBridge | 161:aa5281ff4a02 | 305 | |
AnnaBridge | 161:aa5281ff4a02 | 306 | /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing |
AnnaBridge | 161:aa5281ff4a02 | 307 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 308 | */ |
AnnaBridge | 161:aa5281ff4a02 | 309 | #define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U /*!< Standard data packing mode */ |
AnnaBridge | 161:aa5281ff4a02 | 310 | #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ |
AnnaBridge | 161:aa5281ff4a02 | 311 | #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ |
AnnaBridge | 161:aa5281ff4a02 | 312 | /** |
AnnaBridge | 161:aa5281ff4a02 | 313 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 314 | */ |
AnnaBridge | 161:aa5281ff4a02 | 315 | |
AnnaBridge | 161:aa5281ff4a02 | 316 | /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins |
AnnaBridge | 161:aa5281ff4a02 | 317 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 318 | */ |
AnnaBridge | 161:aa5281ff4a02 | 319 | #define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */ |
AnnaBridge | 161:aa5281ff4a02 | 320 | #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ |
AnnaBridge | 161:aa5281ff4a02 | 321 | /** |
AnnaBridge | 161:aa5281ff4a02 | 322 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 323 | */ |
AnnaBridge | 161:aa5281ff4a02 | 324 | |
AnnaBridge | 161:aa5281ff4a02 | 325 | /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type |
AnnaBridge | 161:aa5281ff4a02 | 326 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 327 | */ |
AnnaBridge | 161:aa5281ff4a02 | 328 | #define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */ |
AnnaBridge | 161:aa5281ff4a02 | 329 | #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ |
AnnaBridge | 161:aa5281ff4a02 | 330 | #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ |
AnnaBridge | 161:aa5281ff4a02 | 331 | #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ |
AnnaBridge | 161:aa5281ff4a02 | 332 | /** |
AnnaBridge | 161:aa5281ff4a02 | 333 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 334 | */ |
AnnaBridge | 161:aa5281ff4a02 | 335 | |
AnnaBridge | 161:aa5281ff4a02 | 336 | /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection |
AnnaBridge | 161:aa5281ff4a02 | 337 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 338 | */ |
AnnaBridge | 161:aa5281ff4a02 | 339 | #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U /*!< External SPI clock */ |
AnnaBridge | 161:aa5281ff4a02 | 340 | #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ |
AnnaBridge | 161:aa5281ff4a02 | 341 | #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ |
AnnaBridge | 161:aa5281ff4a02 | 342 | #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ |
AnnaBridge | 161:aa5281ff4a02 | 343 | /** |
AnnaBridge | 161:aa5281ff4a02 | 344 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 345 | */ |
AnnaBridge | 161:aa5281ff4a02 | 346 | |
AnnaBridge | 161:aa5281ff4a02 | 347 | /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order |
AnnaBridge | 161:aa5281ff4a02 | 348 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 349 | */ |
AnnaBridge | 161:aa5281ff4a02 | 350 | #define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ |
AnnaBridge | 161:aa5281ff4a02 | 351 | #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ |
AnnaBridge | 161:aa5281ff4a02 | 352 | #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ |
AnnaBridge | 161:aa5281ff4a02 | 353 | #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ |
AnnaBridge | 161:aa5281ff4a02 | 354 | /** |
AnnaBridge | 161:aa5281ff4a02 | 355 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 356 | */ |
AnnaBridge | 161:aa5281ff4a02 | 357 | |
AnnaBridge | 161:aa5281ff4a02 | 358 | /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger |
AnnaBridge | 161:aa5281ff4a02 | 359 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 360 | */ |
AnnaBridge | 161:aa5281ff4a02 | 361 | #define DFSDM_FILTER_SW_TRIGGER 0x00000000U /*!< Software trigger */ |
AnnaBridge | 161:aa5281ff4a02 | 362 | #define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */ |
AnnaBridge | 161:aa5281ff4a02 | 363 | #define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /*!< External trigger (only for injected conversion) */ |
AnnaBridge | 161:aa5281ff4a02 | 364 | /** |
AnnaBridge | 161:aa5281ff4a02 | 365 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 366 | */ |
AnnaBridge | 161:aa5281ff4a02 | 367 | |
AnnaBridge | 161:aa5281ff4a02 | 368 | /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger |
AnnaBridge | 161:aa5281ff4a02 | 369 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 370 | */ |
AnnaBridge | 161:aa5281ff4a02 | 371 | #if defined(STM32F413xx) || defined(STM32F423xx) |
AnnaBridge | 161:aa5281ff4a02 | 372 | /* Trigger for stm32f413xx and STM32f423xx devices */ |
AnnaBridge | 161:aa5281ff4a02 | 373 | #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For All DFSDM1/2 filters */ |
AnnaBridge | 161:aa5281ff4a02 | 374 | #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0 /*!< For All DFSDM1/2 filters */ |
AnnaBridge | 161:aa5281ff4a02 | 375 | #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For All DFSDM1/2 filters */ |
AnnaBridge | 161:aa5281ff4a02 | 376 | #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0, 1 and 2 */ |
AnnaBridge | 161:aa5281ff4a02 | 377 | #define DFSDM_FILTER_EXT_TRIG_TIM2_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM2 filter 3 */ |
AnnaBridge | 161:aa5281ff4a02 | 378 | #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0, 1 and 2 */ |
AnnaBridge | 161:aa5281ff4a02 | 379 | #define DFSDM_FILTER_EXT_TRIG_TIM11_OC1 DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM2 filter 3 */ |
AnnaBridge | 161:aa5281ff4a02 | 380 | #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0 and 1 */ |
AnnaBridge | 161:aa5281ff4a02 | 381 | #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM2 filter 2 and 3*/ |
AnnaBridge | 161:aa5281ff4a02 | 382 | #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For All DFSDM1/2 filters */ |
AnnaBridge | 161:aa5281ff4a02 | 383 | #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For All DFSDM1/2 filters */ |
AnnaBridge | 161:aa5281ff4a02 | 384 | #else |
AnnaBridge | 161:aa5281ff4a02 | 385 | /* Trigger for stm32f412xx devices */ |
AnnaBridge | 161:aa5281ff4a02 | 386 | #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM1 filter 0 and 1*/ |
AnnaBridge | 161:aa5281ff4a02 | 387 | #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM1 filter 0 and 1*/ |
AnnaBridge | 161:aa5281ff4a02 | 388 | #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM1 filter 0 and 1*/ |
AnnaBridge | 161:aa5281ff4a02 | 389 | #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM1 filter 0 and 1*/ |
AnnaBridge | 161:aa5281ff4a02 | 390 | #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM1 filter 0 and 1*/ |
AnnaBridge | 161:aa5281ff4a02 | 391 | #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1*/ |
AnnaBridge | 161:aa5281ff4a02 | 392 | #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1*/ |
AnnaBridge | 161:aa5281ff4a02 | 393 | #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM1 filter 0 and 1*/ |
AnnaBridge | 161:aa5281ff4a02 | 394 | #endif |
AnnaBridge | 161:aa5281ff4a02 | 395 | /** |
AnnaBridge | 161:aa5281ff4a02 | 396 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 397 | */ |
AnnaBridge | 161:aa5281ff4a02 | 398 | |
AnnaBridge | 161:aa5281ff4a02 | 399 | /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge |
AnnaBridge | 161:aa5281ff4a02 | 400 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 401 | */ |
AnnaBridge | 161:aa5281ff4a02 | 402 | #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */ |
AnnaBridge | 161:aa5281ff4a02 | 403 | #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */ |
AnnaBridge | 161:aa5281ff4a02 | 404 | #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */ |
AnnaBridge | 161:aa5281ff4a02 | 405 | /** |
AnnaBridge | 161:aa5281ff4a02 | 406 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 407 | */ |
AnnaBridge | 161:aa5281ff4a02 | 408 | |
AnnaBridge | 161:aa5281ff4a02 | 409 | /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order |
AnnaBridge | 161:aa5281ff4a02 | 410 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 411 | */ |
AnnaBridge | 161:aa5281ff4a02 | 412 | #define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ |
AnnaBridge | 161:aa5281ff4a02 | 413 | #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ |
AnnaBridge | 161:aa5281ff4a02 | 414 | #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ |
AnnaBridge | 161:aa5281ff4a02 | 415 | #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ |
AnnaBridge | 161:aa5281ff4a02 | 416 | #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */ |
AnnaBridge | 161:aa5281ff4a02 | 417 | #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */ |
AnnaBridge | 161:aa5281ff4a02 | 418 | /** |
AnnaBridge | 161:aa5281ff4a02 | 419 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 420 | */ |
AnnaBridge | 161:aa5281ff4a02 | 421 | |
AnnaBridge | 161:aa5281ff4a02 | 422 | /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source |
AnnaBridge | 161:aa5281ff4a02 | 423 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 424 | */ |
AnnaBridge | 161:aa5281ff4a02 | 425 | #define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */ |
AnnaBridge | 161:aa5281ff4a02 | 426 | #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ |
AnnaBridge | 161:aa5281ff4a02 | 427 | /** |
AnnaBridge | 161:aa5281ff4a02 | 428 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 429 | */ |
AnnaBridge | 161:aa5281ff4a02 | 430 | |
AnnaBridge | 161:aa5281ff4a02 | 431 | /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code |
AnnaBridge | 161:aa5281ff4a02 | 432 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 433 | */ |
AnnaBridge | 161:aa5281ff4a02 | 434 | #define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */ |
AnnaBridge | 161:aa5281ff4a02 | 435 | #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */ |
AnnaBridge | 161:aa5281ff4a02 | 436 | #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */ |
AnnaBridge | 161:aa5281ff4a02 | 437 | #define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */ |
AnnaBridge | 161:aa5281ff4a02 | 438 | /** |
AnnaBridge | 161:aa5281ff4a02 | 439 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 440 | */ |
AnnaBridge | 161:aa5281ff4a02 | 441 | |
AnnaBridge | 161:aa5281ff4a02 | 442 | /** @defgroup DFSDM_BreakSignals DFSDM break signals |
AnnaBridge | 161:aa5281ff4a02 | 443 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 444 | */ |
AnnaBridge | 161:aa5281ff4a02 | 445 | #define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */ |
AnnaBridge | 161:aa5281ff4a02 | 446 | #define DFSDM_BREAK_SIGNAL_0 0x00000001U /*!< Break signal 0 */ |
AnnaBridge | 161:aa5281ff4a02 | 447 | #define DFSDM_BREAK_SIGNAL_1 0x00000002U /*!< Break signal 1 */ |
AnnaBridge | 161:aa5281ff4a02 | 448 | #define DFSDM_BREAK_SIGNAL_2 0x00000004U /*!< Break signal 2 */ |
AnnaBridge | 161:aa5281ff4a02 | 449 | #define DFSDM_BREAK_SIGNAL_3 0x00000008U /*!< Break signal 3 */ |
AnnaBridge | 161:aa5281ff4a02 | 450 | /** |
AnnaBridge | 161:aa5281ff4a02 | 451 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 452 | */ |
AnnaBridge | 161:aa5281ff4a02 | 453 | |
AnnaBridge | 161:aa5281ff4a02 | 454 | /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection |
AnnaBridge | 161:aa5281ff4a02 | 455 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 456 | */ |
AnnaBridge | 161:aa5281ff4a02 | 457 | /* DFSDM Channels ------------------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 458 | /* The DFSDM channels are defined as follows: |
AnnaBridge | 161:aa5281ff4a02 | 459 | - in 16-bit LSB the channel mask is set |
AnnaBridge | 161:aa5281ff4a02 | 460 | - in 16-bit MSB the channel number is set |
AnnaBridge | 161:aa5281ff4a02 | 461 | e.g. for channel 3 definition: |
AnnaBridge | 161:aa5281ff4a02 | 462 | - the channel mask is 0x00000008 (bit 3 is set) |
AnnaBridge | 161:aa5281ff4a02 | 463 | - the channel number 3 is 0x00030000 |
AnnaBridge | 161:aa5281ff4a02 | 464 | --> Consequently, channel 3 definition is 0x00000008 | 0x00030000 = 0x00030008 */ |
AnnaBridge | 161:aa5281ff4a02 | 465 | #define DFSDM_CHANNEL_0 0x00000001U |
AnnaBridge | 161:aa5281ff4a02 | 466 | #define DFSDM_CHANNEL_1 0x00010002U |
AnnaBridge | 161:aa5281ff4a02 | 467 | #define DFSDM_CHANNEL_2 0x00020004U |
AnnaBridge | 161:aa5281ff4a02 | 468 | #define DFSDM_CHANNEL_3 0x00030008U |
AnnaBridge | 161:aa5281ff4a02 | 469 | #define DFSDM_CHANNEL_4 0x00040010U /* only for stmm32f413xx and stm32f423xx devices */ |
AnnaBridge | 161:aa5281ff4a02 | 470 | #define DFSDM_CHANNEL_5 0x00050020U /* only for stmm32f413xx and stm32f423xx devices */ |
AnnaBridge | 161:aa5281ff4a02 | 471 | #define DFSDM_CHANNEL_6 0x00060040U /* only for stmm32f413xx and stm32f423xx devices */ |
AnnaBridge | 161:aa5281ff4a02 | 472 | #define DFSDM_CHANNEL_7 0x00070080U /* only for stmm32f413xx and stm32f423xx devices */ |
AnnaBridge | 161:aa5281ff4a02 | 473 | /** |
AnnaBridge | 161:aa5281ff4a02 | 474 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 475 | */ |
AnnaBridge | 161:aa5281ff4a02 | 476 | |
AnnaBridge | 161:aa5281ff4a02 | 477 | /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode |
AnnaBridge | 161:aa5281ff4a02 | 478 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 479 | */ |
AnnaBridge | 161:aa5281ff4a02 | 480 | #define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U /*!< Conversion are not continuous */ |
AnnaBridge | 161:aa5281ff4a02 | 481 | #define DFSDM_CONTINUOUS_CONV_ON 0x00000001U /*!< Conversion are continuous */ |
AnnaBridge | 161:aa5281ff4a02 | 482 | /** |
AnnaBridge | 161:aa5281ff4a02 | 483 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 484 | */ |
AnnaBridge | 161:aa5281ff4a02 | 485 | |
AnnaBridge | 161:aa5281ff4a02 | 486 | /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold |
AnnaBridge | 161:aa5281ff4a02 | 487 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 488 | */ |
AnnaBridge | 161:aa5281ff4a02 | 489 | #define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U /*!< Analog watchdog high threshold */ |
AnnaBridge | 161:aa5281ff4a02 | 490 | #define DFSDM_AWD_LOW_THRESHOLD 0x00000001U /*!< Analog watchdog low threshold */ |
AnnaBridge | 161:aa5281ff4a02 | 491 | /** |
AnnaBridge | 161:aa5281ff4a02 | 492 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 493 | */ |
AnnaBridge | 161:aa5281ff4a02 | 494 | |
AnnaBridge | 161:aa5281ff4a02 | 495 | #if defined(SYSCFG_MCHDLYCR_BSCKSEL) |
AnnaBridge | 161:aa5281ff4a02 | 496 | /** @defgroup DFSDM_1_CLOCKOUT_SELECTION DFSDM1 ClockOut Selection |
AnnaBridge | 161:aa5281ff4a02 | 497 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 498 | */ |
AnnaBridge | 161:aa5281ff4a02 | 499 | #define DFSDM1_CKOUT_DFSDM2_CKOUT 0x00000080U |
AnnaBridge | 161:aa5281ff4a02 | 500 | #define DFSDM1_CKOUT_DFSDM1 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 501 | /** |
AnnaBridge | 161:aa5281ff4a02 | 502 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 503 | */ |
AnnaBridge | 161:aa5281ff4a02 | 504 | |
AnnaBridge | 161:aa5281ff4a02 | 505 | /** @defgroup DFSDM_2_CLOCKOUT_SELECTION DFSDM2 ClockOut Selection |
AnnaBridge | 161:aa5281ff4a02 | 506 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 507 | */ |
AnnaBridge | 161:aa5281ff4a02 | 508 | #define DFSDM2_CKOUT_DFSDM2_CKOUT 0x00040000U |
AnnaBridge | 161:aa5281ff4a02 | 509 | #define DFSDM2_CKOUT_DFSDM2 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 510 | /** |
AnnaBridge | 161:aa5281ff4a02 | 511 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 512 | */ |
AnnaBridge | 161:aa5281ff4a02 | 513 | |
AnnaBridge | 161:aa5281ff4a02 | 514 | /** @defgroup DFSDM_1_CLOCKIN_SELECTION DFSDM1 ClockIn Selection |
AnnaBridge | 161:aa5281ff4a02 | 515 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 516 | */ |
AnnaBridge | 161:aa5281ff4a02 | 517 | #define DFSDM1_CKIN_DFSDM2_CKOUT 0x00000040U |
AnnaBridge | 161:aa5281ff4a02 | 518 | #define DFSDM1_CKIN_PAD 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 519 | /** |
AnnaBridge | 161:aa5281ff4a02 | 520 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 521 | */ |
AnnaBridge | 161:aa5281ff4a02 | 522 | |
AnnaBridge | 161:aa5281ff4a02 | 523 | /** @defgroup DFSDM_2_CLOCKIN_SELECTION DFSDM2 ClockIn Selection |
AnnaBridge | 161:aa5281ff4a02 | 524 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 525 | */ |
AnnaBridge | 161:aa5281ff4a02 | 526 | #define DFSDM2_CKIN_DFSDM2_CKOUT 0x00020000U |
AnnaBridge | 161:aa5281ff4a02 | 527 | #define DFSDM2_CKIN_PAD 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 528 | /** |
AnnaBridge | 161:aa5281ff4a02 | 529 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 530 | */ |
AnnaBridge | 161:aa5281ff4a02 | 531 | |
AnnaBridge | 161:aa5281ff4a02 | 532 | /** @defgroup DFSDM_1_BIT_STREAM_DISTRIBUTION DFSDM1 Bit Stream Distribution |
AnnaBridge | 161:aa5281ff4a02 | 533 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 534 | */ |
AnnaBridge | 161:aa5281ff4a02 | 535 | #define DFSDM1_T4_OC2_BITSTREAM_CKIN0 0x00000000U /* TIM4_OC2 to CLKIN0 */ |
AnnaBridge | 161:aa5281ff4a02 | 536 | #define DFSDM1_T4_OC2_BITSTREAM_CKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL /* TIM4_OC2 to CLKIN2 */ |
AnnaBridge | 161:aa5281ff4a02 | 537 | #define DFSDM1_T4_OC1_BITSTREAM_CKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL /* TIM4_OC1 to CLKIN3 */ |
AnnaBridge | 161:aa5281ff4a02 | 538 | #define DFSDM1_T4_OC1_BITSTREAM_CKIN1 0x00000000U /* TIM4_OC1 to CLKIN1 */ |
AnnaBridge | 161:aa5281ff4a02 | 539 | /** |
AnnaBridge | 161:aa5281ff4a02 | 540 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 541 | */ |
AnnaBridge | 161:aa5281ff4a02 | 542 | |
AnnaBridge | 161:aa5281ff4a02 | 543 | /** @defgroup DFSDM_2_BIT_STREAM_DISTRIBUTION DFSDM12 Bit Stream Distribution |
AnnaBridge | 161:aa5281ff4a02 | 544 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 545 | */ |
AnnaBridge | 161:aa5281ff4a02 | 546 | #define DFSDM2_T3_OC4_BITSTREAM_CKIN0 0x00000000U /* TIM3_OC4 to CKIN0 */ |
AnnaBridge | 161:aa5281ff4a02 | 547 | #define DFSDM2_T3_OC4_BITSTREAM_CKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL /* TIM3_OC4 to CKIN4 */ |
AnnaBridge | 161:aa5281ff4a02 | 548 | #define DFSDM2_T3_OC3_BITSTREAM_CKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL /* TIM3_OC3 to CKIN5 */ |
AnnaBridge | 161:aa5281ff4a02 | 549 | #define DFSDM2_T3_OC3_BITSTREAM_CKIN1 0x00000000U /* TIM3_OC3 to CKIN1 */ |
AnnaBridge | 161:aa5281ff4a02 | 550 | #define DFSDM2_T3_OC2_BITSTREAM_CKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL /* TIM3_OC2to CKIN6 */ |
AnnaBridge | 161:aa5281ff4a02 | 551 | #define DFSDM2_T3_OC2_BITSTREAM_CKIN2 0x00000000U /* TIM3_OC2 to CKIN2 */ |
AnnaBridge | 161:aa5281ff4a02 | 552 | #define DFSDM2_T3_OC1_BITSTREAM_CKIN3 0x00000000U /* TIM3_OC1 to CKIN3 */ |
AnnaBridge | 161:aa5281ff4a02 | 553 | #define DFSDM2_T3_OC1_BITSTREAM_CKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL /* TIM3_OC1 to CKIN7 */ |
AnnaBridge | 161:aa5281ff4a02 | 554 | /** |
AnnaBridge | 161:aa5281ff4a02 | 555 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 556 | */ |
AnnaBridge | 161:aa5281ff4a02 | 557 | |
AnnaBridge | 161:aa5281ff4a02 | 558 | /** @defgroup DFSDM_1_DATA_DISTRIBUTION DFSDM1 Data Distribution |
AnnaBridge | 161:aa5281ff4a02 | 559 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 560 | */ |
AnnaBridge | 161:aa5281ff4a02 | 561 | #define DFSDM1_DATIN0_TO_DATIN0_PAD 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 562 | #define DFSDM1_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM1D0SEL |
AnnaBridge | 161:aa5281ff4a02 | 563 | #define DFSDM1_DATIN2_TO_DATIN2_PAD 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 564 | #define DFSDM1_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM1D2SEL |
AnnaBridge | 161:aa5281ff4a02 | 565 | /** |
AnnaBridge | 161:aa5281ff4a02 | 566 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 567 | */ |
AnnaBridge | 161:aa5281ff4a02 | 568 | |
AnnaBridge | 161:aa5281ff4a02 | 569 | /** @defgroup DFSDM_2_DATA_DISTRIBUTION DFSDM2 Data Distribution |
AnnaBridge | 161:aa5281ff4a02 | 570 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 571 | */ |
AnnaBridge | 161:aa5281ff4a02 | 572 | #define DFSDM2_DATIN0_TO_DATIN0_PAD 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 573 | #define DFSDM2_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM2D0SEL |
AnnaBridge | 161:aa5281ff4a02 | 574 | #define DFSDM2_DATIN2_TO_DATIN2_PAD 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 575 | #define DFSDM2_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM2D2SEL |
AnnaBridge | 161:aa5281ff4a02 | 576 | #define DFSDM2_DATIN4_TO_DATIN4_PAD 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 577 | #define DFSDM2_DATIN4_TO_DATIN5_PAD SYSCFG_MCHDLYCR_DFSDM2D4SEL |
AnnaBridge | 161:aa5281ff4a02 | 578 | #define DFSDM2_DATIN6_TO_DATIN6_PAD 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 579 | #define DFSDM2_DATIN6_TO_DATIN7_PAD SYSCFG_MCHDLYCR_DFSDM2D6SEL |
AnnaBridge | 161:aa5281ff4a02 | 580 | /** |
AnnaBridge | 161:aa5281ff4a02 | 581 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 582 | */ |
AnnaBridge | 161:aa5281ff4a02 | 583 | |
AnnaBridge | 161:aa5281ff4a02 | 584 | /** @defgroup HAL_MCHDLY_CLOCK HAL MCHDLY Clock enable |
AnnaBridge | 161:aa5281ff4a02 | 585 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 586 | */ |
AnnaBridge | 161:aa5281ff4a02 | 587 | #define HAL_MCHDLY_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_MCHDLY2EN |
AnnaBridge | 161:aa5281ff4a02 | 588 | #define HAL_MCHDLY_CLOCK_DFSDM1 SYSCFG_MCHDLYCR_MCHDLY1EN |
AnnaBridge | 161:aa5281ff4a02 | 589 | /** |
AnnaBridge | 161:aa5281ff4a02 | 590 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 591 | */ |
AnnaBridge | 161:aa5281ff4a02 | 592 | |
AnnaBridge | 161:aa5281ff4a02 | 593 | /** @defgroup DFSDM_CLOCKIN_SOURCE DFSDM Clock In Source Selection |
AnnaBridge | 161:aa5281ff4a02 | 594 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 595 | */ |
AnnaBridge | 161:aa5281ff4a02 | 596 | #define HAL_DFSDM2_CKIN_PAD 0x00040000U |
AnnaBridge | 161:aa5281ff4a02 | 597 | #define HAL_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG |
AnnaBridge | 161:aa5281ff4a02 | 598 | #define HAL_DFSDM1_CKIN_PAD 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 599 | #define HAL_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG |
AnnaBridge | 161:aa5281ff4a02 | 600 | /** |
AnnaBridge | 161:aa5281ff4a02 | 601 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 602 | */ |
AnnaBridge | 161:aa5281ff4a02 | 603 | |
AnnaBridge | 161:aa5281ff4a02 | 604 | /** @defgroup DFSDM_CLOCKOUT_SOURCE DFSDM Clock Source Selection |
AnnaBridge | 161:aa5281ff4a02 | 605 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 606 | */ |
AnnaBridge | 161:aa5281ff4a02 | 607 | #define HAL_DFSDM2_CKOUT_DFSDM2 0x10000000U |
AnnaBridge | 161:aa5281ff4a02 | 608 | #define HAL_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL |
AnnaBridge | 161:aa5281ff4a02 | 609 | #define HAL_DFSDM1_CKOUT_DFSDM1 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 610 | #define HAL_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL |
AnnaBridge | 161:aa5281ff4a02 | 611 | /** |
AnnaBridge | 161:aa5281ff4a02 | 612 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 613 | */ |
AnnaBridge | 161:aa5281ff4a02 | 614 | |
AnnaBridge | 161:aa5281ff4a02 | 615 | /** @defgroup DFSDM_DATAIN0_SOURCE DFSDM Source Selection For DATAIN0 |
AnnaBridge | 161:aa5281ff4a02 | 616 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 617 | */ |
AnnaBridge | 161:aa5281ff4a02 | 618 | #define HAL_DATAIN0_DFSDM2_PAD 0x10000000U |
AnnaBridge | 161:aa5281ff4a02 | 619 | #define HAL_DATAIN0_DFSDM2_DATAIN1 SYSCFG_MCHDLYCR_DFSDM2D0SEL |
AnnaBridge | 161:aa5281ff4a02 | 620 | #define HAL_DATAIN0_DFSDM1_PAD 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 621 | #define HAL_DATAIN0_DFSDM1_DATAIN1 SYSCFG_MCHDLYCR_DFSDM1D0SEL |
AnnaBridge | 161:aa5281ff4a02 | 622 | /** |
AnnaBridge | 161:aa5281ff4a02 | 623 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 624 | */ |
AnnaBridge | 161:aa5281ff4a02 | 625 | |
AnnaBridge | 161:aa5281ff4a02 | 626 | /** @defgroup DFSDM_DATAIN2_SOURCE DFSDM Source Selection For DATAIN2 |
AnnaBridge | 161:aa5281ff4a02 | 627 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 628 | */ |
AnnaBridge | 161:aa5281ff4a02 | 629 | #define HAL_DATAIN2_DFSDM2_PAD 0x10000000U |
AnnaBridge | 161:aa5281ff4a02 | 630 | #define HAL_DATAIN2_DFSDM2_DATAIN3 SYSCFG_MCHDLYCR_DFSDM2D2SEL |
AnnaBridge | 161:aa5281ff4a02 | 631 | #define HAL_DATAIN2_DFSDM1_PAD 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 632 | #define HAL_DATAIN2_DFSDM1_DATAIN3 SYSCFG_MCHDLYCR_DFSDM1D2SEL |
AnnaBridge | 161:aa5281ff4a02 | 633 | /** |
AnnaBridge | 161:aa5281ff4a02 | 634 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 635 | */ |
AnnaBridge | 161:aa5281ff4a02 | 636 | |
AnnaBridge | 161:aa5281ff4a02 | 637 | /** @defgroup DFSDM_DATAIN4_SOURCE DFSDM Source Selection For DATAIN4 |
AnnaBridge | 161:aa5281ff4a02 | 638 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 639 | */ |
AnnaBridge | 161:aa5281ff4a02 | 640 | #define HAL_DATAIN4_DFSDM2_PAD 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 641 | #define HAL_DATAIN4_DFSDM2_DATAIN5 SYSCFG_MCHDLYCR_DFSDM2D4SEL |
AnnaBridge | 161:aa5281ff4a02 | 642 | /** |
AnnaBridge | 161:aa5281ff4a02 | 643 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 644 | */ |
AnnaBridge | 161:aa5281ff4a02 | 645 | |
AnnaBridge | 161:aa5281ff4a02 | 646 | /** @defgroup DFSDM_DATAIN6_SOURCE DFSDM Source Selection For DATAIN6 |
AnnaBridge | 161:aa5281ff4a02 | 647 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 648 | */ |
AnnaBridge | 161:aa5281ff4a02 | 649 | #define HAL_DATAIN6_DFSDM2_PAD 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 650 | #define HAL_DATAIN6_DFSDM2_DATAIN7 SYSCFG_MCHDLYCR_DFSDM2D6SEL |
AnnaBridge | 161:aa5281ff4a02 | 651 | /** |
AnnaBridge | 161:aa5281ff4a02 | 652 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 653 | */ |
AnnaBridge | 161:aa5281ff4a02 | 654 | |
AnnaBridge | 161:aa5281ff4a02 | 655 | /** @defgroup DFSDM1_CLKIN_SOURCE DFSDM1 Source Selection For CLKIN |
AnnaBridge | 161:aa5281ff4a02 | 656 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 657 | */ |
AnnaBridge | 161:aa5281ff4a02 | 658 | #define HAL_DFSDM1_CLKIN0_TIM4OC2 0x01000000U |
AnnaBridge | 161:aa5281ff4a02 | 659 | #define HAL_DFSDM1_CLKIN2_TIM4OC2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL |
AnnaBridge | 161:aa5281ff4a02 | 660 | #define HAL_DFSDM1_CLKIN1_TIM4OC1 0x02000000U |
AnnaBridge | 161:aa5281ff4a02 | 661 | #define HAL_DFSDM1_CLKIN3_TIM4OC1 SYSCFG_MCHDLYCR_DFSDM1CK13SEL |
AnnaBridge | 161:aa5281ff4a02 | 662 | /** |
AnnaBridge | 161:aa5281ff4a02 | 663 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 664 | */ |
AnnaBridge | 161:aa5281ff4a02 | 665 | |
AnnaBridge | 161:aa5281ff4a02 | 666 | /** @defgroup DFSDM2_CLKIN_SOURCE DFSDM2 Source Selection For CLKIN |
AnnaBridge | 161:aa5281ff4a02 | 667 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 668 | */ |
AnnaBridge | 161:aa5281ff4a02 | 669 | #define HAL_DFSDM2_CLKIN0_TIM3OC4 0x04000000U |
AnnaBridge | 161:aa5281ff4a02 | 670 | #define HAL_DFSDM2_CLKIN4_TIM3OC4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL |
AnnaBridge | 161:aa5281ff4a02 | 671 | #define HAL_DFSDM2_CLKIN1_TIM3OC3 0x08000000U |
AnnaBridge | 161:aa5281ff4a02 | 672 | #define HAL_DFSDM2_CLKIN5_TIM3OC3 SYSCFG_MCHDLYCR_DFSDM2CK15SEL |
AnnaBridge | 161:aa5281ff4a02 | 673 | #define HAL_DFSDM2_CLKIN2_TIM3OC2 0x10000000U |
AnnaBridge | 161:aa5281ff4a02 | 674 | #define HAL_DFSDM2_CLKIN6_TIM3OC2 SYSCFG_MCHDLYCR_DFSDM2CK26SEL |
AnnaBridge | 161:aa5281ff4a02 | 675 | #define HAL_DFSDM2_CLKIN3_TIM3OC1 0x00000000U |
AnnaBridge | 161:aa5281ff4a02 | 676 | #define HAL_DFSDM2_CLKIN7_TIM3OC1 SYSCFG_MCHDLYCR_DFSDM2CK37SEL |
AnnaBridge | 161:aa5281ff4a02 | 677 | /** |
AnnaBridge | 161:aa5281ff4a02 | 678 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 679 | */ |
AnnaBridge | 161:aa5281ff4a02 | 680 | |
AnnaBridge | 161:aa5281ff4a02 | 681 | #endif /* SYSCFG_MCHDLYCR_BSCKSEL*/ |
AnnaBridge | 161:aa5281ff4a02 | 682 | /** |
AnnaBridge | 161:aa5281ff4a02 | 683 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 684 | */ |
AnnaBridge | 161:aa5281ff4a02 | 685 | /* End of exported constants -------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 686 | |
AnnaBridge | 161:aa5281ff4a02 | 687 | /* Exported macros -----------------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 688 | /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros |
AnnaBridge | 161:aa5281ff4a02 | 689 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 690 | */ |
AnnaBridge | 161:aa5281ff4a02 | 691 | |
AnnaBridge | 161:aa5281ff4a02 | 692 | /** @brief Reset DFSDM channel handle state. |
AnnaBridge | 163:e59c8e839560 | 693 | * @param __HANDLE__ DFSDM channel handle. |
AnnaBridge | 161:aa5281ff4a02 | 694 | * @retval None |
AnnaBridge | 161:aa5281ff4a02 | 695 | */ |
AnnaBridge | 161:aa5281ff4a02 | 696 | #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) |
AnnaBridge | 161:aa5281ff4a02 | 697 | |
AnnaBridge | 161:aa5281ff4a02 | 698 | /** @brief Reset DFSDM filter handle state. |
AnnaBridge | 163:e59c8e839560 | 699 | * @param __HANDLE__ DFSDM filter handle. |
AnnaBridge | 161:aa5281ff4a02 | 700 | * @retval None |
AnnaBridge | 161:aa5281ff4a02 | 701 | */ |
AnnaBridge | 161:aa5281ff4a02 | 702 | #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) |
AnnaBridge | 161:aa5281ff4a02 | 703 | |
AnnaBridge | 161:aa5281ff4a02 | 704 | /** |
AnnaBridge | 161:aa5281ff4a02 | 705 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 706 | */ |
AnnaBridge | 161:aa5281ff4a02 | 707 | /* End of exported macros ----------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 708 | |
AnnaBridge | 161:aa5281ff4a02 | 709 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 710 | /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions |
AnnaBridge | 161:aa5281ff4a02 | 711 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 712 | */ |
AnnaBridge | 161:aa5281ff4a02 | 713 | |
AnnaBridge | 161:aa5281ff4a02 | 714 | /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions |
AnnaBridge | 161:aa5281ff4a02 | 715 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 716 | */ |
AnnaBridge | 161:aa5281ff4a02 | 717 | /* Channel initialization and de-initialization functions *********************/ |
AnnaBridge | 161:aa5281ff4a02 | 718 | HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 161:aa5281ff4a02 | 719 | HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 161:aa5281ff4a02 | 720 | void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 161:aa5281ff4a02 | 721 | void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 161:aa5281ff4a02 | 722 | /** |
AnnaBridge | 161:aa5281ff4a02 | 723 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 724 | */ |
AnnaBridge | 161:aa5281ff4a02 | 725 | |
AnnaBridge | 161:aa5281ff4a02 | 726 | /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions |
AnnaBridge | 161:aa5281ff4a02 | 727 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 728 | */ |
AnnaBridge | 161:aa5281ff4a02 | 729 | /* Channel operation functions ************************************************/ |
AnnaBridge | 161:aa5281ff4a02 | 730 | HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 161:aa5281ff4a02 | 731 | HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 161:aa5281ff4a02 | 732 | HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 161:aa5281ff4a02 | 733 | HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 161:aa5281ff4a02 | 734 | |
AnnaBridge | 161:aa5281ff4a02 | 735 | HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); |
AnnaBridge | 161:aa5281ff4a02 | 736 | HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); |
AnnaBridge | 161:aa5281ff4a02 | 737 | HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 161:aa5281ff4a02 | 738 | HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 161:aa5281ff4a02 | 739 | |
AnnaBridge | 161:aa5281ff4a02 | 740 | int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 161:aa5281ff4a02 | 741 | HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); |
AnnaBridge | 161:aa5281ff4a02 | 742 | |
AnnaBridge | 161:aa5281ff4a02 | 743 | HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); |
AnnaBridge | 161:aa5281ff4a02 | 744 | HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); |
AnnaBridge | 161:aa5281ff4a02 | 745 | |
AnnaBridge | 161:aa5281ff4a02 | 746 | void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 161:aa5281ff4a02 | 747 | void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 161:aa5281ff4a02 | 748 | /** |
AnnaBridge | 161:aa5281ff4a02 | 749 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 750 | */ |
AnnaBridge | 161:aa5281ff4a02 | 751 | |
AnnaBridge | 161:aa5281ff4a02 | 752 | /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function |
AnnaBridge | 161:aa5281ff4a02 | 753 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 754 | */ |
AnnaBridge | 161:aa5281ff4a02 | 755 | /* Channel state function *****************************************************/ |
AnnaBridge | 161:aa5281ff4a02 | 756 | HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); |
AnnaBridge | 161:aa5281ff4a02 | 757 | /** |
AnnaBridge | 161:aa5281ff4a02 | 758 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 759 | */ |
AnnaBridge | 161:aa5281ff4a02 | 760 | |
AnnaBridge | 161:aa5281ff4a02 | 761 | /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions |
AnnaBridge | 161:aa5281ff4a02 | 762 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 763 | */ |
AnnaBridge | 161:aa5281ff4a02 | 764 | /* Filter initialization and de-initialization functions *********************/ |
AnnaBridge | 161:aa5281ff4a02 | 765 | HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 766 | HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 767 | void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 768 | void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 769 | /** |
AnnaBridge | 161:aa5281ff4a02 | 770 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 771 | */ |
AnnaBridge | 161:aa5281ff4a02 | 772 | |
AnnaBridge | 161:aa5281ff4a02 | 773 | /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions |
AnnaBridge | 161:aa5281ff4a02 | 774 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 775 | */ |
AnnaBridge | 161:aa5281ff4a02 | 776 | /* Filter control functions *********************/ |
AnnaBridge | 161:aa5281ff4a02 | 777 | HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, |
AnnaBridge | 161:aa5281ff4a02 | 778 | uint32_t Channel, |
AnnaBridge | 161:aa5281ff4a02 | 779 | uint32_t ContinuousMode); |
AnnaBridge | 161:aa5281ff4a02 | 780 | HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, |
AnnaBridge | 161:aa5281ff4a02 | 781 | uint32_t Channel); |
AnnaBridge | 161:aa5281ff4a02 | 782 | /** |
AnnaBridge | 161:aa5281ff4a02 | 783 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 784 | */ |
AnnaBridge | 161:aa5281ff4a02 | 785 | |
AnnaBridge | 161:aa5281ff4a02 | 786 | /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions |
AnnaBridge | 161:aa5281ff4a02 | 787 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 788 | */ |
AnnaBridge | 161:aa5281ff4a02 | 789 | /* Filter operation functions *********************/ |
AnnaBridge | 161:aa5281ff4a02 | 790 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 791 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 792 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); |
AnnaBridge | 161:aa5281ff4a02 | 793 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); |
AnnaBridge | 161:aa5281ff4a02 | 794 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 795 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 796 | HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 797 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 798 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 799 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); |
AnnaBridge | 161:aa5281ff4a02 | 800 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); |
AnnaBridge | 161:aa5281ff4a02 | 801 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 802 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 803 | HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 804 | HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, |
AnnaBridge | 161:aa5281ff4a02 | 805 | DFSDM_Filter_AwdParamTypeDef* awdParam); |
AnnaBridge | 161:aa5281ff4a02 | 806 | HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 807 | HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); |
AnnaBridge | 161:aa5281ff4a02 | 808 | HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 809 | |
AnnaBridge | 161:aa5281ff4a02 | 810 | int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
AnnaBridge | 161:aa5281ff4a02 | 811 | int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
AnnaBridge | 161:aa5281ff4a02 | 812 | int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
AnnaBridge | 161:aa5281ff4a02 | 813 | int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); |
AnnaBridge | 161:aa5281ff4a02 | 814 | uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 815 | |
AnnaBridge | 161:aa5281ff4a02 | 816 | void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 817 | |
AnnaBridge | 161:aa5281ff4a02 | 818 | HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); |
AnnaBridge | 161:aa5281ff4a02 | 819 | HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); |
AnnaBridge | 161:aa5281ff4a02 | 820 | |
AnnaBridge | 161:aa5281ff4a02 | 821 | void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 822 | void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 823 | void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 824 | void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 825 | void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); |
AnnaBridge | 161:aa5281ff4a02 | 826 | void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 827 | /** |
AnnaBridge | 161:aa5281ff4a02 | 828 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 829 | */ |
AnnaBridge | 161:aa5281ff4a02 | 830 | |
AnnaBridge | 161:aa5281ff4a02 | 831 | /** @addtogroup DFSDM_Exported_Functions_Group4_Filter Filter state functions |
AnnaBridge | 161:aa5281ff4a02 | 832 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 833 | */ |
AnnaBridge | 161:aa5281ff4a02 | 834 | /* Filter state functions *****************************************************/ |
AnnaBridge | 161:aa5281ff4a02 | 835 | HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 836 | uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); |
AnnaBridge | 161:aa5281ff4a02 | 837 | /** |
AnnaBridge | 161:aa5281ff4a02 | 838 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 839 | */ |
AnnaBridge | 161:aa5281ff4a02 | 840 | /** @addtogroup DFSDM_Exported_Functions_Group5_Filter MultiChannel operation functions |
AnnaBridge | 161:aa5281ff4a02 | 841 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 842 | */ |
AnnaBridge | 161:aa5281ff4a02 | 843 | #if defined(SYSCFG_MCHDLYCR_BSCKSEL) |
AnnaBridge | 161:aa5281ff4a02 | 844 | void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlystruct); |
AnnaBridge | 161:aa5281ff4a02 | 845 | void HAL_DFSDM_BitstreamClock_Start(void); |
AnnaBridge | 161:aa5281ff4a02 | 846 | void HAL_DFSDM_BitstreamClock_Stop(void); |
AnnaBridge | 161:aa5281ff4a02 | 847 | void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY); |
AnnaBridge | 161:aa5281ff4a02 | 848 | void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY); |
AnnaBridge | 161:aa5281ff4a02 | 849 | void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source); |
AnnaBridge | 161:aa5281ff4a02 | 850 | void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source); |
AnnaBridge | 161:aa5281ff4a02 | 851 | void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source); |
AnnaBridge | 161:aa5281ff4a02 | 852 | void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source); |
AnnaBridge | 161:aa5281ff4a02 | 853 | void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source); |
AnnaBridge | 161:aa5281ff4a02 | 854 | void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source); |
AnnaBridge | 161:aa5281ff4a02 | 855 | void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source); |
AnnaBridge | 161:aa5281ff4a02 | 856 | #endif /* SYSCFG_MCHDLYCR_BSCKSEL */ |
AnnaBridge | 161:aa5281ff4a02 | 857 | /** |
AnnaBridge | 161:aa5281ff4a02 | 858 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 859 | */ |
AnnaBridge | 161:aa5281ff4a02 | 860 | /** |
AnnaBridge | 161:aa5281ff4a02 | 861 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 862 | */ |
AnnaBridge | 161:aa5281ff4a02 | 863 | /* End of exported functions -------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 864 | |
AnnaBridge | 161:aa5281ff4a02 | 865 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 866 | /** @defgroup DFSDM_Private_Macros DFSDM Private Macros |
AnnaBridge | 161:aa5281ff4a02 | 867 | * @{ |
AnnaBridge | 161:aa5281ff4a02 | 868 | */ |
AnnaBridge | 161:aa5281ff4a02 | 869 | #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ |
AnnaBridge | 161:aa5281ff4a02 | 870 | ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) |
AnnaBridge | 161:aa5281ff4a02 | 871 | #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U)) |
AnnaBridge | 161:aa5281ff4a02 | 872 | #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ |
AnnaBridge | 161:aa5281ff4a02 | 873 | ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) |
AnnaBridge | 161:aa5281ff4a02 | 874 | #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ |
AnnaBridge | 161:aa5281ff4a02 | 875 | ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ |
AnnaBridge | 161:aa5281ff4a02 | 876 | ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) |
AnnaBridge | 161:aa5281ff4a02 | 877 | #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \ |
AnnaBridge | 161:aa5281ff4a02 | 878 | ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) |
AnnaBridge | 161:aa5281ff4a02 | 879 | #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \ |
AnnaBridge | 161:aa5281ff4a02 | 880 | ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \ |
AnnaBridge | 161:aa5281ff4a02 | 881 | ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \ |
AnnaBridge | 161:aa5281ff4a02 | 882 | ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) |
AnnaBridge | 161:aa5281ff4a02 | 883 | #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \ |
AnnaBridge | 161:aa5281ff4a02 | 884 | ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \ |
AnnaBridge | 161:aa5281ff4a02 | 885 | ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \ |
AnnaBridge | 161:aa5281ff4a02 | 886 | ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) |
AnnaBridge | 161:aa5281ff4a02 | 887 | #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \ |
AnnaBridge | 161:aa5281ff4a02 | 888 | ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ |
AnnaBridge | 161:aa5281ff4a02 | 889 | ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ |
AnnaBridge | 161:aa5281ff4a02 | 890 | ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) |
AnnaBridge | 161:aa5281ff4a02 | 891 | #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U)) |
AnnaBridge | 161:aa5281ff4a02 | 892 | #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) |
AnnaBridge | 161:aa5281ff4a02 | 893 | #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU) |
AnnaBridge | 161:aa5281ff4a02 | 894 | #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU) |
AnnaBridge | 161:aa5281ff4a02 | 895 | #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ |
AnnaBridge | 161:aa5281ff4a02 | 896 | ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) |
AnnaBridge | 161:aa5281ff4a02 | 897 | #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ |
AnnaBridge | 161:aa5281ff4a02 | 898 | ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ |
AnnaBridge | 161:aa5281ff4a02 | 899 | ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) |
AnnaBridge | 161:aa5281ff4a02 | 900 | #if defined (STM32F413xx) || defined (STM32F423xx) |
AnnaBridge | 161:aa5281ff4a02 | 901 | #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ |
AnnaBridge | 161:aa5281ff4a02 | 902 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ |
AnnaBridge | 161:aa5281ff4a02 | 903 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ |
AnnaBridge | 161:aa5281ff4a02 | 904 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \ |
AnnaBridge | 161:aa5281ff4a02 | 905 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM2_TRGO) || \ |
AnnaBridge | 161:aa5281ff4a02 | 906 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ |
AnnaBridge | 161:aa5281ff4a02 | 907 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM11_OC1) || \ |
AnnaBridge | 161:aa5281ff4a02 | 908 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ |
AnnaBridge | 161:aa5281ff4a02 | 909 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ |
AnnaBridge | 161:aa5281ff4a02 | 910 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) |
AnnaBridge | 161:aa5281ff4a02 | 911 | #define IS_DFSDM_DELAY_CLOCK(CLOCK) (((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM2) || \ |
AnnaBridge | 161:aa5281ff4a02 | 912 | ((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM1)) |
AnnaBridge | 161:aa5281ff4a02 | 913 | #else |
AnnaBridge | 161:aa5281ff4a02 | 914 | #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ |
AnnaBridge | 161:aa5281ff4a02 | 915 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ |
AnnaBridge | 161:aa5281ff4a02 | 916 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ |
AnnaBridge | 161:aa5281ff4a02 | 917 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \ |
AnnaBridge | 161:aa5281ff4a02 | 918 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ |
AnnaBridge | 161:aa5281ff4a02 | 919 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ |
AnnaBridge | 161:aa5281ff4a02 | 920 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ |
AnnaBridge | 161:aa5281ff4a02 | 921 | ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) |
AnnaBridge | 161:aa5281ff4a02 | 922 | #endif |
AnnaBridge | 161:aa5281ff4a02 | 923 | #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ |
AnnaBridge | 161:aa5281ff4a02 | 924 | ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ |
AnnaBridge | 161:aa5281ff4a02 | 925 | ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) |
AnnaBridge | 161:aa5281ff4a02 | 926 | #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \ |
AnnaBridge | 161:aa5281ff4a02 | 927 | ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \ |
AnnaBridge | 161:aa5281ff4a02 | 928 | ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \ |
AnnaBridge | 161:aa5281ff4a02 | 929 | ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ |
AnnaBridge | 161:aa5281ff4a02 | 930 | ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ |
AnnaBridge | 161:aa5281ff4a02 | 931 | ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) |
AnnaBridge | 161:aa5281ff4a02 | 932 | #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U)) |
AnnaBridge | 161:aa5281ff4a02 | 933 | #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U)) |
AnnaBridge | 161:aa5281ff4a02 | 934 | #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ |
AnnaBridge | 161:aa5281ff4a02 | 935 | ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) |
AnnaBridge | 161:aa5281ff4a02 | 936 | #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) |
AnnaBridge | 161:aa5281ff4a02 | 937 | #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0x0FU) |
AnnaBridge | 161:aa5281ff4a02 | 938 | #if defined(DFSDM2_Channel0) |
AnnaBridge | 161:aa5281ff4a02 | 939 | #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ |
AnnaBridge | 161:aa5281ff4a02 | 940 | ((CHANNEL) == DFSDM_CHANNEL_1) || \ |
AnnaBridge | 161:aa5281ff4a02 | 941 | ((CHANNEL) == DFSDM_CHANNEL_2) || \ |
AnnaBridge | 161:aa5281ff4a02 | 942 | ((CHANNEL) == DFSDM_CHANNEL_3) || \ |
AnnaBridge | 161:aa5281ff4a02 | 943 | ((CHANNEL) == DFSDM_CHANNEL_4) || \ |
AnnaBridge | 161:aa5281ff4a02 | 944 | ((CHANNEL) == DFSDM_CHANNEL_5) || \ |
AnnaBridge | 161:aa5281ff4a02 | 945 | ((CHANNEL) == DFSDM_CHANNEL_6) || \ |
AnnaBridge | 161:aa5281ff4a02 | 946 | ((CHANNEL) == DFSDM_CHANNEL_7)) |
AnnaBridge | 161:aa5281ff4a02 | 947 | #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU)) |
AnnaBridge | 161:aa5281ff4a02 | 948 | #else |
AnnaBridge | 161:aa5281ff4a02 | 949 | #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ |
AnnaBridge | 161:aa5281ff4a02 | 950 | ((CHANNEL) == DFSDM_CHANNEL_1) || \ |
AnnaBridge | 161:aa5281ff4a02 | 951 | ((CHANNEL) == DFSDM_CHANNEL_2) || \ |
AnnaBridge | 161:aa5281ff4a02 | 952 | ((CHANNEL) == DFSDM_CHANNEL_3)) |
AnnaBridge | 161:aa5281ff4a02 | 953 | #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU)) |
AnnaBridge | 161:aa5281ff4a02 | 954 | #endif |
AnnaBridge | 161:aa5281ff4a02 | 955 | #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ |
AnnaBridge | 161:aa5281ff4a02 | 956 | ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) |
AnnaBridge | 161:aa5281ff4a02 | 957 | #if defined(DFSDM2_Channel0) |
AnnaBridge | 161:aa5281ff4a02 | 958 | #define IS_DFSDM1_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \ |
AnnaBridge | 161:aa5281ff4a02 | 959 | ((INSTANCE) == DFSDM1_Channel1) || \ |
AnnaBridge | 161:aa5281ff4a02 | 960 | ((INSTANCE) == DFSDM1_Channel2) || \ |
AnnaBridge | 161:aa5281ff4a02 | 961 | ((INSTANCE) == DFSDM1_Channel3)) |
AnnaBridge | 161:aa5281ff4a02 | 962 | #define IS_DFSDM1_FILTER_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \ |
AnnaBridge | 161:aa5281ff4a02 | 963 | ((INSTANCE) == DFSDM1_Filter1)) |
AnnaBridge | 161:aa5281ff4a02 | 964 | #endif /* DFSDM2_Channel0 */ |
AnnaBridge | 161:aa5281ff4a02 | 965 | |
AnnaBridge | 161:aa5281ff4a02 | 966 | #if defined(SYSCFG_MCHDLYCR_BSCKSEL) |
AnnaBridge | 161:aa5281ff4a02 | 967 | #define IS_DFSDM_CLOCKIN_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKIN_PAD) || \ |
AnnaBridge | 161:aa5281ff4a02 | 968 | ((SELECTION) == HAL_DFSDM2_CKIN_DM) || \ |
AnnaBridge | 161:aa5281ff4a02 | 969 | ((SELECTION) == HAL_DFSDM1_CKIN_PAD) || \ |
AnnaBridge | 161:aa5281ff4a02 | 970 | ((SELECTION) == HAL_DFSDM1_CKIN_DM)) |
AnnaBridge | 161:aa5281ff4a02 | 971 | #define IS_DFSDM_CLOCKOUT_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKOUT_DFSDM2) || \ |
AnnaBridge | 161:aa5281ff4a02 | 972 | ((SELECTION) == HAL_DFSDM2_CKOUT_M27) || \ |
AnnaBridge | 161:aa5281ff4a02 | 973 | ((SELECTION) == HAL_DFSDM1_CKOUT_DFSDM1) || \ |
AnnaBridge | 161:aa5281ff4a02 | 974 | ((SELECTION) == HAL_DFSDM1_CKOUT_M27)) |
AnnaBridge | 161:aa5281ff4a02 | 975 | #define IS_DFSDM_DATAIN0_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN0_DFSDM2_PAD) || \ |
AnnaBridge | 161:aa5281ff4a02 | 976 | ((SELECTION) == HAL_DATAIN0_DFSDM2_DATAIN1) || \ |
AnnaBridge | 161:aa5281ff4a02 | 977 | ((SELECTION) == HAL_DATAIN0_DFSDM1_PAD) || \ |
AnnaBridge | 161:aa5281ff4a02 | 978 | ((SELECTION) == HAL_DATAIN0_DFSDM1_DATAIN1)) |
AnnaBridge | 161:aa5281ff4a02 | 979 | #define IS_DFSDM_DATAIN2_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN2_DFSDM2_PAD) || \ |
AnnaBridge | 161:aa5281ff4a02 | 980 | ((SELECTION) == HAL_DATAIN2_DFSDM2_DATAIN3) || \ |
AnnaBridge | 161:aa5281ff4a02 | 981 | ((SELECTION) == HAL_DATAIN2_DFSDM1_PAD) || \ |
AnnaBridge | 161:aa5281ff4a02 | 982 | ((SELECTION) == HAL_DATAIN2_DFSDM1_DATAIN3)) |
AnnaBridge | 161:aa5281ff4a02 | 983 | #define IS_DFSDM_DATAIN4_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN4_DFSDM2_PAD) || \ |
AnnaBridge | 161:aa5281ff4a02 | 984 | ((SELECTION) == HAL_DATAIN4_DFSDM2_DATAIN5)) |
AnnaBridge | 161:aa5281ff4a02 | 985 | #define IS_DFSDM_DATAIN6_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN6_DFSDM2_PAD) || \ |
AnnaBridge | 161:aa5281ff4a02 | 986 | ((SELECTION) == HAL_DATAIN6_DFSDM2_DATAIN7)) |
AnnaBridge | 161:aa5281ff4a02 | 987 | #define IS_DFSDM_BITSTREM_CLK_DISTRIBUTION(DISTRIBUTION) (((DISTRIBUTION) == HAL_DFSDM1_CLKIN0_TIM4OC2) || \ |
AnnaBridge | 161:aa5281ff4a02 | 988 | ((DISTRIBUTION) == HAL_DFSDM1_CLKIN2_TIM4OC2) || \ |
AnnaBridge | 161:aa5281ff4a02 | 989 | ((DISTRIBUTION) == HAL_DFSDM1_CLKIN1_TIM4OC1) || \ |
AnnaBridge | 161:aa5281ff4a02 | 990 | ((DISTRIBUTION) == HAL_DFSDM1_CLKIN3_TIM4OC1) || \ |
AnnaBridge | 161:aa5281ff4a02 | 991 | ((DISTRIBUTION) == HAL_DFSDM2_CLKIN0_TIM3OC4) || \ |
AnnaBridge | 161:aa5281ff4a02 | 992 | ((DISTRIBUTION) == HAL_DFSDM2_CLKIN4_TIM3OC4) || \ |
AnnaBridge | 161:aa5281ff4a02 | 993 | ((DISTRIBUTION) == HAL_DFSDM2_CLKIN1_TIM3OC3)|| \ |
AnnaBridge | 161:aa5281ff4a02 | 994 | ((DISTRIBUTION) == HAL_DFSDM2_CLKIN5_TIM3OC3) || \ |
AnnaBridge | 161:aa5281ff4a02 | 995 | ((DISTRIBUTION) == HAL_DFSDM2_CLKIN2_TIM3OC2) || \ |
AnnaBridge | 161:aa5281ff4a02 | 996 | ((DISTRIBUTION) == HAL_DFSDM2_CLKIN6_TIM3OC2) || \ |
AnnaBridge | 161:aa5281ff4a02 | 997 | ((DISTRIBUTION) == HAL_DFSDM2_CLKIN3_TIM3OC1)|| \ |
AnnaBridge | 161:aa5281ff4a02 | 998 | ((DISTRIBUTION) == HAL_DFSDM2_CLKIN7_TIM3OC1)) |
AnnaBridge | 161:aa5281ff4a02 | 999 | #define IS_DFSDM_DFSDM1_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM1_CKOUT_DFSDM2_CKOUT) || \ |
AnnaBridge | 161:aa5281ff4a02 | 1000 | ((CLKOUT) == DFSDM1_CKOUT_DFSDM1)) |
AnnaBridge | 161:aa5281ff4a02 | 1001 | #define IS_DFSDM_DFSDM2_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM2_CKOUT_DFSDM2_CKOUT) || \ |
AnnaBridge | 161:aa5281ff4a02 | 1002 | ((CLKOUT) == DFSDM2_CKOUT_DFSDM2)) |
AnnaBridge | 161:aa5281ff4a02 | 1003 | #define IS_DFSDM_DFSDM1_CLKIN(CLKIN) (((CLKIN) == DFSDM1_CKIN_DFSDM2_CKOUT) || \ |
AnnaBridge | 161:aa5281ff4a02 | 1004 | ((CLKIN) == DFSDM1_CKIN_PAD)) |
AnnaBridge | 161:aa5281ff4a02 | 1005 | #define IS_DFSDM_DFSDM2_CLKIN(CLKIN) (((CLKIN) == DFSDM2_CKIN_DFSDM2_CKOUT) || \ |
AnnaBridge | 161:aa5281ff4a02 | 1006 | ((CLKIN) == DFSDM2_CKIN_PAD)) |
AnnaBridge | 161:aa5281ff4a02 | 1007 | #define IS_DFSDM_DFSDM1_BIT_CLK(CLK) (((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN0) || \ |
AnnaBridge | 161:aa5281ff4a02 | 1008 | ((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN2) || \ |
AnnaBridge | 161:aa5281ff4a02 | 1009 | ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN3) || \ |
AnnaBridge | 161:aa5281ff4a02 | 1010 | ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN1) || \ |
AnnaBridge | 161:aa5281ff4a02 | 1011 | ((CLK) <= 0x30U)) |
AnnaBridge | 161:aa5281ff4a02 | 1012 | |
AnnaBridge | 161:aa5281ff4a02 | 1013 | #define IS_DFSDM_DFSDM2_BIT_CLK(CLK) (((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN0) || \ |
AnnaBridge | 161:aa5281ff4a02 | 1014 | ((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN4) || \ |
AnnaBridge | 161:aa5281ff4a02 | 1015 | ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN5) || \ |
AnnaBridge | 161:aa5281ff4a02 | 1016 | ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN1) || \ |
AnnaBridge | 161:aa5281ff4a02 | 1017 | ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN6) || \ |
AnnaBridge | 161:aa5281ff4a02 | 1018 | ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN2) || \ |
AnnaBridge | 161:aa5281ff4a02 | 1019 | ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN3) || \ |
AnnaBridge | 161:aa5281ff4a02 | 1020 | ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN7)|| \ |
AnnaBridge | 161:aa5281ff4a02 | 1021 | ((CLK) <= 0x1E000U)) |
AnnaBridge | 161:aa5281ff4a02 | 1022 | |
AnnaBridge | 161:aa5281ff4a02 | 1023 | #define IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN0_PAD )|| \ |
AnnaBridge | 161:aa5281ff4a02 | 1024 | ((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN1_PAD) || \ |
AnnaBridge | 161:aa5281ff4a02 | 1025 | ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN2_PAD) || \ |
AnnaBridge | 161:aa5281ff4a02 | 1026 | ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN3_PAD)|| \ |
AnnaBridge | 161:aa5281ff4a02 | 1027 | ((DISTRIBUTION) <= 0xCU)) |
AnnaBridge | 161:aa5281ff4a02 | 1028 | |
AnnaBridge | 161:aa5281ff4a02 | 1029 | #define IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN0_PAD)|| \ |
AnnaBridge | 161:aa5281ff4a02 | 1030 | ((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN1_PAD)|| \ |
AnnaBridge | 161:aa5281ff4a02 | 1031 | ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN2_PAD)|| \ |
AnnaBridge | 161:aa5281ff4a02 | 1032 | ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN3_PAD)|| \ |
AnnaBridge | 161:aa5281ff4a02 | 1033 | ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN4_PAD)|| \ |
AnnaBridge | 161:aa5281ff4a02 | 1034 | ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN5_PAD)|| \ |
AnnaBridge | 161:aa5281ff4a02 | 1035 | ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN6_PAD)|| \ |
AnnaBridge | 161:aa5281ff4a02 | 1036 | ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN7_PAD)|| \ |
AnnaBridge | 161:aa5281ff4a02 | 1037 | ((DISTRIBUTION) <= 0x1D00U)) |
AnnaBridge | 161:aa5281ff4a02 | 1038 | #endif /* (SYSCFG_MCHDLYCR_BSCKSEL) */ |
AnnaBridge | 161:aa5281ff4a02 | 1039 | /** |
AnnaBridge | 161:aa5281ff4a02 | 1040 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 1041 | */ |
AnnaBridge | 161:aa5281ff4a02 | 1042 | /* End of private macros -----------------------------------------------------*/ |
AnnaBridge | 161:aa5281ff4a02 | 1043 | |
AnnaBridge | 161:aa5281ff4a02 | 1044 | /** |
AnnaBridge | 161:aa5281ff4a02 | 1045 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 1046 | */ |
AnnaBridge | 161:aa5281ff4a02 | 1047 | |
AnnaBridge | 161:aa5281ff4a02 | 1048 | /** |
AnnaBridge | 161:aa5281ff4a02 | 1049 | * @} |
AnnaBridge | 161:aa5281ff4a02 | 1050 | */ |
AnnaBridge | 161:aa5281ff4a02 | 1051 | #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ |
AnnaBridge | 161:aa5281ff4a02 | 1052 | #ifdef __cplusplus |
AnnaBridge | 161:aa5281ff4a02 | 1053 | } |
AnnaBridge | 161:aa5281ff4a02 | 1054 | #endif |
AnnaBridge | 161:aa5281ff4a02 | 1055 | |
AnnaBridge | 161:aa5281ff4a02 | 1056 | #endif /* __STM32F4xx_HAL_DFSDM_H */ |
AnnaBridge | 161:aa5281ff4a02 | 1057 | |
AnnaBridge | 161:aa5281ff4a02 | 1058 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |