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TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_MICRO/stm32f0xx_ll_dac.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f0xx_ll_dac.h |
AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of DAC LL module. |
AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 32 | * |
AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F0xx_LL_DAC_H |
AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F0xx_LL_DAC_H |
AnnaBridge | 171:3a7713b1edbc | 39 | |
AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f0xx.h" |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F0xx_LL_Driver |
AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 49 | */ |
AnnaBridge | 171:3a7713b1edbc | 50 | |
AnnaBridge | 171:3a7713b1edbc | 51 | #if defined (DAC1) |
AnnaBridge | 171:3a7713b1edbc | 52 | |
AnnaBridge | 171:3a7713b1edbc | 53 | /** @defgroup DAC_LL DAC |
AnnaBridge | 171:3a7713b1edbc | 54 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 55 | */ |
AnnaBridge | 171:3a7713b1edbc | 56 | |
AnnaBridge | 171:3a7713b1edbc | 57 | /* Private types -------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 58 | /* Private variables ---------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 59 | |
AnnaBridge | 171:3a7713b1edbc | 60 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 61 | /** @defgroup DAC_LL_Private_Constants DAC Private Constants |
AnnaBridge | 171:3a7713b1edbc | 62 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 63 | */ |
AnnaBridge | 171:3a7713b1edbc | 64 | |
AnnaBridge | 171:3a7713b1edbc | 65 | /* Internal masks for DAC channels definition */ |
AnnaBridge | 171:3a7713b1edbc | 66 | /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ |
AnnaBridge | 171:3a7713b1edbc | 67 | /* - channel bits position into register CR */ |
AnnaBridge | 171:3a7713b1edbc | 68 | /* - channel bits position into register SWTRIG */ |
AnnaBridge | 171:3a7713b1edbc | 69 | /* - channel register offset of data holding register DHRx */ |
AnnaBridge | 171:3a7713b1edbc | 70 | /* - channel register offset of data output register DORx */ |
AnnaBridge | 171:3a7713b1edbc | 71 | #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 72 | #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 73 | #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) |
AnnaBridge | 171:3a7713b1edbc | 74 | |
AnnaBridge | 171:3a7713b1edbc | 75 | #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ |
AnnaBridge | 171:3a7713b1edbc | 76 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 77 | #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ |
AnnaBridge | 171:3a7713b1edbc | 78 | #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) |
AnnaBridge | 171:3a7713b1edbc | 79 | #else |
AnnaBridge | 171:3a7713b1edbc | 80 | #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1) |
AnnaBridge | 171:3a7713b1edbc | 81 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 82 | |
AnnaBridge | 171:3a7713b1edbc | 83 | #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ |
AnnaBridge | 171:3a7713b1edbc | 84 | #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
AnnaBridge | 171:3a7713b1edbc | 85 | #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
AnnaBridge | 171:3a7713b1edbc | 86 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 87 | #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ |
AnnaBridge | 171:3a7713b1edbc | 88 | #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
AnnaBridge | 171:3a7713b1edbc | 89 | #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
AnnaBridge | 171:3a7713b1edbc | 90 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 91 | #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U |
AnnaBridge | 171:3a7713b1edbc | 92 | #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U |
AnnaBridge | 171:3a7713b1edbc | 93 | #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U |
AnnaBridge | 171:3a7713b1edbc | 94 | #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 95 | |
AnnaBridge | 171:3a7713b1edbc | 96 | #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ |
AnnaBridge | 171:3a7713b1edbc | 97 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 98 | #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ |
AnnaBridge | 171:3a7713b1edbc | 99 | #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) |
AnnaBridge | 171:3a7713b1edbc | 100 | #else |
AnnaBridge | 171:3a7713b1edbc | 101 | #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET) |
AnnaBridge | 171:3a7713b1edbc | 102 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 103 | |
AnnaBridge | 171:3a7713b1edbc | 104 | #define DAC_REG_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of registers offset (DHR12Rx, DHR12Lx, DHR8Rx, DORx, ...) when shifted to position 0 */ |
AnnaBridge | 171:3a7713b1edbc | 105 | |
AnnaBridge | 171:3a7713b1edbc | 106 | #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ |
AnnaBridge | 171:3a7713b1edbc | 107 | #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
AnnaBridge | 171:3a7713b1edbc | 108 | #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
AnnaBridge | 171:3a7713b1edbc | 109 | #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */ |
AnnaBridge | 171:3a7713b1edbc | 110 | |
AnnaBridge | 171:3a7713b1edbc | 111 | /* DAC registers bits positions */ |
AnnaBridge | 171:3a7713b1edbc | 112 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 113 | #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ |
AnnaBridge | 171:3a7713b1edbc | 114 | #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ |
AnnaBridge | 171:3a7713b1edbc | 115 | #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ |
AnnaBridge | 171:3a7713b1edbc | 116 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 117 | |
AnnaBridge | 171:3a7713b1edbc | 118 | /* Miscellaneous data */ |
AnnaBridge | 171:3a7713b1edbc | 119 | #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ |
AnnaBridge | 171:3a7713b1edbc | 120 | |
AnnaBridge | 171:3a7713b1edbc | 121 | /** |
AnnaBridge | 171:3a7713b1edbc | 122 | * @} |
AnnaBridge | 171:3a7713b1edbc | 123 | */ |
AnnaBridge | 171:3a7713b1edbc | 124 | |
AnnaBridge | 171:3a7713b1edbc | 125 | |
AnnaBridge | 171:3a7713b1edbc | 126 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 127 | /** @defgroup DAC_LL_Private_Macros DAC Private Macros |
AnnaBridge | 171:3a7713b1edbc | 128 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 129 | */ |
AnnaBridge | 171:3a7713b1edbc | 130 | |
AnnaBridge | 171:3a7713b1edbc | 131 | /** |
AnnaBridge | 171:3a7713b1edbc | 132 | * @brief Driver macro reserved for internal use: set a pointer to |
AnnaBridge | 171:3a7713b1edbc | 133 | * a register from a register basis from which an offset |
AnnaBridge | 171:3a7713b1edbc | 134 | * is applied. |
AnnaBridge | 171:3a7713b1edbc | 135 | * @param __REG__ Register basis from which the offset is applied. |
AnnaBridge | 171:3a7713b1edbc | 136 | * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). |
AnnaBridge | 171:3a7713b1edbc | 137 | * @retval Pointer to register address |
AnnaBridge | 171:3a7713b1edbc | 138 | */ |
AnnaBridge | 171:3a7713b1edbc | 139 | #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ |
AnnaBridge | 171:3a7713b1edbc | 140 | ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) |
AnnaBridge | 171:3a7713b1edbc | 141 | |
AnnaBridge | 171:3a7713b1edbc | 142 | /** |
AnnaBridge | 171:3a7713b1edbc | 143 | * @} |
AnnaBridge | 171:3a7713b1edbc | 144 | */ |
AnnaBridge | 171:3a7713b1edbc | 145 | |
AnnaBridge | 171:3a7713b1edbc | 146 | |
AnnaBridge | 171:3a7713b1edbc | 147 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 148 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 149 | /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure |
AnnaBridge | 171:3a7713b1edbc | 150 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 151 | */ |
AnnaBridge | 171:3a7713b1edbc | 152 | |
AnnaBridge | 171:3a7713b1edbc | 153 | /** |
AnnaBridge | 171:3a7713b1edbc | 154 | * @brief Structure definition of some features of DAC instance. |
AnnaBridge | 171:3a7713b1edbc | 155 | */ |
AnnaBridge | 171:3a7713b1edbc | 156 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 157 | { |
AnnaBridge | 171:3a7713b1edbc | 158 | uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line). |
AnnaBridge | 171:3a7713b1edbc | 159 | This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE |
AnnaBridge | 171:3a7713b1edbc | 160 | |
AnnaBridge | 171:3a7713b1edbc | 161 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */ |
AnnaBridge | 171:3a7713b1edbc | 162 | |
AnnaBridge | 171:3a7713b1edbc | 163 | #if defined(DAC_CR_WAVE1) |
AnnaBridge | 171:3a7713b1edbc | 164 | uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. |
AnnaBridge | 171:3a7713b1edbc | 165 | This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE |
AnnaBridge | 171:3a7713b1edbc | 166 | |
AnnaBridge | 171:3a7713b1edbc | 167 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */ |
AnnaBridge | 171:3a7713b1edbc | 168 | |
AnnaBridge | 171:3a7713b1edbc | 169 | uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. |
AnnaBridge | 171:3a7713b1edbc | 170 | If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS |
AnnaBridge | 171:3a7713b1edbc | 171 | If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE |
AnnaBridge | 171:3a7713b1edbc | 172 | @note If waveform automatic generation mode is disabled, this parameter is discarded. |
AnnaBridge | 171:3a7713b1edbc | 173 | |
AnnaBridge | 171:3a7713b1edbc | 174 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */ |
AnnaBridge | 171:3a7713b1edbc | 175 | #endif |
AnnaBridge | 171:3a7713b1edbc | 176 | |
AnnaBridge | 171:3a7713b1edbc | 177 | uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. |
AnnaBridge | 171:3a7713b1edbc | 178 | This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER |
AnnaBridge | 171:3a7713b1edbc | 179 | |
AnnaBridge | 171:3a7713b1edbc | 180 | This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ |
AnnaBridge | 171:3a7713b1edbc | 181 | |
AnnaBridge | 171:3a7713b1edbc | 182 | } LL_DAC_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 183 | |
AnnaBridge | 171:3a7713b1edbc | 184 | /** |
AnnaBridge | 171:3a7713b1edbc | 185 | * @} |
AnnaBridge | 171:3a7713b1edbc | 186 | */ |
AnnaBridge | 171:3a7713b1edbc | 187 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 171:3a7713b1edbc | 188 | |
AnnaBridge | 171:3a7713b1edbc | 189 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 190 | /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants |
AnnaBridge | 171:3a7713b1edbc | 191 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 192 | */ |
AnnaBridge | 171:3a7713b1edbc | 193 | |
AnnaBridge | 171:3a7713b1edbc | 194 | /** @defgroup DAC_LL_EC_GET_FLAG DAC flags |
AnnaBridge | 171:3a7713b1edbc | 195 | * @brief Flags defines which can be used with LL_DAC_ReadReg function |
AnnaBridge | 171:3a7713b1edbc | 196 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 197 | */ |
AnnaBridge | 171:3a7713b1edbc | 198 | /* DAC channel 1 flags */ |
AnnaBridge | 171:3a7713b1edbc | 199 | #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ |
AnnaBridge | 171:3a7713b1edbc | 200 | |
AnnaBridge | 171:3a7713b1edbc | 201 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 202 | /* DAC channel 2 flags */ |
AnnaBridge | 171:3a7713b1edbc | 203 | #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ |
AnnaBridge | 171:3a7713b1edbc | 204 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 205 | /** |
AnnaBridge | 171:3a7713b1edbc | 206 | * @} |
AnnaBridge | 171:3a7713b1edbc | 207 | */ |
AnnaBridge | 171:3a7713b1edbc | 208 | |
AnnaBridge | 171:3a7713b1edbc | 209 | /** @defgroup DAC_LL_EC_IT DAC interruptions |
AnnaBridge | 171:3a7713b1edbc | 210 | * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions |
AnnaBridge | 171:3a7713b1edbc | 211 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 212 | */ |
AnnaBridge | 171:3a7713b1edbc | 213 | #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ |
AnnaBridge | 171:3a7713b1edbc | 214 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 215 | #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ |
AnnaBridge | 171:3a7713b1edbc | 216 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 217 | /** |
AnnaBridge | 171:3a7713b1edbc | 218 | * @} |
AnnaBridge | 171:3a7713b1edbc | 219 | */ |
AnnaBridge | 171:3a7713b1edbc | 220 | |
AnnaBridge | 171:3a7713b1edbc | 221 | /** @defgroup DAC_LL_EC_CHANNEL DAC channels |
AnnaBridge | 171:3a7713b1edbc | 222 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 223 | */ |
AnnaBridge | 171:3a7713b1edbc | 224 | #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 225 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 226 | #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 227 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 228 | /** |
AnnaBridge | 171:3a7713b1edbc | 229 | * @} |
AnnaBridge | 171:3a7713b1edbc | 230 | */ |
AnnaBridge | 171:3a7713b1edbc | 231 | |
AnnaBridge | 171:3a7713b1edbc | 232 | /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source |
AnnaBridge | 171:3a7713b1edbc | 233 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 234 | */ |
AnnaBridge | 171:3a7713b1edbc | 235 | #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ |
AnnaBridge | 171:3a7713b1edbc | 236 | #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ |
AnnaBridge | 171:3a7713b1edbc | 237 | #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */ |
AnnaBridge | 171:3a7713b1edbc | 238 | #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ |
AnnaBridge | 171:3a7713b1edbc | 239 | #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ |
AnnaBridge | 171:3a7713b1edbc | 240 | #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ |
AnnaBridge | 171:3a7713b1edbc | 241 | #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */ |
AnnaBridge | 171:3a7713b1edbc | 242 | #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ |
AnnaBridge | 171:3a7713b1edbc | 243 | /** |
AnnaBridge | 171:3a7713b1edbc | 244 | * @} |
AnnaBridge | 171:3a7713b1edbc | 245 | */ |
AnnaBridge | 171:3a7713b1edbc | 246 | |
AnnaBridge | 171:3a7713b1edbc | 247 | /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode |
AnnaBridge | 171:3a7713b1edbc | 248 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 249 | */ |
AnnaBridge | 171:3a7713b1edbc | 250 | #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ |
AnnaBridge | 171:3a7713b1edbc | 251 | #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ |
AnnaBridge | 171:3a7713b1edbc | 252 | #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ |
AnnaBridge | 171:3a7713b1edbc | 253 | /** |
AnnaBridge | 171:3a7713b1edbc | 254 | * @} |
AnnaBridge | 171:3a7713b1edbc | 255 | */ |
AnnaBridge | 171:3a7713b1edbc | 256 | |
AnnaBridge | 171:3a7713b1edbc | 257 | /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits |
AnnaBridge | 171:3a7713b1edbc | 258 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 259 | */ |
AnnaBridge | 171:3a7713b1edbc | 260 | #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 261 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 262 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 263 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 264 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 265 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 266 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 267 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 268 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 269 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 270 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 271 | #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 272 | /** |
AnnaBridge | 171:3a7713b1edbc | 273 | * @} |
AnnaBridge | 171:3a7713b1edbc | 274 | */ |
AnnaBridge | 171:3a7713b1edbc | 275 | |
AnnaBridge | 171:3a7713b1edbc | 276 | /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude |
AnnaBridge | 171:3a7713b1edbc | 277 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 278 | */ |
AnnaBridge | 171:3a7713b1edbc | 279 | #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 280 | #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 281 | #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 282 | #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 283 | #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 284 | #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 285 | #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 286 | #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 287 | #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 288 | #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 289 | #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 290 | #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ |
AnnaBridge | 171:3a7713b1edbc | 291 | /** |
AnnaBridge | 171:3a7713b1edbc | 292 | * @} |
AnnaBridge | 171:3a7713b1edbc | 293 | */ |
AnnaBridge | 171:3a7713b1edbc | 294 | |
AnnaBridge | 171:3a7713b1edbc | 295 | /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer |
AnnaBridge | 171:3a7713b1edbc | 296 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 297 | */ |
AnnaBridge | 171:3a7713b1edbc | 298 | #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ |
AnnaBridge | 171:3a7713b1edbc | 299 | #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ |
AnnaBridge | 171:3a7713b1edbc | 300 | /** |
AnnaBridge | 171:3a7713b1edbc | 301 | * @} |
AnnaBridge | 171:3a7713b1edbc | 302 | */ |
AnnaBridge | 171:3a7713b1edbc | 303 | |
AnnaBridge | 171:3a7713b1edbc | 304 | |
AnnaBridge | 171:3a7713b1edbc | 305 | /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution |
AnnaBridge | 171:3a7713b1edbc | 306 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 307 | */ |
AnnaBridge | 171:3a7713b1edbc | 308 | #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */ |
AnnaBridge | 171:3a7713b1edbc | 309 | #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */ |
AnnaBridge | 171:3a7713b1edbc | 310 | /** |
AnnaBridge | 171:3a7713b1edbc | 311 | * @} |
AnnaBridge | 171:3a7713b1edbc | 312 | */ |
AnnaBridge | 171:3a7713b1edbc | 313 | |
AnnaBridge | 171:3a7713b1edbc | 314 | /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose |
AnnaBridge | 171:3a7713b1edbc | 315 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 316 | */ |
AnnaBridge | 171:3a7713b1edbc | 317 | /* List of DAC registers intended to be used (most commonly) with */ |
AnnaBridge | 171:3a7713b1edbc | 318 | /* DMA transfer. */ |
AnnaBridge | 171:3a7713b1edbc | 319 | /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ |
AnnaBridge | 171:3a7713b1edbc | 320 | #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */ |
AnnaBridge | 171:3a7713b1edbc | 321 | #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */ |
AnnaBridge | 171:3a7713b1edbc | 322 | #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */ |
AnnaBridge | 171:3a7713b1edbc | 323 | /** |
AnnaBridge | 171:3a7713b1edbc | 324 | * @} |
AnnaBridge | 171:3a7713b1edbc | 325 | */ |
AnnaBridge | 171:3a7713b1edbc | 326 | |
AnnaBridge | 171:3a7713b1edbc | 327 | /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays |
AnnaBridge | 171:3a7713b1edbc | 328 | * @note Only DAC IP HW delays are defined in DAC LL driver driver, |
AnnaBridge | 171:3a7713b1edbc | 329 | * not timeout values. |
AnnaBridge | 171:3a7713b1edbc | 330 | * For details on delays values, refer to descriptions in source code |
AnnaBridge | 171:3a7713b1edbc | 331 | * above each literal definition. |
AnnaBridge | 171:3a7713b1edbc | 332 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 333 | */ |
AnnaBridge | 171:3a7713b1edbc | 334 | |
AnnaBridge | 171:3a7713b1edbc | 335 | /* Delay for DAC channel voltage settling time from DAC channel startup */ |
AnnaBridge | 171:3a7713b1edbc | 336 | /* (transition from disable to enable). */ |
AnnaBridge | 171:3a7713b1edbc | 337 | /* Note: DAC channel startup time depends on board application environment: */ |
AnnaBridge | 171:3a7713b1edbc | 338 | /* impedance connected to DAC channel output. */ |
AnnaBridge | 171:3a7713b1edbc | 339 | /* The delay below is specified under conditions: */ |
AnnaBridge | 171:3a7713b1edbc | 340 | /* - voltage maximum transition (lowest to highest value) */ |
AnnaBridge | 171:3a7713b1edbc | 341 | /* - until voltage reaches final value +-1LSB */ |
AnnaBridge | 171:3a7713b1edbc | 342 | /* - DAC channel output buffer enabled */ |
AnnaBridge | 171:3a7713b1edbc | 343 | /* - load impedance of 5kOhm (min), 50pF (max) */ |
AnnaBridge | 171:3a7713b1edbc | 344 | /* Literal set to maximum value (refer to device datasheet, */ |
AnnaBridge | 171:3a7713b1edbc | 345 | /* parameter "tWAKEUP"). */ |
AnnaBridge | 171:3a7713b1edbc | 346 | /* Unit: us */ |
AnnaBridge | 171:3a7713b1edbc | 347 | #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ |
AnnaBridge | 171:3a7713b1edbc | 348 | |
AnnaBridge | 171:3a7713b1edbc | 349 | /* Delay for DAC channel voltage settling time. */ |
AnnaBridge | 171:3a7713b1edbc | 350 | /* Note: DAC channel startup time depends on board application environment: */ |
AnnaBridge | 171:3a7713b1edbc | 351 | /* impedance connected to DAC channel output. */ |
AnnaBridge | 171:3a7713b1edbc | 352 | /* The delay below is specified under conditions: */ |
AnnaBridge | 171:3a7713b1edbc | 353 | /* - voltage maximum transition (lowest to highest value) */ |
AnnaBridge | 171:3a7713b1edbc | 354 | /* - until voltage reaches final value +-1LSB */ |
AnnaBridge | 171:3a7713b1edbc | 355 | /* - DAC channel output buffer enabled */ |
AnnaBridge | 171:3a7713b1edbc | 356 | /* - load impedance of 5kOhm min, 50pF max */ |
AnnaBridge | 171:3a7713b1edbc | 357 | /* Literal set to maximum value (refer to device datasheet, */ |
AnnaBridge | 171:3a7713b1edbc | 358 | /* parameter "tSETTLING"). */ |
AnnaBridge | 171:3a7713b1edbc | 359 | /* Unit: us */ |
AnnaBridge | 171:3a7713b1edbc | 360 | #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */ |
AnnaBridge | 171:3a7713b1edbc | 361 | /** |
AnnaBridge | 171:3a7713b1edbc | 362 | * @} |
AnnaBridge | 171:3a7713b1edbc | 363 | */ |
AnnaBridge | 171:3a7713b1edbc | 364 | |
AnnaBridge | 171:3a7713b1edbc | 365 | /** |
AnnaBridge | 171:3a7713b1edbc | 366 | * @} |
AnnaBridge | 171:3a7713b1edbc | 367 | */ |
AnnaBridge | 171:3a7713b1edbc | 368 | |
AnnaBridge | 171:3a7713b1edbc | 369 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 370 | /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros |
AnnaBridge | 171:3a7713b1edbc | 371 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 372 | */ |
AnnaBridge | 171:3a7713b1edbc | 373 | |
AnnaBridge | 171:3a7713b1edbc | 374 | /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros |
AnnaBridge | 171:3a7713b1edbc | 375 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 376 | */ |
AnnaBridge | 171:3a7713b1edbc | 377 | |
AnnaBridge | 171:3a7713b1edbc | 378 | /** |
AnnaBridge | 171:3a7713b1edbc | 379 | * @brief Write a value in DAC register |
AnnaBridge | 171:3a7713b1edbc | 380 | * @param __INSTANCE__ DAC Instance |
AnnaBridge | 171:3a7713b1edbc | 381 | * @param __REG__ Register to be written |
AnnaBridge | 171:3a7713b1edbc | 382 | * @param __VALUE__ Value to be written in the register |
AnnaBridge | 171:3a7713b1edbc | 383 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 384 | */ |
AnnaBridge | 171:3a7713b1edbc | 385 | #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
AnnaBridge | 171:3a7713b1edbc | 386 | |
AnnaBridge | 171:3a7713b1edbc | 387 | /** |
AnnaBridge | 171:3a7713b1edbc | 388 | * @brief Read a value in DAC register |
AnnaBridge | 171:3a7713b1edbc | 389 | * @param __INSTANCE__ DAC Instance |
AnnaBridge | 171:3a7713b1edbc | 390 | * @param __REG__ Register to be read |
AnnaBridge | 171:3a7713b1edbc | 391 | * @retval Register value |
AnnaBridge | 171:3a7713b1edbc | 392 | */ |
AnnaBridge | 171:3a7713b1edbc | 393 | #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
AnnaBridge | 171:3a7713b1edbc | 394 | |
AnnaBridge | 171:3a7713b1edbc | 395 | /** |
AnnaBridge | 171:3a7713b1edbc | 396 | * @} |
AnnaBridge | 171:3a7713b1edbc | 397 | */ |
AnnaBridge | 171:3a7713b1edbc | 398 | |
AnnaBridge | 171:3a7713b1edbc | 399 | /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro |
AnnaBridge | 171:3a7713b1edbc | 400 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 401 | */ |
AnnaBridge | 171:3a7713b1edbc | 402 | |
AnnaBridge | 171:3a7713b1edbc | 403 | /** |
AnnaBridge | 171:3a7713b1edbc | 404 | * @brief Helper macro to get DAC channel number in decimal format |
AnnaBridge | 171:3a7713b1edbc | 405 | * from literals LL_DAC_CHANNEL_x. |
AnnaBridge | 171:3a7713b1edbc | 406 | * Example: |
AnnaBridge | 171:3a7713b1edbc | 407 | * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) |
AnnaBridge | 171:3a7713b1edbc | 408 | * will return decimal number "1". |
AnnaBridge | 171:3a7713b1edbc | 409 | * @note The input can be a value from functions where a channel |
AnnaBridge | 171:3a7713b1edbc | 410 | * number is returned. |
AnnaBridge | 171:3a7713b1edbc | 411 | * @param __CHANNEL__ This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 412 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 413 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 414 | * |
AnnaBridge | 171:3a7713b1edbc | 415 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 416 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 417 | * @retval 1...2 (value "2" depending on DAC channel 2 availability) |
AnnaBridge | 171:3a7713b1edbc | 418 | */ |
AnnaBridge | 171:3a7713b1edbc | 419 | #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ |
AnnaBridge | 171:3a7713b1edbc | 420 | ((__CHANNEL__) & DAC_SWTR_CHX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 421 | |
AnnaBridge | 171:3a7713b1edbc | 422 | /** |
AnnaBridge | 171:3a7713b1edbc | 423 | * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x |
AnnaBridge | 171:3a7713b1edbc | 424 | * from number in decimal format. |
AnnaBridge | 171:3a7713b1edbc | 425 | * Example: |
AnnaBridge | 171:3a7713b1edbc | 426 | * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) |
AnnaBridge | 171:3a7713b1edbc | 427 | * will return a data equivalent to "LL_DAC_CHANNEL_1". |
AnnaBridge | 171:3a7713b1edbc | 428 | * @note If the input parameter does not correspond to a DAC channel, |
AnnaBridge | 171:3a7713b1edbc | 429 | * this macro returns value '0'. |
AnnaBridge | 171:3a7713b1edbc | 430 | * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability) |
AnnaBridge | 171:3a7713b1edbc | 431 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 432 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 433 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 434 | * |
AnnaBridge | 171:3a7713b1edbc | 435 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 436 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 437 | */ |
AnnaBridge | 171:3a7713b1edbc | 438 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 439 | #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ |
AnnaBridge | 171:3a7713b1edbc | 440 | (((__DECIMAL_NB__) == 1U) \ |
AnnaBridge | 171:3a7713b1edbc | 441 | ? ( \ |
AnnaBridge | 171:3a7713b1edbc | 442 | LL_DAC_CHANNEL_1 \ |
AnnaBridge | 171:3a7713b1edbc | 443 | ) \ |
AnnaBridge | 171:3a7713b1edbc | 444 | : \ |
AnnaBridge | 171:3a7713b1edbc | 445 | (((__DECIMAL_NB__) == 2U) \ |
AnnaBridge | 171:3a7713b1edbc | 446 | ? ( \ |
AnnaBridge | 171:3a7713b1edbc | 447 | LL_DAC_CHANNEL_2 \ |
AnnaBridge | 171:3a7713b1edbc | 448 | ) \ |
AnnaBridge | 171:3a7713b1edbc | 449 | : \ |
AnnaBridge | 171:3a7713b1edbc | 450 | ( \ |
AnnaBridge | 171:3a7713b1edbc | 451 | 0 \ |
AnnaBridge | 171:3a7713b1edbc | 452 | ) \ |
AnnaBridge | 171:3a7713b1edbc | 453 | ) \ |
AnnaBridge | 171:3a7713b1edbc | 454 | ) |
AnnaBridge | 171:3a7713b1edbc | 455 | #else |
AnnaBridge | 171:3a7713b1edbc | 456 | #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ |
AnnaBridge | 171:3a7713b1edbc | 457 | (((__DECIMAL_NB__) == 1U) \ |
AnnaBridge | 171:3a7713b1edbc | 458 | ? ( \ |
AnnaBridge | 171:3a7713b1edbc | 459 | LL_DAC_CHANNEL_1 \ |
AnnaBridge | 171:3a7713b1edbc | 460 | ) \ |
AnnaBridge | 171:3a7713b1edbc | 461 | : \ |
AnnaBridge | 171:3a7713b1edbc | 462 | ( \ |
AnnaBridge | 171:3a7713b1edbc | 463 | 0 \ |
AnnaBridge | 171:3a7713b1edbc | 464 | ) \ |
AnnaBridge | 171:3a7713b1edbc | 465 | ) |
AnnaBridge | 171:3a7713b1edbc | 466 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 467 | |
AnnaBridge | 171:3a7713b1edbc | 468 | /** |
AnnaBridge | 171:3a7713b1edbc | 469 | * @brief Helper macro to define the DAC conversion data full-scale digital |
AnnaBridge | 171:3a7713b1edbc | 470 | * value corresponding to the selected DAC resolution. |
AnnaBridge | 171:3a7713b1edbc | 471 | * @note DAC conversion data full-scale corresponds to voltage range |
AnnaBridge | 171:3a7713b1edbc | 472 | * determined by analog voltage references Vref+ and Vref- |
AnnaBridge | 171:3a7713b1edbc | 473 | * (refer to reference manual). |
AnnaBridge | 171:3a7713b1edbc | 474 | * @param __DAC_RESOLUTION__ This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 475 | * @arg @ref LL_DAC_RESOLUTION_12B |
AnnaBridge | 171:3a7713b1edbc | 476 | * @arg @ref LL_DAC_RESOLUTION_8B |
AnnaBridge | 171:3a7713b1edbc | 477 | * @retval ADC conversion data equivalent voltage value (unit: mVolt) |
AnnaBridge | 171:3a7713b1edbc | 478 | */ |
AnnaBridge | 171:3a7713b1edbc | 479 | #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ |
AnnaBridge | 171:3a7713b1edbc | 480 | ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U)) |
AnnaBridge | 171:3a7713b1edbc | 481 | |
AnnaBridge | 171:3a7713b1edbc | 482 | /** |
AnnaBridge | 171:3a7713b1edbc | 483 | * @brief Helper macro to calculate the DAC conversion data (unit: digital |
AnnaBridge | 171:3a7713b1edbc | 484 | * value) corresponding to a voltage (unit: mVolt). |
AnnaBridge | 171:3a7713b1edbc | 485 | * @note This helper macro is intended to provide input data in voltage |
AnnaBridge | 171:3a7713b1edbc | 486 | * rather than digital value, |
AnnaBridge | 171:3a7713b1edbc | 487 | * to be used with LL DAC functions such as |
AnnaBridge | 171:3a7713b1edbc | 488 | * @ref LL_DAC_ConvertData12RightAligned(). |
AnnaBridge | 171:3a7713b1edbc | 489 | * @note Analog reference voltage (Vref+) must be either known from |
AnnaBridge | 171:3a7713b1edbc | 490 | * user board environment or can be calculated using ADC measurement |
AnnaBridge | 171:3a7713b1edbc | 491 | * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). |
AnnaBridge | 171:3a7713b1edbc | 492 | * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) |
AnnaBridge | 171:3a7713b1edbc | 493 | * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel |
AnnaBridge | 171:3a7713b1edbc | 494 | * (unit: mVolt). |
AnnaBridge | 171:3a7713b1edbc | 495 | * @param __DAC_RESOLUTION__ This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 496 | * @arg @ref LL_DAC_RESOLUTION_12B |
AnnaBridge | 171:3a7713b1edbc | 497 | * @arg @ref LL_DAC_RESOLUTION_8B |
AnnaBridge | 171:3a7713b1edbc | 498 | * @retval DAC conversion data (unit: digital value) |
AnnaBridge | 171:3a7713b1edbc | 499 | */ |
AnnaBridge | 171:3a7713b1edbc | 500 | #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ |
AnnaBridge | 171:3a7713b1edbc | 501 | __DAC_VOLTAGE__,\ |
AnnaBridge | 171:3a7713b1edbc | 502 | __DAC_RESOLUTION__) \ |
AnnaBridge | 171:3a7713b1edbc | 503 | ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ |
AnnaBridge | 171:3a7713b1edbc | 504 | / (__VREFANALOG_VOLTAGE__) \ |
AnnaBridge | 171:3a7713b1edbc | 505 | ) |
AnnaBridge | 171:3a7713b1edbc | 506 | |
AnnaBridge | 171:3a7713b1edbc | 507 | /** |
AnnaBridge | 171:3a7713b1edbc | 508 | * @} |
AnnaBridge | 171:3a7713b1edbc | 509 | */ |
AnnaBridge | 171:3a7713b1edbc | 510 | |
AnnaBridge | 171:3a7713b1edbc | 511 | /** |
AnnaBridge | 171:3a7713b1edbc | 512 | * @} |
AnnaBridge | 171:3a7713b1edbc | 513 | */ |
AnnaBridge | 171:3a7713b1edbc | 514 | |
AnnaBridge | 171:3a7713b1edbc | 515 | |
AnnaBridge | 171:3a7713b1edbc | 516 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 517 | /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions |
AnnaBridge | 171:3a7713b1edbc | 518 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 519 | */ |
AnnaBridge | 171:3a7713b1edbc | 520 | /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels |
AnnaBridge | 171:3a7713b1edbc | 521 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 522 | */ |
AnnaBridge | 171:3a7713b1edbc | 523 | |
AnnaBridge | 171:3a7713b1edbc | 524 | /** |
AnnaBridge | 171:3a7713b1edbc | 525 | * @brief Set the conversion trigger source for the selected DAC channel. |
AnnaBridge | 171:3a7713b1edbc | 526 | * @note For conversion trigger source to be effective, DAC trigger |
AnnaBridge | 171:3a7713b1edbc | 527 | * must be enabled using function @ref LL_DAC_EnableTrigger(). |
AnnaBridge | 171:3a7713b1edbc | 528 | * @note To set conversion trigger source, DAC channel must be disabled. |
AnnaBridge | 171:3a7713b1edbc | 529 | * Otherwise, the setting is discarded. |
AnnaBridge | 171:3a7713b1edbc | 530 | * @note Availability of parameters of trigger sources from timer |
AnnaBridge | 171:3a7713b1edbc | 531 | * depends on timers availability on the selected device. |
AnnaBridge | 171:3a7713b1edbc | 532 | * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n |
AnnaBridge | 171:3a7713b1edbc | 533 | * CR TSEL2 LL_DAC_SetTriggerSource |
AnnaBridge | 171:3a7713b1edbc | 534 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 535 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 536 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 537 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 538 | * |
AnnaBridge | 171:3a7713b1edbc | 539 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 540 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 541 | * @param TriggerSource This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 542 | * @arg @ref LL_DAC_TRIG_SOFTWARE |
AnnaBridge | 171:3a7713b1edbc | 543 | * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO |
AnnaBridge | 171:3a7713b1edbc | 544 | * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO |
AnnaBridge | 171:3a7713b1edbc | 545 | * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO |
AnnaBridge | 171:3a7713b1edbc | 546 | * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO |
AnnaBridge | 171:3a7713b1edbc | 547 | * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO |
AnnaBridge | 171:3a7713b1edbc | 548 | * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO |
AnnaBridge | 171:3a7713b1edbc | 549 | * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 |
AnnaBridge | 171:3a7713b1edbc | 550 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 551 | */ |
AnnaBridge | 171:3a7713b1edbc | 552 | __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) |
AnnaBridge | 171:3a7713b1edbc | 553 | { |
AnnaBridge | 171:3a7713b1edbc | 554 | MODIFY_REG(DACx->CR, |
AnnaBridge | 171:3a7713b1edbc | 555 | DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
AnnaBridge | 171:3a7713b1edbc | 556 | TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 171:3a7713b1edbc | 557 | } |
AnnaBridge | 171:3a7713b1edbc | 558 | |
AnnaBridge | 171:3a7713b1edbc | 559 | /** |
AnnaBridge | 171:3a7713b1edbc | 560 | * @brief Get the conversion trigger source for the selected DAC channel. |
AnnaBridge | 171:3a7713b1edbc | 561 | * @note For conversion trigger source to be effective, DAC trigger |
AnnaBridge | 171:3a7713b1edbc | 562 | * must be enabled using function @ref LL_DAC_EnableTrigger(). |
AnnaBridge | 171:3a7713b1edbc | 563 | * @note Availability of parameters of trigger sources from timer |
AnnaBridge | 171:3a7713b1edbc | 564 | * depends on timers availability on the selected device. |
AnnaBridge | 171:3a7713b1edbc | 565 | * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n |
AnnaBridge | 171:3a7713b1edbc | 566 | * CR TSEL2 LL_DAC_GetTriggerSource |
AnnaBridge | 171:3a7713b1edbc | 567 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 568 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 569 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 570 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 571 | * |
AnnaBridge | 171:3a7713b1edbc | 572 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 573 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 574 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 575 | * @arg @ref LL_DAC_TRIG_SOFTWARE |
AnnaBridge | 171:3a7713b1edbc | 576 | * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO |
AnnaBridge | 171:3a7713b1edbc | 577 | * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO |
AnnaBridge | 171:3a7713b1edbc | 578 | * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO |
AnnaBridge | 171:3a7713b1edbc | 579 | * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO |
AnnaBridge | 171:3a7713b1edbc | 580 | * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO |
AnnaBridge | 171:3a7713b1edbc | 581 | * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO |
AnnaBridge | 171:3a7713b1edbc | 582 | * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 |
AnnaBridge | 171:3a7713b1edbc | 583 | */ |
AnnaBridge | 171:3a7713b1edbc | 584 | __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 171:3a7713b1edbc | 585 | { |
AnnaBridge | 171:3a7713b1edbc | 586 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 171:3a7713b1edbc | 587 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 588 | ); |
AnnaBridge | 171:3a7713b1edbc | 589 | } |
AnnaBridge | 171:3a7713b1edbc | 590 | |
AnnaBridge | 171:3a7713b1edbc | 591 | #if defined(DAC_CR_WAVE1) |
AnnaBridge | 171:3a7713b1edbc | 592 | /** |
AnnaBridge | 171:3a7713b1edbc | 593 | * @brief Set the waveform automatic generation mode |
AnnaBridge | 171:3a7713b1edbc | 594 | * for the selected DAC channel. |
AnnaBridge | 171:3a7713b1edbc | 595 | * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n |
AnnaBridge | 171:3a7713b1edbc | 596 | * CR WAVE2 LL_DAC_SetWaveAutoGeneration |
AnnaBridge | 171:3a7713b1edbc | 597 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 598 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 599 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 600 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 601 | * |
AnnaBridge | 171:3a7713b1edbc | 602 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 603 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 604 | * @param WaveAutoGeneration This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 605 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE |
AnnaBridge | 171:3a7713b1edbc | 606 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE |
AnnaBridge | 171:3a7713b1edbc | 607 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE |
AnnaBridge | 171:3a7713b1edbc | 608 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 609 | */ |
AnnaBridge | 171:3a7713b1edbc | 610 | __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) |
AnnaBridge | 171:3a7713b1edbc | 611 | { |
AnnaBridge | 171:3a7713b1edbc | 612 | MODIFY_REG(DACx->CR, |
AnnaBridge | 171:3a7713b1edbc | 613 | DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
AnnaBridge | 171:3a7713b1edbc | 614 | WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 171:3a7713b1edbc | 615 | } |
AnnaBridge | 171:3a7713b1edbc | 616 | |
AnnaBridge | 171:3a7713b1edbc | 617 | /** |
AnnaBridge | 171:3a7713b1edbc | 618 | * @brief Get the waveform automatic generation mode |
AnnaBridge | 171:3a7713b1edbc | 619 | * for the selected DAC channel. |
AnnaBridge | 171:3a7713b1edbc | 620 | * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n |
AnnaBridge | 171:3a7713b1edbc | 621 | * CR WAVE2 LL_DAC_GetWaveAutoGeneration |
AnnaBridge | 171:3a7713b1edbc | 622 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 623 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 624 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 625 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 626 | * |
AnnaBridge | 171:3a7713b1edbc | 627 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 628 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 629 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 630 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE |
AnnaBridge | 171:3a7713b1edbc | 631 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE |
AnnaBridge | 171:3a7713b1edbc | 632 | * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE |
AnnaBridge | 171:3a7713b1edbc | 633 | */ |
AnnaBridge | 171:3a7713b1edbc | 634 | __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 171:3a7713b1edbc | 635 | { |
AnnaBridge | 171:3a7713b1edbc | 636 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 171:3a7713b1edbc | 637 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 638 | ); |
AnnaBridge | 171:3a7713b1edbc | 639 | } |
AnnaBridge | 171:3a7713b1edbc | 640 | |
AnnaBridge | 171:3a7713b1edbc | 641 | /** |
AnnaBridge | 171:3a7713b1edbc | 642 | * @brief Set the noise waveform generation for the selected DAC channel: |
AnnaBridge | 171:3a7713b1edbc | 643 | * Noise mode and parameters LFSR (linear feedback shift register). |
AnnaBridge | 171:3a7713b1edbc | 644 | * @note For wave generation to be effective, DAC channel |
AnnaBridge | 171:3a7713b1edbc | 645 | * wave generation mode must be enabled using |
AnnaBridge | 171:3a7713b1edbc | 646 | * function @ref LL_DAC_SetWaveAutoGeneration(). |
AnnaBridge | 171:3a7713b1edbc | 647 | * @note This setting can be set when the selected DAC channel is disabled |
AnnaBridge | 171:3a7713b1edbc | 648 | * (otherwise, the setting operation is ignored). |
AnnaBridge | 171:3a7713b1edbc | 649 | * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n |
AnnaBridge | 171:3a7713b1edbc | 650 | * CR MAMP2 LL_DAC_SetWaveNoiseLFSR |
AnnaBridge | 171:3a7713b1edbc | 651 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 652 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 653 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 654 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 655 | * |
AnnaBridge | 171:3a7713b1edbc | 656 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 657 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 658 | * @param NoiseLFSRMask This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 659 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 |
AnnaBridge | 171:3a7713b1edbc | 660 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 |
AnnaBridge | 171:3a7713b1edbc | 661 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 |
AnnaBridge | 171:3a7713b1edbc | 662 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 |
AnnaBridge | 171:3a7713b1edbc | 663 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 |
AnnaBridge | 171:3a7713b1edbc | 664 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 |
AnnaBridge | 171:3a7713b1edbc | 665 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 |
AnnaBridge | 171:3a7713b1edbc | 666 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 |
AnnaBridge | 171:3a7713b1edbc | 667 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 |
AnnaBridge | 171:3a7713b1edbc | 668 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 |
AnnaBridge | 171:3a7713b1edbc | 669 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 |
AnnaBridge | 171:3a7713b1edbc | 670 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 |
AnnaBridge | 171:3a7713b1edbc | 671 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 672 | */ |
AnnaBridge | 171:3a7713b1edbc | 673 | __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) |
AnnaBridge | 171:3a7713b1edbc | 674 | { |
AnnaBridge | 171:3a7713b1edbc | 675 | MODIFY_REG(DACx->CR, |
AnnaBridge | 171:3a7713b1edbc | 676 | DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
AnnaBridge | 171:3a7713b1edbc | 677 | NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 171:3a7713b1edbc | 678 | } |
AnnaBridge | 171:3a7713b1edbc | 679 | |
AnnaBridge | 171:3a7713b1edbc | 680 | /** |
AnnaBridge | 171:3a7713b1edbc | 681 | * @brief Set the noise waveform generation for the selected DAC channel: |
AnnaBridge | 171:3a7713b1edbc | 682 | * Noise mode and parameters LFSR (linear feedback shift register). |
AnnaBridge | 171:3a7713b1edbc | 683 | * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n |
AnnaBridge | 171:3a7713b1edbc | 684 | * CR MAMP2 LL_DAC_GetWaveNoiseLFSR |
AnnaBridge | 171:3a7713b1edbc | 685 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 686 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 687 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 688 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 689 | * |
AnnaBridge | 171:3a7713b1edbc | 690 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 691 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 692 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 693 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 |
AnnaBridge | 171:3a7713b1edbc | 694 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 |
AnnaBridge | 171:3a7713b1edbc | 695 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 |
AnnaBridge | 171:3a7713b1edbc | 696 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 |
AnnaBridge | 171:3a7713b1edbc | 697 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 |
AnnaBridge | 171:3a7713b1edbc | 698 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 |
AnnaBridge | 171:3a7713b1edbc | 699 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 |
AnnaBridge | 171:3a7713b1edbc | 700 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 |
AnnaBridge | 171:3a7713b1edbc | 701 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 |
AnnaBridge | 171:3a7713b1edbc | 702 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 |
AnnaBridge | 171:3a7713b1edbc | 703 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 |
AnnaBridge | 171:3a7713b1edbc | 704 | * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 |
AnnaBridge | 171:3a7713b1edbc | 705 | */ |
AnnaBridge | 171:3a7713b1edbc | 706 | __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 171:3a7713b1edbc | 707 | { |
AnnaBridge | 171:3a7713b1edbc | 708 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 171:3a7713b1edbc | 709 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 710 | ); |
AnnaBridge | 171:3a7713b1edbc | 711 | } |
AnnaBridge | 171:3a7713b1edbc | 712 | |
AnnaBridge | 171:3a7713b1edbc | 713 | /** |
AnnaBridge | 171:3a7713b1edbc | 714 | * @brief Set the triangle waveform generation for the selected DAC channel: |
AnnaBridge | 171:3a7713b1edbc | 715 | * triangle mode and amplitude. |
AnnaBridge | 171:3a7713b1edbc | 716 | * @note For wave generation to be effective, DAC channel |
AnnaBridge | 171:3a7713b1edbc | 717 | * wave generation mode must be enabled using |
AnnaBridge | 171:3a7713b1edbc | 718 | * function @ref LL_DAC_SetWaveAutoGeneration(). |
AnnaBridge | 171:3a7713b1edbc | 719 | * @note This setting can be set when the selected DAC channel is disabled |
AnnaBridge | 171:3a7713b1edbc | 720 | * (otherwise, the setting operation is ignored). |
AnnaBridge | 171:3a7713b1edbc | 721 | * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n |
AnnaBridge | 171:3a7713b1edbc | 722 | * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude |
AnnaBridge | 171:3a7713b1edbc | 723 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 724 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 725 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 726 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 727 | * |
AnnaBridge | 171:3a7713b1edbc | 728 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 729 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 730 | * @param TriangleAmplitude This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 731 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 |
AnnaBridge | 171:3a7713b1edbc | 732 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 |
AnnaBridge | 171:3a7713b1edbc | 733 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 |
AnnaBridge | 171:3a7713b1edbc | 734 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 |
AnnaBridge | 171:3a7713b1edbc | 735 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 |
AnnaBridge | 171:3a7713b1edbc | 736 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 |
AnnaBridge | 171:3a7713b1edbc | 737 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 |
AnnaBridge | 171:3a7713b1edbc | 738 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 |
AnnaBridge | 171:3a7713b1edbc | 739 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 |
AnnaBridge | 171:3a7713b1edbc | 740 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 |
AnnaBridge | 171:3a7713b1edbc | 741 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 |
AnnaBridge | 171:3a7713b1edbc | 742 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 |
AnnaBridge | 171:3a7713b1edbc | 743 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 744 | */ |
AnnaBridge | 171:3a7713b1edbc | 745 | __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude) |
AnnaBridge | 171:3a7713b1edbc | 746 | { |
AnnaBridge | 171:3a7713b1edbc | 747 | MODIFY_REG(DACx->CR, |
AnnaBridge | 171:3a7713b1edbc | 748 | DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
AnnaBridge | 171:3a7713b1edbc | 749 | TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 171:3a7713b1edbc | 750 | } |
AnnaBridge | 171:3a7713b1edbc | 751 | |
AnnaBridge | 171:3a7713b1edbc | 752 | /** |
AnnaBridge | 171:3a7713b1edbc | 753 | * @brief Set the triangle waveform generation for the selected DAC channel: |
AnnaBridge | 171:3a7713b1edbc | 754 | * triangle mode and amplitude. |
AnnaBridge | 171:3a7713b1edbc | 755 | * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n |
AnnaBridge | 171:3a7713b1edbc | 756 | * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude |
AnnaBridge | 171:3a7713b1edbc | 757 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 758 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 759 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 760 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 761 | * |
AnnaBridge | 171:3a7713b1edbc | 762 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 763 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 764 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 765 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 |
AnnaBridge | 171:3a7713b1edbc | 766 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 |
AnnaBridge | 171:3a7713b1edbc | 767 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 |
AnnaBridge | 171:3a7713b1edbc | 768 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 |
AnnaBridge | 171:3a7713b1edbc | 769 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 |
AnnaBridge | 171:3a7713b1edbc | 770 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 |
AnnaBridge | 171:3a7713b1edbc | 771 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 |
AnnaBridge | 171:3a7713b1edbc | 772 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 |
AnnaBridge | 171:3a7713b1edbc | 773 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 |
AnnaBridge | 171:3a7713b1edbc | 774 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 |
AnnaBridge | 171:3a7713b1edbc | 775 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 |
AnnaBridge | 171:3a7713b1edbc | 776 | * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 |
AnnaBridge | 171:3a7713b1edbc | 777 | */ |
AnnaBridge | 171:3a7713b1edbc | 778 | __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 171:3a7713b1edbc | 779 | { |
AnnaBridge | 171:3a7713b1edbc | 780 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 171:3a7713b1edbc | 781 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 782 | ); |
AnnaBridge | 171:3a7713b1edbc | 783 | } |
AnnaBridge | 171:3a7713b1edbc | 784 | #endif |
AnnaBridge | 171:3a7713b1edbc | 785 | |
AnnaBridge | 171:3a7713b1edbc | 786 | /** |
AnnaBridge | 171:3a7713b1edbc | 787 | * @brief Set the output buffer for the selected DAC channel. |
AnnaBridge | 171:3a7713b1edbc | 788 | * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n |
AnnaBridge | 171:3a7713b1edbc | 789 | * CR BOFF2 LL_DAC_SetOutputBuffer |
AnnaBridge | 171:3a7713b1edbc | 790 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 791 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 792 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 793 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 794 | * |
AnnaBridge | 171:3a7713b1edbc | 795 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 796 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 797 | * @param OutputBuffer This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 798 | * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE |
AnnaBridge | 171:3a7713b1edbc | 799 | * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE |
AnnaBridge | 171:3a7713b1edbc | 800 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 801 | */ |
AnnaBridge | 171:3a7713b1edbc | 802 | __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) |
AnnaBridge | 171:3a7713b1edbc | 803 | { |
AnnaBridge | 171:3a7713b1edbc | 804 | MODIFY_REG(DACx->CR, |
AnnaBridge | 171:3a7713b1edbc | 805 | DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), |
AnnaBridge | 171:3a7713b1edbc | 806 | OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 171:3a7713b1edbc | 807 | } |
AnnaBridge | 171:3a7713b1edbc | 808 | |
AnnaBridge | 171:3a7713b1edbc | 809 | /** |
AnnaBridge | 171:3a7713b1edbc | 810 | * @brief Get the output buffer state for the selected DAC channel. |
AnnaBridge | 171:3a7713b1edbc | 811 | * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n |
AnnaBridge | 171:3a7713b1edbc | 812 | * CR BOFF2 LL_DAC_GetOutputBuffer |
AnnaBridge | 171:3a7713b1edbc | 813 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 814 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 815 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 816 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 817 | * |
AnnaBridge | 171:3a7713b1edbc | 818 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 819 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 820 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 821 | * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE |
AnnaBridge | 171:3a7713b1edbc | 822 | * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE |
AnnaBridge | 171:3a7713b1edbc | 823 | */ |
AnnaBridge | 171:3a7713b1edbc | 824 | __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 171:3a7713b1edbc | 825 | { |
AnnaBridge | 171:3a7713b1edbc | 826 | return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 171:3a7713b1edbc | 827 | >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 828 | ); |
AnnaBridge | 171:3a7713b1edbc | 829 | } |
AnnaBridge | 171:3a7713b1edbc | 830 | |
AnnaBridge | 171:3a7713b1edbc | 831 | /** |
AnnaBridge | 171:3a7713b1edbc | 832 | * @} |
AnnaBridge | 171:3a7713b1edbc | 833 | */ |
AnnaBridge | 171:3a7713b1edbc | 834 | |
AnnaBridge | 171:3a7713b1edbc | 835 | /** @defgroup DAC_LL_EF_DMA_Management DMA Management |
AnnaBridge | 171:3a7713b1edbc | 836 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 837 | */ |
AnnaBridge | 171:3a7713b1edbc | 838 | |
AnnaBridge | 171:3a7713b1edbc | 839 | /** |
AnnaBridge | 171:3a7713b1edbc | 840 | * @brief Enable DAC DMA transfer request of the selected channel. |
AnnaBridge | 171:3a7713b1edbc | 841 | * @note To configure DMA source address (peripheral address), |
AnnaBridge | 171:3a7713b1edbc | 842 | * use function @ref LL_DAC_DMA_GetRegAddr(). |
AnnaBridge | 171:3a7713b1edbc | 843 | * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n |
AnnaBridge | 171:3a7713b1edbc | 844 | * CR DMAEN2 LL_DAC_EnableDMAReq |
AnnaBridge | 171:3a7713b1edbc | 845 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 846 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 847 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 848 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 849 | * |
AnnaBridge | 171:3a7713b1edbc | 850 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 851 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 852 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 853 | */ |
AnnaBridge | 171:3a7713b1edbc | 854 | __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 171:3a7713b1edbc | 855 | { |
AnnaBridge | 171:3a7713b1edbc | 856 | SET_BIT(DACx->CR, |
AnnaBridge | 171:3a7713b1edbc | 857 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 171:3a7713b1edbc | 858 | } |
AnnaBridge | 171:3a7713b1edbc | 859 | |
AnnaBridge | 171:3a7713b1edbc | 860 | /** |
AnnaBridge | 171:3a7713b1edbc | 861 | * @brief Disable DAC DMA transfer request of the selected channel. |
AnnaBridge | 171:3a7713b1edbc | 862 | * @note To configure DMA source address (peripheral address), |
AnnaBridge | 171:3a7713b1edbc | 863 | * use function @ref LL_DAC_DMA_GetRegAddr(). |
AnnaBridge | 171:3a7713b1edbc | 864 | * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n |
AnnaBridge | 171:3a7713b1edbc | 865 | * CR DMAEN2 LL_DAC_DisableDMAReq |
AnnaBridge | 171:3a7713b1edbc | 866 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 867 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 868 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 869 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 870 | * |
AnnaBridge | 171:3a7713b1edbc | 871 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 872 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 873 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 874 | */ |
AnnaBridge | 171:3a7713b1edbc | 875 | __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 171:3a7713b1edbc | 876 | { |
AnnaBridge | 171:3a7713b1edbc | 877 | CLEAR_BIT(DACx->CR, |
AnnaBridge | 171:3a7713b1edbc | 878 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 171:3a7713b1edbc | 879 | } |
AnnaBridge | 171:3a7713b1edbc | 880 | |
AnnaBridge | 171:3a7713b1edbc | 881 | /** |
AnnaBridge | 171:3a7713b1edbc | 882 | * @brief Get DAC DMA transfer request state of the selected channel. |
AnnaBridge | 171:3a7713b1edbc | 883 | * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) |
AnnaBridge | 171:3a7713b1edbc | 884 | * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n |
AnnaBridge | 171:3a7713b1edbc | 885 | * CR DMAEN2 LL_DAC_IsDMAReqEnabled |
AnnaBridge | 171:3a7713b1edbc | 886 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 887 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 888 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 889 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 890 | * |
AnnaBridge | 171:3a7713b1edbc | 891 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 892 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 893 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 894 | */ |
AnnaBridge | 171:3a7713b1edbc | 895 | __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 171:3a7713b1edbc | 896 | { |
AnnaBridge | 171:3a7713b1edbc | 897 | return (READ_BIT(DACx->CR, |
AnnaBridge | 171:3a7713b1edbc | 898 | DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 171:3a7713b1edbc | 899 | == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); |
AnnaBridge | 171:3a7713b1edbc | 900 | } |
AnnaBridge | 171:3a7713b1edbc | 901 | |
AnnaBridge | 171:3a7713b1edbc | 902 | /** |
AnnaBridge | 171:3a7713b1edbc | 903 | * @brief Function to help to configure DMA transfer to DAC: retrieve the |
AnnaBridge | 171:3a7713b1edbc | 904 | * DAC register address from DAC instance and a list of DAC registers |
AnnaBridge | 171:3a7713b1edbc | 905 | * intended to be used (most commonly) with DMA transfer. |
AnnaBridge | 171:3a7713b1edbc | 906 | * @note These DAC registers are data holding registers: |
AnnaBridge | 171:3a7713b1edbc | 907 | * when DAC conversion is requested, DAC generates a DMA transfer |
AnnaBridge | 171:3a7713b1edbc | 908 | * request to have data available in DAC data holding registers. |
AnnaBridge | 171:3a7713b1edbc | 909 | * @note This macro is intended to be used with LL DMA driver, refer to |
AnnaBridge | 171:3a7713b1edbc | 910 | * function "LL_DMA_ConfigAddresses()". |
AnnaBridge | 171:3a7713b1edbc | 911 | * Example: |
AnnaBridge | 171:3a7713b1edbc | 912 | * LL_DMA_ConfigAddresses(DMA1, |
AnnaBridge | 171:3a7713b1edbc | 913 | * LL_DMA_CHANNEL_1, |
AnnaBridge | 171:3a7713b1edbc | 914 | * (uint32_t)&< array or variable >, |
AnnaBridge | 171:3a7713b1edbc | 915 | * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), |
AnnaBridge | 171:3a7713b1edbc | 916 | * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); |
AnnaBridge | 171:3a7713b1edbc | 917 | * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
AnnaBridge | 171:3a7713b1edbc | 918 | * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
AnnaBridge | 171:3a7713b1edbc | 919 | * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n |
AnnaBridge | 171:3a7713b1edbc | 920 | * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n |
AnnaBridge | 171:3a7713b1edbc | 921 | * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n |
AnnaBridge | 171:3a7713b1edbc | 922 | * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr |
AnnaBridge | 171:3a7713b1edbc | 923 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 924 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 925 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 926 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 927 | * |
AnnaBridge | 171:3a7713b1edbc | 928 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 929 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 930 | * @param Register This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 931 | * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED |
AnnaBridge | 171:3a7713b1edbc | 932 | * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED |
AnnaBridge | 171:3a7713b1edbc | 933 | * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED |
AnnaBridge | 171:3a7713b1edbc | 934 | * @retval DAC register address |
AnnaBridge | 171:3a7713b1edbc | 935 | */ |
AnnaBridge | 171:3a7713b1edbc | 936 | __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) |
AnnaBridge | 171:3a7713b1edbc | 937 | { |
AnnaBridge | 171:3a7713b1edbc | 938 | /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ |
AnnaBridge | 171:3a7713b1edbc | 939 | /* DAC channel selected. */ |
AnnaBridge | 171:3a7713b1edbc | 940 | return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> Register) & DAC_REG_REGOFFSET_MASK_POSBIT0)))); |
AnnaBridge | 171:3a7713b1edbc | 941 | } |
AnnaBridge | 171:3a7713b1edbc | 942 | /** |
AnnaBridge | 171:3a7713b1edbc | 943 | * @} |
AnnaBridge | 171:3a7713b1edbc | 944 | */ |
AnnaBridge | 171:3a7713b1edbc | 945 | |
AnnaBridge | 171:3a7713b1edbc | 946 | /** @defgroup DAC_LL_EF_Operation Operation on DAC channels |
AnnaBridge | 171:3a7713b1edbc | 947 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 948 | */ |
AnnaBridge | 171:3a7713b1edbc | 949 | |
AnnaBridge | 171:3a7713b1edbc | 950 | /** |
AnnaBridge | 171:3a7713b1edbc | 951 | * @brief Enable DAC selected channel. |
AnnaBridge | 171:3a7713b1edbc | 952 | * @rmtoll CR EN1 LL_DAC_Enable\n |
AnnaBridge | 171:3a7713b1edbc | 953 | * CR EN2 LL_DAC_Enable |
AnnaBridge | 171:3a7713b1edbc | 954 | * @note After enable from off state, DAC channel requires a delay |
AnnaBridge | 171:3a7713b1edbc | 955 | * for output voltage to reach accuracy +/- 1 LSB. |
AnnaBridge | 171:3a7713b1edbc | 956 | * Refer to device datasheet, parameter "tWAKEUP". |
AnnaBridge | 171:3a7713b1edbc | 957 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 958 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 959 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 960 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 961 | * |
AnnaBridge | 171:3a7713b1edbc | 962 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 963 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 964 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 965 | */ |
AnnaBridge | 171:3a7713b1edbc | 966 | __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 171:3a7713b1edbc | 967 | { |
AnnaBridge | 171:3a7713b1edbc | 968 | SET_BIT(DACx->CR, |
AnnaBridge | 171:3a7713b1edbc | 969 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 171:3a7713b1edbc | 970 | } |
AnnaBridge | 171:3a7713b1edbc | 971 | |
AnnaBridge | 171:3a7713b1edbc | 972 | /** |
AnnaBridge | 171:3a7713b1edbc | 973 | * @brief Disable DAC selected channel. |
AnnaBridge | 171:3a7713b1edbc | 974 | * @rmtoll CR EN1 LL_DAC_Disable\n |
AnnaBridge | 171:3a7713b1edbc | 975 | * CR EN2 LL_DAC_Disable |
AnnaBridge | 171:3a7713b1edbc | 976 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 977 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 978 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 979 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 980 | * |
AnnaBridge | 171:3a7713b1edbc | 981 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 982 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 983 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 984 | */ |
AnnaBridge | 171:3a7713b1edbc | 985 | __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 171:3a7713b1edbc | 986 | { |
AnnaBridge | 171:3a7713b1edbc | 987 | CLEAR_BIT(DACx->CR, |
AnnaBridge | 171:3a7713b1edbc | 988 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 171:3a7713b1edbc | 989 | } |
AnnaBridge | 171:3a7713b1edbc | 990 | |
AnnaBridge | 171:3a7713b1edbc | 991 | /** |
AnnaBridge | 171:3a7713b1edbc | 992 | * @brief Get DAC enable state of the selected channel. |
AnnaBridge | 171:3a7713b1edbc | 993 | * (0: DAC channel is disabled, 1: DAC channel is enabled) |
AnnaBridge | 171:3a7713b1edbc | 994 | * @rmtoll CR EN1 LL_DAC_IsEnabled\n |
AnnaBridge | 171:3a7713b1edbc | 995 | * CR EN2 LL_DAC_IsEnabled |
AnnaBridge | 171:3a7713b1edbc | 996 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 997 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 998 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 999 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 1000 | * |
AnnaBridge | 171:3a7713b1edbc | 1001 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 1002 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 1003 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1004 | */ |
AnnaBridge | 171:3a7713b1edbc | 1005 | __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 171:3a7713b1edbc | 1006 | { |
AnnaBridge | 171:3a7713b1edbc | 1007 | return (READ_BIT(DACx->CR, |
AnnaBridge | 171:3a7713b1edbc | 1008 | DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 171:3a7713b1edbc | 1009 | == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); |
AnnaBridge | 171:3a7713b1edbc | 1010 | } |
AnnaBridge | 171:3a7713b1edbc | 1011 | |
AnnaBridge | 171:3a7713b1edbc | 1012 | /** |
AnnaBridge | 171:3a7713b1edbc | 1013 | * @brief Enable DAC trigger of the selected channel. |
AnnaBridge | 171:3a7713b1edbc | 1014 | * @note - If DAC trigger is disabled, DAC conversion is performed |
AnnaBridge | 171:3a7713b1edbc | 1015 | * automatically once the data holding register is updated, |
AnnaBridge | 171:3a7713b1edbc | 1016 | * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": |
AnnaBridge | 171:3a7713b1edbc | 1017 | * @ref LL_DAC_ConvertData12RightAligned(), ... |
AnnaBridge | 171:3a7713b1edbc | 1018 | * - If DAC trigger is enabled, DAC conversion is performed |
AnnaBridge | 171:3a7713b1edbc | 1019 | * only when a hardware of software trigger event is occurring. |
AnnaBridge | 171:3a7713b1edbc | 1020 | * Select trigger source using |
AnnaBridge | 171:3a7713b1edbc | 1021 | * function @ref LL_DAC_SetTriggerSource(). |
AnnaBridge | 171:3a7713b1edbc | 1022 | * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n |
AnnaBridge | 171:3a7713b1edbc | 1023 | * CR TEN2 LL_DAC_EnableTrigger |
AnnaBridge | 171:3a7713b1edbc | 1024 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1025 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1026 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1027 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 1028 | * |
AnnaBridge | 171:3a7713b1edbc | 1029 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 1030 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 1031 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1032 | */ |
AnnaBridge | 171:3a7713b1edbc | 1033 | __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 171:3a7713b1edbc | 1034 | { |
AnnaBridge | 171:3a7713b1edbc | 1035 | SET_BIT(DACx->CR, |
AnnaBridge | 171:3a7713b1edbc | 1036 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 171:3a7713b1edbc | 1037 | } |
AnnaBridge | 171:3a7713b1edbc | 1038 | |
AnnaBridge | 171:3a7713b1edbc | 1039 | /** |
AnnaBridge | 171:3a7713b1edbc | 1040 | * @brief Disable DAC trigger of the selected channel. |
AnnaBridge | 171:3a7713b1edbc | 1041 | * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n |
AnnaBridge | 171:3a7713b1edbc | 1042 | * CR TEN2 LL_DAC_DisableTrigger |
AnnaBridge | 171:3a7713b1edbc | 1043 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1044 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1045 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1046 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 1047 | * |
AnnaBridge | 171:3a7713b1edbc | 1048 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 1049 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 1050 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1051 | */ |
AnnaBridge | 171:3a7713b1edbc | 1052 | __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 171:3a7713b1edbc | 1053 | { |
AnnaBridge | 171:3a7713b1edbc | 1054 | CLEAR_BIT(DACx->CR, |
AnnaBridge | 171:3a7713b1edbc | 1055 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); |
AnnaBridge | 171:3a7713b1edbc | 1056 | } |
AnnaBridge | 171:3a7713b1edbc | 1057 | |
AnnaBridge | 171:3a7713b1edbc | 1058 | /** |
AnnaBridge | 171:3a7713b1edbc | 1059 | * @brief Get DAC trigger state of the selected channel. |
AnnaBridge | 171:3a7713b1edbc | 1060 | * (0: DAC trigger is disabled, 1: DAC trigger is enabled) |
AnnaBridge | 171:3a7713b1edbc | 1061 | * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n |
AnnaBridge | 171:3a7713b1edbc | 1062 | * CR TEN2 LL_DAC_IsTriggerEnabled |
AnnaBridge | 171:3a7713b1edbc | 1063 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1064 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1065 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1066 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 1067 | * |
AnnaBridge | 171:3a7713b1edbc | 1068 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 1069 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 1070 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1071 | */ |
AnnaBridge | 171:3a7713b1edbc | 1072 | __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 171:3a7713b1edbc | 1073 | { |
AnnaBridge | 171:3a7713b1edbc | 1074 | return (READ_BIT(DACx->CR, |
AnnaBridge | 171:3a7713b1edbc | 1075 | DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) |
AnnaBridge | 171:3a7713b1edbc | 1076 | == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); |
AnnaBridge | 171:3a7713b1edbc | 1077 | } |
AnnaBridge | 171:3a7713b1edbc | 1078 | |
AnnaBridge | 171:3a7713b1edbc | 1079 | /** |
AnnaBridge | 171:3a7713b1edbc | 1080 | * @brief Trig DAC conversion by software for the selected DAC channel. |
AnnaBridge | 171:3a7713b1edbc | 1081 | * @note Preliminarily, DAC trigger must be set to software trigger |
AnnaBridge | 171:3a7713b1edbc | 1082 | * using function @ref LL_DAC_SetTriggerSource() |
AnnaBridge | 171:3a7713b1edbc | 1083 | * with parameter "LL_DAC_TRIGGER_SOFTWARE". |
AnnaBridge | 171:3a7713b1edbc | 1084 | * and DAC trigger must be enabled using |
AnnaBridge | 171:3a7713b1edbc | 1085 | * function @ref LL_DAC_EnableTrigger(). |
AnnaBridge | 171:3a7713b1edbc | 1086 | * @note For devices featuring DAC with 2 channels: this function |
AnnaBridge | 171:3a7713b1edbc | 1087 | * can perform a SW start of both DAC channels simultaneously. |
AnnaBridge | 171:3a7713b1edbc | 1088 | * Two channels can be selected as parameter. |
AnnaBridge | 171:3a7713b1edbc | 1089 | * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) |
AnnaBridge | 171:3a7713b1edbc | 1090 | * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n |
AnnaBridge | 171:3a7713b1edbc | 1091 | * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion |
AnnaBridge | 171:3a7713b1edbc | 1092 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1093 | * @param DAC_Channel This parameter can a combination of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1094 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1095 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 1096 | * |
AnnaBridge | 171:3a7713b1edbc | 1097 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 1098 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 1099 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1100 | */ |
AnnaBridge | 171:3a7713b1edbc | 1101 | __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 171:3a7713b1edbc | 1102 | { |
AnnaBridge | 171:3a7713b1edbc | 1103 | SET_BIT(DACx->SWTRIGR, |
AnnaBridge | 171:3a7713b1edbc | 1104 | (DAC_Channel & DAC_SWTR_CHX_MASK)); |
AnnaBridge | 171:3a7713b1edbc | 1105 | } |
AnnaBridge | 171:3a7713b1edbc | 1106 | |
AnnaBridge | 171:3a7713b1edbc | 1107 | /** |
AnnaBridge | 171:3a7713b1edbc | 1108 | * @brief Set the data to be loaded in the data holding register |
AnnaBridge | 171:3a7713b1edbc | 1109 | * in format 12 bits left alignment (LSB aligned on bit 0), |
AnnaBridge | 171:3a7713b1edbc | 1110 | * for the selected DAC channel. |
AnnaBridge | 171:3a7713b1edbc | 1111 | * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n |
AnnaBridge | 171:3a7713b1edbc | 1112 | * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned |
AnnaBridge | 171:3a7713b1edbc | 1113 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1114 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1115 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1116 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 1117 | * |
AnnaBridge | 171:3a7713b1edbc | 1118 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 1119 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 1120 | * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 171:3a7713b1edbc | 1121 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1122 | */ |
AnnaBridge | 171:3a7713b1edbc | 1123 | __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
AnnaBridge | 171:3a7713b1edbc | 1124 | { |
AnnaBridge | 171:3a7713b1edbc | 1125 | register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0); |
AnnaBridge | 171:3a7713b1edbc | 1126 | |
AnnaBridge | 171:3a7713b1edbc | 1127 | MODIFY_REG(*preg, |
AnnaBridge | 171:3a7713b1edbc | 1128 | DAC_DHR12R1_DACC1DHR, |
AnnaBridge | 171:3a7713b1edbc | 1129 | Data); |
AnnaBridge | 171:3a7713b1edbc | 1130 | } |
AnnaBridge | 171:3a7713b1edbc | 1131 | |
AnnaBridge | 171:3a7713b1edbc | 1132 | /** |
AnnaBridge | 171:3a7713b1edbc | 1133 | * @brief Set the data to be loaded in the data holding register |
AnnaBridge | 171:3a7713b1edbc | 1134 | * in format 12 bits left alignment (MSB aligned on bit 15), |
AnnaBridge | 171:3a7713b1edbc | 1135 | * for the selected DAC channel. |
AnnaBridge | 171:3a7713b1edbc | 1136 | * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n |
AnnaBridge | 171:3a7713b1edbc | 1137 | * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned |
AnnaBridge | 171:3a7713b1edbc | 1138 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1139 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1140 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1141 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 1142 | * |
AnnaBridge | 171:3a7713b1edbc | 1143 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 1144 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 1145 | * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 171:3a7713b1edbc | 1146 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1147 | */ |
AnnaBridge | 171:3a7713b1edbc | 1148 | __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
AnnaBridge | 171:3a7713b1edbc | 1149 | { |
AnnaBridge | 171:3a7713b1edbc | 1150 | register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0); |
AnnaBridge | 171:3a7713b1edbc | 1151 | |
AnnaBridge | 171:3a7713b1edbc | 1152 | MODIFY_REG(*preg, |
AnnaBridge | 171:3a7713b1edbc | 1153 | DAC_DHR12L1_DACC1DHR, |
AnnaBridge | 171:3a7713b1edbc | 1154 | Data); |
AnnaBridge | 171:3a7713b1edbc | 1155 | } |
AnnaBridge | 171:3a7713b1edbc | 1156 | |
AnnaBridge | 171:3a7713b1edbc | 1157 | /** |
AnnaBridge | 171:3a7713b1edbc | 1158 | * @brief Set the data to be loaded in the data holding register |
AnnaBridge | 171:3a7713b1edbc | 1159 | * in format 8 bits left alignment (LSB aligned on bit 0), |
AnnaBridge | 171:3a7713b1edbc | 1160 | * for the selected DAC channel. |
AnnaBridge | 171:3a7713b1edbc | 1161 | * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n |
AnnaBridge | 171:3a7713b1edbc | 1162 | * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned |
AnnaBridge | 171:3a7713b1edbc | 1163 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1164 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1165 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1166 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 1167 | * |
AnnaBridge | 171:3a7713b1edbc | 1168 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 1169 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 1170 | * @param Data Value between Min_Data=0x00 and Max_Data=0xFF |
AnnaBridge | 171:3a7713b1edbc | 1171 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1172 | */ |
AnnaBridge | 171:3a7713b1edbc | 1173 | __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) |
AnnaBridge | 171:3a7713b1edbc | 1174 | { |
AnnaBridge | 171:3a7713b1edbc | 1175 | register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0); |
AnnaBridge | 171:3a7713b1edbc | 1176 | |
AnnaBridge | 171:3a7713b1edbc | 1177 | MODIFY_REG(*preg, |
AnnaBridge | 171:3a7713b1edbc | 1178 | DAC_DHR8R1_DACC1DHR, |
AnnaBridge | 171:3a7713b1edbc | 1179 | Data); |
AnnaBridge | 171:3a7713b1edbc | 1180 | } |
AnnaBridge | 171:3a7713b1edbc | 1181 | |
AnnaBridge | 171:3a7713b1edbc | 1182 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 1183 | /** |
AnnaBridge | 171:3a7713b1edbc | 1184 | * @brief Set the data to be loaded in the data holding register |
AnnaBridge | 171:3a7713b1edbc | 1185 | * in format 12 bits left alignment (LSB aligned on bit 0), |
AnnaBridge | 171:3a7713b1edbc | 1186 | * for both DAC channels. |
AnnaBridge | 171:3a7713b1edbc | 1187 | * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n |
AnnaBridge | 171:3a7713b1edbc | 1188 | * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned |
AnnaBridge | 171:3a7713b1edbc | 1189 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1190 | * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 171:3a7713b1edbc | 1191 | * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 171:3a7713b1edbc | 1192 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1193 | */ |
AnnaBridge | 171:3a7713b1edbc | 1194 | __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) |
AnnaBridge | 171:3a7713b1edbc | 1195 | { |
AnnaBridge | 171:3a7713b1edbc | 1196 | MODIFY_REG(DACx->DHR12RD, |
AnnaBridge | 171:3a7713b1edbc | 1197 | (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), |
AnnaBridge | 171:3a7713b1edbc | 1198 | ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); |
AnnaBridge | 171:3a7713b1edbc | 1199 | } |
AnnaBridge | 171:3a7713b1edbc | 1200 | |
AnnaBridge | 171:3a7713b1edbc | 1201 | /** |
AnnaBridge | 171:3a7713b1edbc | 1202 | * @brief Set the data to be loaded in the data holding register |
AnnaBridge | 171:3a7713b1edbc | 1203 | * in format 12 bits left alignment (MSB aligned on bit 15), |
AnnaBridge | 171:3a7713b1edbc | 1204 | * for both DAC channels. |
AnnaBridge | 171:3a7713b1edbc | 1205 | * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n |
AnnaBridge | 171:3a7713b1edbc | 1206 | * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned |
AnnaBridge | 171:3a7713b1edbc | 1207 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1208 | * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 171:3a7713b1edbc | 1209 | * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 171:3a7713b1edbc | 1210 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1211 | */ |
AnnaBridge | 171:3a7713b1edbc | 1212 | __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) |
AnnaBridge | 171:3a7713b1edbc | 1213 | { |
AnnaBridge | 171:3a7713b1edbc | 1214 | /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ |
AnnaBridge | 171:3a7713b1edbc | 1215 | /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ |
AnnaBridge | 171:3a7713b1edbc | 1216 | /* the 4 LSB must be taken into account for the shift value. */ |
AnnaBridge | 171:3a7713b1edbc | 1217 | MODIFY_REG(DACx->DHR12LD, |
AnnaBridge | 171:3a7713b1edbc | 1218 | (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), |
AnnaBridge | 171:3a7713b1edbc | 1219 | ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); |
AnnaBridge | 171:3a7713b1edbc | 1220 | } |
AnnaBridge | 171:3a7713b1edbc | 1221 | |
AnnaBridge | 171:3a7713b1edbc | 1222 | /** |
AnnaBridge | 171:3a7713b1edbc | 1223 | * @brief Set the data to be loaded in the data holding register |
AnnaBridge | 171:3a7713b1edbc | 1224 | * in format 8 bits left alignment (LSB aligned on bit 0), |
AnnaBridge | 171:3a7713b1edbc | 1225 | * for both DAC channels. |
AnnaBridge | 171:3a7713b1edbc | 1226 | * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n |
AnnaBridge | 171:3a7713b1edbc | 1227 | * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned |
AnnaBridge | 171:3a7713b1edbc | 1228 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1229 | * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF |
AnnaBridge | 171:3a7713b1edbc | 1230 | * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF |
AnnaBridge | 171:3a7713b1edbc | 1231 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1232 | */ |
AnnaBridge | 171:3a7713b1edbc | 1233 | __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) |
AnnaBridge | 171:3a7713b1edbc | 1234 | { |
AnnaBridge | 171:3a7713b1edbc | 1235 | MODIFY_REG(DACx->DHR8RD, |
AnnaBridge | 171:3a7713b1edbc | 1236 | (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), |
AnnaBridge | 171:3a7713b1edbc | 1237 | ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); |
AnnaBridge | 171:3a7713b1edbc | 1238 | } |
AnnaBridge | 171:3a7713b1edbc | 1239 | |
AnnaBridge | 171:3a7713b1edbc | 1240 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 1241 | /** |
AnnaBridge | 171:3a7713b1edbc | 1242 | * @brief Retrieve output data currently generated for the selected DAC channel. |
AnnaBridge | 171:3a7713b1edbc | 1243 | * @note Whatever alignment and resolution settings |
AnnaBridge | 171:3a7713b1edbc | 1244 | * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": |
AnnaBridge | 171:3a7713b1edbc | 1245 | * @ref LL_DAC_ConvertData12RightAligned(), ...), |
AnnaBridge | 171:3a7713b1edbc | 1246 | * output data format is 12 bits right aligned (LSB aligned on bit 0). |
AnnaBridge | 171:3a7713b1edbc | 1247 | * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n |
AnnaBridge | 171:3a7713b1edbc | 1248 | * DOR2 DACC2DOR LL_DAC_RetrieveOutputData |
AnnaBridge | 171:3a7713b1edbc | 1249 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1250 | * @param DAC_Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1251 | * @arg @ref LL_DAC_CHANNEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1252 | * @arg @ref LL_DAC_CHANNEL_2 (1) |
AnnaBridge | 171:3a7713b1edbc | 1253 | * |
AnnaBridge | 171:3a7713b1edbc | 1254 | * (1) On this STM32 serie, parameter not available on all devices. |
AnnaBridge | 171:3a7713b1edbc | 1255 | * Refer to device datasheet for channels availability. |
AnnaBridge | 171:3a7713b1edbc | 1256 | * @retval Value between Min_Data=0x000 and Max_Data=0xFFF |
AnnaBridge | 171:3a7713b1edbc | 1257 | */ |
AnnaBridge | 171:3a7713b1edbc | 1258 | __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) |
AnnaBridge | 171:3a7713b1edbc | 1259 | { |
AnnaBridge | 171:3a7713b1edbc | 1260 | register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0); |
AnnaBridge | 171:3a7713b1edbc | 1261 | |
AnnaBridge | 171:3a7713b1edbc | 1262 | return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); |
AnnaBridge | 171:3a7713b1edbc | 1263 | } |
AnnaBridge | 171:3a7713b1edbc | 1264 | |
AnnaBridge | 171:3a7713b1edbc | 1265 | /** |
AnnaBridge | 171:3a7713b1edbc | 1266 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1267 | */ |
AnnaBridge | 171:3a7713b1edbc | 1268 | |
AnnaBridge | 171:3a7713b1edbc | 1269 | /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management |
AnnaBridge | 171:3a7713b1edbc | 1270 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1271 | */ |
AnnaBridge | 171:3a7713b1edbc | 1272 | /** |
AnnaBridge | 171:3a7713b1edbc | 1273 | * @brief Get DAC underrun flag for DAC channel 1 |
AnnaBridge | 171:3a7713b1edbc | 1274 | * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 |
AnnaBridge | 171:3a7713b1edbc | 1275 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1276 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1277 | */ |
AnnaBridge | 171:3a7713b1edbc | 1278 | __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) |
AnnaBridge | 171:3a7713b1edbc | 1279 | { |
AnnaBridge | 171:3a7713b1edbc | 1280 | return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)); |
AnnaBridge | 171:3a7713b1edbc | 1281 | } |
AnnaBridge | 171:3a7713b1edbc | 1282 | |
AnnaBridge | 171:3a7713b1edbc | 1283 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 1284 | /** |
AnnaBridge | 171:3a7713b1edbc | 1285 | * @brief Get DAC underrun flag for DAC channel 2 |
AnnaBridge | 171:3a7713b1edbc | 1286 | * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 |
AnnaBridge | 171:3a7713b1edbc | 1287 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1288 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1289 | */ |
AnnaBridge | 171:3a7713b1edbc | 1290 | __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) |
AnnaBridge | 171:3a7713b1edbc | 1291 | { |
AnnaBridge | 171:3a7713b1edbc | 1292 | return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)); |
AnnaBridge | 171:3a7713b1edbc | 1293 | } |
AnnaBridge | 171:3a7713b1edbc | 1294 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 1295 | |
AnnaBridge | 171:3a7713b1edbc | 1296 | /** |
AnnaBridge | 171:3a7713b1edbc | 1297 | * @brief Clear DAC underrun flag for DAC channel 1 |
AnnaBridge | 171:3a7713b1edbc | 1298 | * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 |
AnnaBridge | 171:3a7713b1edbc | 1299 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1300 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1301 | */ |
AnnaBridge | 171:3a7713b1edbc | 1302 | __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) |
AnnaBridge | 171:3a7713b1edbc | 1303 | { |
AnnaBridge | 171:3a7713b1edbc | 1304 | WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); |
AnnaBridge | 171:3a7713b1edbc | 1305 | } |
AnnaBridge | 171:3a7713b1edbc | 1306 | |
AnnaBridge | 171:3a7713b1edbc | 1307 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 1308 | /** |
AnnaBridge | 171:3a7713b1edbc | 1309 | * @brief Clear DAC underrun flag for DAC channel 2 |
AnnaBridge | 171:3a7713b1edbc | 1310 | * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 |
AnnaBridge | 171:3a7713b1edbc | 1311 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1312 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1313 | */ |
AnnaBridge | 171:3a7713b1edbc | 1314 | __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) |
AnnaBridge | 171:3a7713b1edbc | 1315 | { |
AnnaBridge | 171:3a7713b1edbc | 1316 | WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); |
AnnaBridge | 171:3a7713b1edbc | 1317 | } |
AnnaBridge | 171:3a7713b1edbc | 1318 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 1319 | |
AnnaBridge | 171:3a7713b1edbc | 1320 | /** |
AnnaBridge | 171:3a7713b1edbc | 1321 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1322 | */ |
AnnaBridge | 171:3a7713b1edbc | 1323 | |
AnnaBridge | 171:3a7713b1edbc | 1324 | /** @defgroup DAC_LL_EF_IT_Management IT management |
AnnaBridge | 171:3a7713b1edbc | 1325 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1326 | */ |
AnnaBridge | 171:3a7713b1edbc | 1327 | |
AnnaBridge | 171:3a7713b1edbc | 1328 | /** |
AnnaBridge | 171:3a7713b1edbc | 1329 | * @brief Enable DMA underrun interrupt for DAC channel 1 |
AnnaBridge | 171:3a7713b1edbc | 1330 | * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 |
AnnaBridge | 171:3a7713b1edbc | 1331 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1332 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1333 | */ |
AnnaBridge | 171:3a7713b1edbc | 1334 | __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) |
AnnaBridge | 171:3a7713b1edbc | 1335 | { |
AnnaBridge | 171:3a7713b1edbc | 1336 | SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); |
AnnaBridge | 171:3a7713b1edbc | 1337 | } |
AnnaBridge | 171:3a7713b1edbc | 1338 | |
AnnaBridge | 171:3a7713b1edbc | 1339 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 1340 | /** |
AnnaBridge | 171:3a7713b1edbc | 1341 | * @brief Enable DMA underrun interrupt for DAC channel 2 |
AnnaBridge | 171:3a7713b1edbc | 1342 | * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 |
AnnaBridge | 171:3a7713b1edbc | 1343 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1344 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1345 | */ |
AnnaBridge | 171:3a7713b1edbc | 1346 | __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) |
AnnaBridge | 171:3a7713b1edbc | 1347 | { |
AnnaBridge | 171:3a7713b1edbc | 1348 | SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); |
AnnaBridge | 171:3a7713b1edbc | 1349 | } |
AnnaBridge | 171:3a7713b1edbc | 1350 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 1351 | |
AnnaBridge | 171:3a7713b1edbc | 1352 | /** |
AnnaBridge | 171:3a7713b1edbc | 1353 | * @brief Disable DMA underrun interrupt for DAC channel 1 |
AnnaBridge | 171:3a7713b1edbc | 1354 | * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 |
AnnaBridge | 171:3a7713b1edbc | 1355 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1356 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1357 | */ |
AnnaBridge | 171:3a7713b1edbc | 1358 | __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) |
AnnaBridge | 171:3a7713b1edbc | 1359 | { |
AnnaBridge | 171:3a7713b1edbc | 1360 | CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); |
AnnaBridge | 171:3a7713b1edbc | 1361 | } |
AnnaBridge | 171:3a7713b1edbc | 1362 | |
AnnaBridge | 171:3a7713b1edbc | 1363 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 1364 | /** |
AnnaBridge | 171:3a7713b1edbc | 1365 | * @brief Disable DMA underrun interrupt for DAC channel 2 |
AnnaBridge | 171:3a7713b1edbc | 1366 | * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 |
AnnaBridge | 171:3a7713b1edbc | 1367 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1368 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1369 | */ |
AnnaBridge | 171:3a7713b1edbc | 1370 | __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) |
AnnaBridge | 171:3a7713b1edbc | 1371 | { |
AnnaBridge | 171:3a7713b1edbc | 1372 | CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); |
AnnaBridge | 171:3a7713b1edbc | 1373 | } |
AnnaBridge | 171:3a7713b1edbc | 1374 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 1375 | |
AnnaBridge | 171:3a7713b1edbc | 1376 | /** |
AnnaBridge | 171:3a7713b1edbc | 1377 | * @brief Get DMA underrun interrupt for DAC channel 1 |
AnnaBridge | 171:3a7713b1edbc | 1378 | * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 |
AnnaBridge | 171:3a7713b1edbc | 1379 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1380 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1381 | */ |
AnnaBridge | 171:3a7713b1edbc | 1382 | __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) |
AnnaBridge | 171:3a7713b1edbc | 1383 | { |
AnnaBridge | 171:3a7713b1edbc | 1384 | return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)); |
AnnaBridge | 171:3a7713b1edbc | 1385 | } |
AnnaBridge | 171:3a7713b1edbc | 1386 | |
AnnaBridge | 171:3a7713b1edbc | 1387 | #if defined(DAC_CHANNEL2_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 1388 | /** |
AnnaBridge | 171:3a7713b1edbc | 1389 | * @brief Get DMA underrun interrupt for DAC channel 2 |
AnnaBridge | 171:3a7713b1edbc | 1390 | * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 |
AnnaBridge | 171:3a7713b1edbc | 1391 | * @param DACx DAC instance |
AnnaBridge | 171:3a7713b1edbc | 1392 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1393 | */ |
AnnaBridge | 171:3a7713b1edbc | 1394 | __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) |
AnnaBridge | 171:3a7713b1edbc | 1395 | { |
AnnaBridge | 171:3a7713b1edbc | 1396 | return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)); |
AnnaBridge | 171:3a7713b1edbc | 1397 | } |
AnnaBridge | 171:3a7713b1edbc | 1398 | #endif /* DAC_CHANNEL2_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 1399 | |
AnnaBridge | 171:3a7713b1edbc | 1400 | /** |
AnnaBridge | 171:3a7713b1edbc | 1401 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1402 | */ |
AnnaBridge | 171:3a7713b1edbc | 1403 | |
AnnaBridge | 171:3a7713b1edbc | 1404 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 1405 | /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions |
AnnaBridge | 171:3a7713b1edbc | 1406 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1407 | */ |
AnnaBridge | 171:3a7713b1edbc | 1408 | |
AnnaBridge | 171:3a7713b1edbc | 1409 | ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx); |
AnnaBridge | 171:3a7713b1edbc | 1410 | ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct); |
AnnaBridge | 171:3a7713b1edbc | 1411 | void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct); |
AnnaBridge | 171:3a7713b1edbc | 1412 | |
AnnaBridge | 171:3a7713b1edbc | 1413 | /** |
AnnaBridge | 171:3a7713b1edbc | 1414 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1415 | */ |
AnnaBridge | 171:3a7713b1edbc | 1416 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 171:3a7713b1edbc | 1417 | |
AnnaBridge | 171:3a7713b1edbc | 1418 | /** |
AnnaBridge | 171:3a7713b1edbc | 1419 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1420 | */ |
AnnaBridge | 171:3a7713b1edbc | 1421 | |
AnnaBridge | 171:3a7713b1edbc | 1422 | /** |
AnnaBridge | 171:3a7713b1edbc | 1423 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1424 | */ |
AnnaBridge | 171:3a7713b1edbc | 1425 | |
AnnaBridge | 171:3a7713b1edbc | 1426 | #endif /* DAC1 */ |
AnnaBridge | 171:3a7713b1edbc | 1427 | |
AnnaBridge | 171:3a7713b1edbc | 1428 | /** |
AnnaBridge | 171:3a7713b1edbc | 1429 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1430 | */ |
AnnaBridge | 171:3a7713b1edbc | 1431 | |
AnnaBridge | 171:3a7713b1edbc | 1432 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 1433 | } |
AnnaBridge | 171:3a7713b1edbc | 1434 | #endif |
AnnaBridge | 171:3a7713b1edbc | 1435 | |
AnnaBridge | 171:3a7713b1edbc | 1436 | #endif /* __STM32F0xx_LL_DAC_H */ |
AnnaBridge | 171:3a7713b1edbc | 1437 | |
AnnaBridge | 171:3a7713b1edbc | 1438 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |