The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
mbed 2
This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.
TARGET_NUCLEO_F756ZG/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.h@135:176b8275d35d, 2017-02-02 (annotated)
- Committer:
- <>
- Date:
- Thu Feb 02 16:02:30 2017 +0000
- Revision:
- 135:176b8275d35d
- Parent:
- 128:9bcdf88f62b0
- Child:
- 139:856d2700e60b
Release 135 of the mbed library
Ports for Upcoming Targets
3571: DISCO_F769NI introduction https://github.com/ARMmbed/mbed-os/pull/3571
3605: Add DELTA_DFCM_NNN50 platform https://github.com/ARMmbed/mbed-os/pull/3605
3640: [MAX32630FTHR] Adding new platform https://github.com/ARMmbed/mbed-os/pull/3640
Fixes and Changes
3397: Add uVisor support for the DISCO_F429ZI https://github.com/ARMmbed/mbed-os/pull/3397
3573: fix failing RTC initialization for MTS_DRAGONFLY_F411RE https://github.com/ARMmbed/mbed-os/pull/3573
3575: Dev stm factorize gpio https://github.com/ARMmbed/mbed-os/pull/3575
3584: STM32: make PeripheralPins.h a common file https://github.com/ARMmbed/mbed-os/pull/3584
3583: STM32F7 Cube FW new release v1.5.1 https://github.com/ARMmbed/mbed-os/pull/3583
3578: Target system - Inherit names from target parents https://github.com/ARMmbed/mbed-os/pull/3578
3599: K22F: Enable TRNG https://github.com/ARMmbed/mbed-os/pull/3599
3614: STM32: make PortNames.h a common file https://github.com/ARMmbed/mbed-os/pull/3614
3617: EFM32GG: Fix GCC_ARM linker script https://github.com/ARMmbed/mbed-os/pull/3617
3618: STM32: Move types definitions to a common file https://github.com/ARMmbed/mbed-os/pull/3618
3631: F3 CUBE update V1.7.0 https://github.com/ARMmbed/mbed-os/pull/3631
3635: STM32 I2C : Fix bug in i2c_byte_read function https://github.com/ARMmbed/mbed-os/pull/3635
3651: Max32630 - fix LED4 https://github.com/ARMmbed/mbed-os/pull/3651
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Kojto | 122:f9eeca106725 | 1 | /** |
Kojto | 122:f9eeca106725 | 2 | ****************************************************************************** |
Kojto | 122:f9eeca106725 | 3 | * @file stm32f7xx_hal_rcc.h |
Kojto | 122:f9eeca106725 | 4 | * @author MCD Application Team |
<> | 135:176b8275d35d | 5 | * @version V1.1.2 |
<> | 135:176b8275d35d | 6 | * @date 23-September-2016 |
Kojto | 122:f9eeca106725 | 7 | * @brief Header file of RCC HAL module. |
Kojto | 122:f9eeca106725 | 8 | ****************************************************************************** |
Kojto | 122:f9eeca106725 | 9 | * @attention |
Kojto | 122:f9eeca106725 | 10 | * |
Kojto | 122:f9eeca106725 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
Kojto | 122:f9eeca106725 | 12 | * |
Kojto | 122:f9eeca106725 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
Kojto | 122:f9eeca106725 | 14 | * are permitted provided that the following conditions are met: |
Kojto | 122:f9eeca106725 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
Kojto | 122:f9eeca106725 | 16 | * this list of conditions and the following disclaimer. |
Kojto | 122:f9eeca106725 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
Kojto | 122:f9eeca106725 | 18 | * this list of conditions and the following disclaimer in the documentation |
Kojto | 122:f9eeca106725 | 19 | * and/or other materials provided with the distribution. |
Kojto | 122:f9eeca106725 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
Kojto | 122:f9eeca106725 | 21 | * may be used to endorse or promote products derived from this software |
Kojto | 122:f9eeca106725 | 22 | * without specific prior written permission. |
Kojto | 122:f9eeca106725 | 23 | * |
Kojto | 122:f9eeca106725 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
Kojto | 122:f9eeca106725 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
Kojto | 122:f9eeca106725 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
Kojto | 122:f9eeca106725 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
Kojto | 122:f9eeca106725 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
Kojto | 122:f9eeca106725 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
Kojto | 122:f9eeca106725 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
Kojto | 122:f9eeca106725 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
Kojto | 122:f9eeca106725 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
Kojto | 122:f9eeca106725 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Kojto | 122:f9eeca106725 | 34 | * |
Kojto | 122:f9eeca106725 | 35 | ****************************************************************************** |
Kojto | 122:f9eeca106725 | 36 | */ |
Kojto | 122:f9eeca106725 | 37 | |
Kojto | 122:f9eeca106725 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
Kojto | 122:f9eeca106725 | 39 | #ifndef __STM32F7xx_HAL_RCC_H |
Kojto | 122:f9eeca106725 | 40 | #define __STM32F7xx_HAL_RCC_H |
Kojto | 122:f9eeca106725 | 41 | |
Kojto | 122:f9eeca106725 | 42 | #ifdef __cplusplus |
Kojto | 122:f9eeca106725 | 43 | extern "C" { |
Kojto | 122:f9eeca106725 | 44 | #endif |
Kojto | 122:f9eeca106725 | 45 | |
Kojto | 122:f9eeca106725 | 46 | /* Includes ------------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 47 | #include "stm32f7xx_hal_def.h" |
Kojto | 122:f9eeca106725 | 48 | |
Kojto | 122:f9eeca106725 | 49 | /* Include RCC HAL Extended module */ |
Kojto | 122:f9eeca106725 | 50 | /* (include on top of file since RCC structures are defined in extended file) */ |
Kojto | 122:f9eeca106725 | 51 | #include "stm32f7xx_hal_rcc_ex.h" |
Kojto | 122:f9eeca106725 | 52 | |
Kojto | 122:f9eeca106725 | 53 | /** @addtogroup STM32F7xx_HAL_Driver |
Kojto | 122:f9eeca106725 | 54 | * @{ |
Kojto | 122:f9eeca106725 | 55 | */ |
Kojto | 122:f9eeca106725 | 56 | |
Kojto | 122:f9eeca106725 | 57 | /** @addtogroup RCC |
Kojto | 122:f9eeca106725 | 58 | * @{ |
Kojto | 122:f9eeca106725 | 59 | */ |
Kojto | 122:f9eeca106725 | 60 | |
Kojto | 122:f9eeca106725 | 61 | /* Exported types ------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 62 | |
Kojto | 122:f9eeca106725 | 63 | /** @defgroup RCC_Exported_Types RCC Exported Types |
Kojto | 122:f9eeca106725 | 64 | * @{ |
Kojto | 122:f9eeca106725 | 65 | */ |
Kojto | 122:f9eeca106725 | 66 | |
Kojto | 122:f9eeca106725 | 67 | /** |
Kojto | 122:f9eeca106725 | 68 | * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition |
Kojto | 122:f9eeca106725 | 69 | */ |
Kojto | 122:f9eeca106725 | 70 | typedef struct |
Kojto | 122:f9eeca106725 | 71 | { |
Kojto | 122:f9eeca106725 | 72 | uint32_t OscillatorType; /*!< The oscillators to be configured. |
Kojto | 122:f9eeca106725 | 73 | This parameter can be a value of @ref RCC_Oscillator_Type */ |
Kojto | 122:f9eeca106725 | 74 | |
Kojto | 122:f9eeca106725 | 75 | uint32_t HSEState; /*!< The new state of the HSE. |
Kojto | 122:f9eeca106725 | 76 | This parameter can be a value of @ref RCC_HSE_Config */ |
Kojto | 122:f9eeca106725 | 77 | |
Kojto | 122:f9eeca106725 | 78 | uint32_t LSEState; /*!< The new state of the LSE. |
Kojto | 122:f9eeca106725 | 79 | This parameter can be a value of @ref RCC_LSE_Config */ |
Kojto | 122:f9eeca106725 | 80 | |
Kojto | 122:f9eeca106725 | 81 | uint32_t HSIState; /*!< The new state of the HSI. |
Kojto | 122:f9eeca106725 | 82 | This parameter can be a value of @ref RCC_HSI_Config */ |
Kojto | 122:f9eeca106725 | 83 | |
Kojto | 122:f9eeca106725 | 84 | uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). |
Kojto | 122:f9eeca106725 | 85 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
Kojto | 122:f9eeca106725 | 86 | |
Kojto | 122:f9eeca106725 | 87 | uint32_t LSIState; /*!< The new state of the LSI. |
Kojto | 122:f9eeca106725 | 88 | This parameter can be a value of @ref RCC_LSI_Config */ |
Kojto | 122:f9eeca106725 | 89 | |
Kojto | 122:f9eeca106725 | 90 | RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ |
Kojto | 122:f9eeca106725 | 91 | |
Kojto | 122:f9eeca106725 | 92 | }RCC_OscInitTypeDef; |
Kojto | 122:f9eeca106725 | 93 | |
Kojto | 122:f9eeca106725 | 94 | /** |
Kojto | 122:f9eeca106725 | 95 | * @brief RCC System, AHB and APB busses clock configuration structure definition |
Kojto | 122:f9eeca106725 | 96 | */ |
Kojto | 122:f9eeca106725 | 97 | typedef struct |
Kojto | 122:f9eeca106725 | 98 | { |
Kojto | 122:f9eeca106725 | 99 | uint32_t ClockType; /*!< The clock to be configured. |
Kojto | 122:f9eeca106725 | 100 | This parameter can be a value of @ref RCC_System_Clock_Type */ |
Kojto | 122:f9eeca106725 | 101 | |
Kojto | 122:f9eeca106725 | 102 | uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. |
Kojto | 122:f9eeca106725 | 103 | This parameter can be a value of @ref RCC_System_Clock_Source */ |
Kojto | 122:f9eeca106725 | 104 | |
Kojto | 122:f9eeca106725 | 105 | uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). |
Kojto | 122:f9eeca106725 | 106 | This parameter can be a value of @ref RCC_AHB_Clock_Source */ |
Kojto | 122:f9eeca106725 | 107 | |
Kojto | 122:f9eeca106725 | 108 | uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). |
Kojto | 122:f9eeca106725 | 109 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
Kojto | 122:f9eeca106725 | 110 | |
Kojto | 122:f9eeca106725 | 111 | uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). |
Kojto | 122:f9eeca106725 | 112 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
Kojto | 122:f9eeca106725 | 113 | |
Kojto | 122:f9eeca106725 | 114 | }RCC_ClkInitTypeDef; |
Kojto | 122:f9eeca106725 | 115 | |
Kojto | 122:f9eeca106725 | 116 | /** |
Kojto | 122:f9eeca106725 | 117 | * @} |
Kojto | 122:f9eeca106725 | 118 | */ |
Kojto | 122:f9eeca106725 | 119 | |
Kojto | 122:f9eeca106725 | 120 | /* Exported constants --------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 121 | /** @defgroup RCC_Exported_Constants RCC Exported Constants |
Kojto | 122:f9eeca106725 | 122 | * @{ |
Kojto | 122:f9eeca106725 | 123 | */ |
Kojto | 122:f9eeca106725 | 124 | |
Kojto | 122:f9eeca106725 | 125 | /** @defgroup RCC_Oscillator_Type Oscillator Type |
Kojto | 122:f9eeca106725 | 126 | * @{ |
Kojto | 122:f9eeca106725 | 127 | */ |
Kojto | 122:f9eeca106725 | 128 | #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) |
Kojto | 122:f9eeca106725 | 129 | #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) |
Kojto | 122:f9eeca106725 | 130 | #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) |
Kojto | 122:f9eeca106725 | 131 | #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) |
Kojto | 122:f9eeca106725 | 132 | #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) |
Kojto | 122:f9eeca106725 | 133 | /** |
Kojto | 122:f9eeca106725 | 134 | * @} |
Kojto | 122:f9eeca106725 | 135 | */ |
Kojto | 122:f9eeca106725 | 136 | |
Kojto | 122:f9eeca106725 | 137 | /** @defgroup RCC_HSE_Config RCC HSE Config |
Kojto | 122:f9eeca106725 | 138 | * @{ |
Kojto | 122:f9eeca106725 | 139 | */ |
Kojto | 122:f9eeca106725 | 140 | #define RCC_HSE_OFF ((uint32_t)0x00000000U) |
Kojto | 122:f9eeca106725 | 141 | #define RCC_HSE_ON RCC_CR_HSEON |
Kojto | 122:f9eeca106725 | 142 | #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) |
Kojto | 122:f9eeca106725 | 143 | /** |
Kojto | 122:f9eeca106725 | 144 | * @} |
Kojto | 122:f9eeca106725 | 145 | */ |
Kojto | 122:f9eeca106725 | 146 | |
Kojto | 122:f9eeca106725 | 147 | /** @defgroup RCC_LSE_Config RCC LSE Config |
Kojto | 122:f9eeca106725 | 148 | * @{ |
Kojto | 122:f9eeca106725 | 149 | */ |
Kojto | 122:f9eeca106725 | 150 | #define RCC_LSE_OFF ((uint32_t)0x00000000U) |
Kojto | 122:f9eeca106725 | 151 | #define RCC_LSE_ON RCC_BDCR_LSEON |
Kojto | 122:f9eeca106725 | 152 | #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) |
Kojto | 122:f9eeca106725 | 153 | /** |
Kojto | 122:f9eeca106725 | 154 | * @} |
Kojto | 122:f9eeca106725 | 155 | */ |
Kojto | 122:f9eeca106725 | 156 | |
Kojto | 122:f9eeca106725 | 157 | /** @defgroup RCC_HSI_Config RCC HSI Config |
Kojto | 122:f9eeca106725 | 158 | * @{ |
Kojto | 122:f9eeca106725 | 159 | */ |
Kojto | 122:f9eeca106725 | 160 | #define RCC_HSI_OFF ((uint32_t)0x00000000U) |
Kojto | 122:f9eeca106725 | 161 | #define RCC_HSI_ON RCC_CR_HSION |
Kojto | 122:f9eeca106725 | 162 | |
Kojto | 122:f9eeca106725 | 163 | #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */ |
Kojto | 122:f9eeca106725 | 164 | /** |
Kojto | 122:f9eeca106725 | 165 | * @} |
Kojto | 122:f9eeca106725 | 166 | */ |
Kojto | 122:f9eeca106725 | 167 | |
Kojto | 122:f9eeca106725 | 168 | /** @defgroup RCC_LSI_Config RCC LSI Config |
Kojto | 122:f9eeca106725 | 169 | * @{ |
Kojto | 122:f9eeca106725 | 170 | */ |
Kojto | 122:f9eeca106725 | 171 | #define RCC_LSI_OFF ((uint32_t)0x00000000U) |
Kojto | 122:f9eeca106725 | 172 | #define RCC_LSI_ON RCC_CSR_LSION |
Kojto | 122:f9eeca106725 | 173 | /** |
Kojto | 122:f9eeca106725 | 174 | * @} |
Kojto | 122:f9eeca106725 | 175 | */ |
Kojto | 122:f9eeca106725 | 176 | |
Kojto | 122:f9eeca106725 | 177 | /** @defgroup RCC_PLL_Config RCC PLL Config |
Kojto | 122:f9eeca106725 | 178 | * @{ |
Kojto | 122:f9eeca106725 | 179 | */ |
Kojto | 122:f9eeca106725 | 180 | #define RCC_PLL_NONE ((uint32_t)0x00000000U) |
Kojto | 122:f9eeca106725 | 181 | #define RCC_PLL_OFF ((uint32_t)0x00000001U) |
Kojto | 122:f9eeca106725 | 182 | #define RCC_PLL_ON ((uint32_t)0x00000002U) |
Kojto | 122:f9eeca106725 | 183 | /** |
Kojto | 122:f9eeca106725 | 184 | * @} |
Kojto | 122:f9eeca106725 | 185 | */ |
Kojto | 122:f9eeca106725 | 186 | |
Kojto | 122:f9eeca106725 | 187 | /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider |
Kojto | 122:f9eeca106725 | 188 | * @{ |
Kojto | 122:f9eeca106725 | 189 | */ |
Kojto | 122:f9eeca106725 | 190 | #define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) |
Kojto | 122:f9eeca106725 | 191 | #define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) |
Kojto | 122:f9eeca106725 | 192 | #define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) |
Kojto | 122:f9eeca106725 | 193 | #define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) |
Kojto | 122:f9eeca106725 | 194 | /** |
Kojto | 122:f9eeca106725 | 195 | * @} |
Kojto | 122:f9eeca106725 | 196 | */ |
Kojto | 122:f9eeca106725 | 197 | |
Kojto | 122:f9eeca106725 | 198 | /** @defgroup RCC_PLL_Clock_Source PLL Clock Source |
Kojto | 122:f9eeca106725 | 199 | * @{ |
Kojto | 122:f9eeca106725 | 200 | */ |
Kojto | 122:f9eeca106725 | 201 | #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI |
Kojto | 122:f9eeca106725 | 202 | #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE |
Kojto | 122:f9eeca106725 | 203 | /** |
Kojto | 122:f9eeca106725 | 204 | * @} |
Kojto | 122:f9eeca106725 | 205 | */ |
Kojto | 122:f9eeca106725 | 206 | |
Kojto | 122:f9eeca106725 | 207 | /** @defgroup RCC_System_Clock_Type RCC System Clock Type |
Kojto | 122:f9eeca106725 | 208 | * @{ |
Kojto | 122:f9eeca106725 | 209 | */ |
Kojto | 122:f9eeca106725 | 210 | #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) |
Kojto | 122:f9eeca106725 | 211 | #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) |
Kojto | 122:f9eeca106725 | 212 | #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) |
Kojto | 122:f9eeca106725 | 213 | #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) |
Kojto | 122:f9eeca106725 | 214 | /** |
Kojto | 122:f9eeca106725 | 215 | * @} |
Kojto | 122:f9eeca106725 | 216 | */ |
Kojto | 122:f9eeca106725 | 217 | |
Kojto | 122:f9eeca106725 | 218 | /** @defgroup RCC_System_Clock_Source RCC System Clock Source |
Kojto | 122:f9eeca106725 | 219 | * @{ |
Kojto | 122:f9eeca106725 | 220 | */ |
Kojto | 122:f9eeca106725 | 221 | #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI |
Kojto | 122:f9eeca106725 | 222 | #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE |
Kojto | 122:f9eeca106725 | 223 | #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL |
Kojto | 122:f9eeca106725 | 224 | /** |
Kojto | 122:f9eeca106725 | 225 | * @} |
Kojto | 122:f9eeca106725 | 226 | */ |
Kojto | 122:f9eeca106725 | 227 | |
Kojto | 122:f9eeca106725 | 228 | |
Kojto | 122:f9eeca106725 | 229 | /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status |
Kojto | 122:f9eeca106725 | 230 | * @{ |
Kojto | 122:f9eeca106725 | 231 | */ |
Kojto | 122:f9eeca106725 | 232 | #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ |
Kojto | 122:f9eeca106725 | 233 | #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ |
Kojto | 122:f9eeca106725 | 234 | #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ |
Kojto | 122:f9eeca106725 | 235 | /** |
Kojto | 122:f9eeca106725 | 236 | * @} |
Kojto | 122:f9eeca106725 | 237 | */ |
Kojto | 122:f9eeca106725 | 238 | |
Kojto | 122:f9eeca106725 | 239 | /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source |
Kojto | 122:f9eeca106725 | 240 | * @{ |
Kojto | 122:f9eeca106725 | 241 | */ |
Kojto | 122:f9eeca106725 | 242 | #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 |
Kojto | 122:f9eeca106725 | 243 | #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 |
Kojto | 122:f9eeca106725 | 244 | #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 |
Kojto | 122:f9eeca106725 | 245 | #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 |
Kojto | 122:f9eeca106725 | 246 | #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 |
Kojto | 122:f9eeca106725 | 247 | #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 |
Kojto | 122:f9eeca106725 | 248 | #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 |
Kojto | 122:f9eeca106725 | 249 | #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 |
Kojto | 122:f9eeca106725 | 250 | #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 |
Kojto | 122:f9eeca106725 | 251 | /** |
Kojto | 122:f9eeca106725 | 252 | * @} |
Kojto | 122:f9eeca106725 | 253 | */ |
Kojto | 122:f9eeca106725 | 254 | |
Kojto | 122:f9eeca106725 | 255 | /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source |
Kojto | 122:f9eeca106725 | 256 | * @{ |
Kojto | 122:f9eeca106725 | 257 | */ |
Kojto | 122:f9eeca106725 | 258 | #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 |
Kojto | 122:f9eeca106725 | 259 | #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 |
Kojto | 122:f9eeca106725 | 260 | #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 |
Kojto | 122:f9eeca106725 | 261 | #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 |
Kojto | 122:f9eeca106725 | 262 | #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 |
Kojto | 122:f9eeca106725 | 263 | /** |
Kojto | 122:f9eeca106725 | 264 | * @} |
Kojto | 122:f9eeca106725 | 265 | */ |
Kojto | 122:f9eeca106725 | 266 | |
Kojto | 122:f9eeca106725 | 267 | /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source |
Kojto | 122:f9eeca106725 | 268 | * @{ |
Kojto | 122:f9eeca106725 | 269 | */ |
Kojto | 122:f9eeca106725 | 270 | #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U) |
Kojto | 122:f9eeca106725 | 271 | #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U) |
Kojto | 122:f9eeca106725 | 272 | #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U) |
Kojto | 122:f9eeca106725 | 273 | #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U) |
Kojto | 122:f9eeca106725 | 274 | #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U) |
Kojto | 122:f9eeca106725 | 275 | #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U) |
Kojto | 122:f9eeca106725 | 276 | #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U) |
Kojto | 122:f9eeca106725 | 277 | #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U) |
Kojto | 122:f9eeca106725 | 278 | #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U) |
Kojto | 122:f9eeca106725 | 279 | #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U) |
Kojto | 122:f9eeca106725 | 280 | #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U) |
Kojto | 122:f9eeca106725 | 281 | #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U) |
Kojto | 122:f9eeca106725 | 282 | #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U) |
Kojto | 122:f9eeca106725 | 283 | #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U) |
Kojto | 122:f9eeca106725 | 284 | #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U) |
Kojto | 122:f9eeca106725 | 285 | #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U) |
Kojto | 122:f9eeca106725 | 286 | #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U) |
Kojto | 122:f9eeca106725 | 287 | #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U) |
Kojto | 122:f9eeca106725 | 288 | #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U) |
Kojto | 122:f9eeca106725 | 289 | #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U) |
Kojto | 122:f9eeca106725 | 290 | #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U) |
Kojto | 122:f9eeca106725 | 291 | #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U) |
Kojto | 122:f9eeca106725 | 292 | #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U) |
Kojto | 122:f9eeca106725 | 293 | #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U) |
Kojto | 122:f9eeca106725 | 294 | #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U) |
Kojto | 122:f9eeca106725 | 295 | #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U) |
Kojto | 122:f9eeca106725 | 296 | #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U) |
Kojto | 122:f9eeca106725 | 297 | #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U) |
Kojto | 122:f9eeca106725 | 298 | #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U) |
Kojto | 122:f9eeca106725 | 299 | #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U) |
Kojto | 122:f9eeca106725 | 300 | #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U) |
Kojto | 122:f9eeca106725 | 301 | #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U) |
Kojto | 122:f9eeca106725 | 302 | /** |
Kojto | 122:f9eeca106725 | 303 | * @} |
Kojto | 122:f9eeca106725 | 304 | */ |
Kojto | 122:f9eeca106725 | 305 | |
Kojto | 122:f9eeca106725 | 306 | |
Kojto | 122:f9eeca106725 | 307 | |
Kojto | 122:f9eeca106725 | 308 | /** @defgroup RCC_MCO_Index RCC MCO Index |
Kojto | 122:f9eeca106725 | 309 | * @{ |
Kojto | 122:f9eeca106725 | 310 | */ |
Kojto | 122:f9eeca106725 | 311 | #define RCC_MCO1 ((uint32_t)0x00000000U) |
Kojto | 122:f9eeca106725 | 312 | #define RCC_MCO2 ((uint32_t)0x00000001U) |
Kojto | 122:f9eeca106725 | 313 | /** |
Kojto | 122:f9eeca106725 | 314 | * @} |
Kojto | 122:f9eeca106725 | 315 | */ |
Kojto | 122:f9eeca106725 | 316 | |
Kojto | 122:f9eeca106725 | 317 | /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source |
Kojto | 122:f9eeca106725 | 318 | * @{ |
Kojto | 122:f9eeca106725 | 319 | */ |
Kojto | 122:f9eeca106725 | 320 | #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U) |
Kojto | 122:f9eeca106725 | 321 | #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 |
Kojto | 122:f9eeca106725 | 322 | #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 |
Kojto | 122:f9eeca106725 | 323 | #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 |
Kojto | 122:f9eeca106725 | 324 | /** |
Kojto | 122:f9eeca106725 | 325 | * @} |
Kojto | 122:f9eeca106725 | 326 | */ |
Kojto | 122:f9eeca106725 | 327 | |
Kojto | 122:f9eeca106725 | 328 | /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source |
Kojto | 122:f9eeca106725 | 329 | * @{ |
Kojto | 122:f9eeca106725 | 330 | */ |
Kojto | 122:f9eeca106725 | 331 | #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U) |
Kojto | 122:f9eeca106725 | 332 | #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 |
Kojto | 122:f9eeca106725 | 333 | #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 |
Kojto | 122:f9eeca106725 | 334 | #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 |
Kojto | 122:f9eeca106725 | 335 | /** |
Kojto | 122:f9eeca106725 | 336 | * @} |
Kojto | 122:f9eeca106725 | 337 | */ |
Kojto | 122:f9eeca106725 | 338 | |
Kojto | 122:f9eeca106725 | 339 | /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler |
Kojto | 122:f9eeca106725 | 340 | * @{ |
Kojto | 122:f9eeca106725 | 341 | */ |
Kojto | 122:f9eeca106725 | 342 | #define RCC_MCODIV_1 ((uint32_t)0x00000000U) |
Kojto | 122:f9eeca106725 | 343 | #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 |
Kojto | 122:f9eeca106725 | 344 | #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) |
Kojto | 122:f9eeca106725 | 345 | #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) |
Kojto | 122:f9eeca106725 | 346 | #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE |
Kojto | 122:f9eeca106725 | 347 | /** |
Kojto | 122:f9eeca106725 | 348 | * @} |
Kojto | 122:f9eeca106725 | 349 | */ |
Kojto | 122:f9eeca106725 | 350 | |
Kojto | 122:f9eeca106725 | 351 | /** @defgroup RCC_Interrupt RCC Interrupt |
Kojto | 122:f9eeca106725 | 352 | * @{ |
Kojto | 122:f9eeca106725 | 353 | */ |
Kojto | 122:f9eeca106725 | 354 | #define RCC_IT_LSIRDY ((uint8_t)0x01U) |
Kojto | 122:f9eeca106725 | 355 | #define RCC_IT_LSERDY ((uint8_t)0x02U) |
Kojto | 122:f9eeca106725 | 356 | #define RCC_IT_HSIRDY ((uint8_t)0x04U) |
Kojto | 122:f9eeca106725 | 357 | #define RCC_IT_HSERDY ((uint8_t)0x08U) |
Kojto | 122:f9eeca106725 | 358 | #define RCC_IT_PLLRDY ((uint8_t)0x10U) |
Kojto | 122:f9eeca106725 | 359 | #define RCC_IT_PLLI2SRDY ((uint8_t)0x20U) |
Kojto | 122:f9eeca106725 | 360 | #define RCC_IT_PLLSAIRDY ((uint8_t)0x40U) |
Kojto | 122:f9eeca106725 | 361 | #define RCC_IT_CSS ((uint8_t)0x80U) |
Kojto | 122:f9eeca106725 | 362 | /** |
Kojto | 122:f9eeca106725 | 363 | * @} |
Kojto | 122:f9eeca106725 | 364 | */ |
Kojto | 122:f9eeca106725 | 365 | |
Kojto | 122:f9eeca106725 | 366 | /** @defgroup RCC_Flag RCC Flags |
Kojto | 122:f9eeca106725 | 367 | * Elements values convention: 0XXYYYYYb |
Kojto | 122:f9eeca106725 | 368 | * - YYYYY : Flag position in the register |
Kojto | 122:f9eeca106725 | 369 | * - 0XX : Register index |
Kojto | 122:f9eeca106725 | 370 | * - 01: CR register |
Kojto | 122:f9eeca106725 | 371 | * - 10: BDCR register |
Kojto | 122:f9eeca106725 | 372 | * - 11: CSR register |
Kojto | 122:f9eeca106725 | 373 | * @{ |
Kojto | 122:f9eeca106725 | 374 | */ |
Kojto | 122:f9eeca106725 | 375 | /* Flags in the CR register */ |
Kojto | 122:f9eeca106725 | 376 | #define RCC_FLAG_HSIRDY ((uint8_t)0x21U) |
Kojto | 122:f9eeca106725 | 377 | #define RCC_FLAG_HSERDY ((uint8_t)0x31U) |
Kojto | 122:f9eeca106725 | 378 | #define RCC_FLAG_PLLRDY ((uint8_t)0x39U) |
Kojto | 122:f9eeca106725 | 379 | #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU) |
Kojto | 122:f9eeca106725 | 380 | #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU) |
Kojto | 122:f9eeca106725 | 381 | |
Kojto | 122:f9eeca106725 | 382 | /* Flags in the BDCR register */ |
Kojto | 122:f9eeca106725 | 383 | #define RCC_FLAG_LSERDY ((uint8_t)0x41U) |
Kojto | 122:f9eeca106725 | 384 | |
Kojto | 122:f9eeca106725 | 385 | /* Flags in the CSR register */ |
Kojto | 122:f9eeca106725 | 386 | #define RCC_FLAG_LSIRDY ((uint8_t)0x61U) |
Kojto | 122:f9eeca106725 | 387 | #define RCC_FLAG_BORRST ((uint8_t)0x79U) |
Kojto | 122:f9eeca106725 | 388 | #define RCC_FLAG_PINRST ((uint8_t)0x7AU) |
Kojto | 122:f9eeca106725 | 389 | #define RCC_FLAG_PORRST ((uint8_t)0x7BU) |
Kojto | 122:f9eeca106725 | 390 | #define RCC_FLAG_SFTRST ((uint8_t)0x7CU) |
Kojto | 122:f9eeca106725 | 391 | #define RCC_FLAG_IWDGRST ((uint8_t)0x7DU) |
Kojto | 122:f9eeca106725 | 392 | #define RCC_FLAG_WWDGRST ((uint8_t)0x7EU) |
Kojto | 122:f9eeca106725 | 393 | #define RCC_FLAG_LPWRRST ((uint8_t)0x7FU) |
Kojto | 122:f9eeca106725 | 394 | /** |
Kojto | 122:f9eeca106725 | 395 | * @} |
Kojto | 122:f9eeca106725 | 396 | */ |
Kojto | 122:f9eeca106725 | 397 | |
Kojto | 122:f9eeca106725 | 398 | /** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations |
Kojto | 122:f9eeca106725 | 399 | * @{ |
Kojto | 122:f9eeca106725 | 400 | */ |
Kojto | 122:f9eeca106725 | 401 | #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) |
Kojto | 122:f9eeca106725 | 402 | #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 |
Kojto | 122:f9eeca106725 | 403 | #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 |
Kojto | 122:f9eeca106725 | 404 | #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV |
Kojto | 122:f9eeca106725 | 405 | /** |
Kojto | 122:f9eeca106725 | 406 | * @} |
Kojto | 122:f9eeca106725 | 407 | */ |
Kojto | 122:f9eeca106725 | 408 | |
Kojto | 122:f9eeca106725 | 409 | /** |
Kojto | 122:f9eeca106725 | 410 | * @} |
Kojto | 122:f9eeca106725 | 411 | */ |
Kojto | 122:f9eeca106725 | 412 | |
Kojto | 122:f9eeca106725 | 413 | /* Exported macro ------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 414 | /** @defgroup RCC_Exported_Macros RCC Exported Macros |
Kojto | 122:f9eeca106725 | 415 | * @{ |
Kojto | 122:f9eeca106725 | 416 | */ |
Kojto | 122:f9eeca106725 | 417 | |
Kojto | 122:f9eeca106725 | 418 | /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable |
Kojto | 122:f9eeca106725 | 419 | * @brief Enable or disable the AHB1 peripheral clock. |
Kojto | 122:f9eeca106725 | 420 | * @note After reset, the peripheral clock (used for registers read/write access) |
Kojto | 122:f9eeca106725 | 421 | * is disabled and the application software has to enable this clock before |
Kojto | 122:f9eeca106725 | 422 | * using it. |
Kojto | 122:f9eeca106725 | 423 | * @{ |
Kojto | 122:f9eeca106725 | 424 | */ |
Kojto | 122:f9eeca106725 | 425 | #define __HAL_RCC_CRC_CLK_ENABLE() do { \ |
Kojto | 122:f9eeca106725 | 426 | __IO uint32_t tmpreg; \ |
Kojto | 122:f9eeca106725 | 427 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ |
Kojto | 122:f9eeca106725 | 428 | /* Delay after an RCC peripheral clock enabling */ \ |
Kojto | 122:f9eeca106725 | 429 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ |
Kojto | 122:f9eeca106725 | 430 | UNUSED(tmpreg); \ |
Kojto | 122:f9eeca106725 | 431 | } while(0) |
Kojto | 122:f9eeca106725 | 432 | |
Kojto | 122:f9eeca106725 | 433 | #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ |
Kojto | 122:f9eeca106725 | 434 | __IO uint32_t tmpreg; \ |
Kojto | 122:f9eeca106725 | 435 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ |
Kojto | 122:f9eeca106725 | 436 | /* Delay after an RCC peripheral clock enabling */ \ |
Kojto | 122:f9eeca106725 | 437 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ |
Kojto | 122:f9eeca106725 | 438 | UNUSED(tmpreg); \ |
Kojto | 122:f9eeca106725 | 439 | } while(0) |
Kojto | 122:f9eeca106725 | 440 | |
Kojto | 122:f9eeca106725 | 441 | #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) |
Kojto | 122:f9eeca106725 | 442 | #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) |
Kojto | 122:f9eeca106725 | 443 | |
Kojto | 122:f9eeca106725 | 444 | /** |
Kojto | 122:f9eeca106725 | 445 | * @} |
Kojto | 122:f9eeca106725 | 446 | */ |
Kojto | 122:f9eeca106725 | 447 | |
Kojto | 122:f9eeca106725 | 448 | /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable |
Kojto | 122:f9eeca106725 | 449 | * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
Kojto | 122:f9eeca106725 | 450 | * @note After reset, the peripheral clock (used for registers read/write access) |
Kojto | 122:f9eeca106725 | 451 | * is disabled and the application software has to enable this clock before |
Kojto | 122:f9eeca106725 | 452 | * using it. |
Kojto | 122:f9eeca106725 | 453 | * @{ |
Kojto | 122:f9eeca106725 | 454 | */ |
Kojto | 122:f9eeca106725 | 455 | #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ |
Kojto | 122:f9eeca106725 | 456 | __IO uint32_t tmpreg; \ |
Kojto | 122:f9eeca106725 | 457 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ |
Kojto | 122:f9eeca106725 | 458 | /* Delay after an RCC peripheral clock enabling */ \ |
Kojto | 122:f9eeca106725 | 459 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ |
Kojto | 122:f9eeca106725 | 460 | UNUSED(tmpreg); \ |
Kojto | 122:f9eeca106725 | 461 | } while(0) |
Kojto | 122:f9eeca106725 | 462 | |
Kojto | 122:f9eeca106725 | 463 | #define __HAL_RCC_PWR_CLK_ENABLE() do { \ |
Kojto | 122:f9eeca106725 | 464 | __IO uint32_t tmpreg; \ |
Kojto | 122:f9eeca106725 | 465 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ |
Kojto | 122:f9eeca106725 | 466 | /* Delay after an RCC peripheral clock enabling */ \ |
Kojto | 122:f9eeca106725 | 467 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ |
Kojto | 122:f9eeca106725 | 468 | UNUSED(tmpreg); \ |
Kojto | 122:f9eeca106725 | 469 | } while(0) |
Kojto | 122:f9eeca106725 | 470 | |
Kojto | 122:f9eeca106725 | 471 | #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) |
Kojto | 122:f9eeca106725 | 472 | #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) |
Kojto | 122:f9eeca106725 | 473 | /** |
Kojto | 122:f9eeca106725 | 474 | * @} |
Kojto | 122:f9eeca106725 | 475 | */ |
Kojto | 122:f9eeca106725 | 476 | |
Kojto | 122:f9eeca106725 | 477 | /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable |
Kojto | 122:f9eeca106725 | 478 | * @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
Kojto | 122:f9eeca106725 | 479 | * @note After reset, the peripheral clock (used for registers read/write access) |
Kojto | 122:f9eeca106725 | 480 | * is disabled and the application software has to enable this clock before |
Kojto | 122:f9eeca106725 | 481 | * using it. |
Kojto | 122:f9eeca106725 | 482 | * @{ |
Kojto | 122:f9eeca106725 | 483 | */ |
Kojto | 122:f9eeca106725 | 484 | #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ |
Kojto | 122:f9eeca106725 | 485 | __IO uint32_t tmpreg; \ |
Kojto | 122:f9eeca106725 | 486 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ |
Kojto | 122:f9eeca106725 | 487 | /* Delay after an RCC peripheral clock enabling */ \ |
Kojto | 122:f9eeca106725 | 488 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ |
Kojto | 122:f9eeca106725 | 489 | UNUSED(tmpreg); \ |
Kojto | 122:f9eeca106725 | 490 | } while(0) |
Kojto | 122:f9eeca106725 | 491 | |
Kojto | 122:f9eeca106725 | 492 | #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) |
Kojto | 122:f9eeca106725 | 493 | |
Kojto | 122:f9eeca106725 | 494 | /** |
Kojto | 122:f9eeca106725 | 495 | * @} |
Kojto | 122:f9eeca106725 | 496 | */ |
Kojto | 122:f9eeca106725 | 497 | |
Kojto | 122:f9eeca106725 | 498 | /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status |
Kojto | 122:f9eeca106725 | 499 | * @brief Get the enable or disable status of the AHB1 peripheral clock. |
Kojto | 122:f9eeca106725 | 500 | * @note After reset, the peripheral clock (used for registers read/write access) |
Kojto | 122:f9eeca106725 | 501 | * is disabled and the application software has to enable this clock before |
Kojto | 122:f9eeca106725 | 502 | * using it. |
Kojto | 122:f9eeca106725 | 503 | * @{ |
Kojto | 122:f9eeca106725 | 504 | */ |
Kojto | 122:f9eeca106725 | 505 | #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) |
Kojto | 122:f9eeca106725 | 506 | #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET) |
Kojto | 122:f9eeca106725 | 507 | |
Kojto | 122:f9eeca106725 | 508 | #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) |
Kojto | 122:f9eeca106725 | 509 | #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET) |
Kojto | 122:f9eeca106725 | 510 | /** |
Kojto | 122:f9eeca106725 | 511 | * @} |
Kojto | 122:f9eeca106725 | 512 | */ |
Kojto | 122:f9eeca106725 | 513 | |
Kojto | 122:f9eeca106725 | 514 | /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status |
Kojto | 122:f9eeca106725 | 515 | * @brief Get the enable or disable status of the APB1 peripheral clock. |
Kojto | 122:f9eeca106725 | 516 | * @note After reset, the peripheral clock (used for registers read/write access) |
Kojto | 122:f9eeca106725 | 517 | * is disabled and the application software has to enable this clock before |
Kojto | 122:f9eeca106725 | 518 | * using it. |
Kojto | 122:f9eeca106725 | 519 | * @{ |
Kojto | 122:f9eeca106725 | 520 | */ |
Kojto | 122:f9eeca106725 | 521 | #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) |
Kojto | 122:f9eeca106725 | 522 | #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) |
Kojto | 122:f9eeca106725 | 523 | |
Kojto | 122:f9eeca106725 | 524 | #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) |
Kojto | 122:f9eeca106725 | 525 | #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) |
Kojto | 122:f9eeca106725 | 526 | /** |
Kojto | 122:f9eeca106725 | 527 | * @} |
Kojto | 122:f9eeca106725 | 528 | */ |
Kojto | 122:f9eeca106725 | 529 | |
Kojto | 122:f9eeca106725 | 530 | /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status |
Kojto | 122:f9eeca106725 | 531 | * @brief EGet the enable or disable status of the APB2 peripheral clock. |
Kojto | 122:f9eeca106725 | 532 | * @note After reset, the peripheral clock (used for registers read/write access) |
Kojto | 122:f9eeca106725 | 533 | * is disabled and the application software has to enable this clock before |
Kojto | 122:f9eeca106725 | 534 | * using it. |
Kojto | 122:f9eeca106725 | 535 | * @{ |
Kojto | 122:f9eeca106725 | 536 | */ |
Kojto | 122:f9eeca106725 | 537 | #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) |
Kojto | 122:f9eeca106725 | 538 | #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) |
Kojto | 122:f9eeca106725 | 539 | /** |
Kojto | 122:f9eeca106725 | 540 | * @} |
Kojto | 122:f9eeca106725 | 541 | */ |
Kojto | 122:f9eeca106725 | 542 | |
Kojto | 122:f9eeca106725 | 543 | /** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release |
Kojto | 122:f9eeca106725 | 544 | * @brief Force or release AHB peripheral reset. |
Kojto | 122:f9eeca106725 | 545 | * @{ |
Kojto | 122:f9eeca106725 | 546 | */ |
Kojto | 122:f9eeca106725 | 547 | #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) |
Kojto | 122:f9eeca106725 | 548 | #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) |
Kojto | 122:f9eeca106725 | 549 | #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) |
Kojto | 122:f9eeca106725 | 550 | |
Kojto | 122:f9eeca106725 | 551 | #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) |
Kojto | 122:f9eeca106725 | 552 | #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) |
Kojto | 122:f9eeca106725 | 553 | #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) |
Kojto | 122:f9eeca106725 | 554 | /** |
Kojto | 122:f9eeca106725 | 555 | * @} |
Kojto | 122:f9eeca106725 | 556 | */ |
Kojto | 122:f9eeca106725 | 557 | |
Kojto | 122:f9eeca106725 | 558 | /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset |
Kojto | 122:f9eeca106725 | 559 | * @brief Force or release APB1 peripheral reset. |
Kojto | 122:f9eeca106725 | 560 | * @{ |
Kojto | 122:f9eeca106725 | 561 | */ |
Kojto | 122:f9eeca106725 | 562 | #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) |
Kojto | 122:f9eeca106725 | 563 | #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) |
Kojto | 122:f9eeca106725 | 564 | #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) |
Kojto | 122:f9eeca106725 | 565 | |
Kojto | 122:f9eeca106725 | 566 | #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) |
Kojto | 122:f9eeca106725 | 567 | #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) |
Kojto | 122:f9eeca106725 | 568 | #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) |
Kojto | 122:f9eeca106725 | 569 | /** |
Kojto | 122:f9eeca106725 | 570 | * @} |
Kojto | 122:f9eeca106725 | 571 | */ |
Kojto | 122:f9eeca106725 | 572 | |
Kojto | 122:f9eeca106725 | 573 | /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset |
Kojto | 122:f9eeca106725 | 574 | * @brief Force or release APB2 peripheral reset. |
Kojto | 122:f9eeca106725 | 575 | * @{ |
Kojto | 122:f9eeca106725 | 576 | */ |
Kojto | 122:f9eeca106725 | 577 | #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) |
Kojto | 122:f9eeca106725 | 578 | #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) |
Kojto | 122:f9eeca106725 | 579 | |
Kojto | 122:f9eeca106725 | 580 | #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) |
Kojto | 122:f9eeca106725 | 581 | #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) |
Kojto | 122:f9eeca106725 | 582 | |
Kojto | 122:f9eeca106725 | 583 | /** |
Kojto | 122:f9eeca106725 | 584 | * @} |
Kojto | 122:f9eeca106725 | 585 | */ |
Kojto | 122:f9eeca106725 | 586 | |
Kojto | 122:f9eeca106725 | 587 | /** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable |
Kojto | 122:f9eeca106725 | 588 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
Kojto | 122:f9eeca106725 | 589 | * power consumption. |
Kojto | 122:f9eeca106725 | 590 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
Kojto | 122:f9eeca106725 | 591 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
Kojto | 122:f9eeca106725 | 592 | * @{ |
Kojto | 122:f9eeca106725 | 593 | */ |
Kojto | 122:f9eeca106725 | 594 | #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) |
Kojto | 122:f9eeca106725 | 595 | #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) |
Kojto | 122:f9eeca106725 | 596 | |
Kojto | 122:f9eeca106725 | 597 | #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) |
Kojto | 122:f9eeca106725 | 598 | #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) |
Kojto | 122:f9eeca106725 | 599 | |
Kojto | 122:f9eeca106725 | 600 | /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. |
Kojto | 122:f9eeca106725 | 601 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
Kojto | 122:f9eeca106725 | 602 | * power consumption. |
Kojto | 122:f9eeca106725 | 603 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
Kojto | 122:f9eeca106725 | 604 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
Kojto | 122:f9eeca106725 | 605 | */ |
Kojto | 122:f9eeca106725 | 606 | #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) |
Kojto | 122:f9eeca106725 | 607 | #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) |
Kojto | 122:f9eeca106725 | 608 | |
Kojto | 122:f9eeca106725 | 609 | #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) |
Kojto | 122:f9eeca106725 | 610 | #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) |
Kojto | 122:f9eeca106725 | 611 | |
Kojto | 122:f9eeca106725 | 612 | /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. |
Kojto | 122:f9eeca106725 | 613 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
Kojto | 122:f9eeca106725 | 614 | * power consumption. |
Kojto | 122:f9eeca106725 | 615 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
Kojto | 122:f9eeca106725 | 616 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
Kojto | 122:f9eeca106725 | 617 | */ |
Kojto | 122:f9eeca106725 | 618 | #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) |
Kojto | 122:f9eeca106725 | 619 | #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) |
Kojto | 122:f9eeca106725 | 620 | |
Kojto | 122:f9eeca106725 | 621 | /** |
Kojto | 122:f9eeca106725 | 622 | * @} |
Kojto | 122:f9eeca106725 | 623 | */ |
Kojto | 122:f9eeca106725 | 624 | |
Kojto | 122:f9eeca106725 | 625 | /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status |
Kojto | 122:f9eeca106725 | 626 | * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. |
Kojto | 122:f9eeca106725 | 627 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
Kojto | 122:f9eeca106725 | 628 | * power consumption. |
Kojto | 122:f9eeca106725 | 629 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
Kojto | 122:f9eeca106725 | 630 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
Kojto | 122:f9eeca106725 | 631 | * @{ |
Kojto | 122:f9eeca106725 | 632 | */ |
Kojto | 122:f9eeca106725 | 633 | #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET) |
Kojto | 122:f9eeca106725 | 634 | #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET) |
Kojto | 122:f9eeca106725 | 635 | |
Kojto | 122:f9eeca106725 | 636 | #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET) |
Kojto | 122:f9eeca106725 | 637 | #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET) |
Kojto | 122:f9eeca106725 | 638 | /** |
Kojto | 122:f9eeca106725 | 639 | * @} |
Kojto | 122:f9eeca106725 | 640 | */ |
Kojto | 122:f9eeca106725 | 641 | |
Kojto | 122:f9eeca106725 | 642 | /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status |
Kojto | 122:f9eeca106725 | 643 | * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. |
Kojto | 122:f9eeca106725 | 644 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
Kojto | 122:f9eeca106725 | 645 | * power consumption. |
Kojto | 122:f9eeca106725 | 646 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
Kojto | 122:f9eeca106725 | 647 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
Kojto | 122:f9eeca106725 | 648 | * @{ |
Kojto | 122:f9eeca106725 | 649 | */ |
Kojto | 122:f9eeca106725 | 650 | #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET) |
Kojto | 122:f9eeca106725 | 651 | #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET) |
Kojto | 122:f9eeca106725 | 652 | |
Kojto | 122:f9eeca106725 | 653 | #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET) |
Kojto | 122:f9eeca106725 | 654 | #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET) |
Kojto | 122:f9eeca106725 | 655 | /** |
Kojto | 122:f9eeca106725 | 656 | * @} |
Kojto | 122:f9eeca106725 | 657 | */ |
Kojto | 122:f9eeca106725 | 658 | |
Kojto | 122:f9eeca106725 | 659 | /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status |
Kojto | 122:f9eeca106725 | 660 | * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. |
Kojto | 122:f9eeca106725 | 661 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
Kojto | 122:f9eeca106725 | 662 | * power consumption. |
Kojto | 122:f9eeca106725 | 663 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
Kojto | 122:f9eeca106725 | 664 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
Kojto | 122:f9eeca106725 | 665 | * @{ |
Kojto | 122:f9eeca106725 | 666 | */ |
Kojto | 122:f9eeca106725 | 667 | #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET) |
Kojto | 122:f9eeca106725 | 668 | #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET) |
Kojto | 122:f9eeca106725 | 669 | /** |
Kojto | 122:f9eeca106725 | 670 | * @} |
Kojto | 122:f9eeca106725 | 671 | */ |
Kojto | 122:f9eeca106725 | 672 | |
Kojto | 122:f9eeca106725 | 673 | /** @defgroup RCC_HSI_Configuration HSI Configuration |
Kojto | 122:f9eeca106725 | 674 | * @{ |
Kojto | 122:f9eeca106725 | 675 | */ |
Kojto | 122:f9eeca106725 | 676 | |
Kojto | 122:f9eeca106725 | 677 | /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). |
Kojto | 122:f9eeca106725 | 678 | * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. |
Kojto | 122:f9eeca106725 | 679 | * It is used (enabled by hardware) as system clock source after startup |
Kojto | 122:f9eeca106725 | 680 | * from Reset, wakeup from STOP and STANDBY mode, or in case of failure |
Kojto | 122:f9eeca106725 | 681 | * of the HSE used directly or indirectly as system clock (if the Clock |
Kojto | 122:f9eeca106725 | 682 | * Security System CSS is enabled). |
Kojto | 122:f9eeca106725 | 683 | * @note HSI can not be stopped if it is used as system clock source. In this case, |
Kojto | 122:f9eeca106725 | 684 | * you have to select another source of the system clock then stop the HSI. |
Kojto | 122:f9eeca106725 | 685 | * @note After enabling the HSI, the application software should wait on HSIRDY |
Kojto | 122:f9eeca106725 | 686 | * flag to be set indicating that HSI clock is stable and can be used as |
Kojto | 122:f9eeca106725 | 687 | * system clock source. |
Kojto | 122:f9eeca106725 | 688 | * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator |
Kojto | 122:f9eeca106725 | 689 | * clock cycles. |
Kojto | 122:f9eeca106725 | 690 | */ |
Kojto | 122:f9eeca106725 | 691 | #define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION)) |
Kojto | 122:f9eeca106725 | 692 | #define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION)) |
Kojto | 122:f9eeca106725 | 693 | |
Kojto | 122:f9eeca106725 | 694 | /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. |
Kojto | 122:f9eeca106725 | 695 | * @note The calibration is used to compensate for the variations in voltage |
Kojto | 122:f9eeca106725 | 696 | * and temperature that influence the frequency of the internal HSI RC. |
Kojto | 122:f9eeca106725 | 697 | * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value. |
Kojto | 122:f9eeca106725 | 698 | * (default is RCC_HSICALIBRATION_DEFAULT). |
Kojto | 122:f9eeca106725 | 699 | */ |
Kojto | 122:f9eeca106725 | 700 | #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\ |
Kojto | 122:f9eeca106725 | 701 | RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM))) |
Kojto | 122:f9eeca106725 | 702 | /** |
Kojto | 122:f9eeca106725 | 703 | * @} |
Kojto | 122:f9eeca106725 | 704 | */ |
Kojto | 122:f9eeca106725 | 705 | |
Kojto | 122:f9eeca106725 | 706 | /** @defgroup RCC_LSI_Configuration LSI Configuration |
Kojto | 122:f9eeca106725 | 707 | * @{ |
Kojto | 122:f9eeca106725 | 708 | */ |
Kojto | 122:f9eeca106725 | 709 | |
Kojto | 122:f9eeca106725 | 710 | /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). |
Kojto | 122:f9eeca106725 | 711 | * @note After enabling the LSI, the application software should wait on |
Kojto | 122:f9eeca106725 | 712 | * LSIRDY flag to be set indicating that LSI clock is stable and can |
Kojto | 122:f9eeca106725 | 713 | * be used to clock the IWDG and/or the RTC. |
Kojto | 122:f9eeca106725 | 714 | * @note LSI can not be disabled if the IWDG is running. |
Kojto | 122:f9eeca106725 | 715 | * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator |
Kojto | 122:f9eeca106725 | 716 | * clock cycles. |
Kojto | 122:f9eeca106725 | 717 | */ |
Kojto | 122:f9eeca106725 | 718 | #define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION)) |
Kojto | 122:f9eeca106725 | 719 | #define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION)) |
Kojto | 122:f9eeca106725 | 720 | /** |
Kojto | 122:f9eeca106725 | 721 | * @} |
Kojto | 122:f9eeca106725 | 722 | */ |
Kojto | 122:f9eeca106725 | 723 | |
Kojto | 122:f9eeca106725 | 724 | /** @defgroup RCC_HSE_Configuration HSE Configuration |
Kojto | 122:f9eeca106725 | 725 | * @{ |
Kojto | 122:f9eeca106725 | 726 | */ |
Kojto | 122:f9eeca106725 | 727 | /** |
Kojto | 122:f9eeca106725 | 728 | * @brief Macro to configure the External High Speed oscillator (HSE). |
Kojto | 122:f9eeca106725 | 729 | * @note Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not |
Kojto | 122:f9eeca106725 | 730 | * supported by this macro. User should request a transition to HSE Off |
Kojto | 122:f9eeca106725 | 731 | * first and then HSE On or HSE Bypass. |
Kojto | 122:f9eeca106725 | 732 | * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application |
Kojto | 122:f9eeca106725 | 733 | * software should wait on HSERDY flag to be set indicating that HSE clock |
Kojto | 122:f9eeca106725 | 734 | * is stable and can be used to clock the PLL and/or system clock. |
Kojto | 122:f9eeca106725 | 735 | * @note HSE state can not be changed if it is used directly or through the |
Kojto | 122:f9eeca106725 | 736 | * PLL as system clock. In this case, you have to select another source |
Kojto | 122:f9eeca106725 | 737 | * of the system clock then change the HSE state (ex. disable it). |
Kojto | 122:f9eeca106725 | 738 | * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. |
Kojto | 122:f9eeca106725 | 739 | * @note This function reset the CSSON bit, so if the clock security system(CSS) |
Kojto | 122:f9eeca106725 | 740 | * was previously enabled you have to enable it again after calling this |
Kojto | 122:f9eeca106725 | 741 | * function. |
Kojto | 122:f9eeca106725 | 742 | * @param __STATE__: specifies the new state of the HSE. |
Kojto | 122:f9eeca106725 | 743 | * This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 744 | * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after |
Kojto | 122:f9eeca106725 | 745 | * 6 HSE oscillator clock cycles. |
Kojto | 122:f9eeca106725 | 746 | * @arg RCC_HSE_ON: turn ON the HSE oscillator. |
Kojto | 122:f9eeca106725 | 747 | * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. |
Kojto | 122:f9eeca106725 | 748 | */ |
Kojto | 122:f9eeca106725 | 749 | #define __HAL_RCC_HSE_CONFIG(__STATE__) \ |
Kojto | 122:f9eeca106725 | 750 | do { \ |
Kojto | 122:f9eeca106725 | 751 | if ((__STATE__) == RCC_HSE_ON) \ |
Kojto | 122:f9eeca106725 | 752 | { \ |
Kojto | 122:f9eeca106725 | 753 | SET_BIT(RCC->CR, RCC_CR_HSEON); \ |
Kojto | 122:f9eeca106725 | 754 | } \ |
Kojto | 122:f9eeca106725 | 755 | else if ((__STATE__) == RCC_HSE_OFF) \ |
Kojto | 122:f9eeca106725 | 756 | { \ |
Kojto | 122:f9eeca106725 | 757 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ |
Kojto | 122:f9eeca106725 | 758 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
Kojto | 122:f9eeca106725 | 759 | } \ |
Kojto | 122:f9eeca106725 | 760 | else if ((__STATE__) == RCC_HSE_BYPASS) \ |
Kojto | 122:f9eeca106725 | 761 | { \ |
Kojto | 122:f9eeca106725 | 762 | SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
Kojto | 122:f9eeca106725 | 763 | SET_BIT(RCC->CR, RCC_CR_HSEON); \ |
Kojto | 122:f9eeca106725 | 764 | } \ |
Kojto | 122:f9eeca106725 | 765 | else \ |
Kojto | 122:f9eeca106725 | 766 | { \ |
Kojto | 122:f9eeca106725 | 767 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ |
Kojto | 122:f9eeca106725 | 768 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
Kojto | 122:f9eeca106725 | 769 | } \ |
Kojto | 122:f9eeca106725 | 770 | } while(0) |
Kojto | 122:f9eeca106725 | 771 | /** |
Kojto | 122:f9eeca106725 | 772 | * @} |
Kojto | 122:f9eeca106725 | 773 | */ |
Kojto | 122:f9eeca106725 | 774 | |
Kojto | 122:f9eeca106725 | 775 | /** @defgroup RCC_LSE_Configuration LSE Configuration |
Kojto | 122:f9eeca106725 | 776 | * @{ |
Kojto | 122:f9eeca106725 | 777 | */ |
Kojto | 122:f9eeca106725 | 778 | |
Kojto | 122:f9eeca106725 | 779 | /** |
Kojto | 122:f9eeca106725 | 780 | * @brief Macro to configure the External Low Speed oscillator (LSE). |
Kojto | 122:f9eeca106725 | 781 | * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. |
Kojto | 122:f9eeca106725 | 782 | * User should request a transition to LSE Off first and then LSE On or LSE Bypass. |
Kojto | 122:f9eeca106725 | 783 | * @note As the LSE is in the Backup domain and write access is denied to |
Kojto | 122:f9eeca106725 | 784 | * this domain after reset, you have to enable write access using |
Kojto | 122:f9eeca106725 | 785 | * HAL_PWR_EnableBkUpAccess() function before to configure the LSE |
Kojto | 122:f9eeca106725 | 786 | * (to be done once after reset). |
Kojto | 122:f9eeca106725 | 787 | * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application |
Kojto | 122:f9eeca106725 | 788 | * software should wait on LSERDY flag to be set indicating that LSE clock |
Kojto | 122:f9eeca106725 | 789 | * is stable and can be used to clock the RTC. |
Kojto | 122:f9eeca106725 | 790 | * @param __STATE__: specifies the new state of the LSE. |
Kojto | 122:f9eeca106725 | 791 | * This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 792 | * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after |
Kojto | 122:f9eeca106725 | 793 | * 6 LSE oscillator clock cycles. |
Kojto | 122:f9eeca106725 | 794 | * @arg RCC_LSE_ON: turn ON the LSE oscillator. |
Kojto | 122:f9eeca106725 | 795 | * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. |
Kojto | 122:f9eeca106725 | 796 | */ |
Kojto | 122:f9eeca106725 | 797 | #define __HAL_RCC_LSE_CONFIG(__STATE__) \ |
Kojto | 122:f9eeca106725 | 798 | do { \ |
Kojto | 122:f9eeca106725 | 799 | if((__STATE__) == RCC_LSE_ON) \ |
Kojto | 122:f9eeca106725 | 800 | { \ |
Kojto | 122:f9eeca106725 | 801 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
Kojto | 122:f9eeca106725 | 802 | } \ |
Kojto | 122:f9eeca106725 | 803 | else if((__STATE__) == RCC_LSE_OFF) \ |
Kojto | 122:f9eeca106725 | 804 | { \ |
Kojto | 122:f9eeca106725 | 805 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
Kojto | 122:f9eeca106725 | 806 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
Kojto | 122:f9eeca106725 | 807 | } \ |
Kojto | 122:f9eeca106725 | 808 | else if((__STATE__) == RCC_LSE_BYPASS) \ |
Kojto | 122:f9eeca106725 | 809 | { \ |
Kojto | 122:f9eeca106725 | 810 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
Kojto | 122:f9eeca106725 | 811 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
Kojto | 122:f9eeca106725 | 812 | } \ |
Kojto | 122:f9eeca106725 | 813 | else \ |
Kojto | 122:f9eeca106725 | 814 | { \ |
Kojto | 122:f9eeca106725 | 815 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
Kojto | 122:f9eeca106725 | 816 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
Kojto | 122:f9eeca106725 | 817 | } \ |
Kojto | 122:f9eeca106725 | 818 | } while(0) |
Kojto | 122:f9eeca106725 | 819 | /** |
Kojto | 122:f9eeca106725 | 820 | * @} |
Kojto | 122:f9eeca106725 | 821 | */ |
Kojto | 122:f9eeca106725 | 822 | |
Kojto | 122:f9eeca106725 | 823 | /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration |
Kojto | 122:f9eeca106725 | 824 | * @{ |
Kojto | 122:f9eeca106725 | 825 | */ |
Kojto | 122:f9eeca106725 | 826 | |
Kojto | 122:f9eeca106725 | 827 | /** @brief Macros to enable or disable the RTC clock. |
Kojto | 122:f9eeca106725 | 828 | * @note These macros must be used only after the RTC clock source was selected. |
Kojto | 122:f9eeca106725 | 829 | */ |
Kojto | 122:f9eeca106725 | 830 | #define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN)) |
Kojto | 122:f9eeca106725 | 831 | #define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN)) |
Kojto | 122:f9eeca106725 | 832 | |
Kojto | 122:f9eeca106725 | 833 | /** @brief Macros to configure the RTC clock (RTCCLK). |
Kojto | 122:f9eeca106725 | 834 | * @note As the RTC clock configuration bits are in the Backup domain and write |
Kojto | 122:f9eeca106725 | 835 | * access is denied to this domain after reset, you have to enable write |
Kojto | 122:f9eeca106725 | 836 | * access using the Power Backup Access macro before to configure |
Kojto | 122:f9eeca106725 | 837 | * the RTC clock source (to be done once after reset). |
Kojto | 122:f9eeca106725 | 838 | * @note Once the RTC clock is configured it can't be changed unless the |
Kojto | 122:f9eeca106725 | 839 | * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by |
Kojto | 122:f9eeca106725 | 840 | * a Power On Reset (POR). |
Kojto | 122:f9eeca106725 | 841 | * @param __RTCCLKSource__: specifies the RTC clock source. |
Kojto | 122:f9eeca106725 | 842 | * This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 843 | * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. |
Kojto | 122:f9eeca106725 | 844 | * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. |
Kojto | 122:f9eeca106725 | 845 | * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected |
Kojto | 122:f9eeca106725 | 846 | * as RTC clock, where x:[2,31] |
Kojto | 122:f9eeca106725 | 847 | * @note If the LSE or LSI is used as RTC clock source, the RTC continues to |
Kojto | 122:f9eeca106725 | 848 | * work in STOP and STANDBY modes, and can be used as wakeup source. |
Kojto | 122:f9eeca106725 | 849 | * However, when the HSE clock is used as RTC clock source, the RTC |
Kojto | 122:f9eeca106725 | 850 | * cannot be used in STOP and STANDBY modes. |
Kojto | 122:f9eeca106725 | 851 | * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as |
Kojto | 122:f9eeca106725 | 852 | * RTC clock source). |
Kojto | 122:f9eeca106725 | 853 | */ |
Kojto | 122:f9eeca106725 | 854 | #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ |
Kojto | 122:f9eeca106725 | 855 | MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) |
Kojto | 122:f9eeca106725 | 856 | |
Kojto | 122:f9eeca106725 | 857 | #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ |
Kojto | 122:f9eeca106725 | 858 | RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \ |
Kojto | 122:f9eeca106725 | 859 | } while (0) |
Kojto | 122:f9eeca106725 | 860 | |
Kojto | 122:f9eeca106725 | 861 | /** @brief Macros to force or release the Backup domain reset. |
Kojto | 122:f9eeca106725 | 862 | * @note This function resets the RTC peripheral (including the backup registers) |
Kojto | 122:f9eeca106725 | 863 | * and the RTC clock source selection in RCC_CSR register. |
Kojto | 122:f9eeca106725 | 864 | * @note The BKPSRAM is not affected by this reset. |
Kojto | 122:f9eeca106725 | 865 | */ |
Kojto | 122:f9eeca106725 | 866 | #define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST)) |
Kojto | 122:f9eeca106725 | 867 | #define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST)) |
Kojto | 122:f9eeca106725 | 868 | /** |
Kojto | 122:f9eeca106725 | 869 | * @} |
Kojto | 122:f9eeca106725 | 870 | */ |
Kojto | 122:f9eeca106725 | 871 | |
Kojto | 122:f9eeca106725 | 872 | /** @defgroup RCC_PLL_Configuration PLL Configuration |
Kojto | 122:f9eeca106725 | 873 | * @{ |
Kojto | 122:f9eeca106725 | 874 | */ |
Kojto | 122:f9eeca106725 | 875 | |
Kojto | 122:f9eeca106725 | 876 | /** @brief Macros to enable or disable the main PLL. |
Kojto | 122:f9eeca106725 | 877 | * @note After enabling the main PLL, the application software should wait on |
Kojto | 122:f9eeca106725 | 878 | * PLLRDY flag to be set indicating that PLL clock is stable and can |
Kojto | 122:f9eeca106725 | 879 | * be used as system clock source. |
Kojto | 122:f9eeca106725 | 880 | * @note The main PLL can not be disabled if it is used as system clock source |
Kojto | 122:f9eeca106725 | 881 | * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. |
Kojto | 122:f9eeca106725 | 882 | */ |
Kojto | 122:f9eeca106725 | 883 | #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) |
Kojto | 122:f9eeca106725 | 884 | #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) |
Kojto | 122:f9eeca106725 | 885 | |
Kojto | 122:f9eeca106725 | 886 | /** @brief Macro to configure the PLL clock source. |
Kojto | 122:f9eeca106725 | 887 | * @note This function must be used only when the main PLL is disabled. |
Kojto | 122:f9eeca106725 | 888 | * @param __PLLSOURCE__: specifies the PLL entry clock source. |
Kojto | 122:f9eeca106725 | 889 | * This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 890 | * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry |
Kojto | 122:f9eeca106725 | 891 | * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry |
Kojto | 122:f9eeca106725 | 892 | * |
Kojto | 122:f9eeca106725 | 893 | */ |
Kojto | 122:f9eeca106725 | 894 | #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) |
Kojto | 122:f9eeca106725 | 895 | |
Kojto | 122:f9eeca106725 | 896 | /** @brief Macro to configure the PLL multiplication factor. |
Kojto | 122:f9eeca106725 | 897 | * @note This function must be used only when the main PLL is disabled. |
Kojto | 122:f9eeca106725 | 898 | * @param __PLLM__: specifies the division factor for PLL VCO input clock |
Kojto | 122:f9eeca106725 | 899 | * This parameter must be a number between Min_Data = 2 and Max_Data = 63. |
Kojto | 122:f9eeca106725 | 900 | * @note You have to set the PLLM parameter correctly to ensure that the VCO input |
Kojto | 122:f9eeca106725 | 901 | * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency |
Kojto | 122:f9eeca106725 | 902 | * of 2 MHz to limit PLL jitter. |
Kojto | 122:f9eeca106725 | 903 | * |
Kojto | 122:f9eeca106725 | 904 | */ |
Kojto | 122:f9eeca106725 | 905 | #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) |
Kojto | 122:f9eeca106725 | 906 | /** |
Kojto | 122:f9eeca106725 | 907 | * @} |
Kojto | 122:f9eeca106725 | 908 | */ |
Kojto | 122:f9eeca106725 | 909 | |
Kojto | 122:f9eeca106725 | 910 | /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration |
Kojto | 122:f9eeca106725 | 911 | * @{ |
Kojto | 122:f9eeca106725 | 912 | */ |
Kojto | 122:f9eeca106725 | 913 | |
Kojto | 122:f9eeca106725 | 914 | /** @brief Macro to configure the I2S clock source (I2SCLK). |
Kojto | 122:f9eeca106725 | 915 | * @note This function must be called before enabling the I2S APB clock. |
Kojto | 122:f9eeca106725 | 916 | * @param __SOURCE__: specifies the I2S clock source. |
Kojto | 122:f9eeca106725 | 917 | * This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 918 | * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. |
Kojto | 122:f9eeca106725 | 919 | * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin |
Kojto | 122:f9eeca106725 | 920 | * used as I2S clock source. |
Kojto | 122:f9eeca106725 | 921 | */ |
Kojto | 122:f9eeca106725 | 922 | #define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \ |
Kojto | 122:f9eeca106725 | 923 | RCC->CFGR |= (__SOURCE__); \ |
Kojto | 122:f9eeca106725 | 924 | }while(0) |
Kojto | 122:f9eeca106725 | 925 | |
Kojto | 122:f9eeca106725 | 926 | /** @brief Macros to enable or disable the PLLI2S. |
Kojto | 122:f9eeca106725 | 927 | * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. |
Kojto | 122:f9eeca106725 | 928 | */ |
Kojto | 122:f9eeca106725 | 929 | #define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON)) |
Kojto | 122:f9eeca106725 | 930 | #define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON)) |
Kojto | 122:f9eeca106725 | 931 | /** |
Kojto | 122:f9eeca106725 | 932 | * @} |
Kojto | 122:f9eeca106725 | 933 | */ |
Kojto | 122:f9eeca106725 | 934 | |
Kojto | 122:f9eeca106725 | 935 | /** @defgroup RCC_Get_Clock_source Get Clock source |
Kojto | 122:f9eeca106725 | 936 | * @{ |
Kojto | 122:f9eeca106725 | 937 | */ |
Kojto | 122:f9eeca106725 | 938 | /** |
Kojto | 122:f9eeca106725 | 939 | * @brief Macro to configure the system clock source. |
Kojto | 122:f9eeca106725 | 940 | * @param __RCC_SYSCLKSOURCE__: specifies the system clock source. |
Kojto | 122:f9eeca106725 | 941 | * This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 942 | * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. |
Kojto | 122:f9eeca106725 | 943 | * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. |
Kojto | 122:f9eeca106725 | 944 | * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. |
Kojto | 122:f9eeca106725 | 945 | */ |
Kojto | 122:f9eeca106725 | 946 | #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) |
Kojto | 122:f9eeca106725 | 947 | |
Kojto | 122:f9eeca106725 | 948 | /** @brief Macro to get the clock source used as system clock. |
Kojto | 122:f9eeca106725 | 949 | * @retval The clock source used as system clock. The returned value can be one |
Kojto | 122:f9eeca106725 | 950 | * of the following: |
Kojto | 122:f9eeca106725 | 951 | * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. |
Kojto | 122:f9eeca106725 | 952 | * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. |
Kojto | 122:f9eeca106725 | 953 | * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. |
Kojto | 122:f9eeca106725 | 954 | */ |
Kojto | 122:f9eeca106725 | 955 | #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) |
Kojto | 122:f9eeca106725 | 956 | |
Kojto | 122:f9eeca106725 | 957 | /** |
Kojto | 122:f9eeca106725 | 958 | * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability. |
Kojto | 122:f9eeca106725 | 959 | * @note As the LSE is in the Backup domain and write access is denied to |
Kojto | 122:f9eeca106725 | 960 | * this domain after reset, you have to enable write access using |
Kojto | 122:f9eeca106725 | 961 | * HAL_PWR_EnableBkUpAccess() function before to configure the LSE |
Kojto | 122:f9eeca106725 | 962 | * (to be done once after reset). |
Kojto | 122:f9eeca106725 | 963 | * @param __RCC_LSEDRIVE__: specifies the new state of the LSE drive capability. |
Kojto | 122:f9eeca106725 | 964 | * This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 965 | * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability. |
Kojto | 122:f9eeca106725 | 966 | * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. |
Kojto | 122:f9eeca106725 | 967 | * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. |
Kojto | 122:f9eeca106725 | 968 | * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. |
Kojto | 122:f9eeca106725 | 969 | * @retval None |
Kojto | 122:f9eeca106725 | 970 | */ |
Kojto | 122:f9eeca106725 | 971 | #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \ |
Kojto | 122:f9eeca106725 | 972 | (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) |
Kojto | 122:f9eeca106725 | 973 | |
Kojto | 122:f9eeca106725 | 974 | /** @brief Macro to get the oscillator used as PLL clock source. |
Kojto | 122:f9eeca106725 | 975 | * @retval The oscillator used as PLL clock source. The returned value can be one |
Kojto | 122:f9eeca106725 | 976 | * of the following: |
Kojto | 122:f9eeca106725 | 977 | * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. |
Kojto | 122:f9eeca106725 | 978 | * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. |
Kojto | 122:f9eeca106725 | 979 | */ |
Kojto | 122:f9eeca106725 | 980 | #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) |
Kojto | 122:f9eeca106725 | 981 | /** |
Kojto | 122:f9eeca106725 | 982 | * @} |
Kojto | 122:f9eeca106725 | 983 | */ |
Kojto | 122:f9eeca106725 | 984 | |
Kojto | 122:f9eeca106725 | 985 | /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config |
Kojto | 122:f9eeca106725 | 986 | * @{ |
Kojto | 122:f9eeca106725 | 987 | */ |
Kojto | 122:f9eeca106725 | 988 | |
Kojto | 122:f9eeca106725 | 989 | /** @brief Macro to configure the MCO1 clock. |
Kojto | 122:f9eeca106725 | 990 | * @param __MCOCLKSOURCE__ specifies the MCO clock source. |
Kojto | 122:f9eeca106725 | 991 | * This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 992 | * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source |
Kojto | 122:f9eeca106725 | 993 | * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source |
Kojto | 122:f9eeca106725 | 994 | * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source |
Kojto | 122:f9eeca106725 | 995 | * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source |
Kojto | 122:f9eeca106725 | 996 | * @param __MCODIV__ specifies the MCO clock prescaler. |
Kojto | 122:f9eeca106725 | 997 | * This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 998 | * @arg RCC_MCODIV_1: no division applied to MCOx clock |
Kojto | 122:f9eeca106725 | 999 | * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock |
Kojto | 122:f9eeca106725 | 1000 | * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock |
Kojto | 122:f9eeca106725 | 1001 | * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock |
Kojto | 122:f9eeca106725 | 1002 | * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock |
Kojto | 122:f9eeca106725 | 1003 | */ |
Kojto | 122:f9eeca106725 | 1004 | |
Kojto | 122:f9eeca106725 | 1005 | #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ |
Kojto | 122:f9eeca106725 | 1006 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) |
Kojto | 122:f9eeca106725 | 1007 | |
Kojto | 122:f9eeca106725 | 1008 | /** @brief Macro to configure the MCO2 clock. |
Kojto | 122:f9eeca106725 | 1009 | * @param __MCOCLKSOURCE__ specifies the MCO clock source. |
Kojto | 122:f9eeca106725 | 1010 | * This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 1011 | * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source |
Kojto | 122:f9eeca106725 | 1012 | * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source |
Kojto | 122:f9eeca106725 | 1013 | * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source |
Kojto | 122:f9eeca106725 | 1014 | * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source |
Kojto | 122:f9eeca106725 | 1015 | * @param __MCODIV__ specifies the MCO clock prescaler. |
Kojto | 122:f9eeca106725 | 1016 | * This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 1017 | * @arg RCC_MCODIV_1: no division applied to MCOx clock |
Kojto | 122:f9eeca106725 | 1018 | * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock |
Kojto | 122:f9eeca106725 | 1019 | * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock |
Kojto | 122:f9eeca106725 | 1020 | * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock |
Kojto | 122:f9eeca106725 | 1021 | * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock |
Kojto | 122:f9eeca106725 | 1022 | */ |
Kojto | 122:f9eeca106725 | 1023 | |
Kojto | 122:f9eeca106725 | 1024 | #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ |
Kojto | 122:f9eeca106725 | 1025 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3))); |
Kojto | 122:f9eeca106725 | 1026 | /** |
Kojto | 122:f9eeca106725 | 1027 | * @} |
Kojto | 122:f9eeca106725 | 1028 | */ |
Kojto | 122:f9eeca106725 | 1029 | |
Kojto | 122:f9eeca106725 | 1030 | /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management |
Kojto | 122:f9eeca106725 | 1031 | * @brief macros to manage the specified RCC Flags and interrupts. |
Kojto | 122:f9eeca106725 | 1032 | * @{ |
Kojto | 122:f9eeca106725 | 1033 | */ |
Kojto | 122:f9eeca106725 | 1034 | |
Kojto | 122:f9eeca106725 | 1035 | /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable |
Kojto | 122:f9eeca106725 | 1036 | * the selected interrupts). |
Kojto | 122:f9eeca106725 | 1037 | * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. |
Kojto | 122:f9eeca106725 | 1038 | * This parameter can be any combination of the following values: |
Kojto | 122:f9eeca106725 | 1039 | * @arg RCC_IT_LSIRDY: LSI ready interrupt. |
Kojto | 122:f9eeca106725 | 1040 | * @arg RCC_IT_LSERDY: LSE ready interrupt. |
Kojto | 122:f9eeca106725 | 1041 | * @arg RCC_IT_HSIRDY: HSI ready interrupt. |
Kojto | 122:f9eeca106725 | 1042 | * @arg RCC_IT_HSERDY: HSE ready interrupt. |
Kojto | 122:f9eeca106725 | 1043 | * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. |
Kojto | 122:f9eeca106725 | 1044 | * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. |
Kojto | 122:f9eeca106725 | 1045 | */ |
Kojto | 122:f9eeca106725 | 1046 | #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) |
Kojto | 122:f9eeca106725 | 1047 | |
Kojto | 122:f9eeca106725 | 1048 | /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable |
Kojto | 122:f9eeca106725 | 1049 | * the selected interrupts). |
Kojto | 122:f9eeca106725 | 1050 | * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. |
Kojto | 122:f9eeca106725 | 1051 | * This parameter can be any combination of the following values: |
Kojto | 122:f9eeca106725 | 1052 | * @arg RCC_IT_LSIRDY: LSI ready interrupt. |
Kojto | 122:f9eeca106725 | 1053 | * @arg RCC_IT_LSERDY: LSE ready interrupt. |
Kojto | 122:f9eeca106725 | 1054 | * @arg RCC_IT_HSIRDY: HSI ready interrupt. |
Kojto | 122:f9eeca106725 | 1055 | * @arg RCC_IT_HSERDY: HSE ready interrupt. |
Kojto | 122:f9eeca106725 | 1056 | * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. |
Kojto | 122:f9eeca106725 | 1057 | * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. |
Kojto | 122:f9eeca106725 | 1058 | */ |
Kojto | 122:f9eeca106725 | 1059 | #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) |
Kojto | 122:f9eeca106725 | 1060 | |
Kojto | 122:f9eeca106725 | 1061 | /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] |
Kojto | 122:f9eeca106725 | 1062 | * bits to clear the selected interrupt pending bits. |
Kojto | 122:f9eeca106725 | 1063 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
Kojto | 122:f9eeca106725 | 1064 | * This parameter can be any combination of the following values: |
Kojto | 122:f9eeca106725 | 1065 | * @arg RCC_IT_LSIRDY: LSI ready interrupt. |
Kojto | 122:f9eeca106725 | 1066 | * @arg RCC_IT_LSERDY: LSE ready interrupt. |
Kojto | 122:f9eeca106725 | 1067 | * @arg RCC_IT_HSIRDY: HSI ready interrupt. |
Kojto | 122:f9eeca106725 | 1068 | * @arg RCC_IT_HSERDY: HSE ready interrupt. |
Kojto | 122:f9eeca106725 | 1069 | * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. |
Kojto | 122:f9eeca106725 | 1070 | * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. |
Kojto | 122:f9eeca106725 | 1071 | * @arg RCC_IT_CSS: Clock Security System interrupt |
Kojto | 122:f9eeca106725 | 1072 | */ |
Kojto | 122:f9eeca106725 | 1073 | #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) |
Kojto | 122:f9eeca106725 | 1074 | |
Kojto | 122:f9eeca106725 | 1075 | /** @brief Check the RCC's interrupt has occurred or not. |
Kojto | 122:f9eeca106725 | 1076 | * @param __INTERRUPT__: specifies the RCC interrupt source to check. |
Kojto | 122:f9eeca106725 | 1077 | * This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 1078 | * @arg RCC_IT_LSIRDY: LSI ready interrupt. |
Kojto | 122:f9eeca106725 | 1079 | * @arg RCC_IT_LSERDY: LSE ready interrupt. |
Kojto | 122:f9eeca106725 | 1080 | * @arg RCC_IT_HSIRDY: HSI ready interrupt. |
Kojto | 122:f9eeca106725 | 1081 | * @arg RCC_IT_HSERDY: HSE ready interrupt. |
Kojto | 122:f9eeca106725 | 1082 | * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. |
Kojto | 122:f9eeca106725 | 1083 | * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. |
Kojto | 122:f9eeca106725 | 1084 | * @arg RCC_IT_CSS: Clock Security System interrupt |
Kojto | 122:f9eeca106725 | 1085 | * @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
Kojto | 122:f9eeca106725 | 1086 | */ |
Kojto | 122:f9eeca106725 | 1087 | #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) |
Kojto | 122:f9eeca106725 | 1088 | |
Kojto | 122:f9eeca106725 | 1089 | /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, |
Kojto | 122:f9eeca106725 | 1090 | * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. |
Kojto | 122:f9eeca106725 | 1091 | */ |
Kojto | 122:f9eeca106725 | 1092 | #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) |
Kojto | 122:f9eeca106725 | 1093 | |
Kojto | 122:f9eeca106725 | 1094 | /** @brief Check RCC flag is set or not. |
Kojto | 122:f9eeca106725 | 1095 | * @param __FLAG__: specifies the flag to check. |
Kojto | 122:f9eeca106725 | 1096 | * This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 1097 | * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. |
Kojto | 122:f9eeca106725 | 1098 | * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. |
Kojto | 122:f9eeca106725 | 1099 | * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. |
Kojto | 122:f9eeca106725 | 1100 | * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready. |
Kojto | 122:f9eeca106725 | 1101 | * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. |
Kojto | 122:f9eeca106725 | 1102 | * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. |
Kojto | 122:f9eeca106725 | 1103 | * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. |
Kojto | 122:f9eeca106725 | 1104 | * @arg RCC_FLAG_PINRST: Pin reset. |
Kojto | 122:f9eeca106725 | 1105 | * @arg RCC_FLAG_PORRST: POR/PDR reset. |
Kojto | 122:f9eeca106725 | 1106 | * @arg RCC_FLAG_SFTRST: Software reset. |
Kojto | 122:f9eeca106725 | 1107 | * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. |
Kojto | 122:f9eeca106725 | 1108 | * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. |
Kojto | 122:f9eeca106725 | 1109 | * @arg RCC_FLAG_LPWRRST: Low Power reset. |
Kojto | 122:f9eeca106725 | 1110 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
Kojto | 122:f9eeca106725 | 1111 | */ |
Kojto | 122:f9eeca106725 | 1112 | #define RCC_FLAG_MASK ((uint8_t)0x1F) |
Kojto | 122:f9eeca106725 | 1113 | #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0) |
Kojto | 122:f9eeca106725 | 1114 | |
Kojto | 122:f9eeca106725 | 1115 | /** |
Kojto | 122:f9eeca106725 | 1116 | * @} |
Kojto | 122:f9eeca106725 | 1117 | */ |
Kojto | 122:f9eeca106725 | 1118 | |
Kojto | 122:f9eeca106725 | 1119 | /** |
Kojto | 122:f9eeca106725 | 1120 | * @} |
Kojto | 122:f9eeca106725 | 1121 | */ |
Kojto | 122:f9eeca106725 | 1122 | |
Kojto | 122:f9eeca106725 | 1123 | /* Include RCC HAL Extension module */ |
Kojto | 122:f9eeca106725 | 1124 | #include "stm32f7xx_hal_rcc_ex.h" |
Kojto | 122:f9eeca106725 | 1125 | |
Kojto | 122:f9eeca106725 | 1126 | /* Exported functions --------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 1127 | /** @addtogroup RCC_Exported_Functions |
Kojto | 122:f9eeca106725 | 1128 | * @{ |
Kojto | 122:f9eeca106725 | 1129 | */ |
Kojto | 122:f9eeca106725 | 1130 | |
Kojto | 122:f9eeca106725 | 1131 | /** @addtogroup RCC_Exported_Functions_Group1 |
Kojto | 122:f9eeca106725 | 1132 | * @{ |
Kojto | 122:f9eeca106725 | 1133 | */ |
Kojto | 122:f9eeca106725 | 1134 | /* Initialization and de-initialization functions ******************************/ |
Kojto | 122:f9eeca106725 | 1135 | void HAL_RCC_DeInit(void); |
Kojto | 122:f9eeca106725 | 1136 | HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
Kojto | 122:f9eeca106725 | 1137 | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); |
Kojto | 122:f9eeca106725 | 1138 | /** |
Kojto | 122:f9eeca106725 | 1139 | * @} |
Kojto | 122:f9eeca106725 | 1140 | */ |
Kojto | 122:f9eeca106725 | 1141 | |
Kojto | 122:f9eeca106725 | 1142 | /** @addtogroup RCC_Exported_Functions_Group2 |
Kojto | 122:f9eeca106725 | 1143 | * @{ |
Kojto | 122:f9eeca106725 | 1144 | */ |
Kojto | 122:f9eeca106725 | 1145 | /* Peripheral Control functions ************************************************/ |
Kojto | 122:f9eeca106725 | 1146 | void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); |
Kojto | 122:f9eeca106725 | 1147 | void HAL_RCC_EnableCSS(void); |
Kojto | 122:f9eeca106725 | 1148 | void HAL_RCC_DisableCSS(void); |
Kojto | 122:f9eeca106725 | 1149 | uint32_t HAL_RCC_GetSysClockFreq(void); |
Kojto | 122:f9eeca106725 | 1150 | uint32_t HAL_RCC_GetHCLKFreq(void); |
Kojto | 122:f9eeca106725 | 1151 | uint32_t HAL_RCC_GetPCLK1Freq(void); |
Kojto | 122:f9eeca106725 | 1152 | uint32_t HAL_RCC_GetPCLK2Freq(void); |
Kojto | 122:f9eeca106725 | 1153 | void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
Kojto | 122:f9eeca106725 | 1154 | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); |
Kojto | 122:f9eeca106725 | 1155 | |
Kojto | 122:f9eeca106725 | 1156 | /* CSS NMI IRQ handler */ |
Kojto | 122:f9eeca106725 | 1157 | void HAL_RCC_NMI_IRQHandler(void); |
Kojto | 122:f9eeca106725 | 1158 | |
Kojto | 122:f9eeca106725 | 1159 | /* User Callbacks in non blocking mode (IT mode) */ |
Kojto | 122:f9eeca106725 | 1160 | void HAL_RCC_CSSCallback(void); |
Kojto | 122:f9eeca106725 | 1161 | /** |
Kojto | 122:f9eeca106725 | 1162 | * @} |
Kojto | 122:f9eeca106725 | 1163 | */ |
Kojto | 122:f9eeca106725 | 1164 | |
Kojto | 122:f9eeca106725 | 1165 | /** |
Kojto | 122:f9eeca106725 | 1166 | * @} |
Kojto | 122:f9eeca106725 | 1167 | */ |
Kojto | 122:f9eeca106725 | 1168 | |
Kojto | 122:f9eeca106725 | 1169 | /* Private types -------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 1170 | /* Private variables ---------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 1171 | /* Private constants ---------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 1172 | /** @defgroup RCC_Private_Constants RCC Private Constants |
Kojto | 122:f9eeca106725 | 1173 | * @{ |
Kojto | 122:f9eeca106725 | 1174 | */ |
Kojto | 122:f9eeca106725 | 1175 | #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT |
Kojto | 122:f9eeca106725 | 1176 | #define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ |
Kojto | 122:f9eeca106725 | 1177 | #define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ |
Kojto | 122:f9eeca106725 | 1178 | #define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ |
Kojto | 122:f9eeca106725 | 1179 | #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ |
Kojto | 122:f9eeca106725 | 1180 | |
Kojto | 122:f9eeca106725 | 1181 | /** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias |
Kojto | 122:f9eeca106725 | 1182 | * @brief RCC registers bit address alias |
Kojto | 122:f9eeca106725 | 1183 | * @{ |
Kojto | 122:f9eeca106725 | 1184 | */ |
Kojto | 122:f9eeca106725 | 1185 | /* CIR register byte 2 (Bits[15:8]) base address */ |
Kojto | 122:f9eeca106725 | 1186 | #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) |
Kojto | 122:f9eeca106725 | 1187 | |
Kojto | 122:f9eeca106725 | 1188 | /* CIR register byte 3 (Bits[23:16]) base address */ |
Kojto | 122:f9eeca106725 | 1189 | #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) |
Kojto | 122:f9eeca106725 | 1190 | |
Kojto | 122:f9eeca106725 | 1191 | #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) |
Kojto | 122:f9eeca106725 | 1192 | #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT |
Kojto | 122:f9eeca106725 | 1193 | /** |
Kojto | 122:f9eeca106725 | 1194 | * @} |
Kojto | 122:f9eeca106725 | 1195 | */ |
Kojto | 122:f9eeca106725 | 1196 | /** |
Kojto | 122:f9eeca106725 | 1197 | * @} |
Kojto | 122:f9eeca106725 | 1198 | */ |
Kojto | 122:f9eeca106725 | 1199 | |
Kojto | 122:f9eeca106725 | 1200 | /* Private macros ------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 1201 | /** @addtogroup RCC_Private_Macros RCC Private Macros |
Kojto | 122:f9eeca106725 | 1202 | * @{ |
Kojto | 122:f9eeca106725 | 1203 | */ |
Kojto | 122:f9eeca106725 | 1204 | |
Kojto | 122:f9eeca106725 | 1205 | /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters |
Kojto | 122:f9eeca106725 | 1206 | * @{ |
Kojto | 122:f9eeca106725 | 1207 | */ |
Kojto | 122:f9eeca106725 | 1208 | #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15) |
Kojto | 122:f9eeca106725 | 1209 | |
Kojto | 122:f9eeca106725 | 1210 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ |
Kojto | 122:f9eeca106725 | 1211 | ((HSE) == RCC_HSE_BYPASS)) |
Kojto | 122:f9eeca106725 | 1212 | |
Kojto | 122:f9eeca106725 | 1213 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ |
Kojto | 122:f9eeca106725 | 1214 | ((LSE) == RCC_LSE_BYPASS)) |
Kojto | 122:f9eeca106725 | 1215 | |
Kojto | 122:f9eeca106725 | 1216 | #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) |
Kojto | 122:f9eeca106725 | 1217 | |
Kojto | 122:f9eeca106725 | 1218 | #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) |
Kojto | 122:f9eeca106725 | 1219 | |
Kojto | 122:f9eeca106725 | 1220 | #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) |
Kojto | 122:f9eeca106725 | 1221 | |
Kojto | 122:f9eeca106725 | 1222 | #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ |
Kojto | 122:f9eeca106725 | 1223 | ((SOURCE) == RCC_PLLSOURCE_HSE)) |
Kojto | 122:f9eeca106725 | 1224 | |
Kojto | 122:f9eeca106725 | 1225 | #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ |
Kojto | 122:f9eeca106725 | 1226 | ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ |
Kojto | 122:f9eeca106725 | 1227 | ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) |
Kojto | 122:f9eeca106725 | 1228 | #define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63)) |
Kojto | 122:f9eeca106725 | 1229 | |
Kojto | 122:f9eeca106725 | 1230 | #define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) |
Kojto | 122:f9eeca106725 | 1231 | |
Kojto | 122:f9eeca106725 | 1232 | #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \ |
Kojto | 122:f9eeca106725 | 1233 | ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8)) |
Kojto | 122:f9eeca106725 | 1234 | #define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) |
Kojto | 122:f9eeca106725 | 1235 | |
Kojto | 122:f9eeca106725 | 1236 | #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ |
Kojto | 122:f9eeca106725 | 1237 | ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ |
Kojto | 122:f9eeca106725 | 1238 | ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ |
Kojto | 122:f9eeca106725 | 1239 | ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ |
Kojto | 122:f9eeca106725 | 1240 | ((HCLK) == RCC_SYSCLK_DIV512)) |
Kojto | 122:f9eeca106725 | 1241 | |
Kojto | 122:f9eeca106725 | 1242 | #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15)) |
Kojto | 122:f9eeca106725 | 1243 | |
Kojto | 122:f9eeca106725 | 1244 | #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ |
Kojto | 122:f9eeca106725 | 1245 | ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ |
Kojto | 122:f9eeca106725 | 1246 | ((PCLK) == RCC_HCLK_DIV16)) |
Kojto | 122:f9eeca106725 | 1247 | |
Kojto | 122:f9eeca106725 | 1248 | #define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2)) |
Kojto | 122:f9eeca106725 | 1249 | |
Kojto | 122:f9eeca106725 | 1250 | |
Kojto | 122:f9eeca106725 | 1251 | #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ |
Kojto | 122:f9eeca106725 | 1252 | ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) |
Kojto | 122:f9eeca106725 | 1253 | |
Kojto | 122:f9eeca106725 | 1254 | #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ |
Kojto | 122:f9eeca106725 | 1255 | ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) |
Kojto | 122:f9eeca106725 | 1256 | |
Kojto | 122:f9eeca106725 | 1257 | #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ |
Kojto | 122:f9eeca106725 | 1258 | ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ |
Kojto | 122:f9eeca106725 | 1259 | ((DIV) == RCC_MCODIV_5)) |
Kojto | 122:f9eeca106725 | 1260 | #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) |
Kojto | 122:f9eeca106725 | 1261 | |
Kojto | 122:f9eeca106725 | 1262 | #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ |
Kojto | 122:f9eeca106725 | 1263 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ |
Kojto | 122:f9eeca106725 | 1264 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ |
Kojto | 122:f9eeca106725 | 1265 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ |
Kojto | 122:f9eeca106725 | 1266 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ |
Kojto | 122:f9eeca106725 | 1267 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ |
Kojto | 122:f9eeca106725 | 1268 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ |
Kojto | 122:f9eeca106725 | 1269 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ |
Kojto | 122:f9eeca106725 | 1270 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ |
Kojto | 122:f9eeca106725 | 1271 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ |
Kojto | 122:f9eeca106725 | 1272 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ |
Kojto | 122:f9eeca106725 | 1273 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ |
Kojto | 122:f9eeca106725 | 1274 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ |
Kojto | 122:f9eeca106725 | 1275 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ |
Kojto | 122:f9eeca106725 | 1276 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ |
Kojto | 122:f9eeca106725 | 1277 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31)) |
Kojto | 122:f9eeca106725 | 1278 | |
Kojto | 122:f9eeca106725 | 1279 | |
Kojto | 122:f9eeca106725 | 1280 | #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \ |
Kojto | 122:f9eeca106725 | 1281 | ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \ |
Kojto | 122:f9eeca106725 | 1282 | ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \ |
Kojto | 122:f9eeca106725 | 1283 | ((DRIVE) == RCC_LSEDRIVE_HIGH)) |
Kojto | 122:f9eeca106725 | 1284 | /** |
Kojto | 122:f9eeca106725 | 1285 | * @} |
Kojto | 122:f9eeca106725 | 1286 | */ |
Kojto | 122:f9eeca106725 | 1287 | |
Kojto | 122:f9eeca106725 | 1288 | /** |
Kojto | 122:f9eeca106725 | 1289 | * @} |
Kojto | 122:f9eeca106725 | 1290 | */ |
Kojto | 122:f9eeca106725 | 1291 | |
Kojto | 122:f9eeca106725 | 1292 | /** |
Kojto | 122:f9eeca106725 | 1293 | * @} |
Kojto | 122:f9eeca106725 | 1294 | */ |
Kojto | 122:f9eeca106725 | 1295 | |
Kojto | 122:f9eeca106725 | 1296 | /** |
Kojto | 122:f9eeca106725 | 1297 | * @} |
Kojto | 122:f9eeca106725 | 1298 | */ |
Kojto | 122:f9eeca106725 | 1299 | |
Kojto | 122:f9eeca106725 | 1300 | #ifdef __cplusplus |
Kojto | 122:f9eeca106725 | 1301 | } |
Kojto | 122:f9eeca106725 | 1302 | #endif |
Kojto | 122:f9eeca106725 | 1303 | |
Kojto | 122:f9eeca106725 | 1304 | #endif /* __STM32F7xx_HAL_RCC_H */ |
Kojto | 122:f9eeca106725 | 1305 | |
Kojto | 122:f9eeca106725 | 1306 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |