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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/system_LPC11xx.c@635:a11c0372f0ba, 2015-09-30 (annotated)

Committer:
mbed_official
Date:
Wed Sep 30 17:00:09 2015 +0100
Revision:
635:a11c0372f0ba
Parent:
30:91c1d09ada54 
Synchronized with git revision d29c98dae61be0946ddf3a3c641c7726056f9452



Full URL: https://github.com/mbedmicro/mbed/commit/d29c98dae61be0946ddf3a3c641c7726056f9452/



Added support for SAMW25

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 30:91c1d09ada54 1 /**************************************************************************//**
mbed_official 30:91c1d09ada54 2 * @file system_LPC11xx.c
mbed_official 30:91c1d09ada54 3 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File
mbed_official 30:91c1d09ada54 4 * for the NXP LPC11xx/LPC11Cxx Devices
mbed_official 30:91c1d09ada54 5 * @version V1.10
mbed_official 30:91c1d09ada54 6 * @date 24. November 2010
mbed_official 30:91c1d09ada54 7 *
mbed_official 30:91c1d09ada54 8 * @note
mbed_official 30:91c1d09ada54 9 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
mbed_official 30:91c1d09ada54 10 *
mbed_official 30:91c1d09ada54 11 * @par
mbed_official 30:91c1d09ada54 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
mbed_official 30:91c1d09ada54 13 * processor based microcontrollers. This file can be freely distributed
mbed_official 30:91c1d09ada54 14 * within development tools that are supporting such ARM based processors.
mbed_official 30:91c1d09ada54 15 *
mbed_official 30:91c1d09ada54 16 * @par
mbed_official 30:91c1d09ada54 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
mbed_official 30:91c1d09ada54 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
mbed_official 30:91c1d09ada54 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
mbed_official 30:91c1d09ada54 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
mbed_official 30:91c1d09ada54 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
mbed_official 30:91c1d09ada54 22 *
mbed_official 30:91c1d09ada54 23 ******************************************************************************/
mbed_official 30:91c1d09ada54 24
mbed_official 30:91c1d09ada54 25
mbed_official 30:91c1d09ada54 26 #include <stdint.h>
mbed_official 30:91c1d09ada54 27 #include "LPC11xx.h"
mbed_official 30:91c1d09ada54 28
mbed_official 30:91c1d09ada54 29 /*
mbed_official 30:91c1d09ada54 30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
mbed_official 30:91c1d09ada54 31 */
mbed_official 30:91c1d09ada54 32
mbed_official 30:91c1d09ada54 33 /*--------------------- Clock Configuration ----------------------------------
mbed_official 30:91c1d09ada54 34 //
mbed_official 30:91c1d09ada54 35 // <e> Clock Configuration
mbed_official 30:91c1d09ada54 36 // <h> System Oscillator Control Register (SYSOSCCTRL)
mbed_official 30:91c1d09ada54 37 // <o1.0> BYPASS: System Oscillator Bypass Enable
mbed_official 30:91c1d09ada54 38 // <i> If enabled then PLL input (sys_osc_clk) is fed
mbed_official 30:91c1d09ada54 39 // <i> directly from XTALIN and XTALOUT pins.
mbed_official 30:91c1d09ada54 40 // <o1.9> FREQRANGE: System Oscillator Frequency Range
mbed_official 30:91c1d09ada54 41 // <i> Determines frequency range for Low-power oscillator.
mbed_official 30:91c1d09ada54 42 // <0=> 1 - 20 MHz
mbed_official 30:91c1d09ada54 43 // <1=> 15 - 25 MHz
mbed_official 30:91c1d09ada54 44 // </h>
mbed_official 30:91c1d09ada54 45 //
mbed_official 30:91c1d09ada54 46 // <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
mbed_official 30:91c1d09ada54 47 // <o2.0..4> DIVSEL: Select Divider for Fclkana
mbed_official 30:91c1d09ada54 48 // <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
mbed_official 30:91c1d09ada54 49 // <0-31>
mbed_official 30:91c1d09ada54 50 // <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
mbed_official 30:91c1d09ada54 51 // <0=> Undefined
mbed_official 30:91c1d09ada54 52 // <1=> 0.5 MHz
mbed_official 30:91c1d09ada54 53 // <2=> 0.8 MHz
mbed_official 30:91c1d09ada54 54 // <3=> 1.1 MHz
mbed_official 30:91c1d09ada54 55 // <4=> 1.4 MHz
mbed_official 30:91c1d09ada54 56 // <5=> 1.6 MHz
mbed_official 30:91c1d09ada54 57 // <6=> 1.8 MHz
mbed_official 30:91c1d09ada54 58 // <7=> 2.0 MHz
mbed_official 30:91c1d09ada54 59 // <8=> 2.2 MHz
mbed_official 30:91c1d09ada54 60 // <9=> 2.4 MHz
mbed_official 30:91c1d09ada54 61 // <10=> 2.6 MHz
mbed_official 30:91c1d09ada54 62 // <11=> 2.7 MHz
mbed_official 30:91c1d09ada54 63 // <12=> 2.9 MHz
mbed_official 30:91c1d09ada54 64 // <13=> 3.1 MHz
mbed_official 30:91c1d09ada54 65 // <14=> 3.2 MHz
mbed_official 30:91c1d09ada54 66 // <15=> 3.4 MHz
mbed_official 30:91c1d09ada54 67 // </h>
mbed_official 30:91c1d09ada54 68 //
mbed_official 30:91c1d09ada54 69 // <h> System PLL Control Register (SYSPLLCTRL)
mbed_official 30:91c1d09ada54 70 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
mbed_official 30:91c1d09ada54 71 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
mbed_official 30:91c1d09ada54 72 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
mbed_official 30:91c1d09ada54 73 // <o3.0..4> MSEL: Feedback Divider Selection
mbed_official 30:91c1d09ada54 74 // <i> M = MSEL + 1
mbed_official 30:91c1d09ada54 75 // <0-31>
mbed_official 30:91c1d09ada54 76 // <o3.5..6> PSEL: Post Divider Selection
mbed_official 30:91c1d09ada54 77 // <0=> P = 1
mbed_official 30:91c1d09ada54 78 // <1=> P = 2
mbed_official 30:91c1d09ada54 79 // <2=> P = 4
mbed_official 30:91c1d09ada54 80 // <3=> P = 8
mbed_official 30:91c1d09ada54 81 // </h>
mbed_official 30:91c1d09ada54 82 //
mbed_official 30:91c1d09ada54 83 // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
mbed_official 30:91c1d09ada54 84 // <o4.0..1> SEL: System PLL Clock Source
mbed_official 30:91c1d09ada54 85 // <0=> IRC Oscillator
mbed_official 30:91c1d09ada54 86 // <1=> System Oscillator
mbed_official 30:91c1d09ada54 87 // <2=> Reserved
mbed_official 30:91c1d09ada54 88 // <3=> Reserved
mbed_official 30:91c1d09ada54 89 // </h>
mbed_official 30:91c1d09ada54 90 //
mbed_official 30:91c1d09ada54 91 // <h> Main Clock Source Select Register (MAINCLKSEL)
mbed_official 30:91c1d09ada54 92 // <o5.0..1> SEL: Clock Source for Main Clock
mbed_official 30:91c1d09ada54 93 // <0=> IRC Oscillator
mbed_official 30:91c1d09ada54 94 // <1=> Input Clock to System PLL
mbed_official 30:91c1d09ada54 95 // <2=> WDT Oscillator
mbed_official 30:91c1d09ada54 96 // <3=> System PLL Clock Out
mbed_official 30:91c1d09ada54 97 // </h>
mbed_official 30:91c1d09ada54 98 //
mbed_official 30:91c1d09ada54 99 // <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
mbed_official 30:91c1d09ada54 100 // <o6.0..7> DIV: System AHB Clock Divider
mbed_official 30:91c1d09ada54 101 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
mbed_official 30:91c1d09ada54 102 // <i> 0 = is disabled
mbed_official 30:91c1d09ada54 103 // <0-255>
mbed_official 30:91c1d09ada54 104 // </h>
mbed_official 30:91c1d09ada54 105 // </e>
mbed_official 30:91c1d09ada54 106 */
mbed_official 30:91c1d09ada54 107 #define CLOCK_SETUP 1
mbed_official 30:91c1d09ada54 108 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
mbed_official 30:91c1d09ada54 109 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
mbed_official 30:91c1d09ada54 110 #define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000
mbed_official 30:91c1d09ada54 111 #define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 // Define as using IRC
mbed_official 30:91c1d09ada54 112 #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 // Define as using System PLL clock out
mbed_official 30:91c1d09ada54 113 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
mbed_official 30:91c1d09ada54 114
mbed_official 30:91c1d09ada54 115 /*
mbed_official 30:91c1d09ada54 116 //-------- <<< end of configuration section >>> ------------------------------
mbed_official 30:91c1d09ada54 117 */
mbed_official 30:91c1d09ada54 118
mbed_official 30:91c1d09ada54 119 /*----------------------------------------------------------------------------
mbed_official 30:91c1d09ada54 120 Check the register settings
mbed_official 30:91c1d09ada54 121 *----------------------------------------------------------------------------*/
mbed_official 30:91c1d09ada54 122 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
mbed_official 30:91c1d09ada54 123 #define CHECK_RSVD(val, mask) (val & mask)
mbed_official 30:91c1d09ada54 124
mbed_official 30:91c1d09ada54 125 /* Clock Configuration -------------------------------------------------------*/
mbed_official 30:91c1d09ada54 126 #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
mbed_official 30:91c1d09ada54 127 #error "SYSOSCCTRL: Invalid values of reserved bits!"
mbed_official 30:91c1d09ada54 128 #endif
mbed_official 30:91c1d09ada54 129
mbed_official 30:91c1d09ada54 130 #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
mbed_official 30:91c1d09ada54 131 #error "WDTOSCCTRL: Invalid values of reserved bits!"
mbed_official 30:91c1d09ada54 132 #endif
mbed_official 30:91c1d09ada54 133
mbed_official 30:91c1d09ada54 134 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
mbed_official 30:91c1d09ada54 135 #error "SYSPLLCLKSEL: Value out of range!"
mbed_official 30:91c1d09ada54 136 #endif
mbed_official 30:91c1d09ada54 137
mbed_official 30:91c1d09ada54 138 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
mbed_official 30:91c1d09ada54 139 #error "SYSPLLCTRL: Invalid values of reserved bits!"
mbed_official 30:91c1d09ada54 140 #endif
mbed_official 30:91c1d09ada54 141
mbed_official 30:91c1d09ada54 142 #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
mbed_official 30:91c1d09ada54 143 #error "MAINCLKSEL: Invalid values of reserved bits!"
mbed_official 30:91c1d09ada54 144 #endif
mbed_official 30:91c1d09ada54 145
mbed_official 30:91c1d09ada54 146 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
mbed_official 30:91c1d09ada54 147 #error "SYSAHBCLKDIV: Value out of range!"
mbed_official 30:91c1d09ada54 148 #endif
mbed_official 30:91c1d09ada54 149
mbed_official 30:91c1d09ada54 150
mbed_official 30:91c1d09ada54 151 /*----------------------------------------------------------------------------
mbed_official 30:91c1d09ada54 152 DEFINES
mbed_official 30:91c1d09ada54 153 *----------------------------------------------------------------------------*/
mbed_official 30:91c1d09ada54 154
mbed_official 30:91c1d09ada54 155 /*----------------------------------------------------------------------------
mbed_official 30:91c1d09ada54 156 Define clocks
mbed_official 30:91c1d09ada54 157 *----------------------------------------------------------------------------*/
mbed_official 30:91c1d09ada54 158 #define __XTAL (12000000UL) /* Oscillator frequency */
mbed_official 30:91c1d09ada54 159 #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
mbed_official 30:91c1d09ada54 160 #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
mbed_official 30:91c1d09ada54 161
mbed_official 30:91c1d09ada54 162
mbed_official 30:91c1d09ada54 163 #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
mbed_official 30:91c1d09ada54 164 #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
mbed_official 30:91c1d09ada54 165
mbed_official 30:91c1d09ada54 166 #if (CLOCK_SETUP) /* Clock Setup */
mbed_official 30:91c1d09ada54 167 #if (__FREQSEL == 0)
mbed_official 30:91c1d09ada54 168 #define __WDT_OSC_CLK ( 0) /* undefined */
mbed_official 30:91c1d09ada54 169 #elif (__FREQSEL == 1)
mbed_official 30:91c1d09ada54 170 #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
mbed_official 30:91c1d09ada54 171 #elif (__FREQSEL == 2)
mbed_official 30:91c1d09ada54 172 #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
mbed_official 30:91c1d09ada54 173 #elif (__FREQSEL == 3)
mbed_official 30:91c1d09ada54 174 #define __WDT_OSC_CLK (1100000 / __DIVSEL)
mbed_official 30:91c1d09ada54 175 #elif (__FREQSEL == 4)
mbed_official 30:91c1d09ada54 176 #define __WDT_OSC_CLK (1400000 / __DIVSEL)
mbed_official 30:91c1d09ada54 177 #elif (__FREQSEL == 5)
mbed_official 30:91c1d09ada54 178 #define __WDT_OSC_CLK (1600000 / __DIVSEL)
mbed_official 30:91c1d09ada54 179 #elif (__FREQSEL == 6)
mbed_official 30:91c1d09ada54 180 #define __WDT_OSC_CLK (1800000 / __DIVSEL)
mbed_official 30:91c1d09ada54 181 #elif (__FREQSEL == 7)
mbed_official 30:91c1d09ada54 182 #define __WDT_OSC_CLK (2000000 / __DIVSEL)
mbed_official 30:91c1d09ada54 183 #elif (__FREQSEL == 8)
mbed_official 30:91c1d09ada54 184 #define __WDT_OSC_CLK (2200000 / __DIVSEL)
mbed_official 30:91c1d09ada54 185 #elif (__FREQSEL == 9)
mbed_official 30:91c1d09ada54 186 #define __WDT_OSC_CLK (2400000 / __DIVSEL)
mbed_official 30:91c1d09ada54 187 #elif (__FREQSEL == 10)
mbed_official 30:91c1d09ada54 188 #define __WDT_OSC_CLK (2600000 / __DIVSEL)
mbed_official 30:91c1d09ada54 189 #elif (__FREQSEL == 11)
mbed_official 30:91c1d09ada54 190 #define __WDT_OSC_CLK (2700000 / __DIVSEL)
mbed_official 30:91c1d09ada54 191 #elif (__FREQSEL == 12)
mbed_official 30:91c1d09ada54 192 #define __WDT_OSC_CLK (2900000 / __DIVSEL)
mbed_official 30:91c1d09ada54 193 #elif (__FREQSEL == 13)
mbed_official 30:91c1d09ada54 194 #define __WDT_OSC_CLK (3100000 / __DIVSEL)
mbed_official 30:91c1d09ada54 195 #elif (__FREQSEL == 14)
mbed_official 30:91c1d09ada54 196 #define __WDT_OSC_CLK (3200000 / __DIVSEL)
mbed_official 30:91c1d09ada54 197 #else
mbed_official 30:91c1d09ada54 198 #define __WDT_OSC_CLK (3400000 / __DIVSEL)
mbed_official 30:91c1d09ada54 199 #endif
mbed_official 30:91c1d09ada54 200
mbed_official 30:91c1d09ada54 201 /* sys_pllclkin calculation */
mbed_official 30:91c1d09ada54 202 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
mbed_official 30:91c1d09ada54 203 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
mbed_official 30:91c1d09ada54 204 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
mbed_official 30:91c1d09ada54 205 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
mbed_official 30:91c1d09ada54 206 #else
mbed_official 30:91c1d09ada54 207 #define __SYS_PLLCLKIN (0)
mbed_official 30:91c1d09ada54 208 #endif
mbed_official 30:91c1d09ada54 209
mbed_official 30:91c1d09ada54 210 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
mbed_official 30:91c1d09ada54 211
mbed_official 30:91c1d09ada54 212 /* main clock calculation */
mbed_official 30:91c1d09ada54 213 #if ((MAINCLKSEL_Val & 0x03) == 0)
mbed_official 30:91c1d09ada54 214 #define __MAIN_CLOCK (__IRC_OSC_CLK)
mbed_official 30:91c1d09ada54 215 #elif ((MAINCLKSEL_Val & 0x03) == 1)
mbed_official 30:91c1d09ada54 216 #define __MAIN_CLOCK (__SYS_PLLCLKIN)
mbed_official 30:91c1d09ada54 217 #elif ((MAINCLKSEL_Val & 0x03) == 2)
mbed_official 30:91c1d09ada54 218 #if (__FREQSEL == 0)
mbed_official 30:91c1d09ada54 219 #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
mbed_official 30:91c1d09ada54 220 #else
mbed_official 30:91c1d09ada54 221 #define __MAIN_CLOCK (__WDT_OSC_CLK)
mbed_official 30:91c1d09ada54 222 #endif
mbed_official 30:91c1d09ada54 223 #elif ((MAINCLKSEL_Val & 0x03) == 3)
mbed_official 30:91c1d09ada54 224 #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
mbed_official 30:91c1d09ada54 225 #else
mbed_official 30:91c1d09ada54 226 #define __MAIN_CLOCK (0)
mbed_official 30:91c1d09ada54 227 #endif
mbed_official 30:91c1d09ada54 228
mbed_official 30:91c1d09ada54 229 #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
mbed_official 30:91c1d09ada54 230
mbed_official 30:91c1d09ada54 231 #else
mbed_official 30:91c1d09ada54 232 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
mbed_official 30:91c1d09ada54 233 #endif // CLOCK_SETUP
mbed_official 30:91c1d09ada54 234
mbed_official 30:91c1d09ada54 235
mbed_official 30:91c1d09ada54 236 /*----------------------------------------------------------------------------
mbed_official 30:91c1d09ada54 237 Clock Variable definitions
mbed_official 30:91c1d09ada54 238 *----------------------------------------------------------------------------*/
mbed_official 30:91c1d09ada54 239 uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
mbed_official 30:91c1d09ada54 240
mbed_official 30:91c1d09ada54 241
mbed_official 30:91c1d09ada54 242 /*----------------------------------------------------------------------------
mbed_official 30:91c1d09ada54 243 Clock functions
mbed_official 30:91c1d09ada54 244 *----------------------------------------------------------------------------*/
mbed_official 30:91c1d09ada54 245 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
mbed_official 30:91c1d09ada54 246 {
mbed_official 30:91c1d09ada54 247 uint32_t wdt_osc = 0;
mbed_official 30:91c1d09ada54 248
mbed_official 30:91c1d09ada54 249 /* Determine clock frequency according to clock register values */
mbed_official 30:91c1d09ada54 250 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
mbed_official 30:91c1d09ada54 251 case 0: wdt_osc = 0; break;
mbed_official 30:91c1d09ada54 252 case 1: wdt_osc = 500000; break;
mbed_official 30:91c1d09ada54 253 case 2: wdt_osc = 800000; break;
mbed_official 30:91c1d09ada54 254 case 3: wdt_osc = 1100000; break;
mbed_official 30:91c1d09ada54 255 case 4: wdt_osc = 1400000; break;
mbed_official 30:91c1d09ada54 256 case 5: wdt_osc = 1600000; break;
mbed_official 30:91c1d09ada54 257 case 6: wdt_osc = 1800000; break;
mbed_official 30:91c1d09ada54 258 case 7: wdt_osc = 2000000; break;
mbed_official 30:91c1d09ada54 259 case 8: wdt_osc = 2200000; break;
mbed_official 30:91c1d09ada54 260 case 9: wdt_osc = 2400000; break;
mbed_official 30:91c1d09ada54 261 case 10: wdt_osc = 2600000; break;
mbed_official 30:91c1d09ada54 262 case 11: wdt_osc = 2700000; break;
mbed_official 30:91c1d09ada54 263 case 12: wdt_osc = 2900000; break;
mbed_official 30:91c1d09ada54 264 case 13: wdt_osc = 3100000; break;
mbed_official 30:91c1d09ada54 265 case 14: wdt_osc = 3200000; break;
mbed_official 30:91c1d09ada54 266 case 15: wdt_osc = 3400000; break;
mbed_official 30:91c1d09ada54 267 }
mbed_official 30:91c1d09ada54 268 wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
mbed_official 30:91c1d09ada54 269
mbed_official 30:91c1d09ada54 270 switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
mbed_official 30:91c1d09ada54 271 case 0: /* Internal RC oscillator */
mbed_official 30:91c1d09ada54 272 SystemCoreClock = __IRC_OSC_CLK;
mbed_official 30:91c1d09ada54 273 break;
mbed_official 30:91c1d09ada54 274 case 1: /* Input Clock to System PLL */
mbed_official 30:91c1d09ada54 275 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
mbed_official 30:91c1d09ada54 276 case 0: /* Internal RC oscillator */
mbed_official 30:91c1d09ada54 277 SystemCoreClock = __IRC_OSC_CLK;
mbed_official 30:91c1d09ada54 278 break;
mbed_official 30:91c1d09ada54 279 case 1: /* System oscillator */
mbed_official 30:91c1d09ada54 280 SystemCoreClock = __SYS_OSC_CLK;
mbed_official 30:91c1d09ada54 281 break;
mbed_official 30:91c1d09ada54 282 case 2: /* Reserved */
mbed_official 30:91c1d09ada54 283 case 3: /* Reserved */
mbed_official 30:91c1d09ada54 284 SystemCoreClock = 0;
mbed_official 30:91c1d09ada54 285 break;
mbed_official 30:91c1d09ada54 286 }
mbed_official 30:91c1d09ada54 287 break;
mbed_official 30:91c1d09ada54 288 case 2: /* WDT Oscillator */
mbed_official 30:91c1d09ada54 289 SystemCoreClock = wdt_osc;
mbed_official 30:91c1d09ada54 290 break;
mbed_official 30:91c1d09ada54 291 case 3: /* System PLL Clock Out */
mbed_official 30:91c1d09ada54 292 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
mbed_official 30:91c1d09ada54 293 case 0: /* Internal RC oscillator */
mbed_official 30:91c1d09ada54 294 if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
mbed_official 30:91c1d09ada54 295 SystemCoreClock = __IRC_OSC_CLK;
mbed_official 30:91c1d09ada54 296 } else {
mbed_official 30:91c1d09ada54 297 SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
mbed_official 30:91c1d09ada54 298 }
mbed_official 30:91c1d09ada54 299 break;
mbed_official 30:91c1d09ada54 300 case 1: /* System oscillator */
mbed_official 30:91c1d09ada54 301 if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
mbed_official 30:91c1d09ada54 302 SystemCoreClock = __SYS_OSC_CLK;
mbed_official 30:91c1d09ada54 303 } else {
mbed_official 30:91c1d09ada54 304 SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
mbed_official 30:91c1d09ada54 305 }
mbed_official 30:91c1d09ada54 306 break;
mbed_official 30:91c1d09ada54 307 case 2: /* Reserved */
mbed_official 30:91c1d09ada54 308 case 3: /* Reserved */
mbed_official 30:91c1d09ada54 309 SystemCoreClock = 0;
mbed_official 30:91c1d09ada54 310 break;
mbed_official 30:91c1d09ada54 311 }
mbed_official 30:91c1d09ada54 312 break;
mbed_official 30:91c1d09ada54 313 }
mbed_official 30:91c1d09ada54 314
mbed_official 30:91c1d09ada54 315 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
mbed_official 30:91c1d09ada54 316
mbed_official 30:91c1d09ada54 317 }
mbed_official 30:91c1d09ada54 318
mbed_official 30:91c1d09ada54 319 /**
mbed_official 30:91c1d09ada54 320 * Initialize the system
mbed_official 30:91c1d09ada54 321 *
mbed_official 30:91c1d09ada54 322 * @param none
mbed_official 30:91c1d09ada54 323 * @return none
mbed_official 30:91c1d09ada54 324 *
mbed_official 30:91c1d09ada54 325 * @brief Setup the microcontroller system.
mbed_official 30:91c1d09ada54 326 * Initialize the System.
mbed_official 30:91c1d09ada54 327 */
mbed_official 30:91c1d09ada54 328 void SystemInit (void) {
mbed_official 30:91c1d09ada54 329 volatile uint32_t i;
mbed_official 30:91c1d09ada54 330
mbed_official 30:91c1d09ada54 331 #if (CLOCK_SETUP) /* Clock Setup */
mbed_official 30:91c1d09ada54 332
mbed_official 30:91c1d09ada54 333 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
mbed_official 30:91c1d09ada54 334 LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
mbed_official 30:91c1d09ada54 335 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
mbed_official 30:91c1d09ada54 336 for (i = 0; i < 200; i++) __NOP();
mbed_official 30:91c1d09ada54 337 #endif
mbed_official 30:91c1d09ada54 338
mbed_official 30:91c1d09ada54 339 LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
mbed_official 30:91c1d09ada54 340 LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
mbed_official 30:91c1d09ada54 341 LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
mbed_official 30:91c1d09ada54 342 LPC_SYSCON->SYSPLLCLKUEN = 0x01;
mbed_official 30:91c1d09ada54 343 while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
mbed_official 30:91c1d09ada54 344 #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
mbed_official 30:91c1d09ada54 345 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
mbed_official 30:91c1d09ada54 346 LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
mbed_official 30:91c1d09ada54 347 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
mbed_official 30:91c1d09ada54 348 #endif
mbed_official 30:91c1d09ada54 349
mbed_official 30:91c1d09ada54 350 #if (((MAINCLKSEL_Val & 0x03) == 2) )
mbed_official 30:91c1d09ada54 351 LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
mbed_official 30:91c1d09ada54 352 LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
mbed_official 30:91c1d09ada54 353 for (i = 0; i < 200; i++) __NOP();
mbed_official 30:91c1d09ada54 354 #endif
mbed_official 30:91c1d09ada54 355
mbed_official 30:91c1d09ada54 356 LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
mbed_official 30:91c1d09ada54 357 LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
mbed_official 30:91c1d09ada54 358 LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
mbed_official 30:91c1d09ada54 359 LPC_SYSCON->MAINCLKUEN = 0x01;
mbed_official 30:91c1d09ada54 360 while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
mbed_official 30:91c1d09ada54 361
mbed_official 30:91c1d09ada54 362 LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
mbed_official 30:91c1d09ada54 363 #endif
mbed_official 30:91c1d09ada54 364 /* System clock to the IOCON needs to be enabled or
mbed_official 30:91c1d09ada54 365 most of the I/O related peripherals won't work. */
mbed_official 30:91c1d09ada54 366 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
mbed_official 30:91c1d09ada54 367 }