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Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/system_stm32f30x.c@185:e752b4ee7de1, 2014-05-09 (annotated)

Committer:
mbed_official
Date:
Fri May 09 14:00:08 2014 +0100
Revision:
185:e752b4ee7de1
Parent:
167:d5744491c362 
Synchronized with git revision c761a5e0a90087e87817c38ae4e3034675dacfde



Full URL: https://github.com/mbedmicro/mbed/commit/c761a5e0a90087e87817c38ae4e3034675dacfde/



Solve also the problem with the SetSysClock function not declared in

sleep.c



Conflicts:

	libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/i2c_api.c

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 125:23cc3068a9e4 1 /**
mbed_official 125:23cc3068a9e4 2 ******************************************************************************
mbed_official 125:23cc3068a9e4 3 * @file system_stm32f30x.c
mbed_official 125:23cc3068a9e4 4 * @author MCD Application Team
mbed_official 125:23cc3068a9e4 5 * @version V1.0.0
mbed_official 125:23cc3068a9e4 6 * @date 05-March-2014
mbed_official 125:23cc3068a9e4 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
mbed_official 125:23cc3068a9e4 8 * This file contains the system clock configuration for STM32F30x devices,
mbed_official 125:23cc3068a9e4 9 * and is generated by the clock configuration tool
mbed_official 125:23cc3068a9e4 10 * stm32f30x_Clock_Configuration_V1.0.0.xls
mbed_official 125:23cc3068a9e4 11 *
mbed_official 125:23cc3068a9e4 12 * 1. This file provides two functions and one global variable to be called from
mbed_official 125:23cc3068a9e4 13 * user application:
mbed_official 125:23cc3068a9e4 14 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
mbed_official 125:23cc3068a9e4 15 * and Divider factors, AHB/APBx prescalers and Flash settings),
mbed_official 125:23cc3068a9e4 16 * depending on the configuration made in the clock xls tool.
mbed_official 125:23cc3068a9e4 17 * This function is called at startup just after reset and
mbed_official 125:23cc3068a9e4 18 * before branch to main program. This call is made inside
mbed_official 125:23cc3068a9e4 19 * the "startup_stm32f30x.s" file.
mbed_official 125:23cc3068a9e4 20 *
mbed_official 125:23cc3068a9e4 21 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 125:23cc3068a9e4 22 * by the user application to setup the SysTick
mbed_official 125:23cc3068a9e4 23 * timer or configure other parameters.
mbed_official 125:23cc3068a9e4 24 *
mbed_official 125:23cc3068a9e4 25 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 125:23cc3068a9e4 26 * be called whenever the core clock is changed
mbed_official 125:23cc3068a9e4 27 * during program execution.
mbed_official 125:23cc3068a9e4 28 *
mbed_official 125:23cc3068a9e4 29 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
mbed_official 125:23cc3068a9e4 30 * Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
mbed_official 125:23cc3068a9e4 31 * configure the system clock before to branch to main program.
mbed_official 125:23cc3068a9e4 32 *
mbed_official 125:23cc3068a9e4 33 * 3. If the system clock source selected by user fails to startup, the SystemInit()
mbed_official 125:23cc3068a9e4 34 * function will do nothing and HSI still used as system clock source. User can
mbed_official 125:23cc3068a9e4 35 * add some code to deal with this issue inside the SetSysClock() function.
mbed_official 125:23cc3068a9e4 36 *
mbed_official 125:23cc3068a9e4 37 * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
mbed_official 125:23cc3068a9e4 38 * in "stm32f30x.h" file. When HSE is used as system clock source, directly or
mbed_official 125:23cc3068a9e4 39 * through PLL, and you are using different crystal you have to adapt the HSE
mbed_official 125:23cc3068a9e4 40 * value to your own configuration.
mbed_official 125:23cc3068a9e4 41 *
mbed_official 125:23cc3068a9e4 42 * 5. This file configures the system clock as follows:
mbed_official 125:23cc3068a9e4 43 *-----------------------------------------------------------------------------
mbed_official 135:067cc8ba23da 44 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 135:067cc8ba23da 45 * | (external 8 MHz clock) | (internal 8 MHz)
mbed_official 135:067cc8ba23da 46 * | 2- PLL_HSE_XTAL |
mbed_official 135:067cc8ba23da 47 * | (external 8 MHz xtal) |
mbed_official 125:23cc3068a9e4 48 *-----------------------------------------------------------------------------
mbed_official 135:067cc8ba23da 49 * SYSCLK(MHz) | 72 | 64
mbed_official 125:23cc3068a9e4 50 *-----------------------------------------------------------------------------
mbed_official 135:067cc8ba23da 51 * AHBCLK (MHz) | 72 | 64
mbed_official 125:23cc3068a9e4 52 *-----------------------------------------------------------------------------
mbed_official 135:067cc8ba23da 53 * APB1CLK (MHz) | 36 | 32
mbed_official 125:23cc3068a9e4 54 *-----------------------------------------------------------------------------
mbed_official 135:067cc8ba23da 55 * APB2CLK (MHz) | 72 | 64
mbed_official 125:23cc3068a9e4 56 *-----------------------------------------------------------------------------
mbed_official 135:067cc8ba23da 57 * USB capable (48 MHz precise clock) | YES | NO
mbed_official 135:067cc8ba23da 58 *-----------------------------------------------------------------------------
mbed_official 125:23cc3068a9e4 59 ******************************************************************************
mbed_official 125:23cc3068a9e4 60 * @attention
mbed_official 125:23cc3068a9e4 61 *
mbed_official 125:23cc3068a9e4 62 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 125:23cc3068a9e4 63 *
mbed_official 125:23cc3068a9e4 64 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 125:23cc3068a9e4 65 * are permitted provided that the following conditions are met:
mbed_official 125:23cc3068a9e4 66 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 125:23cc3068a9e4 67 * this list of conditions and the following disclaimer.
mbed_official 125:23cc3068a9e4 68 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 125:23cc3068a9e4 69 * this list of conditions and the following disclaimer in the documentation
mbed_official 125:23cc3068a9e4 70 * and/or other materials provided with the distribution.
mbed_official 125:23cc3068a9e4 71 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 125:23cc3068a9e4 72 * may be used to endorse or promote products derived from this software
mbed_official 125:23cc3068a9e4 73 * without specific prior written permission.
mbed_official 125:23cc3068a9e4 74 *
mbed_official 125:23cc3068a9e4 75 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 125:23cc3068a9e4 76 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 125:23cc3068a9e4 77 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 125:23cc3068a9e4 78 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 125:23cc3068a9e4 79 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 125:23cc3068a9e4 80 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 125:23cc3068a9e4 81 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 125:23cc3068a9e4 82 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 125:23cc3068a9e4 83 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 125:23cc3068a9e4 84 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 125:23cc3068a9e4 85 *
mbed_official 125:23cc3068a9e4 86 ******************************************************************************
mbed_official 125:23cc3068a9e4 87 */
mbed_official 135:067cc8ba23da 88
mbed_official 125:23cc3068a9e4 89 /** @addtogroup CMSIS
mbed_official 125:23cc3068a9e4 90 * @{
mbed_official 125:23cc3068a9e4 91 */
mbed_official 125:23cc3068a9e4 92
mbed_official 125:23cc3068a9e4 93 /** @addtogroup stm32f30x_system
mbed_official 125:23cc3068a9e4 94 * @{
mbed_official 125:23cc3068a9e4 95 */
mbed_official 125:23cc3068a9e4 96
mbed_official 125:23cc3068a9e4 97 /** @addtogroup STM32F30x_System_Private_Includes
mbed_official 125:23cc3068a9e4 98 * @{
mbed_official 125:23cc3068a9e4 99 */
mbed_official 125:23cc3068a9e4 100
mbed_official 125:23cc3068a9e4 101 #include "stm32f30x.h"
mbed_official 125:23cc3068a9e4 102
mbed_official 125:23cc3068a9e4 103 /**
mbed_official 125:23cc3068a9e4 104 * @}
mbed_official 125:23cc3068a9e4 105 */
mbed_official 125:23cc3068a9e4 106
mbed_official 125:23cc3068a9e4 107 /** @addtogroup STM32F30x_System_Private_TypesDefinitions
mbed_official 125:23cc3068a9e4 108 * @{
mbed_official 125:23cc3068a9e4 109 */
mbed_official 125:23cc3068a9e4 110
mbed_official 125:23cc3068a9e4 111 /**
mbed_official 125:23cc3068a9e4 112 * @}
mbed_official 125:23cc3068a9e4 113 */
mbed_official 125:23cc3068a9e4 114
mbed_official 125:23cc3068a9e4 115 /** @addtogroup STM32F30x_System_Private_Defines
mbed_official 125:23cc3068a9e4 116 * @{
mbed_official 125:23cc3068a9e4 117 */
mbed_official 135:067cc8ba23da 118
mbed_official 125:23cc3068a9e4 119 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 125:23cc3068a9e4 120 Internal SRAM. */
mbed_official 125:23cc3068a9e4 121 /* #define VECT_TAB_SRAM */
mbed_official 125:23cc3068a9e4 122 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
mbed_official 125:23cc3068a9e4 123 This value must be a multiple of 0x200. */
mbed_official 125:23cc3068a9e4 124 /**
mbed_official 125:23cc3068a9e4 125 * @}
mbed_official 125:23cc3068a9e4 126 */
mbed_official 125:23cc3068a9e4 127
mbed_official 125:23cc3068a9e4 128 /** @addtogroup STM32F30x_System_Private_Macros
mbed_official 125:23cc3068a9e4 129 * @{
mbed_official 125:23cc3068a9e4 130 */
mbed_official 125:23cc3068a9e4 131
mbed_official 135:067cc8ba23da 132 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 135:067cc8ba23da 133 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 135:067cc8ba23da 134 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 135:067cc8ba23da 135
mbed_official 125:23cc3068a9e4 136 /**
mbed_official 125:23cc3068a9e4 137 * @}
mbed_official 125:23cc3068a9e4 138 */
mbed_official 125:23cc3068a9e4 139
mbed_official 125:23cc3068a9e4 140 /** @addtogroup STM32F30x_System_Private_Variables
mbed_official 125:23cc3068a9e4 141 * @{
mbed_official 125:23cc3068a9e4 142 */
mbed_official 125:23cc3068a9e4 143
mbed_official 138:ec7ee4660c49 144 uint32_t SystemCoreClock = 64000000; /* Default with HSI. Will be updated if HSE is used */
mbed_official 125:23cc3068a9e4 145
mbed_official 135:067cc8ba23da 146 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 125:23cc3068a9e4 147
mbed_official 125:23cc3068a9e4 148 /**
mbed_official 125:23cc3068a9e4 149 * @}
mbed_official 125:23cc3068a9e4 150 */
mbed_official 125:23cc3068a9e4 151
mbed_official 125:23cc3068a9e4 152 /** @addtogroup STM32F30x_System_Private_FunctionPrototypes
mbed_official 125:23cc3068a9e4 153 * @{
mbed_official 125:23cc3068a9e4 154 */
mbed_official 125:23cc3068a9e4 155
mbed_official 135:067cc8ba23da 156 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 135:067cc8ba23da 157 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 135:067cc8ba23da 158 #endif
mbed_official 135:067cc8ba23da 159
mbed_official 135:067cc8ba23da 160 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 135:067cc8ba23da 161
mbed_official 125:23cc3068a9e4 162 /**
mbed_official 125:23cc3068a9e4 163 * @}
mbed_official 125:23cc3068a9e4 164 */
mbed_official 125:23cc3068a9e4 165
mbed_official 125:23cc3068a9e4 166 /** @addtogroup STM32F30x_System_Private_Functions
mbed_official 125:23cc3068a9e4 167 * @{
mbed_official 125:23cc3068a9e4 168 */
mbed_official 125:23cc3068a9e4 169
mbed_official 125:23cc3068a9e4 170 /**
mbed_official 125:23cc3068a9e4 171 * @brief Setup the microcontroller system
mbed_official 125:23cc3068a9e4 172 * Initialize the Embedded Flash Interface, the PLL and update the
mbed_official 125:23cc3068a9e4 173 * SystemFrequency variable.
mbed_official 125:23cc3068a9e4 174 * @param None
mbed_official 125:23cc3068a9e4 175 * @retval None
mbed_official 125:23cc3068a9e4 176 */
mbed_official 125:23cc3068a9e4 177 void SystemInit(void)
mbed_official 125:23cc3068a9e4 178 {
mbed_official 125:23cc3068a9e4 179 /* FPU settings ------------------------------------------------------------*/
mbed_official 125:23cc3068a9e4 180 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 125:23cc3068a9e4 181 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 125:23cc3068a9e4 182 #endif
mbed_official 125:23cc3068a9e4 183
mbed_official 125:23cc3068a9e4 184 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 125:23cc3068a9e4 185 /* Set HSION bit */
mbed_official 125:23cc3068a9e4 186 RCC->CR |= (uint32_t)0x00000001;
mbed_official 125:23cc3068a9e4 187
mbed_official 125:23cc3068a9e4 188 /* Reset CFGR register */
mbed_official 125:23cc3068a9e4 189 RCC->CFGR &= 0xF87FC00C;
mbed_official 125:23cc3068a9e4 190
mbed_official 125:23cc3068a9e4 191 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 125:23cc3068a9e4 192 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 125:23cc3068a9e4 193
mbed_official 125:23cc3068a9e4 194 /* Reset HSEBYP bit */
mbed_official 125:23cc3068a9e4 195 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 125:23cc3068a9e4 196
mbed_official 125:23cc3068a9e4 197 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
mbed_official 125:23cc3068a9e4 198 RCC->CFGR &= (uint32_t)0xFF80FFFF;
mbed_official 125:23cc3068a9e4 199
mbed_official 125:23cc3068a9e4 200 /* Reset PREDIV1[3:0] bits */
mbed_official 125:23cc3068a9e4 201 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
mbed_official 125:23cc3068a9e4 202
mbed_official 125:23cc3068a9e4 203 /* Reset USARTSW[1:0], I2CSW and TIMs bits */
mbed_official 125:23cc3068a9e4 204 RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
mbed_official 125:23cc3068a9e4 205
mbed_official 125:23cc3068a9e4 206 /* Disable all interrupts */
mbed_official 125:23cc3068a9e4 207 RCC->CIR = 0x00000000;
mbed_official 125:23cc3068a9e4 208
mbed_official 135:067cc8ba23da 209 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 125:23cc3068a9e4 210 #ifdef VECT_TAB_SRAM
mbed_official 135:067cc8ba23da 211 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 125:23cc3068a9e4 212 #else
mbed_official 135:067cc8ba23da 213 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 125:23cc3068a9e4 214 #endif
mbed_official 167:d5744491c362 215
mbed_official 167:d5744491c362 216 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 167:d5744491c362 217 AHB/APBx prescalers and Flash settings */
mbed_official 167:d5744491c362 218 SetSysClock();
mbed_official 125:23cc3068a9e4 219 }
mbed_official 125:23cc3068a9e4 220
mbed_official 125:23cc3068a9e4 221 /**
mbed_official 125:23cc3068a9e4 222 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 125:23cc3068a9e4 223 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 125:23cc3068a9e4 224 * be used by the user application to setup the SysTick timer or configure
mbed_official 125:23cc3068a9e4 225 * other parameters.
mbed_official 125:23cc3068a9e4 226 *
mbed_official 125:23cc3068a9e4 227 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 125:23cc3068a9e4 228 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 125:23cc3068a9e4 229 * based on this variable will be incorrect.
mbed_official 125:23cc3068a9e4 230 *
mbed_official 125:23cc3068a9e4 231 * @note - The system frequency computed by this function is not the real
mbed_official 125:23cc3068a9e4 232 * frequency in the chip. It is calculated based on the predefined
mbed_official 125:23cc3068a9e4 233 * constant and the selected clock source:
mbed_official 125:23cc3068a9e4 234 *
mbed_official 125:23cc3068a9e4 235 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 125:23cc3068a9e4 236 *
mbed_official 125:23cc3068a9e4 237 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 125:23cc3068a9e4 238 *
mbed_official 125:23cc3068a9e4 239 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 125:23cc3068a9e4 240 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 125:23cc3068a9e4 241 *
mbed_official 125:23cc3068a9e4 242 * (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
mbed_official 125:23cc3068a9e4 243 * 8 MHz) but the real value may vary depending on the variations
mbed_official 125:23cc3068a9e4 244 * in voltage and temperature.
mbed_official 125:23cc3068a9e4 245 *
mbed_official 125:23cc3068a9e4 246 * (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
mbed_official 125:23cc3068a9e4 247 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 125:23cc3068a9e4 248 * frequency of the crystal used. Otherwise, this function may
mbed_official 125:23cc3068a9e4 249 * have wrong result.
mbed_official 125:23cc3068a9e4 250 *
mbed_official 125:23cc3068a9e4 251 * - The result of this function could be not correct when using fractional
mbed_official 125:23cc3068a9e4 252 * value for HSE crystal.
mbed_official 125:23cc3068a9e4 253 *
mbed_official 125:23cc3068a9e4 254 * @param None
mbed_official 125:23cc3068a9e4 255 * @retval None
mbed_official 125:23cc3068a9e4 256 */
mbed_official 125:23cc3068a9e4 257 void SystemCoreClockUpdate (void)
mbed_official 125:23cc3068a9e4 258 {
mbed_official 125:23cc3068a9e4 259 uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
mbed_official 125:23cc3068a9e4 260
mbed_official 125:23cc3068a9e4 261 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 125:23cc3068a9e4 262 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 125:23cc3068a9e4 263
mbed_official 125:23cc3068a9e4 264 switch (tmp)
mbed_official 125:23cc3068a9e4 265 {
mbed_official 125:23cc3068a9e4 266 case 0x00: /* HSI used as system clock */
mbed_official 125:23cc3068a9e4 267 SystemCoreClock = HSI_VALUE;
mbed_official 125:23cc3068a9e4 268 break;
mbed_official 125:23cc3068a9e4 269 case 0x04: /* HSE used as system clock */
mbed_official 125:23cc3068a9e4 270 SystemCoreClock = HSE_VALUE;
mbed_official 125:23cc3068a9e4 271 break;
mbed_official 125:23cc3068a9e4 272 case 0x08: /* PLL used as system clock */
mbed_official 125:23cc3068a9e4 273 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 125:23cc3068a9e4 274 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
mbed_official 125:23cc3068a9e4 275 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 125:23cc3068a9e4 276 pllmull = ( pllmull >> 18) + 2;
mbed_official 125:23cc3068a9e4 277
mbed_official 125:23cc3068a9e4 278 if (pllsource == 0x00)
mbed_official 125:23cc3068a9e4 279 {
mbed_official 125:23cc3068a9e4 280 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official 125:23cc3068a9e4 281 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 125:23cc3068a9e4 282 }
mbed_official 125:23cc3068a9e4 283 else
mbed_official 125:23cc3068a9e4 284 {
mbed_official 125:23cc3068a9e4 285 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
mbed_official 125:23cc3068a9e4 286 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 125:23cc3068a9e4 287 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
mbed_official 125:23cc3068a9e4 288 }
mbed_official 125:23cc3068a9e4 289 break;
mbed_official 125:23cc3068a9e4 290 default: /* HSI used as system clock */
mbed_official 125:23cc3068a9e4 291 SystemCoreClock = HSI_VALUE;
mbed_official 125:23cc3068a9e4 292 break;
mbed_official 125:23cc3068a9e4 293 }
mbed_official 125:23cc3068a9e4 294 /* Compute HCLK clock frequency ----------------*/
mbed_official 125:23cc3068a9e4 295 /* Get HCLK prescaler */
mbed_official 125:23cc3068a9e4 296 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 125:23cc3068a9e4 297 /* HCLK clock frequency */
mbed_official 125:23cc3068a9e4 298 SystemCoreClock >>= tmp;
mbed_official 125:23cc3068a9e4 299 }
mbed_official 125:23cc3068a9e4 300
mbed_official 125:23cc3068a9e4 301 /**
mbed_official 125:23cc3068a9e4 302 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 125:23cc3068a9e4 303 * AHB/APBx prescalers and Flash settings
mbed_official 125:23cc3068a9e4 304 * @note This function should be called only once the RCC clock configuration
mbed_official 125:23cc3068a9e4 305 * is reset to the default reset state (done in SystemInit() function).
mbed_official 125:23cc3068a9e4 306 * @param None
mbed_official 125:23cc3068a9e4 307 * @retval None
mbed_official 125:23cc3068a9e4 308 */
mbed_official 125:23cc3068a9e4 309 void SetSysClock(void)
mbed_official 125:23cc3068a9e4 310 {
mbed_official 135:067cc8ba23da 311 /* 1- Try to start with HSE and external clock */
mbed_official 135:067cc8ba23da 312 #if USE_PLL_HSE_EXTC != 0
mbed_official 135:067cc8ba23da 313 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 135:067cc8ba23da 314 #endif
mbed_official 135:067cc8ba23da 315 {
mbed_official 135:067cc8ba23da 316 /* 2- If fail try to start with HSE and external xtal */
mbed_official 135:067cc8ba23da 317 #if USE_PLL_HSE_XTAL != 0
mbed_official 135:067cc8ba23da 318 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 135:067cc8ba23da 319 #endif
mbed_official 135:067cc8ba23da 320 {
mbed_official 135:067cc8ba23da 321 /* 3- If fail start with HSI clock */
mbed_official 135:067cc8ba23da 322 if (SetSysClock_PLL_HSI() == 0)
mbed_official 135:067cc8ba23da 323 {
mbed_official 135:067cc8ba23da 324 while(1)
mbed_official 135:067cc8ba23da 325 {
mbed_official 135:067cc8ba23da 326 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 135:067cc8ba23da 327 }
mbed_official 135:067cc8ba23da 328 }
mbed_official 135:067cc8ba23da 329 }
mbed_official 135:067cc8ba23da 330 }
mbed_official 135:067cc8ba23da 331
mbed_official 135:067cc8ba23da 332 /* Output SYSCLK on MCO pin(PA8) for debugging purpose */
mbed_official 135:067cc8ba23da 333 /*
mbed_official 135:067cc8ba23da 334 // Enable GPIOA clock
mbed_official 135:067cc8ba23da 335 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
mbed_official 135:067cc8ba23da 336 // Configure MCO pin (PA8)
mbed_official 135:067cc8ba23da 337 GPIO_InitTypeDef GPIO_InitStructure;
mbed_official 135:067cc8ba23da 338 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
mbed_official 135:067cc8ba23da 339 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
mbed_official 135:067cc8ba23da 340 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
mbed_official 135:067cc8ba23da 341 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
mbed_official 135:067cc8ba23da 342 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
mbed_official 135:067cc8ba23da 343 GPIO_Init(GPIOA, &GPIO_InitStructure);
mbed_official 135:067cc8ba23da 344 // Select the clock to output
mbed_official 135:067cc8ba23da 345 RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCOPrescaler_1);
mbed_official 135:067cc8ba23da 346 */
mbed_official 135:067cc8ba23da 347 }
mbed_official 135:067cc8ba23da 348
mbed_official 135:067cc8ba23da 349 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 135:067cc8ba23da 350 /******************************************************************************/
mbed_official 135:067cc8ba23da 351 /* PLL (clocked by HSE) used as System clock source */
mbed_official 135:067cc8ba23da 352 /******************************************************************************/
mbed_official 135:067cc8ba23da 353 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 135:067cc8ba23da 354 {
mbed_official 135:067cc8ba23da 355 __IO uint32_t StartUpCounter = 0;
mbed_official 135:067cc8ba23da 356 __IO uint32_t HSEStatus = 0;
mbed_official 135:067cc8ba23da 357
mbed_official 135:067cc8ba23da 358 /* Bypass HSE: can be done only if HSE is OFF */
mbed_official 138:ec7ee4660c49 359 RCC->CR &= ((uint32_t)~RCC_CR_HSEON); /* To be sure HSE is OFF */
mbed_official 135:067cc8ba23da 360 if (bypass != 0)
mbed_official 135:067cc8ba23da 361 {
mbed_official 135:067cc8ba23da 362 RCC->CR |= ((uint32_t)RCC_CR_HSEBYP);
mbed_official 135:067cc8ba23da 363 }
mbed_official 138:ec7ee4660c49 364 else
mbed_official 138:ec7ee4660c49 365 {
mbed_official 138:ec7ee4660c49 366 RCC->CR &= ((uint32_t)~RCC_CR_HSEBYP);
mbed_official 138:ec7ee4660c49 367 }
mbed_official 135:067cc8ba23da 368
mbed_official 135:067cc8ba23da 369 /* Enable HSE */
mbed_official 135:067cc8ba23da 370 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
mbed_official 135:067cc8ba23da 371
mbed_official 135:067cc8ba23da 372 /* Wait till HSE is ready */
mbed_official 135:067cc8ba23da 373 do
mbed_official 135:067cc8ba23da 374 {
mbed_official 135:067cc8ba23da 375 HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official 135:067cc8ba23da 376 StartUpCounter++;
mbed_official 135:067cc8ba23da 377 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official 135:067cc8ba23da 378
mbed_official 135:067cc8ba23da 379 /* Check if HSE has started correctly */
mbed_official 135:067cc8ba23da 380 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official 135:067cc8ba23da 381 {
mbed_official 135:067cc8ba23da 382 /* Enable prefetch buffer and set flash latency
mbed_official 135:067cc8ba23da 383 0WS for 0 < SYSCLK <= 24 MHz
mbed_official 135:067cc8ba23da 384 1WS for 24 < SYSCLK <= 48 MHz
mbed_official 135:067cc8ba23da 385 2WS for 48 < SYSCLK <= 72 MHz */
mbed_official 135:067cc8ba23da 386 FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; /* 2 WS */
mbed_official 135:067cc8ba23da 387
mbed_official 135:067cc8ba23da 388 /* Warning: values are obtained with external xtal or clock = 8 MHz */
mbed_official 135:067cc8ba23da 389 /* SYSCLK = 72 MHz (8 MHz * 9) */
mbed_official 135:067cc8ba23da 390 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 135:067cc8ba23da 391 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9
mbed_official 135:067cc8ba23da 392 | RCC_CFGR_HPRE_DIV1 /* HCLK = 72 MHz */
mbed_official 135:067cc8ba23da 393 | RCC_CFGR_PPRE2_DIV1 /* PCLK2 = 72 MHz */
mbed_official 135:067cc8ba23da 394 | RCC_CFGR_PPRE1_DIV2); /* PCLK1 = 36 MHz */
mbed_official 135:067cc8ba23da 395 /* USBCLK = 48 MHz (72 MHz / 1.5) --> USB OK */
mbed_official 135:067cc8ba23da 396
mbed_official 135:067cc8ba23da 397 /* Enable PLL */
mbed_official 135:067cc8ba23da 398 RCC->CR |= RCC_CR_PLLON;
mbed_official 135:067cc8ba23da 399
mbed_official 135:067cc8ba23da 400 /* Wait till PLL is ready */
mbed_official 135:067cc8ba23da 401 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 135:067cc8ba23da 402 {
mbed_official 135:067cc8ba23da 403 }
mbed_official 135:067cc8ba23da 404
mbed_official 135:067cc8ba23da 405 /* Select PLL as system clock source */
mbed_official 135:067cc8ba23da 406 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 135:067cc8ba23da 407 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 135:067cc8ba23da 408
mbed_official 135:067cc8ba23da 409 /* Wait till PLL is used as system clock source */
mbed_official 135:067cc8ba23da 410 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
mbed_official 135:067cc8ba23da 411 {
mbed_official 135:067cc8ba23da 412 }
mbed_official 137:f9a97811e98c 413
mbed_official 135:067cc8ba23da 414 return 1; // OK
mbed_official 135:067cc8ba23da 415 }
mbed_official 135:067cc8ba23da 416 else
mbed_official 135:067cc8ba23da 417 {
mbed_official 135:067cc8ba23da 418 return 0; // FAIL
mbed_official 135:067cc8ba23da 419 }
mbed_official 135:067cc8ba23da 420 }
mbed_official 135:067cc8ba23da 421 #endif
mbed_official 135:067cc8ba23da 422
mbed_official 125:23cc3068a9e4 423 /******************************************************************************/
mbed_official 125:23cc3068a9e4 424 /* PLL (clocked by HSI) used as System clock source */
mbed_official 125:23cc3068a9e4 425 /******************************************************************************/
mbed_official 135:067cc8ba23da 426 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 135:067cc8ba23da 427 {
mbed_official 125:23cc3068a9e4 428 /* At this stage the HSI is already enabled and used as System clock source */
mbed_official 125:23cc3068a9e4 429
mbed_official 135:067cc8ba23da 430 /* Enable prefetch buffer and set flash latency
mbed_official 135:067cc8ba23da 431 0WS for 0 < SYSCLK <= 24 MHz
mbed_official 135:067cc8ba23da 432 1WS for 24 < SYSCLK <= 48 MHz
mbed_official 135:067cc8ba23da 433 2WS for 48 < SYSCLK <= 72 MHz */
mbed_official 135:067cc8ba23da 434 FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; /* 2 WS */
mbed_official 135:067cc8ba23da 435
mbed_official 135:067cc8ba23da 436 /* SYSCLK = 64 MHz (8 MHz / 2 * 16) */
mbed_official 125:23cc3068a9e4 437 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 135:067cc8ba23da 438 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL16
mbed_official 135:067cc8ba23da 439 | RCC_CFGR_HPRE_DIV1 /* HCLK = 64 MHz */
mbed_official 135:067cc8ba23da 440 | RCC_CFGR_PPRE2_DIV1 /* PCLK2 = 64 MHz */
mbed_official 135:067cc8ba23da 441 | RCC_CFGR_PPRE1_DIV2); /* PCLK1 = 32 MHz */
mbed_official 135:067cc8ba23da 442 /* USBCLK = 42.667 MHz (64 MHz / 1.5) --> USB NOT POSSIBLE */
mbed_official 125:23cc3068a9e4 443
mbed_official 125:23cc3068a9e4 444 /* Enable PLL */
mbed_official 125:23cc3068a9e4 445 RCC->CR |= RCC_CR_PLLON;
mbed_official 125:23cc3068a9e4 446
mbed_official 125:23cc3068a9e4 447 /* Wait till PLL is ready */
mbed_official 125:23cc3068a9e4 448 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 125:23cc3068a9e4 449 {
mbed_official 125:23cc3068a9e4 450 }
mbed_official 125:23cc3068a9e4 451
mbed_official 125:23cc3068a9e4 452 /* Select PLL as system clock source */
mbed_official 125:23cc3068a9e4 453 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 125:23cc3068a9e4 454 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 125:23cc3068a9e4 455
mbed_official 125:23cc3068a9e4 456 /* Wait till PLL is used as system clock source */
mbed_official 125:23cc3068a9e4 457 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
mbed_official 125:23cc3068a9e4 458 {
mbed_official 125:23cc3068a9e4 459 }
mbed_official 135:067cc8ba23da 460
mbed_official 135:067cc8ba23da 461 return 1; // OK
mbed_official 125:23cc3068a9e4 462 }
mbed_official 125:23cc3068a9e4 463
mbed_official 125:23cc3068a9e4 464 /**
mbed_official 125:23cc3068a9e4 465 * @}
mbed_official 125:23cc3068a9e4 466 */
mbed_official 125:23cc3068a9e4 467
mbed_official 125:23cc3068a9e4 468 /**
mbed_official 125:23cc3068a9e4 469 * @}
mbed_official 125:23cc3068a9e4 470 */
mbed_official 125:23cc3068a9e4 471
mbed_official 125:23cc3068a9e4 472 /**
mbed_official 125:23cc3068a9e4 473 * @}
mbed_official 125:23cc3068a9e4 474 */
mbed_official 125:23cc3068a9e4 475
mbed_official 125:23cc3068a9e4 476 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/