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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_STM/TARGET_NUCLEO_F030R8/stm32f0xx_hal_spi.h@340:28d1f895c6fe, 2014-10-09 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Oct 09 08:15:07 2014 +0100
- Revision:
- 340:28d1f895c6fe
Synchronized with git revision b5a4c8e80393336b2656fb29ab46d405d3068602
Full URL: https://github.com/mbedmicro/mbed/commit/b5a4c8e80393336b2656fb29ab46d405d3068602/
HAL: nrf51822 - Few fixes for PWM and Serial
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 340:28d1f895c6fe | 1 | /** |
| mbed_official | 340:28d1f895c6fe | 2 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 3 | * @file stm32f0xx_hal_spi.h |
| mbed_official | 340:28d1f895c6fe | 4 | * @author MCD Application Team |
| mbed_official | 340:28d1f895c6fe | 5 | * @version V1.1.0 |
| mbed_official | 340:28d1f895c6fe | 6 | * @date 03-Oct-2014 |
| mbed_official | 340:28d1f895c6fe | 7 | * @brief Header file of SPI HAL module. |
| mbed_official | 340:28d1f895c6fe | 8 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 9 | * @attention |
| mbed_official | 340:28d1f895c6fe | 10 | * |
| mbed_official | 340:28d1f895c6fe | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 340:28d1f895c6fe | 12 | * |
| mbed_official | 340:28d1f895c6fe | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 340:28d1f895c6fe | 14 | * are permitted provided that the following conditions are met: |
| mbed_official | 340:28d1f895c6fe | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 340:28d1f895c6fe | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 340:28d1f895c6fe | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 340:28d1f895c6fe | 18 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 340:28d1f895c6fe | 19 | * and/or other materials provided with the distribution. |
| mbed_official | 340:28d1f895c6fe | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 340:28d1f895c6fe | 21 | * may be used to endorse or promote products derived from this software |
| mbed_official | 340:28d1f895c6fe | 22 | * without specific prior written permission. |
| mbed_official | 340:28d1f895c6fe | 23 | * |
| mbed_official | 340:28d1f895c6fe | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 340:28d1f895c6fe | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 340:28d1f895c6fe | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 340:28d1f895c6fe | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 340:28d1f895c6fe | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 340:28d1f895c6fe | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 340:28d1f895c6fe | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 340:28d1f895c6fe | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 340:28d1f895c6fe | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 340:28d1f895c6fe | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 340:28d1f895c6fe | 34 | * |
| mbed_official | 340:28d1f895c6fe | 35 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 36 | */ |
| mbed_official | 340:28d1f895c6fe | 37 | |
| mbed_official | 340:28d1f895c6fe | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 39 | #ifndef __STM32F0xx_HAL_SPI_H |
| mbed_official | 340:28d1f895c6fe | 40 | #define __STM32F0xx_HAL_SPI_H |
| mbed_official | 340:28d1f895c6fe | 41 | |
| mbed_official | 340:28d1f895c6fe | 42 | #ifdef __cplusplus |
| mbed_official | 340:28d1f895c6fe | 43 | extern "C" { |
| mbed_official | 340:28d1f895c6fe | 44 | #endif |
| mbed_official | 340:28d1f895c6fe | 45 | |
| mbed_official | 340:28d1f895c6fe | 46 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 47 | #include "stm32f0xx_hal_def.h" |
| mbed_official | 340:28d1f895c6fe | 48 | |
| mbed_official | 340:28d1f895c6fe | 49 | /** @addtogroup STM32F0xx_HAL_Driver |
| mbed_official | 340:28d1f895c6fe | 50 | * @{ |
| mbed_official | 340:28d1f895c6fe | 51 | */ |
| mbed_official | 340:28d1f895c6fe | 52 | |
| mbed_official | 340:28d1f895c6fe | 53 | /** @addtogroup SPI |
| mbed_official | 340:28d1f895c6fe | 54 | * @{ |
| mbed_official | 340:28d1f895c6fe | 55 | */ |
| mbed_official | 340:28d1f895c6fe | 56 | |
| mbed_official | 340:28d1f895c6fe | 57 | /* Exported types ------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 58 | /** @defgroup SPI_Exported_Types SPI Exported Types |
| mbed_official | 340:28d1f895c6fe | 59 | * @{ |
| mbed_official | 340:28d1f895c6fe | 60 | */ |
| mbed_official | 340:28d1f895c6fe | 61 | |
| mbed_official | 340:28d1f895c6fe | 62 | /** |
| mbed_official | 340:28d1f895c6fe | 63 | * @brief SPI Configuration Structure definition |
| mbed_official | 340:28d1f895c6fe | 64 | */ |
| mbed_official | 340:28d1f895c6fe | 65 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 66 | { |
| mbed_official | 340:28d1f895c6fe | 67 | uint32_t Mode; /*!< Specifies the SPI operating mode. |
| mbed_official | 340:28d1f895c6fe | 68 | This parameter can be a value of @ref SPI_mode */ |
| mbed_official | 340:28d1f895c6fe | 69 | |
| mbed_official | 340:28d1f895c6fe | 70 | uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. |
| mbed_official | 340:28d1f895c6fe | 71 | This parameter can be a value of @ref SPI_Direction */ |
| mbed_official | 340:28d1f895c6fe | 72 | |
| mbed_official | 340:28d1f895c6fe | 73 | uint32_t DataSize; /*!< Specifies the SPI data size. |
| mbed_official | 340:28d1f895c6fe | 74 | This parameter can be a value of @ref SPI_data_size */ |
| mbed_official | 340:28d1f895c6fe | 75 | |
| mbed_official | 340:28d1f895c6fe | 76 | uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. |
| mbed_official | 340:28d1f895c6fe | 77 | This parameter can be a value of @ref SPI_Clock_Polarity */ |
| mbed_official | 340:28d1f895c6fe | 78 | |
| mbed_official | 340:28d1f895c6fe | 79 | uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. |
| mbed_official | 340:28d1f895c6fe | 80 | This parameter can be a value of @ref SPI_Clock_Phase */ |
| mbed_official | 340:28d1f895c6fe | 81 | |
| mbed_official | 340:28d1f895c6fe | 82 | uint32_t NSS; /*!< Specifies whether the NSS signal is managed by |
| mbed_official | 340:28d1f895c6fe | 83 | hardware (NSS pin) or by software using the SSI bit. |
| mbed_official | 340:28d1f895c6fe | 84 | This parameter can be a value of @ref SPI_Slave_Select_management */ |
| mbed_official | 340:28d1f895c6fe | 85 | |
| mbed_official | 340:28d1f895c6fe | 86 | uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be |
| mbed_official | 340:28d1f895c6fe | 87 | used to configure the transmit and receive SCK clock. |
| mbed_official | 340:28d1f895c6fe | 88 | This parameter can be a value of @ref SPI_BaudRate_Prescaler |
| mbed_official | 340:28d1f895c6fe | 89 | @note The communication clock is derived from the master |
| mbed_official | 340:28d1f895c6fe | 90 | clock. The slave clock does not need to be set. */ |
| mbed_official | 340:28d1f895c6fe | 91 | |
| mbed_official | 340:28d1f895c6fe | 92 | uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. |
| mbed_official | 340:28d1f895c6fe | 93 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ |
| mbed_official | 340:28d1f895c6fe | 94 | |
| mbed_official | 340:28d1f895c6fe | 95 | uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not . |
| mbed_official | 340:28d1f895c6fe | 96 | This parameter can be a value of @ref SPI_TI_mode */ |
| mbed_official | 340:28d1f895c6fe | 97 | |
| mbed_official | 340:28d1f895c6fe | 98 | uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. |
| mbed_official | 340:28d1f895c6fe | 99 | This parameter can be a value of @ref SPI_CRC_Calculation */ |
| mbed_official | 340:28d1f895c6fe | 100 | |
| mbed_official | 340:28d1f895c6fe | 101 | uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. |
| mbed_official | 340:28d1f895c6fe | 102 | This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ |
| mbed_official | 340:28d1f895c6fe | 103 | |
| mbed_official | 340:28d1f895c6fe | 104 | uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. |
| mbed_official | 340:28d1f895c6fe | 105 | CRC Length is only used with Data8 and Data16, not other data size |
| mbed_official | 340:28d1f895c6fe | 106 | This parameter must 0 or 1 or 2*/ |
| mbed_official | 340:28d1f895c6fe | 107 | |
| mbed_official | 340:28d1f895c6fe | 108 | uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . |
| mbed_official | 340:28d1f895c6fe | 109 | This mode is activated by the NSSP bit in the SPIx_CR2 register and |
| mbed_official | 340:28d1f895c6fe | 110 | it takes effect only if the SPI interface is configured as Motorola SPI |
| mbed_official | 340:28d1f895c6fe | 111 | master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, |
| mbed_official | 340:28d1f895c6fe | 112 | CPOL setting is ignored).. */ |
| mbed_official | 340:28d1f895c6fe | 113 | } SPI_InitTypeDef; |
| mbed_official | 340:28d1f895c6fe | 114 | |
| mbed_official | 340:28d1f895c6fe | 115 | /** |
| mbed_official | 340:28d1f895c6fe | 116 | * @brief HAL State structures definition |
| mbed_official | 340:28d1f895c6fe | 117 | */ |
| mbed_official | 340:28d1f895c6fe | 118 | typedef enum |
| mbed_official | 340:28d1f895c6fe | 119 | { |
| mbed_official | 340:28d1f895c6fe | 120 | HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */ |
| mbed_official | 340:28d1f895c6fe | 121 | HAL_SPI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ |
| mbed_official | 340:28d1f895c6fe | 122 | HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ |
| mbed_official | 340:28d1f895c6fe | 123 | HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */ |
| mbed_official | 340:28d1f895c6fe | 124 | HAL_SPI_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */ |
| mbed_official | 340:28d1f895c6fe | 125 | HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */ |
| mbed_official | 340:28d1f895c6fe | 126 | HAL_SPI_STATE_TIMEOUT = 0x06, /*!< Timeout state */ |
| mbed_official | 340:28d1f895c6fe | 127 | HAL_SPI_STATE_ERROR = 0x07 /*!< Data Transmission and Reception process is ongoing */ |
| mbed_official | 340:28d1f895c6fe | 128 | |
| mbed_official | 340:28d1f895c6fe | 129 | }HAL_SPI_StateTypeDef; |
| mbed_official | 340:28d1f895c6fe | 130 | |
| mbed_official | 340:28d1f895c6fe | 131 | /** |
| mbed_official | 340:28d1f895c6fe | 132 | * @brief HAL SPI Error Code structure definition |
| mbed_official | 340:28d1f895c6fe | 133 | */ |
| mbed_official | 340:28d1f895c6fe | 134 | typedef enum |
| mbed_official | 340:28d1f895c6fe | 135 | { |
| mbed_official | 340:28d1f895c6fe | 136 | HAL_SPI_ERROR_NONE = 0x00, /*!< No error */ |
| mbed_official | 340:28d1f895c6fe | 137 | HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */ |
| mbed_official | 340:28d1f895c6fe | 138 | HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */ |
| mbed_official | 340:28d1f895c6fe | 139 | HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */ |
| mbed_official | 340:28d1f895c6fe | 140 | HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */ |
| mbed_official | 340:28d1f895c6fe | 141 | HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */ |
| mbed_official | 340:28d1f895c6fe | 142 | HAL_SPI_ERROR_FLAG = 0x20, /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */ |
| mbed_official | 340:28d1f895c6fe | 143 | HAL_SPI_ERROR_UNKNOW = 0x40, /*!< Unknow Error error */ |
| mbed_official | 340:28d1f895c6fe | 144 | }HAL_SPI_ErrorTypeDef; |
| mbed_official | 340:28d1f895c6fe | 145 | |
| mbed_official | 340:28d1f895c6fe | 146 | /** |
| mbed_official | 340:28d1f895c6fe | 147 | * @brief SPI handle Structure definition |
| mbed_official | 340:28d1f895c6fe | 148 | */ |
| mbed_official | 340:28d1f895c6fe | 149 | typedef struct __SPI_HandleTypeDef |
| mbed_official | 340:28d1f895c6fe | 150 | { |
| mbed_official | 340:28d1f895c6fe | 151 | SPI_TypeDef *Instance; /* SPI registers base address */ |
| mbed_official | 340:28d1f895c6fe | 152 | |
| mbed_official | 340:28d1f895c6fe | 153 | SPI_InitTypeDef Init; /* SPI communication parameters */ |
| mbed_official | 340:28d1f895c6fe | 154 | |
| mbed_official | 340:28d1f895c6fe | 155 | uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */ |
| mbed_official | 340:28d1f895c6fe | 156 | |
| mbed_official | 340:28d1f895c6fe | 157 | uint16_t TxXferSize; /* SPI Tx Transfer size */ |
| mbed_official | 340:28d1f895c6fe | 158 | |
| mbed_official | 340:28d1f895c6fe | 159 | uint16_t TxXferCount; /* SPI Tx Transfer Counter */ |
| mbed_official | 340:28d1f895c6fe | 160 | |
| mbed_official | 340:28d1f895c6fe | 161 | uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */ |
| mbed_official | 340:28d1f895c6fe | 162 | |
| mbed_official | 340:28d1f895c6fe | 163 | uint16_t RxXferSize; /* SPI Rx Transfer size */ |
| mbed_official | 340:28d1f895c6fe | 164 | |
| mbed_official | 340:28d1f895c6fe | 165 | uint16_t RxXferCount; /* SPI Rx Transfer Counter */ |
| mbed_official | 340:28d1f895c6fe | 166 | |
| mbed_official | 340:28d1f895c6fe | 167 | uint32_t CRCSize; /* SPI CRC size used for the transfer */ |
| mbed_official | 340:28d1f895c6fe | 168 | |
| mbed_official | 340:28d1f895c6fe | 169 | void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler */ |
| mbed_official | 340:28d1f895c6fe | 170 | |
| mbed_official | 340:28d1f895c6fe | 171 | void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler */ |
| mbed_official | 340:28d1f895c6fe | 172 | |
| mbed_official | 340:28d1f895c6fe | 173 | DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */ |
| mbed_official | 340:28d1f895c6fe | 174 | |
| mbed_official | 340:28d1f895c6fe | 175 | DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */ |
| mbed_official | 340:28d1f895c6fe | 176 | |
| mbed_official | 340:28d1f895c6fe | 177 | HAL_LockTypeDef Lock; /* Locking object */ |
| mbed_official | 340:28d1f895c6fe | 178 | |
| mbed_official | 340:28d1f895c6fe | 179 | HAL_SPI_StateTypeDef State; /* SPI communication state */ |
| mbed_official | 340:28d1f895c6fe | 180 | |
| mbed_official | 340:28d1f895c6fe | 181 | HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */ |
| mbed_official | 340:28d1f895c6fe | 182 | |
| mbed_official | 340:28d1f895c6fe | 183 | }SPI_HandleTypeDef; |
| mbed_official | 340:28d1f895c6fe | 184 | |
| mbed_official | 340:28d1f895c6fe | 185 | /** |
| mbed_official | 340:28d1f895c6fe | 186 | * @} |
| mbed_official | 340:28d1f895c6fe | 187 | */ |
| mbed_official | 340:28d1f895c6fe | 188 | |
| mbed_official | 340:28d1f895c6fe | 189 | /* Exported constants --------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 190 | |
| mbed_official | 340:28d1f895c6fe | 191 | /** @defgroup SPI_Exported_Constants SPI Exported Constants |
| mbed_official | 340:28d1f895c6fe | 192 | * @{ |
| mbed_official | 340:28d1f895c6fe | 193 | */ |
| mbed_official | 340:28d1f895c6fe | 194 | |
| mbed_official | 340:28d1f895c6fe | 195 | /** @defgroup SPI_mode SPI mode |
| mbed_official | 340:28d1f895c6fe | 196 | * @{ |
| mbed_official | 340:28d1f895c6fe | 197 | */ |
| mbed_official | 340:28d1f895c6fe | 198 | |
| mbed_official | 340:28d1f895c6fe | 199 | #define SPI_MODE_SLAVE ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 200 | #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) |
| mbed_official | 340:28d1f895c6fe | 201 | #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ |
| mbed_official | 340:28d1f895c6fe | 202 | ((MODE) == SPI_MODE_MASTER)) |
| mbed_official | 340:28d1f895c6fe | 203 | /** |
| mbed_official | 340:28d1f895c6fe | 204 | * @} |
| mbed_official | 340:28d1f895c6fe | 205 | */ |
| mbed_official | 340:28d1f895c6fe | 206 | |
| mbed_official | 340:28d1f895c6fe | 207 | /** @defgroup SPI_Direction SPI Direction |
| mbed_official | 340:28d1f895c6fe | 208 | * @{ |
| mbed_official | 340:28d1f895c6fe | 209 | */ |
| mbed_official | 340:28d1f895c6fe | 210 | #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 211 | #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY |
| mbed_official | 340:28d1f895c6fe | 212 | #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE |
| mbed_official | 340:28d1f895c6fe | 213 | |
| mbed_official | 340:28d1f895c6fe | 214 | #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ |
| mbed_official | 340:28d1f895c6fe | 215 | ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\ |
| mbed_official | 340:28d1f895c6fe | 216 | ((MODE) == SPI_DIRECTION_1LINE)) |
| mbed_official | 340:28d1f895c6fe | 217 | |
| mbed_official | 340:28d1f895c6fe | 218 | #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) |
| mbed_official | 340:28d1f895c6fe | 219 | |
| mbed_official | 340:28d1f895c6fe | 220 | #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ |
| mbed_official | 340:28d1f895c6fe | 221 | ((MODE) == SPI_DIRECTION_1LINE)) |
| mbed_official | 340:28d1f895c6fe | 222 | /** |
| mbed_official | 340:28d1f895c6fe | 223 | * @} |
| mbed_official | 340:28d1f895c6fe | 224 | */ |
| mbed_official | 340:28d1f895c6fe | 225 | |
| mbed_official | 340:28d1f895c6fe | 226 | /** @defgroup SPI_data_size SPI data size |
| mbed_official | 340:28d1f895c6fe | 227 | * @{ |
| mbed_official | 340:28d1f895c6fe | 228 | */ |
| mbed_official | 340:28d1f895c6fe | 229 | |
| mbed_official | 340:28d1f895c6fe | 230 | #define SPI_DATASIZE_4BIT ((uint16_t)0x0300) |
| mbed_official | 340:28d1f895c6fe | 231 | #define SPI_DATASIZE_5BIT ((uint16_t)0x0400) |
| mbed_official | 340:28d1f895c6fe | 232 | #define SPI_DATASIZE_6BIT ((uint16_t)0x0500) |
| mbed_official | 340:28d1f895c6fe | 233 | #define SPI_DATASIZE_7BIT ((uint16_t)0x0600) |
| mbed_official | 340:28d1f895c6fe | 234 | #define SPI_DATASIZE_8BIT ((uint16_t)0x0700) |
| mbed_official | 340:28d1f895c6fe | 235 | #define SPI_DATASIZE_9BIT ((uint16_t)0x0800) |
| mbed_official | 340:28d1f895c6fe | 236 | #define SPI_DATASIZE_10BIT ((uint16_t)0x0900) |
| mbed_official | 340:28d1f895c6fe | 237 | #define SPI_DATASIZE_11BIT ((uint16_t)0x0A00) |
| mbed_official | 340:28d1f895c6fe | 238 | #define SPI_DATASIZE_12BIT ((uint16_t)0x0B00) |
| mbed_official | 340:28d1f895c6fe | 239 | #define SPI_DATASIZE_13BIT ((uint16_t)0x0C00) |
| mbed_official | 340:28d1f895c6fe | 240 | #define SPI_DATASIZE_14BIT ((uint16_t)0x0D00) |
| mbed_official | 340:28d1f895c6fe | 241 | #define SPI_DATASIZE_15BIT ((uint16_t)0x0E00) |
| mbed_official | 340:28d1f895c6fe | 242 | #define SPI_DATASIZE_16BIT ((uint16_t)0x0F00) |
| mbed_official | 340:28d1f895c6fe | 243 | #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ |
| mbed_official | 340:28d1f895c6fe | 244 | ((DATASIZE) == SPI_DATASIZE_15BIT) || \ |
| mbed_official | 340:28d1f895c6fe | 245 | ((DATASIZE) == SPI_DATASIZE_14BIT) || \ |
| mbed_official | 340:28d1f895c6fe | 246 | ((DATASIZE) == SPI_DATASIZE_13BIT) || \ |
| mbed_official | 340:28d1f895c6fe | 247 | ((DATASIZE) == SPI_DATASIZE_12BIT) || \ |
| mbed_official | 340:28d1f895c6fe | 248 | ((DATASIZE) == SPI_DATASIZE_11BIT) || \ |
| mbed_official | 340:28d1f895c6fe | 249 | ((DATASIZE) == SPI_DATASIZE_10BIT) || \ |
| mbed_official | 340:28d1f895c6fe | 250 | ((DATASIZE) == SPI_DATASIZE_9BIT) || \ |
| mbed_official | 340:28d1f895c6fe | 251 | ((DATASIZE) == SPI_DATASIZE_8BIT) || \ |
| mbed_official | 340:28d1f895c6fe | 252 | ((DATASIZE) == SPI_DATASIZE_7BIT) || \ |
| mbed_official | 340:28d1f895c6fe | 253 | ((DATASIZE) == SPI_DATASIZE_6BIT) || \ |
| mbed_official | 340:28d1f895c6fe | 254 | ((DATASIZE) == SPI_DATASIZE_5BIT) || \ |
| mbed_official | 340:28d1f895c6fe | 255 | ((DATASIZE) == SPI_DATASIZE_4BIT)) |
| mbed_official | 340:28d1f895c6fe | 256 | |
| mbed_official | 340:28d1f895c6fe | 257 | /** |
| mbed_official | 340:28d1f895c6fe | 258 | * @} |
| mbed_official | 340:28d1f895c6fe | 259 | */ |
| mbed_official | 340:28d1f895c6fe | 260 | |
| mbed_official | 340:28d1f895c6fe | 261 | /** @defgroup SPI_Clock_Polarity SPI Clock Polarity |
| mbed_official | 340:28d1f895c6fe | 262 | * @{ |
| mbed_official | 340:28d1f895c6fe | 263 | */ |
| mbed_official | 340:28d1f895c6fe | 264 | |
| mbed_official | 340:28d1f895c6fe | 265 | #define SPI_POLARITY_LOW ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 266 | #define SPI_POLARITY_HIGH SPI_CR1_CPOL |
| mbed_official | 340:28d1f895c6fe | 267 | #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ |
| mbed_official | 340:28d1f895c6fe | 268 | ((CPOL) == SPI_POLARITY_HIGH)) |
| mbed_official | 340:28d1f895c6fe | 269 | /** |
| mbed_official | 340:28d1f895c6fe | 270 | * @} |
| mbed_official | 340:28d1f895c6fe | 271 | */ |
| mbed_official | 340:28d1f895c6fe | 272 | |
| mbed_official | 340:28d1f895c6fe | 273 | /** @defgroup SPI_Clock_Phase SPI Clock Phase |
| mbed_official | 340:28d1f895c6fe | 274 | * @{ |
| mbed_official | 340:28d1f895c6fe | 275 | */ |
| mbed_official | 340:28d1f895c6fe | 276 | |
| mbed_official | 340:28d1f895c6fe | 277 | #define SPI_PHASE_1EDGE ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 278 | #define SPI_PHASE_2EDGE SPI_CR1_CPHA |
| mbed_official | 340:28d1f895c6fe | 279 | #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ |
| mbed_official | 340:28d1f895c6fe | 280 | ((CPHA) == SPI_PHASE_2EDGE)) |
| mbed_official | 340:28d1f895c6fe | 281 | /** |
| mbed_official | 340:28d1f895c6fe | 282 | * @} |
| mbed_official | 340:28d1f895c6fe | 283 | */ |
| mbed_official | 340:28d1f895c6fe | 284 | |
| mbed_official | 340:28d1f895c6fe | 285 | /** @defgroup SPI_Slave_Select_management SPI Slave Select management |
| mbed_official | 340:28d1f895c6fe | 286 | * @{ |
| mbed_official | 340:28d1f895c6fe | 287 | */ |
| mbed_official | 340:28d1f895c6fe | 288 | |
| mbed_official | 340:28d1f895c6fe | 289 | #define SPI_NSS_SOFT SPI_CR1_SSM |
| mbed_official | 340:28d1f895c6fe | 290 | #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 291 | #define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000) |
| mbed_official | 340:28d1f895c6fe | 292 | #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ |
| mbed_official | 340:28d1f895c6fe | 293 | ((NSS) == SPI_NSS_HARD_INPUT) || \ |
| mbed_official | 340:28d1f895c6fe | 294 | ((NSS) == SPI_NSS_HARD_OUTPUT)) |
| mbed_official | 340:28d1f895c6fe | 295 | |
| mbed_official | 340:28d1f895c6fe | 296 | /** |
| mbed_official | 340:28d1f895c6fe | 297 | * @} |
| mbed_official | 340:28d1f895c6fe | 298 | */ |
| mbed_official | 340:28d1f895c6fe | 299 | |
| mbed_official | 340:28d1f895c6fe | 300 | /** @defgroup SPI_NSS_pulse_management SPI NSS pulse management |
| mbed_official | 340:28d1f895c6fe | 301 | * @{ |
| mbed_official | 340:28d1f895c6fe | 302 | */ |
| mbed_official | 340:28d1f895c6fe | 303 | #define SPI_NSS_PULSE_ENABLED SPI_CR2_NSSP |
| mbed_official | 340:28d1f895c6fe | 304 | #define SPI_NSS_PULSE_DISABLED ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 305 | |
| mbed_official | 340:28d1f895c6fe | 306 | #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLED) || \ |
| mbed_official | 340:28d1f895c6fe | 307 | ((NSSP) == SPI_NSS_PULSE_DISABLED)) |
| mbed_official | 340:28d1f895c6fe | 308 | |
| mbed_official | 340:28d1f895c6fe | 309 | /** |
| mbed_official | 340:28d1f895c6fe | 310 | * @} |
| mbed_official | 340:28d1f895c6fe | 311 | */ |
| mbed_official | 340:28d1f895c6fe | 312 | |
| mbed_official | 340:28d1f895c6fe | 313 | |
| mbed_official | 340:28d1f895c6fe | 314 | /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler |
| mbed_official | 340:28d1f895c6fe | 315 | * @{ |
| mbed_official | 340:28d1f895c6fe | 316 | */ |
| mbed_official | 340:28d1f895c6fe | 317 | |
| mbed_official | 340:28d1f895c6fe | 318 | #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 319 | #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008) |
| mbed_official | 340:28d1f895c6fe | 320 | #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 321 | #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018) |
| mbed_official | 340:28d1f895c6fe | 322 | #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020) |
| mbed_official | 340:28d1f895c6fe | 323 | #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028) |
| mbed_official | 340:28d1f895c6fe | 324 | #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030) |
| mbed_official | 340:28d1f895c6fe | 325 | #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038) |
| mbed_official | 340:28d1f895c6fe | 326 | #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ |
| mbed_official | 340:28d1f895c6fe | 327 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ |
| mbed_official | 340:28d1f895c6fe | 328 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ |
| mbed_official | 340:28d1f895c6fe | 329 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ |
| mbed_official | 340:28d1f895c6fe | 330 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ |
| mbed_official | 340:28d1f895c6fe | 331 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ |
| mbed_official | 340:28d1f895c6fe | 332 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ |
| mbed_official | 340:28d1f895c6fe | 333 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) |
| mbed_official | 340:28d1f895c6fe | 334 | /** |
| mbed_official | 340:28d1f895c6fe | 335 | * @} |
| mbed_official | 340:28d1f895c6fe | 336 | */ |
| mbed_official | 340:28d1f895c6fe | 337 | |
| mbed_official | 340:28d1f895c6fe | 338 | /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission |
| mbed_official | 340:28d1f895c6fe | 339 | * @{ |
| mbed_official | 340:28d1f895c6fe | 340 | */ |
| mbed_official | 340:28d1f895c6fe | 341 | |
| mbed_official | 340:28d1f895c6fe | 342 | #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 343 | #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST |
| mbed_official | 340:28d1f895c6fe | 344 | #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ |
| mbed_official | 340:28d1f895c6fe | 345 | ((BIT) == SPI_FIRSTBIT_LSB)) |
| mbed_official | 340:28d1f895c6fe | 346 | /** |
| mbed_official | 340:28d1f895c6fe | 347 | * @} |
| mbed_official | 340:28d1f895c6fe | 348 | */ |
| mbed_official | 340:28d1f895c6fe | 349 | |
| mbed_official | 340:28d1f895c6fe | 350 | /** @defgroup SPI_TI_mode SPI TI mode |
| mbed_official | 340:28d1f895c6fe | 351 | * @{ |
| mbed_official | 340:28d1f895c6fe | 352 | */ |
| mbed_official | 340:28d1f895c6fe | 353 | |
| mbed_official | 340:28d1f895c6fe | 354 | #define SPI_TIMODE_DISABLED ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 355 | #define SPI_TIMODE_ENABLED SPI_CR2_FRF |
| mbed_official | 340:28d1f895c6fe | 356 | #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \ |
| mbed_official | 340:28d1f895c6fe | 357 | ((MODE) == SPI_TIMODE_ENABLED)) |
| mbed_official | 340:28d1f895c6fe | 358 | /** |
| mbed_official | 340:28d1f895c6fe | 359 | * @} |
| mbed_official | 340:28d1f895c6fe | 360 | */ |
| mbed_official | 340:28d1f895c6fe | 361 | |
| mbed_official | 340:28d1f895c6fe | 362 | /** @defgroup SPI_CRC_Calculation SPI CRC Calculation |
| mbed_official | 340:28d1f895c6fe | 363 | * @{ |
| mbed_official | 340:28d1f895c6fe | 364 | */ |
| mbed_official | 340:28d1f895c6fe | 365 | |
| mbed_official | 340:28d1f895c6fe | 366 | #define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 367 | #define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN |
| mbed_official | 340:28d1f895c6fe | 368 | #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \ |
| mbed_official | 340:28d1f895c6fe | 369 | ((CALCULATION) == SPI_CRCCALCULATION_ENABLED)) |
| mbed_official | 340:28d1f895c6fe | 370 | /** |
| mbed_official | 340:28d1f895c6fe | 371 | * @} |
| mbed_official | 340:28d1f895c6fe | 372 | */ |
| mbed_official | 340:28d1f895c6fe | 373 | |
| mbed_official | 340:28d1f895c6fe | 374 | /** @defgroup SPI_CRC_length SPI CRC length |
| mbed_official | 340:28d1f895c6fe | 375 | * @{ |
| mbed_official | 340:28d1f895c6fe | 376 | * This parameter can be one of the following values: |
| mbed_official | 340:28d1f895c6fe | 377 | * SPI_CRC_LENGTH_DATASIZE: aligned with the data size |
| mbed_official | 340:28d1f895c6fe | 378 | * SPI_CRC_LENGTH_8BIT : CRC 8bit |
| mbed_official | 340:28d1f895c6fe | 379 | * SPI_CRC_LENGTH_16BIT : CRC 16bit |
| mbed_official | 340:28d1f895c6fe | 380 | */ |
| mbed_official | 340:28d1f895c6fe | 381 | #define SPI_CRC_LENGTH_DATASIZE 0 |
| mbed_official | 340:28d1f895c6fe | 382 | #define SPI_CRC_LENGTH_8BIT 1 |
| mbed_official | 340:28d1f895c6fe | 383 | #define SPI_CRC_LENGTH_16BIT 2 |
| mbed_official | 340:28d1f895c6fe | 384 | #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\ |
| mbed_official | 340:28d1f895c6fe | 385 | ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ |
| mbed_official | 340:28d1f895c6fe | 386 | ((LENGTH) == SPI_CRC_LENGTH_16BIT)) |
| mbed_official | 340:28d1f895c6fe | 387 | /** |
| mbed_official | 340:28d1f895c6fe | 388 | * @} |
| mbed_official | 340:28d1f895c6fe | 389 | */ |
| mbed_official | 340:28d1f895c6fe | 390 | |
| mbed_official | 340:28d1f895c6fe | 391 | /** @defgroup SPI_FIFO_reception_threshold SPI FIFO reception threshold |
| mbed_official | 340:28d1f895c6fe | 392 | * @{ |
| mbed_official | 340:28d1f895c6fe | 393 | * This parameter can be one of the following values: |
| mbed_official | 340:28d1f895c6fe | 394 | * SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO |
| mbed_official | 340:28d1f895c6fe | 395 | * level is greater or equal to 1/2(16-bits). |
| mbed_official | 340:28d1f895c6fe | 396 | * SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO |
| mbed_official | 340:28d1f895c6fe | 397 | * level is greater or equal to 1/4(8 bits). |
| mbed_official | 340:28d1f895c6fe | 398 | */ |
| mbed_official | 340:28d1f895c6fe | 399 | #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH |
| mbed_official | 340:28d1f895c6fe | 400 | #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH |
| mbed_official | 340:28d1f895c6fe | 401 | #define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x0) |
| mbed_official | 340:28d1f895c6fe | 402 | |
| mbed_official | 340:28d1f895c6fe | 403 | /** |
| mbed_official | 340:28d1f895c6fe | 404 | * @} |
| mbed_official | 340:28d1f895c6fe | 405 | */ |
| mbed_official | 340:28d1f895c6fe | 406 | |
| mbed_official | 340:28d1f895c6fe | 407 | /** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition |
| mbed_official | 340:28d1f895c6fe | 408 | * @brief SPI Interrupt definition |
| mbed_official | 340:28d1f895c6fe | 409 | * Elements values convention: 0xXXXXXXXX |
| mbed_official | 340:28d1f895c6fe | 410 | * - XXXXXXXX : Interrupt control mask |
| mbed_official | 340:28d1f895c6fe | 411 | * @{ |
| mbed_official | 340:28d1f895c6fe | 412 | */ |
| mbed_official | 340:28d1f895c6fe | 413 | #define SPI_IT_TXE SPI_CR2_TXEIE |
| mbed_official | 340:28d1f895c6fe | 414 | #define SPI_IT_RXNE SPI_CR2_RXNEIE |
| mbed_official | 340:28d1f895c6fe | 415 | #define SPI_IT_ERR SPI_CR2_ERRIE |
| mbed_official | 340:28d1f895c6fe | 416 | /** |
| mbed_official | 340:28d1f895c6fe | 417 | * @} |
| mbed_official | 340:28d1f895c6fe | 418 | */ |
| mbed_official | 340:28d1f895c6fe | 419 | |
| mbed_official | 340:28d1f895c6fe | 420 | |
| mbed_official | 340:28d1f895c6fe | 421 | /** @defgroup SPI_Flag_definition SPI Flag definition |
| mbed_official | 340:28d1f895c6fe | 422 | * @brief Flag definition |
| mbed_official | 340:28d1f895c6fe | 423 | * Elements values convention: 0xXXXXYYYY |
| mbed_official | 340:28d1f895c6fe | 424 | * - XXXX : Flag register Index |
| mbed_official | 340:28d1f895c6fe | 425 | * - YYYY : Flag mask |
| mbed_official | 340:28d1f895c6fe | 426 | * @{ |
| mbed_official | 340:28d1f895c6fe | 427 | */ |
| mbed_official | 340:28d1f895c6fe | 428 | #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ |
| mbed_official | 340:28d1f895c6fe | 429 | #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ |
| mbed_official | 340:28d1f895c6fe | 430 | #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ |
| mbed_official | 340:28d1f895c6fe | 431 | #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ |
| mbed_official | 340:28d1f895c6fe | 432 | #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ |
| mbed_official | 340:28d1f895c6fe | 433 | #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ |
| mbed_official | 340:28d1f895c6fe | 434 | #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ |
| mbed_official | 340:28d1f895c6fe | 435 | #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ |
| mbed_official | 340:28d1f895c6fe | 436 | #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ |
| mbed_official | 340:28d1f895c6fe | 437 | /** |
| mbed_official | 340:28d1f895c6fe | 438 | * @} |
| mbed_official | 340:28d1f895c6fe | 439 | */ |
| mbed_official | 340:28d1f895c6fe | 440 | |
| mbed_official | 340:28d1f895c6fe | 441 | /** @defgroup SPI_transmission_fifo_status_level SPI transmission fifo status level |
| mbed_official | 340:28d1f895c6fe | 442 | * @{ |
| mbed_official | 340:28d1f895c6fe | 443 | */ |
| mbed_official | 340:28d1f895c6fe | 444 | |
| mbed_official | 340:28d1f895c6fe | 445 | #define SPI_FTLVL_EMPTY ((uint16_t)0x0000) |
| mbed_official | 340:28d1f895c6fe | 446 | #define SPI_FTLVL_QUARTER_FULL ((uint16_t)0x0800) |
| mbed_official | 340:28d1f895c6fe | 447 | #define SPI_FTLVL_HALF_FULL ((uint16_t)0x1000) |
| mbed_official | 340:28d1f895c6fe | 448 | #define SPI_FTLVL_FULL ((uint16_t)0x1800) |
| mbed_official | 340:28d1f895c6fe | 449 | |
| mbed_official | 340:28d1f895c6fe | 450 | /** |
| mbed_official | 340:28d1f895c6fe | 451 | * @} |
| mbed_official | 340:28d1f895c6fe | 452 | */ |
| mbed_official | 340:28d1f895c6fe | 453 | |
| mbed_official | 340:28d1f895c6fe | 454 | /** @defgroup SPI_reception_fifo_status_level SPI reception fifo status level |
| mbed_official | 340:28d1f895c6fe | 455 | * @{ |
| mbed_official | 340:28d1f895c6fe | 456 | */ |
| mbed_official | 340:28d1f895c6fe | 457 | #define SPI_FRLVL_EMPTY ((uint16_t)0x0000) |
| mbed_official | 340:28d1f895c6fe | 458 | #define SPI_FRLVL_QUARTER_FULL ((uint16_t)0x0200) |
| mbed_official | 340:28d1f895c6fe | 459 | #define SPI_FRLVL_HALF_FULL ((uint16_t)0x0400) |
| mbed_official | 340:28d1f895c6fe | 460 | #define SPI_FRLVL_FULL ((uint16_t)0x0600) |
| mbed_official | 340:28d1f895c6fe | 461 | |
| mbed_official | 340:28d1f895c6fe | 462 | /** |
| mbed_official | 340:28d1f895c6fe | 463 | * @} |
| mbed_official | 340:28d1f895c6fe | 464 | */ |
| mbed_official | 340:28d1f895c6fe | 465 | |
| mbed_official | 340:28d1f895c6fe | 466 | /** |
| mbed_official | 340:28d1f895c6fe | 467 | * @} |
| mbed_official | 340:28d1f895c6fe | 468 | */ |
| mbed_official | 340:28d1f895c6fe | 469 | |
| mbed_official | 340:28d1f895c6fe | 470 | |
| mbed_official | 340:28d1f895c6fe | 471 | /* Exported macros ------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 472 | /** @defgroup SPI_Exported_Macros SPI Exported Macros |
| mbed_official | 340:28d1f895c6fe | 473 | * @{ |
| mbed_official | 340:28d1f895c6fe | 474 | */ |
| mbed_official | 340:28d1f895c6fe | 475 | |
| mbed_official | 340:28d1f895c6fe | 476 | /** @brief Reset SPI handle state |
| mbed_official | 340:28d1f895c6fe | 477 | * @param __HANDLE__: SPI handle. |
| mbed_official | 340:28d1f895c6fe | 478 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 479 | */ |
| mbed_official | 340:28d1f895c6fe | 480 | #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) |
| mbed_official | 340:28d1f895c6fe | 481 | |
| mbed_official | 340:28d1f895c6fe | 482 | /** @brief Enables or disables the specified SPI interrupts. |
| mbed_official | 340:28d1f895c6fe | 483 | * @param __HANDLE__: specifies the SPI Handle. |
| mbed_official | 340:28d1f895c6fe | 484 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 340:28d1f895c6fe | 485 | * @param __INTERRUPT__: specifies the interrupt source to enable or disable. |
| mbed_official | 340:28d1f895c6fe | 486 | * This parameter can be one of the following values: |
| mbed_official | 340:28d1f895c6fe | 487 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| mbed_official | 340:28d1f895c6fe | 488 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| mbed_official | 340:28d1f895c6fe | 489 | * @arg SPI_IT_ERR: Error interrupt enable |
| mbed_official | 340:28d1f895c6fe | 490 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 491 | */ |
| mbed_official | 340:28d1f895c6fe | 492 | |
| mbed_official | 340:28d1f895c6fe | 493 | #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) |
| mbed_official | 340:28d1f895c6fe | 494 | #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__))) |
| mbed_official | 340:28d1f895c6fe | 495 | |
| mbed_official | 340:28d1f895c6fe | 496 | /** @brief Checks if the specified SPI interrupt source is enabled or disabled. |
| mbed_official | 340:28d1f895c6fe | 497 | * @param __HANDLE__: specifies the SPI Handle. |
| mbed_official | 340:28d1f895c6fe | 498 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 340:28d1f895c6fe | 499 | * @param __INTERRUPT__: specifies the SPI interrupt source to check. |
| mbed_official | 340:28d1f895c6fe | 500 | * This parameter can be one of the following values: |
| mbed_official | 340:28d1f895c6fe | 501 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| mbed_official | 340:28d1f895c6fe | 502 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| mbed_official | 340:28d1f895c6fe | 503 | * @arg SPI_IT_ERR: Error interrupt enable |
| mbed_official | 340:28d1f895c6fe | 504 | * @retval The new state of __IT__ (TRUE or FALSE). |
| mbed_official | 340:28d1f895c6fe | 505 | */ |
| mbed_official | 340:28d1f895c6fe | 506 | #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| mbed_official | 340:28d1f895c6fe | 507 | |
| mbed_official | 340:28d1f895c6fe | 508 | /** @brief Checks whether the specified SPI flag is set or not. |
| mbed_official | 340:28d1f895c6fe | 509 | * @param __HANDLE__: specifies the SPI Handle. |
| mbed_official | 340:28d1f895c6fe | 510 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 340:28d1f895c6fe | 511 | * @param __FLAG__: specifies the flag to check. |
| mbed_official | 340:28d1f895c6fe | 512 | * This parameter can be one of the following values: |
| mbed_official | 340:28d1f895c6fe | 513 | * @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
| mbed_official | 340:28d1f895c6fe | 514 | * @arg SPI_FLAG_TXE: Transmit buffer empty flag |
| mbed_official | 340:28d1f895c6fe | 515 | * @arg SPI_FLAG_CRCERR: CRC error flag |
| mbed_official | 340:28d1f895c6fe | 516 | * @arg SPI_FLAG_MODF: Mode fault flag |
| mbed_official | 340:28d1f895c6fe | 517 | * @arg SPI_FLAG_OVR: Overrun flag |
| mbed_official | 340:28d1f895c6fe | 518 | * @arg SPI_FLAG_BSY: Busy flag |
| mbed_official | 340:28d1f895c6fe | 519 | * @arg SPI_FLAG_FRE: Frame format error flag |
| mbed_official | 340:28d1f895c6fe | 520 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| mbed_official | 340:28d1f895c6fe | 521 | */ |
| mbed_official | 340:28d1f895c6fe | 522 | #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| mbed_official | 340:28d1f895c6fe | 523 | |
| mbed_official | 340:28d1f895c6fe | 524 | /** @brief Clears the SPI CRCERR pending flag. |
| mbed_official | 340:28d1f895c6fe | 525 | * @param __HANDLE__: specifies the SPI Handle. |
| mbed_official | 340:28d1f895c6fe | 526 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 340:28d1f895c6fe | 527 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 528 | */ |
| mbed_official | 340:28d1f895c6fe | 529 | #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) |
| mbed_official | 340:28d1f895c6fe | 530 | |
| mbed_official | 340:28d1f895c6fe | 531 | /** @brief Clears the SPI MODF pending flag. |
| mbed_official | 340:28d1f895c6fe | 532 | * @param __HANDLE__: specifies the SPI Handle. |
| mbed_official | 340:28d1f895c6fe | 533 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 340:28d1f895c6fe | 534 | * |
| mbed_official | 340:28d1f895c6fe | 535 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 536 | */ |
| mbed_official | 340:28d1f895c6fe | 537 | #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ |
| mbed_official | 340:28d1f895c6fe | 538 | (__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_SPE);}while(0) |
| mbed_official | 340:28d1f895c6fe | 539 | |
| mbed_official | 340:28d1f895c6fe | 540 | /** @brief Clears the SPI OVR pending flag. |
| mbed_official | 340:28d1f895c6fe | 541 | * @param __HANDLE__: specifies the SPI Handle. |
| mbed_official | 340:28d1f895c6fe | 542 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 340:28d1f895c6fe | 543 | * |
| mbed_official | 340:28d1f895c6fe | 544 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 545 | */ |
| mbed_official | 340:28d1f895c6fe | 546 | #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\ |
| mbed_official | 340:28d1f895c6fe | 547 | (__HANDLE__)->Instance->SR;}while(0) |
| mbed_official | 340:28d1f895c6fe | 548 | |
| mbed_official | 340:28d1f895c6fe | 549 | /** @brief Clears the SPI FRE pending flag. |
| mbed_official | 340:28d1f895c6fe | 550 | * @param __HANDLE__: specifies the SPI Handle. |
| mbed_official | 340:28d1f895c6fe | 551 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 340:28d1f895c6fe | 552 | * |
| mbed_official | 340:28d1f895c6fe | 553 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 554 | */ |
| mbed_official | 340:28d1f895c6fe | 555 | #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR) |
| mbed_official | 340:28d1f895c6fe | 556 | |
| mbed_official | 340:28d1f895c6fe | 557 | /** @brief Enables the SPI. |
| mbed_official | 340:28d1f895c6fe | 558 | * @param __HANDLE__: specifies the SPI Handle. |
| mbed_official | 340:28d1f895c6fe | 559 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 340:28d1f895c6fe | 560 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 561 | */ |
| mbed_official | 340:28d1f895c6fe | 562 | #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) |
| mbed_official | 340:28d1f895c6fe | 563 | |
| mbed_official | 340:28d1f895c6fe | 564 | /** @brief Disables the SPI. |
| mbed_official | 340:28d1f895c6fe | 565 | * @param __HANDLE__: specifies the SPI Handle. |
| mbed_official | 340:28d1f895c6fe | 566 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 340:28d1f895c6fe | 567 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 568 | */ |
| mbed_official | 340:28d1f895c6fe | 569 | #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_SPE)) |
| mbed_official | 340:28d1f895c6fe | 570 | |
| mbed_official | 340:28d1f895c6fe | 571 | /** @brief Sets the SPI transmit-only mode. |
| mbed_official | 340:28d1f895c6fe | 572 | * @param __HANDLE__: specifies the SPI Handle. |
| mbed_official | 340:28d1f895c6fe | 573 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 340:28d1f895c6fe | 574 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 575 | */ |
| mbed_official | 340:28d1f895c6fe | 576 | #define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) |
| mbed_official | 340:28d1f895c6fe | 577 | |
| mbed_official | 340:28d1f895c6fe | 578 | /** @brief Sets the SPI receive-only mode. |
| mbed_official | 340:28d1f895c6fe | 579 | * @param __HANDLE__: specifies the SPI Handle. |
| mbed_official | 340:28d1f895c6fe | 580 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 340:28d1f895c6fe | 581 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 582 | */ |
| mbed_official | 340:28d1f895c6fe | 583 | #define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_BIDIOE)) |
| mbed_official | 340:28d1f895c6fe | 584 | |
| mbed_official | 340:28d1f895c6fe | 585 | /** @brief Resets the CRC calculation of the SPI. |
| mbed_official | 340:28d1f895c6fe | 586 | * @param __HANDLE__: specifies the SPI Handle. |
| mbed_official | 340:28d1f895c6fe | 587 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| mbed_official | 340:28d1f895c6fe | 588 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 589 | */ |
| mbed_official | 340:28d1f895c6fe | 590 | #define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\ |
| mbed_official | 340:28d1f895c6fe | 591 | (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0) |
| mbed_official | 340:28d1f895c6fe | 592 | |
| mbed_official | 340:28d1f895c6fe | 593 | |
| mbed_official | 340:28d1f895c6fe | 594 | #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF)) |
| mbed_official | 340:28d1f895c6fe | 595 | /** |
| mbed_official | 340:28d1f895c6fe | 596 | * @} |
| mbed_official | 340:28d1f895c6fe | 597 | */ |
| mbed_official | 340:28d1f895c6fe | 598 | |
| mbed_official | 340:28d1f895c6fe | 599 | /* Exported functions --------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 600 | /** @addtogroup SPI_Exported_Functions |
| mbed_official | 340:28d1f895c6fe | 601 | * @{ |
| mbed_official | 340:28d1f895c6fe | 602 | */ |
| mbed_official | 340:28d1f895c6fe | 603 | |
| mbed_official | 340:28d1f895c6fe | 604 | /** @addtogroup SPI_Exported_Functions_Group1 |
| mbed_official | 340:28d1f895c6fe | 605 | * @{ |
| mbed_official | 340:28d1f895c6fe | 606 | */ |
| mbed_official | 340:28d1f895c6fe | 607 | |
| mbed_official | 340:28d1f895c6fe | 608 | /* Initialization and de-initialization functions ****************************/ |
| mbed_official | 340:28d1f895c6fe | 609 | HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 610 | HAL_StatusTypeDef HAL_SPI_InitExtended(SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 611 | HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 612 | void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 613 | void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 614 | /** |
| mbed_official | 340:28d1f895c6fe | 615 | * @} |
| mbed_official | 340:28d1f895c6fe | 616 | */ |
| mbed_official | 340:28d1f895c6fe | 617 | |
| mbed_official | 340:28d1f895c6fe | 618 | /** @addtogroup SPI_Exported_Functions_Group2 |
| mbed_official | 340:28d1f895c6fe | 619 | * @{ |
| mbed_official | 340:28d1f895c6fe | 620 | */ |
| mbed_official | 340:28d1f895c6fe | 621 | |
| mbed_official | 340:28d1f895c6fe | 622 | /* IO operation functions *****************************************************/ |
| mbed_official | 340:28d1f895c6fe | 623 | HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| mbed_official | 340:28d1f895c6fe | 624 | HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| mbed_official | 340:28d1f895c6fe | 625 | HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); |
| mbed_official | 340:28d1f895c6fe | 626 | HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| mbed_official | 340:28d1f895c6fe | 627 | HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| mbed_official | 340:28d1f895c6fe | 628 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); |
| mbed_official | 340:28d1f895c6fe | 629 | HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| mbed_official | 340:28d1f895c6fe | 630 | HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| mbed_official | 340:28d1f895c6fe | 631 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); |
| mbed_official | 340:28d1f895c6fe | 632 | void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 633 | void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 634 | void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 635 | void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 636 | void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 637 | /** |
| mbed_official | 340:28d1f895c6fe | 638 | * @} |
| mbed_official | 340:28d1f895c6fe | 639 | */ |
| mbed_official | 340:28d1f895c6fe | 640 | |
| mbed_official | 340:28d1f895c6fe | 641 | /** @addtogroup SPI_Exported_Functions_Group3 |
| mbed_official | 340:28d1f895c6fe | 642 | * @{ |
| mbed_official | 340:28d1f895c6fe | 643 | */ |
| mbed_official | 340:28d1f895c6fe | 644 | |
| mbed_official | 340:28d1f895c6fe | 645 | /* Peripheral State and Error functions ***************************************/ |
| mbed_official | 340:28d1f895c6fe | 646 | HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 647 | /** |
| mbed_official | 340:28d1f895c6fe | 648 | * @} |
| mbed_official | 340:28d1f895c6fe | 649 | */ |
| mbed_official | 340:28d1f895c6fe | 650 | |
| mbed_official | 340:28d1f895c6fe | 651 | /** |
| mbed_official | 340:28d1f895c6fe | 652 | * @} |
| mbed_official | 340:28d1f895c6fe | 653 | */ |
| mbed_official | 340:28d1f895c6fe | 654 | |
| mbed_official | 340:28d1f895c6fe | 655 | /** |
| mbed_official | 340:28d1f895c6fe | 656 | * @} |
| mbed_official | 340:28d1f895c6fe | 657 | */ |
| mbed_official | 340:28d1f895c6fe | 658 | |
| mbed_official | 340:28d1f895c6fe | 659 | /** |
| mbed_official | 340:28d1f895c6fe | 660 | * @} |
| mbed_official | 340:28d1f895c6fe | 661 | */ |
| mbed_official | 340:28d1f895c6fe | 662 | |
| mbed_official | 340:28d1f895c6fe | 663 | #ifdef __cplusplus |
| mbed_official | 340:28d1f895c6fe | 664 | } |
| mbed_official | 340:28d1f895c6fe | 665 | #endif |
| mbed_official | 340:28d1f895c6fe | 666 | |
| mbed_official | 340:28d1f895c6fe | 667 | #endif /* __STM32F0xx_HAL_SPI_H */ |
| mbed_official | 340:28d1f895c6fe | 668 | |
| mbed_official | 340:28d1f895c6fe | 669 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| mbed_official | 340:28d1f895c6fe | 670 |
