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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/system_stm32f30x.c@125:23cc3068a9e4, 2014-03-19 (annotated)

Committer:
mbed_official
Date:
Wed Mar 19 10:15:22 2014 +0000
Revision:
125:23cc3068a9e4
Child:
135:067cc8ba23da
Synchronized with git revision ace35dfba3748c7cdc102eb38ec6b9e1067c3252



Full URL: https://github.com/mbedmicro/mbed/commit/ace35dfba3748c7cdc102eb38ec6b9e1067c3252/



[NUCLEO_F302R8] Add cmsis and hal files + change F401RE clock to 84MHz

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 125:23cc3068a9e4 1 /**
mbed_official 125:23cc3068a9e4 2 ******************************************************************************
mbed_official 125:23cc3068a9e4 3 * @file system_stm32f30x.c
mbed_official 125:23cc3068a9e4 4 * @author MCD Application Team
mbed_official 125:23cc3068a9e4 5 * @version V1.0.0
mbed_official 125:23cc3068a9e4 6 * @date 05-March-2014
mbed_official 125:23cc3068a9e4 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
mbed_official 125:23cc3068a9e4 8 * This file contains the system clock configuration for STM32F30x devices,
mbed_official 125:23cc3068a9e4 9 * and is generated by the clock configuration tool
mbed_official 125:23cc3068a9e4 10 * stm32f30x_Clock_Configuration_V1.0.0.xls
mbed_official 125:23cc3068a9e4 11 *
mbed_official 125:23cc3068a9e4 12 * 1. This file provides two functions and one global variable to be called from
mbed_official 125:23cc3068a9e4 13 * user application:
mbed_official 125:23cc3068a9e4 14 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
mbed_official 125:23cc3068a9e4 15 * and Divider factors, AHB/APBx prescalers and Flash settings),
mbed_official 125:23cc3068a9e4 16 * depending on the configuration made in the clock xls tool.
mbed_official 125:23cc3068a9e4 17 * This function is called at startup just after reset and
mbed_official 125:23cc3068a9e4 18 * before branch to main program. This call is made inside
mbed_official 125:23cc3068a9e4 19 * the "startup_stm32f30x.s" file.
mbed_official 125:23cc3068a9e4 20 *
mbed_official 125:23cc3068a9e4 21 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 125:23cc3068a9e4 22 * by the user application to setup the SysTick
mbed_official 125:23cc3068a9e4 23 * timer or configure other parameters.
mbed_official 125:23cc3068a9e4 24 *
mbed_official 125:23cc3068a9e4 25 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 125:23cc3068a9e4 26 * be called whenever the core clock is changed
mbed_official 125:23cc3068a9e4 27 * during program execution.
mbed_official 125:23cc3068a9e4 28 *
mbed_official 125:23cc3068a9e4 29 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
mbed_official 125:23cc3068a9e4 30 * Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
mbed_official 125:23cc3068a9e4 31 * configure the system clock before to branch to main program.
mbed_official 125:23cc3068a9e4 32 *
mbed_official 125:23cc3068a9e4 33 * 3. If the system clock source selected by user fails to startup, the SystemInit()
mbed_official 125:23cc3068a9e4 34 * function will do nothing and HSI still used as system clock source. User can
mbed_official 125:23cc3068a9e4 35 * add some code to deal with this issue inside the SetSysClock() function.
mbed_official 125:23cc3068a9e4 36 *
mbed_official 125:23cc3068a9e4 37 * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
mbed_official 125:23cc3068a9e4 38 * in "stm32f30x.h" file. When HSE is used as system clock source, directly or
mbed_official 125:23cc3068a9e4 39 * through PLL, and you are using different crystal you have to adapt the HSE
mbed_official 125:23cc3068a9e4 40 * value to your own configuration.
mbed_official 125:23cc3068a9e4 41 *
mbed_official 125:23cc3068a9e4 42 * 5. This file configures the system clock as follows:
mbed_official 125:23cc3068a9e4 43 *=============================================================================
mbed_official 125:23cc3068a9e4 44 * Supported STM32F30x device
mbed_official 125:23cc3068a9e4 45 *-----------------------------------------------------------------------------
mbed_official 125:23cc3068a9e4 46 * System Clock source | PLL(HSI)
mbed_official 125:23cc3068a9e4 47 *-----------------------------------------------------------------------------
mbed_official 125:23cc3068a9e4 48 * SYSCLK(Hz) | 64000000
mbed_official 125:23cc3068a9e4 49 *-----------------------------------------------------------------------------
mbed_official 125:23cc3068a9e4 50 * HCLK(Hz) | 64000000
mbed_official 125:23cc3068a9e4 51 *-----------------------------------------------------------------------------
mbed_official 125:23cc3068a9e4 52 * AHB Prescaler | 1
mbed_official 125:23cc3068a9e4 53 *-----------------------------------------------------------------------------
mbed_official 125:23cc3068a9e4 54 * APB2 Prescaler | 1
mbed_official 125:23cc3068a9e4 55 *-----------------------------------------------------------------------------
mbed_official 125:23cc3068a9e4 56 * APB1 Prescaler (Max = 36MHz) | 2 (SPI, ...)
mbed_official 125:23cc3068a9e4 57 *-----------------------------------------------------------------------------
mbed_official 125:23cc3068a9e4 58 * HSE Frequency(Hz) | 8000000
mbed_official 125:23cc3068a9e4 59 *----------------------------------------------------------------------------
mbed_official 125:23cc3068a9e4 60 * PLLMUL | 16
mbed_official 125:23cc3068a9e4 61 *-----------------------------------------------------------------------------
mbed_official 125:23cc3068a9e4 62 * PREDIV | 2
mbed_official 125:23cc3068a9e4 63 *-----------------------------------------------------------------------------
mbed_official 125:23cc3068a9e4 64 * USB Clock | DISABLE
mbed_official 125:23cc3068a9e4 65 *-----------------------------------------------------------------------------
mbed_official 125:23cc3068a9e4 66 * Flash Latency(WS) | 2
mbed_official 125:23cc3068a9e4 67 *-----------------------------------------------------------------------------
mbed_official 125:23cc3068a9e4 68 * Prefetch Buffer | OFF
mbed_official 125:23cc3068a9e4 69 *-----------------------------------------------------------------------------
mbed_official 125:23cc3068a9e4 70 *=============================================================================
mbed_official 125:23cc3068a9e4 71 ******************************************************************************
mbed_official 125:23cc3068a9e4 72 * @attention
mbed_official 125:23cc3068a9e4 73 *
mbed_official 125:23cc3068a9e4 74 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 125:23cc3068a9e4 75 *
mbed_official 125:23cc3068a9e4 76 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 125:23cc3068a9e4 77 * are permitted provided that the following conditions are met:
mbed_official 125:23cc3068a9e4 78 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 125:23cc3068a9e4 79 * this list of conditions and the following disclaimer.
mbed_official 125:23cc3068a9e4 80 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 125:23cc3068a9e4 81 * this list of conditions and the following disclaimer in the documentation
mbed_official 125:23cc3068a9e4 82 * and/or other materials provided with the distribution.
mbed_official 125:23cc3068a9e4 83 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 125:23cc3068a9e4 84 * may be used to endorse or promote products derived from this software
mbed_official 125:23cc3068a9e4 85 * without specific prior written permission.
mbed_official 125:23cc3068a9e4 86 *
mbed_official 125:23cc3068a9e4 87 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 125:23cc3068a9e4 88 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 125:23cc3068a9e4 89 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 125:23cc3068a9e4 90 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 125:23cc3068a9e4 91 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 125:23cc3068a9e4 92 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 125:23cc3068a9e4 93 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 125:23cc3068a9e4 94 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 125:23cc3068a9e4 95 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 125:23cc3068a9e4 96 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 125:23cc3068a9e4 97 *
mbed_official 125:23cc3068a9e4 98 ******************************************************************************
mbed_official 125:23cc3068a9e4 99 */
mbed_official 125:23cc3068a9e4 100 /** @addtogroup CMSIS
mbed_official 125:23cc3068a9e4 101 * @{
mbed_official 125:23cc3068a9e4 102 */
mbed_official 125:23cc3068a9e4 103
mbed_official 125:23cc3068a9e4 104 /** @addtogroup stm32f30x_system
mbed_official 125:23cc3068a9e4 105 * @{
mbed_official 125:23cc3068a9e4 106 */
mbed_official 125:23cc3068a9e4 107
mbed_official 125:23cc3068a9e4 108 /** @addtogroup STM32F30x_System_Private_Includes
mbed_official 125:23cc3068a9e4 109 * @{
mbed_official 125:23cc3068a9e4 110 */
mbed_official 125:23cc3068a9e4 111
mbed_official 125:23cc3068a9e4 112 #include "stm32f30x.h"
mbed_official 125:23cc3068a9e4 113
mbed_official 125:23cc3068a9e4 114 /**
mbed_official 125:23cc3068a9e4 115 * @}
mbed_official 125:23cc3068a9e4 116 */
mbed_official 125:23cc3068a9e4 117
mbed_official 125:23cc3068a9e4 118 /** @addtogroup STM32F30x_System_Private_TypesDefinitions
mbed_official 125:23cc3068a9e4 119 * @{
mbed_official 125:23cc3068a9e4 120 */
mbed_official 125:23cc3068a9e4 121
mbed_official 125:23cc3068a9e4 122 /**
mbed_official 125:23cc3068a9e4 123 * @}
mbed_official 125:23cc3068a9e4 124 */
mbed_official 125:23cc3068a9e4 125
mbed_official 125:23cc3068a9e4 126 /** @addtogroup STM32F30x_System_Private_Defines
mbed_official 125:23cc3068a9e4 127 * @{
mbed_official 125:23cc3068a9e4 128 */
mbed_official 125:23cc3068a9e4 129 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 125:23cc3068a9e4 130 Internal SRAM. */
mbed_official 125:23cc3068a9e4 131 /* #define VECT_TAB_SRAM */
mbed_official 125:23cc3068a9e4 132 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
mbed_official 125:23cc3068a9e4 133 This value must be a multiple of 0x200. */
mbed_official 125:23cc3068a9e4 134 /**
mbed_official 125:23cc3068a9e4 135 * @}
mbed_official 125:23cc3068a9e4 136 */
mbed_official 125:23cc3068a9e4 137
mbed_official 125:23cc3068a9e4 138 /** @addtogroup STM32F30x_System_Private_Macros
mbed_official 125:23cc3068a9e4 139 * @{
mbed_official 125:23cc3068a9e4 140 */
mbed_official 125:23cc3068a9e4 141
mbed_official 125:23cc3068a9e4 142 /**
mbed_official 125:23cc3068a9e4 143 * @}
mbed_official 125:23cc3068a9e4 144 */
mbed_official 125:23cc3068a9e4 145
mbed_official 125:23cc3068a9e4 146 /** @addtogroup STM32F30x_System_Private_Variables
mbed_official 125:23cc3068a9e4 147 * @{
mbed_official 125:23cc3068a9e4 148 */
mbed_official 125:23cc3068a9e4 149
mbed_official 125:23cc3068a9e4 150 uint32_t SystemCoreClock = 64000000;
mbed_official 125:23cc3068a9e4 151
mbed_official 125:23cc3068a9e4 152 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 125:23cc3068a9e4 153
mbed_official 125:23cc3068a9e4 154 /**
mbed_official 125:23cc3068a9e4 155 * @}
mbed_official 125:23cc3068a9e4 156 */
mbed_official 125:23cc3068a9e4 157
mbed_official 125:23cc3068a9e4 158 /** @addtogroup STM32F30x_System_Private_FunctionPrototypes
mbed_official 125:23cc3068a9e4 159 * @{
mbed_official 125:23cc3068a9e4 160 */
mbed_official 125:23cc3068a9e4 161
mbed_official 125:23cc3068a9e4 162 void SetSysClock(void);
mbed_official 125:23cc3068a9e4 163
mbed_official 125:23cc3068a9e4 164 /**
mbed_official 125:23cc3068a9e4 165 * @}
mbed_official 125:23cc3068a9e4 166 */
mbed_official 125:23cc3068a9e4 167
mbed_official 125:23cc3068a9e4 168 /** @addtogroup STM32F30x_System_Private_Functions
mbed_official 125:23cc3068a9e4 169 * @{
mbed_official 125:23cc3068a9e4 170 */
mbed_official 125:23cc3068a9e4 171
mbed_official 125:23cc3068a9e4 172 /**
mbed_official 125:23cc3068a9e4 173 * @brief Setup the microcontroller system
mbed_official 125:23cc3068a9e4 174 * Initialize the Embedded Flash Interface, the PLL and update the
mbed_official 125:23cc3068a9e4 175 * SystemFrequency variable.
mbed_official 125:23cc3068a9e4 176 * @param None
mbed_official 125:23cc3068a9e4 177 * @retval None
mbed_official 125:23cc3068a9e4 178 */
mbed_official 125:23cc3068a9e4 179 void SystemInit(void)
mbed_official 125:23cc3068a9e4 180 {
mbed_official 125:23cc3068a9e4 181 /* FPU settings ------------------------------------------------------------*/
mbed_official 125:23cc3068a9e4 182 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 125:23cc3068a9e4 183 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 125:23cc3068a9e4 184 #endif
mbed_official 125:23cc3068a9e4 185
mbed_official 125:23cc3068a9e4 186 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 125:23cc3068a9e4 187 /* Set HSION bit */
mbed_official 125:23cc3068a9e4 188 RCC->CR |= (uint32_t)0x00000001;
mbed_official 125:23cc3068a9e4 189
mbed_official 125:23cc3068a9e4 190 /* Reset CFGR register */
mbed_official 125:23cc3068a9e4 191 RCC->CFGR &= 0xF87FC00C;
mbed_official 125:23cc3068a9e4 192
mbed_official 125:23cc3068a9e4 193 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 125:23cc3068a9e4 194 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 125:23cc3068a9e4 195
mbed_official 125:23cc3068a9e4 196 /* Reset HSEBYP bit */
mbed_official 125:23cc3068a9e4 197 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 125:23cc3068a9e4 198
mbed_official 125:23cc3068a9e4 199 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
mbed_official 125:23cc3068a9e4 200 RCC->CFGR &= (uint32_t)0xFF80FFFF;
mbed_official 125:23cc3068a9e4 201
mbed_official 125:23cc3068a9e4 202 /* Reset PREDIV1[3:0] bits */
mbed_official 125:23cc3068a9e4 203 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
mbed_official 125:23cc3068a9e4 204
mbed_official 125:23cc3068a9e4 205 /* Reset USARTSW[1:0], I2CSW and TIMs bits */
mbed_official 125:23cc3068a9e4 206 RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
mbed_official 125:23cc3068a9e4 207
mbed_official 125:23cc3068a9e4 208 /* Disable all interrupts */
mbed_official 125:23cc3068a9e4 209 RCC->CIR = 0x00000000;
mbed_official 125:23cc3068a9e4 210
mbed_official 125:23cc3068a9e4 211 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 125:23cc3068a9e4 212 AHB/APBx prescalers and Flash settings ----------------------------------*/
mbed_official 125:23cc3068a9e4 213 SetSysClock();
mbed_official 125:23cc3068a9e4 214
mbed_official 125:23cc3068a9e4 215 #ifdef VECT_TAB_SRAM
mbed_official 125:23cc3068a9e4 216 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
mbed_official 125:23cc3068a9e4 217 #else
mbed_official 125:23cc3068a9e4 218 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
mbed_official 125:23cc3068a9e4 219 #endif
mbed_official 125:23cc3068a9e4 220
mbed_official 125:23cc3068a9e4 221 // ADDED FOR MBED DEBUGGING PURPOSE
mbed_official 125:23cc3068a9e4 222 /*
mbed_official 125:23cc3068a9e4 223 // Enable GPIOA clock
mbed_official 125:23cc3068a9e4 224 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
mbed_official 125:23cc3068a9e4 225 // Configure MCO pin (PA8)
mbed_official 125:23cc3068a9e4 226 GPIO_InitTypeDef GPIO_InitStructure;
mbed_official 125:23cc3068a9e4 227 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
mbed_official 125:23cc3068a9e4 228 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
mbed_official 125:23cc3068a9e4 229 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
mbed_official 125:23cc3068a9e4 230 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
mbed_official 125:23cc3068a9e4 231 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
mbed_official 125:23cc3068a9e4 232 GPIO_Init(GPIOA, &GPIO_InitStructure);
mbed_official 125:23cc3068a9e4 233 // Select the clock to output
mbed_official 125:23cc3068a9e4 234 RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCOPrescaler_1);
mbed_official 125:23cc3068a9e4 235 */
mbed_official 125:23cc3068a9e4 236 }
mbed_official 125:23cc3068a9e4 237
mbed_official 125:23cc3068a9e4 238 /**
mbed_official 125:23cc3068a9e4 239 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 125:23cc3068a9e4 240 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 125:23cc3068a9e4 241 * be used by the user application to setup the SysTick timer or configure
mbed_official 125:23cc3068a9e4 242 * other parameters.
mbed_official 125:23cc3068a9e4 243 *
mbed_official 125:23cc3068a9e4 244 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 125:23cc3068a9e4 245 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 125:23cc3068a9e4 246 * based on this variable will be incorrect.
mbed_official 125:23cc3068a9e4 247 *
mbed_official 125:23cc3068a9e4 248 * @note - The system frequency computed by this function is not the real
mbed_official 125:23cc3068a9e4 249 * frequency in the chip. It is calculated based on the predefined
mbed_official 125:23cc3068a9e4 250 * constant and the selected clock source:
mbed_official 125:23cc3068a9e4 251 *
mbed_official 125:23cc3068a9e4 252 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 125:23cc3068a9e4 253 *
mbed_official 125:23cc3068a9e4 254 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 125:23cc3068a9e4 255 *
mbed_official 125:23cc3068a9e4 256 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 125:23cc3068a9e4 257 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 125:23cc3068a9e4 258 *
mbed_official 125:23cc3068a9e4 259 * (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
mbed_official 125:23cc3068a9e4 260 * 8 MHz) but the real value may vary depending on the variations
mbed_official 125:23cc3068a9e4 261 * in voltage and temperature.
mbed_official 125:23cc3068a9e4 262 *
mbed_official 125:23cc3068a9e4 263 * (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
mbed_official 125:23cc3068a9e4 264 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 125:23cc3068a9e4 265 * frequency of the crystal used. Otherwise, this function may
mbed_official 125:23cc3068a9e4 266 * have wrong result.
mbed_official 125:23cc3068a9e4 267 *
mbed_official 125:23cc3068a9e4 268 * - The result of this function could be not correct when using fractional
mbed_official 125:23cc3068a9e4 269 * value for HSE crystal.
mbed_official 125:23cc3068a9e4 270 *
mbed_official 125:23cc3068a9e4 271 * @param None
mbed_official 125:23cc3068a9e4 272 * @retval None
mbed_official 125:23cc3068a9e4 273 */
mbed_official 125:23cc3068a9e4 274 void SystemCoreClockUpdate (void)
mbed_official 125:23cc3068a9e4 275 {
mbed_official 125:23cc3068a9e4 276 uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
mbed_official 125:23cc3068a9e4 277
mbed_official 125:23cc3068a9e4 278 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 125:23cc3068a9e4 279 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 125:23cc3068a9e4 280
mbed_official 125:23cc3068a9e4 281 switch (tmp)
mbed_official 125:23cc3068a9e4 282 {
mbed_official 125:23cc3068a9e4 283 case 0x00: /* HSI used as system clock */
mbed_official 125:23cc3068a9e4 284 SystemCoreClock = HSI_VALUE;
mbed_official 125:23cc3068a9e4 285 break;
mbed_official 125:23cc3068a9e4 286 case 0x04: /* HSE used as system clock */
mbed_official 125:23cc3068a9e4 287 SystemCoreClock = HSE_VALUE;
mbed_official 125:23cc3068a9e4 288 break;
mbed_official 125:23cc3068a9e4 289 case 0x08: /* PLL used as system clock */
mbed_official 125:23cc3068a9e4 290 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 125:23cc3068a9e4 291 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
mbed_official 125:23cc3068a9e4 292 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 125:23cc3068a9e4 293 pllmull = ( pllmull >> 18) + 2;
mbed_official 125:23cc3068a9e4 294
mbed_official 125:23cc3068a9e4 295 if (pllsource == 0x00)
mbed_official 125:23cc3068a9e4 296 {
mbed_official 125:23cc3068a9e4 297 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official 125:23cc3068a9e4 298 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 125:23cc3068a9e4 299 }
mbed_official 125:23cc3068a9e4 300 else
mbed_official 125:23cc3068a9e4 301 {
mbed_official 125:23cc3068a9e4 302 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
mbed_official 125:23cc3068a9e4 303 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 125:23cc3068a9e4 304 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
mbed_official 125:23cc3068a9e4 305 }
mbed_official 125:23cc3068a9e4 306 break;
mbed_official 125:23cc3068a9e4 307 default: /* HSI used as system clock */
mbed_official 125:23cc3068a9e4 308 SystemCoreClock = HSI_VALUE;
mbed_official 125:23cc3068a9e4 309 break;
mbed_official 125:23cc3068a9e4 310 }
mbed_official 125:23cc3068a9e4 311 /* Compute HCLK clock frequency ----------------*/
mbed_official 125:23cc3068a9e4 312 /* Get HCLK prescaler */
mbed_official 125:23cc3068a9e4 313 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 125:23cc3068a9e4 314 /* HCLK clock frequency */
mbed_official 125:23cc3068a9e4 315 SystemCoreClock >>= tmp;
mbed_official 125:23cc3068a9e4 316 }
mbed_official 125:23cc3068a9e4 317
mbed_official 125:23cc3068a9e4 318 /**
mbed_official 125:23cc3068a9e4 319 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 125:23cc3068a9e4 320 * AHB/APBx prescalers and Flash settings
mbed_official 125:23cc3068a9e4 321 * @note This function should be called only once the RCC clock configuration
mbed_official 125:23cc3068a9e4 322 * is reset to the default reset state (done in SystemInit() function).
mbed_official 125:23cc3068a9e4 323 * @param None
mbed_official 125:23cc3068a9e4 324 * @retval None
mbed_official 125:23cc3068a9e4 325 */
mbed_official 125:23cc3068a9e4 326 void SetSysClock(void)
mbed_official 125:23cc3068a9e4 327 {
mbed_official 125:23cc3068a9e4 328 /******************************************************************************/
mbed_official 125:23cc3068a9e4 329 /* PLL (clocked by HSI) used as System clock source */
mbed_official 125:23cc3068a9e4 330 /******************************************************************************/
mbed_official 125:23cc3068a9e4 331
mbed_official 125:23cc3068a9e4 332 /* At this stage the HSI is already enabled and used as System clock source */
mbed_official 125:23cc3068a9e4 333
mbed_official 125:23cc3068a9e4 334 /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
mbed_official 125:23cc3068a9e4 335
mbed_official 125:23cc3068a9e4 336 /* Disable Prefetch Buffer and set Flash Latency */
mbed_official 125:23cc3068a9e4 337 FLASH->ACR = (uint32_t)FLASH_ACR_LATENCY_1;
mbed_official 125:23cc3068a9e4 338
mbed_official 125:23cc3068a9e4 339 /* HCLK = 64 MHz */
mbed_official 125:23cc3068a9e4 340 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official 125:23cc3068a9e4 341
mbed_official 125:23cc3068a9e4 342 /* PCLK2 = 64 MHz */
mbed_official 125:23cc3068a9e4 343 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official 125:23cc3068a9e4 344
mbed_official 125:23cc3068a9e4 345 /* PCLK1 = 32 MHz (SPI, ...) */
mbed_official 125:23cc3068a9e4 346 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
mbed_official 125:23cc3068a9e4 347
mbed_official 125:23cc3068a9e4 348 /* PLL configuration
mbed_official 125:23cc3068a9e4 349 SYSCLK = 4 MHz * 16 = 64 MHz
mbed_official 125:23cc3068a9e4 350 */
mbed_official 125:23cc3068a9e4 351 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 125:23cc3068a9e4 352 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL16);
mbed_official 125:23cc3068a9e4 353
mbed_official 125:23cc3068a9e4 354 /* Enable PLL */
mbed_official 125:23cc3068a9e4 355 RCC->CR |= RCC_CR_PLLON;
mbed_official 125:23cc3068a9e4 356
mbed_official 125:23cc3068a9e4 357 /* Wait till PLL is ready */
mbed_official 125:23cc3068a9e4 358 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 125:23cc3068a9e4 359 {
mbed_official 125:23cc3068a9e4 360 }
mbed_official 125:23cc3068a9e4 361
mbed_official 125:23cc3068a9e4 362 /* Select PLL as system clock source */
mbed_official 125:23cc3068a9e4 363 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 125:23cc3068a9e4 364 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 125:23cc3068a9e4 365
mbed_official 125:23cc3068a9e4 366 /* Wait till PLL is used as system clock source */
mbed_official 125:23cc3068a9e4 367 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
mbed_official 125:23cc3068a9e4 368 {
mbed_official 125:23cc3068a9e4 369 }
mbed_official 125:23cc3068a9e4 370 }
mbed_official 125:23cc3068a9e4 371
mbed_official 125:23cc3068a9e4 372 /**
mbed_official 125:23cc3068a9e4 373 * @}
mbed_official 125:23cc3068a9e4 374 */
mbed_official 125:23cc3068a9e4 375
mbed_official 125:23cc3068a9e4 376 /**
mbed_official 125:23cc3068a9e4 377 * @}
mbed_official 125:23cc3068a9e4 378 */
mbed_official 125:23cc3068a9e4 379
mbed_official 125:23cc3068a9e4 380 /**
mbed_official 125:23cc3068a9e4 381 * @}
mbed_official 125:23cc3068a9e4 382 */
mbed_official 125:23cc3068a9e4 383
mbed_official 125:23cc3068a9e4 384 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
mbed_official 125:23cc3068a9e4 385