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CMSIS DSP library

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cmsis_dsp/SupportFunctions/arm_q15_to_q31.c@5:3762170b6d4d, 2015-11-20 (annotated)

Committer:
mbed_official
Date:
Fri Nov 20 08:45:18 2015 +0000
Revision:
5:3762170b6d4d
Parent:
3:7a284390b0ce 
Synchronized with git revision 2eb940b9a73af188d3004a2575fdfbb05febe62b



Full URL: https://github.com/mbedmicro/mbed/commit/2eb940b9a73af188d3004a2575fdfbb05febe62b/



Added option to build rpc library. closes #1426

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 1:fdd22bb7aa52 1 /* ----------------------------------------------------------------------------
mbed_official 5:3762170b6d4d 2 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
emilmont 1:fdd22bb7aa52 3 *
mbed_official 5:3762170b6d4d 4 * $Date: 19. March 2015
mbed_official 5:3762170b6d4d 5 * $Revision: V.1.4.5
emilmont 1:fdd22bb7aa52 6 *
emilmont 2:da51fb522205 7 * Project: CMSIS DSP Library
emilmont 2:da51fb522205 8 * Title: arm_q15_to_q31.c
emilmont 1:fdd22bb7aa52 9 *
emilmont 2:da51fb522205 10 * Description: Converts the elements of the Q15 vector to Q31 vector.
emilmont 1:fdd22bb7aa52 11 *
emilmont 1:fdd22bb7aa52 12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emilmont 1:fdd22bb7aa52 13 *
mbed_official 3:7a284390b0ce 14 * Redistribution and use in source and binary forms, with or without
mbed_official 3:7a284390b0ce 15 * modification, are permitted provided that the following conditions
mbed_official 3:7a284390b0ce 16 * are met:
mbed_official 3:7a284390b0ce 17 * - Redistributions of source code must retain the above copyright
mbed_official 3:7a284390b0ce 18 * notice, this list of conditions and the following disclaimer.
mbed_official 3:7a284390b0ce 19 * - Redistributions in binary form must reproduce the above copyright
mbed_official 3:7a284390b0ce 20 * notice, this list of conditions and the following disclaimer in
mbed_official 3:7a284390b0ce 21 * the documentation and/or other materials provided with the
mbed_official 3:7a284390b0ce 22 * distribution.
mbed_official 3:7a284390b0ce 23 * - Neither the name of ARM LIMITED nor the names of its contributors
mbed_official 3:7a284390b0ce 24 * may be used to endorse or promote products derived from this
mbed_official 3:7a284390b0ce 25 * software without specific prior written permission.
mbed_official 3:7a284390b0ce 26 *
mbed_official 3:7a284390b0ce 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
mbed_official 3:7a284390b0ce 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
mbed_official 3:7a284390b0ce 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
mbed_official 3:7a284390b0ce 30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
mbed_official 3:7a284390b0ce 31 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
mbed_official 3:7a284390b0ce 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
mbed_official 3:7a284390b0ce 33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 3:7a284390b0ce 34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 3:7a284390b0ce 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
mbed_official 3:7a284390b0ce 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 3:7a284390b0ce 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 3:7a284390b0ce 38 * POSSIBILITY OF SUCH DAMAGE.
emilmont 1:fdd22bb7aa52 39 * ---------------------------------------------------------------------------- */
emilmont 1:fdd22bb7aa52 40
emilmont 1:fdd22bb7aa52 41 #include "arm_math.h"
emilmont 1:fdd22bb7aa52 42
emilmont 1:fdd22bb7aa52 43 /**
emilmont 1:fdd22bb7aa52 44 * @ingroup groupSupport
emilmont 1:fdd22bb7aa52 45 */
emilmont 1:fdd22bb7aa52 46
emilmont 1:fdd22bb7aa52 47 /**
emilmont 1:fdd22bb7aa52 48 * @addtogroup q15_to_x
emilmont 1:fdd22bb7aa52 49 * @{
emilmont 1:fdd22bb7aa52 50 */
emilmont 1:fdd22bb7aa52 51
emilmont 1:fdd22bb7aa52 52 /**
emilmont 1:fdd22bb7aa52 53 * @brief Converts the elements of the Q15 vector to Q31 vector.
emilmont 1:fdd22bb7aa52 54 * @param[in] *pSrc points to the Q15 input vector
emilmont 1:fdd22bb7aa52 55 * @param[out] *pDst points to the Q31 output vector
emilmont 1:fdd22bb7aa52 56 * @param[in] blockSize length of the input vector
emilmont 1:fdd22bb7aa52 57 * @return none.
emilmont 1:fdd22bb7aa52 58 *
emilmont 1:fdd22bb7aa52 59 * \par Description:
emilmont 1:fdd22bb7aa52 60 *
emilmont 1:fdd22bb7aa52 61 * The equation used for the conversion process is:
emilmont 1:fdd22bb7aa52 62 *
emilmont 1:fdd22bb7aa52 63 * <pre>
emilmont 2:da51fb522205 64 * pDst[n] = (q31_t) pSrc[n] << 16; 0 <= n < blockSize.
emilmont 1:fdd22bb7aa52 65 * </pre>
emilmont 1:fdd22bb7aa52 66 *
emilmont 1:fdd22bb7aa52 67 */
emilmont 1:fdd22bb7aa52 68
emilmont 1:fdd22bb7aa52 69
emilmont 1:fdd22bb7aa52 70 void arm_q15_to_q31(
emilmont 1:fdd22bb7aa52 71 q15_t * pSrc,
emilmont 1:fdd22bb7aa52 72 q31_t * pDst,
emilmont 1:fdd22bb7aa52 73 uint32_t blockSize)
emilmont 1:fdd22bb7aa52 74 {
emilmont 1:fdd22bb7aa52 75 q15_t *pIn = pSrc; /* Src pointer */
emilmont 1:fdd22bb7aa52 76 uint32_t blkCnt; /* loop counter */
emilmont 1:fdd22bb7aa52 77
mbed_official 3:7a284390b0ce 78 #ifndef ARM_MATH_CM0_FAMILY
emilmont 1:fdd22bb7aa52 79
emilmont 1:fdd22bb7aa52 80 /* Run the below code for Cortex-M4 and Cortex-M3 */
emilmont 1:fdd22bb7aa52 81 q31_t in1, in2;
emilmont 1:fdd22bb7aa52 82 q31_t out1, out2, out3, out4;
emilmont 1:fdd22bb7aa52 83
emilmont 1:fdd22bb7aa52 84 /*loop Unrolling */
emilmont 1:fdd22bb7aa52 85 blkCnt = blockSize >> 2u;
emilmont 1:fdd22bb7aa52 86
emilmont 1:fdd22bb7aa52 87 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
emilmont 1:fdd22bb7aa52 88 ** a second loop below computes the remaining 1 to 3 samples. */
emilmont 1:fdd22bb7aa52 89 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 90 {
emilmont 1:fdd22bb7aa52 91 /* C = (q31_t)A << 16 */
emilmont 1:fdd22bb7aa52 92 /* convert from q15 to q31 and then store the results in the destination buffer */
emilmont 1:fdd22bb7aa52 93 in1 = *__SIMD32(pIn)++;
emilmont 1:fdd22bb7aa52 94 in2 = *__SIMD32(pIn)++;
emilmont 1:fdd22bb7aa52 95
emilmont 1:fdd22bb7aa52 96 #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 97
emilmont 1:fdd22bb7aa52 98 /* extract lower 16 bits to 32 bit result */
emilmont 1:fdd22bb7aa52 99 out1 = in1 << 16u;
emilmont 1:fdd22bb7aa52 100 /* extract upper 16 bits to 32 bit result */
emilmont 1:fdd22bb7aa52 101 out2 = in1 & 0xFFFF0000;
emilmont 1:fdd22bb7aa52 102 /* extract lower 16 bits to 32 bit result */
emilmont 1:fdd22bb7aa52 103 out3 = in2 << 16u;
emilmont 1:fdd22bb7aa52 104 /* extract upper 16 bits to 32 bit result */
emilmont 1:fdd22bb7aa52 105 out4 = in2 & 0xFFFF0000;
emilmont 1:fdd22bb7aa52 106
emilmont 1:fdd22bb7aa52 107 #else
emilmont 1:fdd22bb7aa52 108
emilmont 1:fdd22bb7aa52 109 /* extract upper 16 bits to 32 bit result */
emilmont 1:fdd22bb7aa52 110 out1 = in1 & 0xFFFF0000;
emilmont 1:fdd22bb7aa52 111 /* extract lower 16 bits to 32 bit result */
emilmont 1:fdd22bb7aa52 112 out2 = in1 << 16u;
emilmont 1:fdd22bb7aa52 113 /* extract upper 16 bits to 32 bit result */
emilmont 1:fdd22bb7aa52 114 out3 = in2 & 0xFFFF0000;
emilmont 1:fdd22bb7aa52 115 /* extract lower 16 bits to 32 bit result */
emilmont 1:fdd22bb7aa52 116 out4 = in2 << 16u;
emilmont 1:fdd22bb7aa52 117
emilmont 1:fdd22bb7aa52 118 #endif // #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 119
emilmont 1:fdd22bb7aa52 120 *pDst++ = out1;
emilmont 1:fdd22bb7aa52 121 *pDst++ = out2;
emilmont 1:fdd22bb7aa52 122 *pDst++ = out3;
emilmont 1:fdd22bb7aa52 123 *pDst++ = out4;
emilmont 1:fdd22bb7aa52 124
emilmont 1:fdd22bb7aa52 125 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 126 blkCnt--;
emilmont 1:fdd22bb7aa52 127 }
emilmont 1:fdd22bb7aa52 128
emilmont 1:fdd22bb7aa52 129 /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
emilmont 1:fdd22bb7aa52 130 ** No loop unrolling is used. */
emilmont 1:fdd22bb7aa52 131 blkCnt = blockSize % 0x4u;
emilmont 1:fdd22bb7aa52 132
emilmont 1:fdd22bb7aa52 133 #else
emilmont 1:fdd22bb7aa52 134
emilmont 1:fdd22bb7aa52 135 /* Run the below code for Cortex-M0 */
emilmont 1:fdd22bb7aa52 136
emilmont 1:fdd22bb7aa52 137 /* Loop over blockSize number of values */
emilmont 1:fdd22bb7aa52 138 blkCnt = blockSize;
emilmont 1:fdd22bb7aa52 139
mbed_official 3:7a284390b0ce 140 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
emilmont 1:fdd22bb7aa52 141
emilmont 1:fdd22bb7aa52 142 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 143 {
emilmont 1:fdd22bb7aa52 144 /* C = (q31_t)A << 16 */
emilmont 1:fdd22bb7aa52 145 /* convert from q15 to q31 and then store the results in the destination buffer */
emilmont 1:fdd22bb7aa52 146 *pDst++ = (q31_t) * pIn++ << 16;
emilmont 1:fdd22bb7aa52 147
emilmont 1:fdd22bb7aa52 148 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 149 blkCnt--;
emilmont 1:fdd22bb7aa52 150 }
emilmont 1:fdd22bb7aa52 151
emilmont 1:fdd22bb7aa52 152 }
emilmont 1:fdd22bb7aa52 153
emilmont 1:fdd22bb7aa52 154 /**
emilmont 1:fdd22bb7aa52 155 * @} end of q15_to_x group
emilmont 1:fdd22bb7aa52 156 */