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CMSIS DSP library

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cmsis_dsp/StatisticsFunctions/arm_power_q31.c@5:3762170b6d4d, 2015-11-20 (annotated)

Committer:
mbed_official
Date:
Fri Nov 20 08:45:18 2015 +0000
Revision:
5:3762170b6d4d
Parent:
3:7a284390b0ce 
Synchronized with git revision 2eb940b9a73af188d3004a2575fdfbb05febe62b



Full URL: https://github.com/mbedmicro/mbed/commit/2eb940b9a73af188d3004a2575fdfbb05febe62b/



Added option to build rpc library. closes #1426

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 1:fdd22bb7aa52 1 /* ----------------------------------------------------------------------
mbed_official 5:3762170b6d4d 2 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
emilmont 1:fdd22bb7aa52 3 *
mbed_official 5:3762170b6d4d 4 * $Date: 19. March 2015
mbed_official 5:3762170b6d4d 5 * $Revision: V.1.4.5
emilmont 1:fdd22bb7aa52 6 *
emilmont 2:da51fb522205 7 * Project: CMSIS DSP Library
emilmont 2:da51fb522205 8 * Title: arm_power_q31.c
emilmont 1:fdd22bb7aa52 9 *
emilmont 2:da51fb522205 10 * Description: Sum of the squares of the elements of a Q31 vector.
emilmont 1:fdd22bb7aa52 11 *
emilmont 1:fdd22bb7aa52 12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emilmont 1:fdd22bb7aa52 13 *
mbed_official 3:7a284390b0ce 14 * Redistribution and use in source and binary forms, with or without
mbed_official 3:7a284390b0ce 15 * modification, are permitted provided that the following conditions
mbed_official 3:7a284390b0ce 16 * are met:
mbed_official 3:7a284390b0ce 17 * - Redistributions of source code must retain the above copyright
mbed_official 3:7a284390b0ce 18 * notice, this list of conditions and the following disclaimer.
mbed_official 3:7a284390b0ce 19 * - Redistributions in binary form must reproduce the above copyright
mbed_official 3:7a284390b0ce 20 * notice, this list of conditions and the following disclaimer in
mbed_official 3:7a284390b0ce 21 * the documentation and/or other materials provided with the
mbed_official 3:7a284390b0ce 22 * distribution.
mbed_official 3:7a284390b0ce 23 * - Neither the name of ARM LIMITED nor the names of its contributors
mbed_official 3:7a284390b0ce 24 * may be used to endorse or promote products derived from this
mbed_official 3:7a284390b0ce 25 * software without specific prior written permission.
mbed_official 3:7a284390b0ce 26 *
mbed_official 3:7a284390b0ce 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
mbed_official 3:7a284390b0ce 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
mbed_official 3:7a284390b0ce 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
mbed_official 3:7a284390b0ce 30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
mbed_official 3:7a284390b0ce 31 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
mbed_official 3:7a284390b0ce 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
mbed_official 3:7a284390b0ce 33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 3:7a284390b0ce 34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 3:7a284390b0ce 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
mbed_official 3:7a284390b0ce 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 3:7a284390b0ce 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 3:7a284390b0ce 38 * POSSIBILITY OF SUCH DAMAGE.
emilmont 1:fdd22bb7aa52 39 * -------------------------------------------------------------------- */
emilmont 1:fdd22bb7aa52 40
emilmont 1:fdd22bb7aa52 41 #include "arm_math.h"
emilmont 1:fdd22bb7aa52 42
emilmont 1:fdd22bb7aa52 43 /**
emilmont 1:fdd22bb7aa52 44 * @ingroup groupStats
emilmont 1:fdd22bb7aa52 45 */
emilmont 1:fdd22bb7aa52 46
emilmont 1:fdd22bb7aa52 47 /**
emilmont 1:fdd22bb7aa52 48 * @addtogroup power
emilmont 1:fdd22bb7aa52 49 * @{
emilmont 1:fdd22bb7aa52 50 */
emilmont 1:fdd22bb7aa52 51
emilmont 1:fdd22bb7aa52 52 /**
emilmont 1:fdd22bb7aa52 53 * @brief Sum of the squares of the elements of a Q31 vector.
emilmont 1:fdd22bb7aa52 54 * @param[in] *pSrc points to the input vector
emilmont 1:fdd22bb7aa52 55 * @param[in] blockSize length of the input vector
emilmont 1:fdd22bb7aa52 56 * @param[out] *pResult sum of the squares value returned here
emilmont 1:fdd22bb7aa52 57 * @return none.
emilmont 1:fdd22bb7aa52 58 *
emilmont 1:fdd22bb7aa52 59 * @details
emilmont 1:fdd22bb7aa52 60 * <b>Scaling and Overflow Behavior:</b>
emilmont 1:fdd22bb7aa52 61 *
emilmont 1:fdd22bb7aa52 62 * \par
emilmont 1:fdd22bb7aa52 63 * The function is implemented using a 64-bit internal accumulator.
emilmont 1:fdd22bb7aa52 64 * The input is represented in 1.31 format.
emilmont 1:fdd22bb7aa52 65 * Intermediate multiplication yields a 2.62 format, and this
emilmont 1:fdd22bb7aa52 66 * result is truncated to 2.48 format by discarding the lower 14 bits.
emilmont 1:fdd22bb7aa52 67 * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.
emilmont 1:fdd22bb7aa52 68 * With 15 guard bits in the accumulator, there is no risk of overflow, and the
emilmont 1:fdd22bb7aa52 69 * full precision of the intermediate multiplication is preserved.
emilmont 1:fdd22bb7aa52 70 * Finally, the return result is in 16.48 format.
emilmont 1:fdd22bb7aa52 71 *
emilmont 1:fdd22bb7aa52 72 */
emilmont 1:fdd22bb7aa52 73
emilmont 1:fdd22bb7aa52 74 void arm_power_q31(
emilmont 1:fdd22bb7aa52 75 q31_t * pSrc,
emilmont 1:fdd22bb7aa52 76 uint32_t blockSize,
emilmont 1:fdd22bb7aa52 77 q63_t * pResult)
emilmont 1:fdd22bb7aa52 78 {
emilmont 1:fdd22bb7aa52 79 q63_t sum = 0; /* Temporary result storage */
emilmont 1:fdd22bb7aa52 80 q31_t in;
emilmont 1:fdd22bb7aa52 81 uint32_t blkCnt; /* loop counter */
emilmont 1:fdd22bb7aa52 82
emilmont 1:fdd22bb7aa52 83
mbed_official 3:7a284390b0ce 84 #ifndef ARM_MATH_CM0_FAMILY
emilmont 1:fdd22bb7aa52 85
emilmont 1:fdd22bb7aa52 86 /* Run the below code for Cortex-M4 and Cortex-M3 */
emilmont 1:fdd22bb7aa52 87
emilmont 1:fdd22bb7aa52 88 /*loop Unrolling */
emilmont 1:fdd22bb7aa52 89 blkCnt = blockSize >> 2u;
emilmont 1:fdd22bb7aa52 90
emilmont 1:fdd22bb7aa52 91 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
emilmont 1:fdd22bb7aa52 92 ** a second loop below computes the remaining 1 to 3 samples. */
emilmont 1:fdd22bb7aa52 93 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 94 {
emilmont 1:fdd22bb7aa52 95 /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
emilmont 1:fdd22bb7aa52 96 /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */
emilmont 1:fdd22bb7aa52 97 in = *pSrc++;
emilmont 1:fdd22bb7aa52 98 sum += ((q63_t) in * in) >> 14u;
emilmont 1:fdd22bb7aa52 99
emilmont 1:fdd22bb7aa52 100 in = *pSrc++;
emilmont 1:fdd22bb7aa52 101 sum += ((q63_t) in * in) >> 14u;
emilmont 1:fdd22bb7aa52 102
emilmont 1:fdd22bb7aa52 103 in = *pSrc++;
emilmont 1:fdd22bb7aa52 104 sum += ((q63_t) in * in) >> 14u;
emilmont 1:fdd22bb7aa52 105
emilmont 1:fdd22bb7aa52 106 in = *pSrc++;
emilmont 1:fdd22bb7aa52 107 sum += ((q63_t) in * in) >> 14u;
emilmont 1:fdd22bb7aa52 108
emilmont 1:fdd22bb7aa52 109 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 110 blkCnt--;
emilmont 1:fdd22bb7aa52 111 }
emilmont 1:fdd22bb7aa52 112
emilmont 1:fdd22bb7aa52 113 /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
emilmont 1:fdd22bb7aa52 114 ** No loop unrolling is used. */
emilmont 1:fdd22bb7aa52 115 blkCnt = blockSize % 0x4u;
emilmont 1:fdd22bb7aa52 116
emilmont 1:fdd22bb7aa52 117 #else
emilmont 1:fdd22bb7aa52 118
emilmont 1:fdd22bb7aa52 119 /* Run the below code for Cortex-M0 */
emilmont 1:fdd22bb7aa52 120
emilmont 1:fdd22bb7aa52 121 /* Loop over blockSize number of values */
emilmont 1:fdd22bb7aa52 122 blkCnt = blockSize;
emilmont 1:fdd22bb7aa52 123
mbed_official 3:7a284390b0ce 124 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
emilmont 1:fdd22bb7aa52 125
emilmont 1:fdd22bb7aa52 126 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 127 {
emilmont 1:fdd22bb7aa52 128 /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
emilmont 1:fdd22bb7aa52 129 /* Compute Power and then store the result in a temporary variable, sum. */
emilmont 1:fdd22bb7aa52 130 in = *pSrc++;
emilmont 1:fdd22bb7aa52 131 sum += ((q63_t) in * in) >> 14u;
emilmont 1:fdd22bb7aa52 132
emilmont 1:fdd22bb7aa52 133 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 134 blkCnt--;
emilmont 1:fdd22bb7aa52 135 }
emilmont 1:fdd22bb7aa52 136
emilmont 1:fdd22bb7aa52 137 /* Store the results in 16.48 format */
emilmont 1:fdd22bb7aa52 138 *pResult = sum;
emilmont 1:fdd22bb7aa52 139 }
emilmont 1:fdd22bb7aa52 140
emilmont 1:fdd22bb7aa52 141 /**
emilmont 1:fdd22bb7aa52 142 * @} end of power group
emilmont 1:fdd22bb7aa52 143 */