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CMSIS DSP library

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cmsis_dsp/FilteringFunctions/arm_iir_lattice_q15.c@5:3762170b6d4d, 2015-11-20 (annotated)

Committer:
mbed_official
Date:
Fri Nov 20 08:45:18 2015 +0000
Revision:
5:3762170b6d4d
Parent:
3:7a284390b0ce 
Synchronized with git revision 2eb940b9a73af188d3004a2575fdfbb05febe62b



Full URL: https://github.com/mbedmicro/mbed/commit/2eb940b9a73af188d3004a2575fdfbb05febe62b/



Added option to build rpc library. closes #1426

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 1:fdd22bb7aa52 1 /* ----------------------------------------------------------------------
mbed_official 5:3762170b6d4d 2 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
emilmont 1:fdd22bb7aa52 3 *
mbed_official 5:3762170b6d4d 4 * $Date: 19. March 2015
mbed_official 5:3762170b6d4d 5 * $Revision: V.1.4.5
emilmont 1:fdd22bb7aa52 6 *
emilmont 2:da51fb522205 7 * Project: CMSIS DSP Library
emilmont 2:da51fb522205 8 * Title: arm_iir_lattice_q15.c
emilmont 1:fdd22bb7aa52 9 *
emilmont 2:da51fb522205 10 * Description: Q15 IIR lattice filter processing function.
emilmont 1:fdd22bb7aa52 11 *
emilmont 1:fdd22bb7aa52 12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emilmont 1:fdd22bb7aa52 13 *
mbed_official 3:7a284390b0ce 14 * Redistribution and use in source and binary forms, with or without
mbed_official 3:7a284390b0ce 15 * modification, are permitted provided that the following conditions
mbed_official 3:7a284390b0ce 16 * are met:
mbed_official 3:7a284390b0ce 17 * - Redistributions of source code must retain the above copyright
mbed_official 3:7a284390b0ce 18 * notice, this list of conditions and the following disclaimer.
mbed_official 3:7a284390b0ce 19 * - Redistributions in binary form must reproduce the above copyright
mbed_official 3:7a284390b0ce 20 * notice, this list of conditions and the following disclaimer in
mbed_official 3:7a284390b0ce 21 * the documentation and/or other materials provided with the
mbed_official 3:7a284390b0ce 22 * distribution.
mbed_official 3:7a284390b0ce 23 * - Neither the name of ARM LIMITED nor the names of its contributors
mbed_official 3:7a284390b0ce 24 * may be used to endorse or promote products derived from this
mbed_official 3:7a284390b0ce 25 * software without specific prior written permission.
mbed_official 3:7a284390b0ce 26 *
mbed_official 3:7a284390b0ce 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
mbed_official 3:7a284390b0ce 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
mbed_official 3:7a284390b0ce 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
mbed_official 3:7a284390b0ce 30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
mbed_official 3:7a284390b0ce 31 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
mbed_official 3:7a284390b0ce 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
mbed_official 3:7a284390b0ce 33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 3:7a284390b0ce 34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 3:7a284390b0ce 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
mbed_official 3:7a284390b0ce 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 3:7a284390b0ce 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 3:7a284390b0ce 38 * POSSIBILITY OF SUCH DAMAGE.
emilmont 1:fdd22bb7aa52 39 * -------------------------------------------------------------------- */
emilmont 1:fdd22bb7aa52 40
emilmont 1:fdd22bb7aa52 41 #include "arm_math.h"
emilmont 1:fdd22bb7aa52 42
emilmont 1:fdd22bb7aa52 43 /**
emilmont 1:fdd22bb7aa52 44 * @ingroup groupFilters
emilmont 1:fdd22bb7aa52 45 */
emilmont 1:fdd22bb7aa52 46
emilmont 1:fdd22bb7aa52 47 /**
emilmont 1:fdd22bb7aa52 48 * @addtogroup IIR_Lattice
emilmont 1:fdd22bb7aa52 49 * @{
emilmont 1:fdd22bb7aa52 50 */
emilmont 1:fdd22bb7aa52 51
emilmont 1:fdd22bb7aa52 52 /**
emilmont 1:fdd22bb7aa52 53 * @brief Processing function for the Q15 IIR lattice filter.
emilmont 1:fdd22bb7aa52 54 * @param[in] *S points to an instance of the Q15 IIR lattice structure.
emilmont 1:fdd22bb7aa52 55 * @param[in] *pSrc points to the block of input data.
emilmont 1:fdd22bb7aa52 56 * @param[out] *pDst points to the block of output data.
emilmont 1:fdd22bb7aa52 57 * @param[in] blockSize number of samples to process.
emilmont 1:fdd22bb7aa52 58 * @return none.
emilmont 1:fdd22bb7aa52 59 *
emilmont 1:fdd22bb7aa52 60 * @details
emilmont 1:fdd22bb7aa52 61 * <b>Scaling and Overflow Behavior:</b>
emilmont 1:fdd22bb7aa52 62 * \par
emilmont 1:fdd22bb7aa52 63 * The function is implemented using a 64-bit internal accumulator.
emilmont 1:fdd22bb7aa52 64 * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
emilmont 1:fdd22bb7aa52 65 * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
emilmont 1:fdd22bb7aa52 66 * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
emilmont 1:fdd22bb7aa52 67 * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
emilmont 1:fdd22bb7aa52 68 * Lastly, the accumulator is saturated to yield a result in 1.15 format.
emilmont 1:fdd22bb7aa52 69 */
emilmont 1:fdd22bb7aa52 70
emilmont 1:fdd22bb7aa52 71 void arm_iir_lattice_q15(
emilmont 1:fdd22bb7aa52 72 const arm_iir_lattice_instance_q15 * S,
emilmont 1:fdd22bb7aa52 73 q15_t * pSrc,
emilmont 1:fdd22bb7aa52 74 q15_t * pDst,
emilmont 1:fdd22bb7aa52 75 uint32_t blockSize)
emilmont 1:fdd22bb7aa52 76 {
emilmont 1:fdd22bb7aa52 77
emilmont 1:fdd22bb7aa52 78
mbed_official 3:7a284390b0ce 79 #ifndef ARM_MATH_CM0_FAMILY
emilmont 1:fdd22bb7aa52 80
emilmont 1:fdd22bb7aa52 81 /* Run the below code for Cortex-M4 and Cortex-M3 */
emilmont 1:fdd22bb7aa52 82
emilmont 1:fdd22bb7aa52 83 q31_t fcurr, fnext, gcurr = 0, gnext; /* Temporary variables for lattice stages */
emilmont 1:fdd22bb7aa52 84 q15_t gnext1, gnext2; /* Temporary variables for lattice stages */
emilmont 1:fdd22bb7aa52 85 uint32_t stgCnt; /* Temporary variables for counts */
emilmont 1:fdd22bb7aa52 86 q63_t acc; /* Accumlator */
emilmont 1:fdd22bb7aa52 87 uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
emilmont 1:fdd22bb7aa52 88 q15_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
emilmont 1:fdd22bb7aa52 89 uint32_t numStages = S->numStages; /* number of stages */
emilmont 1:fdd22bb7aa52 90 q15_t *pState; /* State pointer */
emilmont 1:fdd22bb7aa52 91 q15_t *pStateCurnt; /* State current pointer */
emilmont 1:fdd22bb7aa52 92 q15_t out; /* Temporary variable for output */
mbed_official 3:7a284390b0ce 93 q31_t v; /* Temporary variable for ladder coefficient */
emilmont 1:fdd22bb7aa52 94 #ifdef UNALIGNED_SUPPORT_DISABLE
mbed_official 3:7a284390b0ce 95 q15_t v1, v2;
emilmont 1:fdd22bb7aa52 96 #endif
emilmont 1:fdd22bb7aa52 97
emilmont 1:fdd22bb7aa52 98
emilmont 1:fdd22bb7aa52 99 blkCnt = blockSize;
emilmont 1:fdd22bb7aa52 100
emilmont 1:fdd22bb7aa52 101 pState = &S->pState[0];
emilmont 1:fdd22bb7aa52 102
emilmont 1:fdd22bb7aa52 103 /* Sample processing */
emilmont 1:fdd22bb7aa52 104 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 105 {
emilmont 1:fdd22bb7aa52 106 /* Read Sample from input buffer */
emilmont 1:fdd22bb7aa52 107 /* fN(n) = x(n) */
emilmont 1:fdd22bb7aa52 108 fcurr = *pSrc++;
emilmont 1:fdd22bb7aa52 109
emilmont 1:fdd22bb7aa52 110 /* Initialize state read pointer */
emilmont 1:fdd22bb7aa52 111 px1 = pState;
emilmont 1:fdd22bb7aa52 112 /* Initialize state write pointer */
emilmont 1:fdd22bb7aa52 113 px2 = pState;
emilmont 1:fdd22bb7aa52 114 /* Set accumulator to zero */
emilmont 1:fdd22bb7aa52 115 acc = 0;
emilmont 1:fdd22bb7aa52 116 /* Initialize Ladder coeff pointer */
emilmont 1:fdd22bb7aa52 117 pv = &S->pvCoeffs[0];
emilmont 1:fdd22bb7aa52 118 /* Initialize Reflection coeff pointer */
emilmont 1:fdd22bb7aa52 119 pk = &S->pkCoeffs[0];
emilmont 1:fdd22bb7aa52 120
emilmont 1:fdd22bb7aa52 121
emilmont 1:fdd22bb7aa52 122 /* Process sample for first tap */
emilmont 1:fdd22bb7aa52 123 gcurr = *px1++;
emilmont 1:fdd22bb7aa52 124 /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
emilmont 1:fdd22bb7aa52 125 fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
emilmont 1:fdd22bb7aa52 126 fnext = __SSAT(fnext, 16);
emilmont 1:fdd22bb7aa52 127 /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
emilmont 1:fdd22bb7aa52 128 gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
emilmont 1:fdd22bb7aa52 129 gnext = __SSAT(gnext, 16);
emilmont 1:fdd22bb7aa52 130 /* write gN(n) into state for next sample processing */
emilmont 1:fdd22bb7aa52 131 *px2++ = (q15_t) gnext;
emilmont 1:fdd22bb7aa52 132 /* y(n) += gN(n) * vN */
emilmont 1:fdd22bb7aa52 133 acc += (q31_t) ((gnext * (*pv++)));
emilmont 1:fdd22bb7aa52 134
emilmont 1:fdd22bb7aa52 135
emilmont 1:fdd22bb7aa52 136 /* Update f values for next coefficient processing */
emilmont 1:fdd22bb7aa52 137 fcurr = fnext;
emilmont 1:fdd22bb7aa52 138
emilmont 1:fdd22bb7aa52 139 /* Loop unrolling. Process 4 taps at a time. */
emilmont 1:fdd22bb7aa52 140 tapCnt = (numStages - 1u) >> 2;
emilmont 1:fdd22bb7aa52 141
emilmont 1:fdd22bb7aa52 142 while(tapCnt > 0u)
emilmont 1:fdd22bb7aa52 143 {
emilmont 1:fdd22bb7aa52 144
emilmont 1:fdd22bb7aa52 145 /* Process sample for 2nd, 6th ...taps */
emilmont 1:fdd22bb7aa52 146 /* Read gN-2(n-1) from state buffer */
emilmont 1:fdd22bb7aa52 147 gcurr = *px1++;
emilmont 1:fdd22bb7aa52 148 /* Process sample for 2nd, 6th .. taps */
emilmont 1:fdd22bb7aa52 149 /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
emilmont 1:fdd22bb7aa52 150 fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
emilmont 1:fdd22bb7aa52 151 fnext = __SSAT(fnext, 16);
emilmont 1:fdd22bb7aa52 152 /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
emilmont 1:fdd22bb7aa52 153 gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
emilmont 1:fdd22bb7aa52 154 gnext1 = (q15_t) __SSAT(gnext, 16);
emilmont 1:fdd22bb7aa52 155 /* write gN-1(n) into state */
emilmont 1:fdd22bb7aa52 156 *px2++ = (q15_t) gnext1;
emilmont 1:fdd22bb7aa52 157
emilmont 1:fdd22bb7aa52 158
emilmont 1:fdd22bb7aa52 159 /* Process sample for 3nd, 7th ...taps */
emilmont 1:fdd22bb7aa52 160 /* Read gN-3(n-1) from state */
emilmont 1:fdd22bb7aa52 161 gcurr = *px1++;
emilmont 1:fdd22bb7aa52 162 /* Process sample for 3rd, 7th .. taps */
emilmont 1:fdd22bb7aa52 163 /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
emilmont 1:fdd22bb7aa52 164 fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
emilmont 1:fdd22bb7aa52 165 fcurr = __SSAT(fcurr, 16);
emilmont 1:fdd22bb7aa52 166 /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
emilmont 1:fdd22bb7aa52 167 gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
emilmont 1:fdd22bb7aa52 168 gnext2 = (q15_t) __SSAT(gnext, 16);
emilmont 1:fdd22bb7aa52 169 /* write gN-2(n) into state */
emilmont 1:fdd22bb7aa52 170 *px2++ = (q15_t) gnext2;
emilmont 1:fdd22bb7aa52 171
emilmont 1:fdd22bb7aa52 172 /* Read vN-1 and vN-2 at a time */
emilmont 1:fdd22bb7aa52 173 #ifndef UNALIGNED_SUPPORT_DISABLE
emilmont 1:fdd22bb7aa52 174
emilmont 1:fdd22bb7aa52 175 v = *__SIMD32(pv)++;
emilmont 1:fdd22bb7aa52 176
emilmont 1:fdd22bb7aa52 177 #else
emilmont 1:fdd22bb7aa52 178
emilmont 2:da51fb522205 179 v1 = *pv++;
emilmont 2:da51fb522205 180 v2 = *pv++;
emilmont 1:fdd22bb7aa52 181
emilmont 1:fdd22bb7aa52 182 #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 183
emilmont 2:da51fb522205 184 v = __PKHBT(v1, v2, 16);
emilmont 1:fdd22bb7aa52 185
emilmont 1:fdd22bb7aa52 186 #else
emilmont 1:fdd22bb7aa52 187
emilmont 2:da51fb522205 188 v = __PKHBT(v2, v1, 16);
emilmont 1:fdd22bb7aa52 189
emilmont 2:da51fb522205 190 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
emilmont 1:fdd22bb7aa52 191
emilmont 2:da51fb522205 192 #endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
emilmont 1:fdd22bb7aa52 193
emilmont 1:fdd22bb7aa52 194
emilmont 1:fdd22bb7aa52 195 /* Pack gN-1(n) and gN-2(n) */
emilmont 1:fdd22bb7aa52 196
emilmont 1:fdd22bb7aa52 197 #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 198
emilmont 1:fdd22bb7aa52 199 gnext = __PKHBT(gnext1, gnext2, 16);
emilmont 1:fdd22bb7aa52 200
emilmont 1:fdd22bb7aa52 201 #else
emilmont 1:fdd22bb7aa52 202
emilmont 1:fdd22bb7aa52 203 gnext = __PKHBT(gnext2, gnext1, 16);
emilmont 1:fdd22bb7aa52 204
emilmont 1:fdd22bb7aa52 205 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
emilmont 1:fdd22bb7aa52 206
emilmont 1:fdd22bb7aa52 207 /* y(n) += gN-1(n) * vN-1 */
emilmont 1:fdd22bb7aa52 208 /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
emilmont 1:fdd22bb7aa52 209 /* y(n) += gN-2(n) * vN-2 */
emilmont 1:fdd22bb7aa52 210 /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
emilmont 1:fdd22bb7aa52 211 acc = __SMLALD(gnext, v, acc);
emilmont 1:fdd22bb7aa52 212
emilmont 1:fdd22bb7aa52 213
emilmont 1:fdd22bb7aa52 214 /* Process sample for 4th, 8th ...taps */
emilmont 1:fdd22bb7aa52 215 /* Read gN-4(n-1) from state */
emilmont 1:fdd22bb7aa52 216 gcurr = *px1++;
emilmont 1:fdd22bb7aa52 217 /* Process sample for 4th, 8th .. taps */
emilmont 1:fdd22bb7aa52 218 /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
emilmont 1:fdd22bb7aa52 219 fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
emilmont 1:fdd22bb7aa52 220 fnext = __SSAT(fnext, 16);
emilmont 1:fdd22bb7aa52 221 /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */
emilmont 1:fdd22bb7aa52 222 gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
emilmont 1:fdd22bb7aa52 223 gnext1 = (q15_t) __SSAT(gnext, 16);
emilmont 1:fdd22bb7aa52 224 /* write gN-3(n) for the next sample process */
emilmont 1:fdd22bb7aa52 225 *px2++ = (q15_t) gnext1;
emilmont 1:fdd22bb7aa52 226
emilmont 1:fdd22bb7aa52 227
emilmont 1:fdd22bb7aa52 228 /* Process sample for 5th, 9th ...taps */
emilmont 1:fdd22bb7aa52 229 /* Read gN-5(n-1) from state */
emilmont 1:fdd22bb7aa52 230 gcurr = *px1++;
emilmont 1:fdd22bb7aa52 231 /* Process sample for 5th, 9th .. taps */
emilmont 1:fdd22bb7aa52 232 /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */
emilmont 1:fdd22bb7aa52 233 fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
emilmont 1:fdd22bb7aa52 234 fcurr = __SSAT(fcurr, 16);
emilmont 1:fdd22bb7aa52 235 /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
emilmont 1:fdd22bb7aa52 236 gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
emilmont 1:fdd22bb7aa52 237 gnext2 = (q15_t) __SSAT(gnext, 16);
emilmont 1:fdd22bb7aa52 238 /* write gN-4(n) for the next sample process */
emilmont 1:fdd22bb7aa52 239 *px2++ = (q15_t) gnext2;
emilmont 1:fdd22bb7aa52 240
emilmont 1:fdd22bb7aa52 241 /* Read vN-3 and vN-4 at a time */
emilmont 1:fdd22bb7aa52 242 #ifndef UNALIGNED_SUPPORT_DISABLE
emilmont 1:fdd22bb7aa52 243
emilmont 1:fdd22bb7aa52 244 v = *__SIMD32(pv)++;
emilmont 1:fdd22bb7aa52 245
emilmont 1:fdd22bb7aa52 246 #else
emilmont 1:fdd22bb7aa52 247
emilmont 2:da51fb522205 248 v1 = *pv++;
emilmont 2:da51fb522205 249 v2 = *pv++;
emilmont 1:fdd22bb7aa52 250
emilmont 1:fdd22bb7aa52 251 #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 252
emilmont 2:da51fb522205 253 v = __PKHBT(v1, v2, 16);
emilmont 1:fdd22bb7aa52 254
emilmont 1:fdd22bb7aa52 255 #else
emilmont 1:fdd22bb7aa52 256
emilmont 2:da51fb522205 257 v = __PKHBT(v2, v1, 16);
emilmont 1:fdd22bb7aa52 258
emilmont 2:da51fb522205 259 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
emilmont 1:fdd22bb7aa52 260
emilmont 2:da51fb522205 261 #endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
emilmont 1:fdd22bb7aa52 262
emilmont 1:fdd22bb7aa52 263
emilmont 1:fdd22bb7aa52 264 /* Pack gN-3(n) and gN-4(n) */
emilmont 1:fdd22bb7aa52 265 #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 266
emilmont 1:fdd22bb7aa52 267 gnext = __PKHBT(gnext1, gnext2, 16);
emilmont 1:fdd22bb7aa52 268
emilmont 1:fdd22bb7aa52 269 #else
emilmont 1:fdd22bb7aa52 270
emilmont 1:fdd22bb7aa52 271 gnext = __PKHBT(gnext2, gnext1, 16);
emilmont 1:fdd22bb7aa52 272
emilmont 1:fdd22bb7aa52 273 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
emilmont 1:fdd22bb7aa52 274
emilmont 1:fdd22bb7aa52 275 /* y(n) += gN-4(n) * vN-4 */
emilmont 1:fdd22bb7aa52 276 /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
emilmont 1:fdd22bb7aa52 277 /* y(n) += gN-3(n) * vN-3 */
emilmont 1:fdd22bb7aa52 278 /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
emilmont 1:fdd22bb7aa52 279 acc = __SMLALD(gnext, v, acc);
emilmont 1:fdd22bb7aa52 280
emilmont 1:fdd22bb7aa52 281 tapCnt--;
emilmont 1:fdd22bb7aa52 282
emilmont 1:fdd22bb7aa52 283 }
emilmont 1:fdd22bb7aa52 284
emilmont 1:fdd22bb7aa52 285 fnext = fcurr;
emilmont 1:fdd22bb7aa52 286
emilmont 1:fdd22bb7aa52 287 /* If the filter length is not a multiple of 4, compute the remaining filter taps */
emilmont 1:fdd22bb7aa52 288 tapCnt = (numStages - 1u) % 0x4u;
emilmont 1:fdd22bb7aa52 289
emilmont 1:fdd22bb7aa52 290 while(tapCnt > 0u)
emilmont 1:fdd22bb7aa52 291 {
emilmont 1:fdd22bb7aa52 292 gcurr = *px1++;
emilmont 1:fdd22bb7aa52 293 /* Process sample for last taps */
emilmont 1:fdd22bb7aa52 294 fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
emilmont 1:fdd22bb7aa52 295 fnext = __SSAT(fnext, 16);
emilmont 1:fdd22bb7aa52 296 gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
emilmont 1:fdd22bb7aa52 297 gnext = __SSAT(gnext, 16);
emilmont 1:fdd22bb7aa52 298 /* Output samples for last taps */
emilmont 1:fdd22bb7aa52 299 acc += (q31_t) (((q31_t) gnext * (*pv++)));
emilmont 1:fdd22bb7aa52 300 *px2++ = (q15_t) gnext;
emilmont 1:fdd22bb7aa52 301 fcurr = fnext;
emilmont 1:fdd22bb7aa52 302
emilmont 1:fdd22bb7aa52 303 tapCnt--;
emilmont 1:fdd22bb7aa52 304 }
emilmont 1:fdd22bb7aa52 305
emilmont 1:fdd22bb7aa52 306 /* y(n) += g0(n) * v0 */
emilmont 1:fdd22bb7aa52 307 acc += (q31_t) (((q31_t) fnext * (*pv++)));
emilmont 1:fdd22bb7aa52 308
emilmont 1:fdd22bb7aa52 309 out = (q15_t) __SSAT(acc >> 15, 16);
emilmont 1:fdd22bb7aa52 310 *px2++ = (q15_t) fnext;
emilmont 1:fdd22bb7aa52 311
emilmont 1:fdd22bb7aa52 312 /* write out into pDst */
emilmont 1:fdd22bb7aa52 313 *pDst++ = out;
emilmont 1:fdd22bb7aa52 314
emilmont 1:fdd22bb7aa52 315 /* Advance the state pointer by 4 to process the next group of 4 samples */
emilmont 1:fdd22bb7aa52 316 pState = pState + 1u;
emilmont 1:fdd22bb7aa52 317 blkCnt--;
emilmont 1:fdd22bb7aa52 318
emilmont 1:fdd22bb7aa52 319 }
emilmont 1:fdd22bb7aa52 320
emilmont 1:fdd22bb7aa52 321 /* Processing is complete. Now copy last S->numStages samples to start of the buffer
emilmont 1:fdd22bb7aa52 322 for the preperation of next frame process */
emilmont 1:fdd22bb7aa52 323 /* Points to the start of the state buffer */
emilmont 1:fdd22bb7aa52 324 pStateCurnt = &S->pState[0];
emilmont 1:fdd22bb7aa52 325 pState = &S->pState[blockSize];
emilmont 1:fdd22bb7aa52 326
emilmont 1:fdd22bb7aa52 327 stgCnt = (numStages >> 2u);
emilmont 1:fdd22bb7aa52 328
emilmont 1:fdd22bb7aa52 329 /* copy data */
emilmont 1:fdd22bb7aa52 330 while(stgCnt > 0u)
emilmont 1:fdd22bb7aa52 331 {
emilmont 1:fdd22bb7aa52 332 #ifndef UNALIGNED_SUPPORT_DISABLE
emilmont 1:fdd22bb7aa52 333
emilmont 1:fdd22bb7aa52 334 *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
emilmont 1:fdd22bb7aa52 335 *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
emilmont 1:fdd22bb7aa52 336
emilmont 1:fdd22bb7aa52 337 #else
emilmont 1:fdd22bb7aa52 338
emilmont 1:fdd22bb7aa52 339 *pStateCurnt++ = *pState++;
emilmont 1:fdd22bb7aa52 340 *pStateCurnt++ = *pState++;
emilmont 1:fdd22bb7aa52 341 *pStateCurnt++ = *pState++;
emilmont 1:fdd22bb7aa52 342 *pStateCurnt++ = *pState++;
emilmont 1:fdd22bb7aa52 343
emilmont 2:da51fb522205 344 #endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
emilmont 1:fdd22bb7aa52 345
emilmont 1:fdd22bb7aa52 346 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 347 stgCnt--;
emilmont 1:fdd22bb7aa52 348
emilmont 1:fdd22bb7aa52 349 }
emilmont 1:fdd22bb7aa52 350
emilmont 1:fdd22bb7aa52 351 /* Calculation of count for remaining q15_t data */
emilmont 1:fdd22bb7aa52 352 stgCnt = (numStages) % 0x4u;
emilmont 1:fdd22bb7aa52 353
emilmont 1:fdd22bb7aa52 354 /* copy data */
emilmont 1:fdd22bb7aa52 355 while(stgCnt > 0u)
emilmont 1:fdd22bb7aa52 356 {
emilmont 1:fdd22bb7aa52 357 *pStateCurnt++ = *pState++;
emilmont 1:fdd22bb7aa52 358
emilmont 1:fdd22bb7aa52 359 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 360 stgCnt--;
emilmont 1:fdd22bb7aa52 361 }
emilmont 1:fdd22bb7aa52 362
emilmont 1:fdd22bb7aa52 363 #else
emilmont 1:fdd22bb7aa52 364
emilmont 1:fdd22bb7aa52 365 /* Run the below code for Cortex-M0 */
emilmont 1:fdd22bb7aa52 366
emilmont 1:fdd22bb7aa52 367 q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */
emilmont 1:fdd22bb7aa52 368 uint32_t stgCnt; /* Temporary variables for counts */
emilmont 1:fdd22bb7aa52 369 q63_t acc; /* Accumlator */
emilmont 1:fdd22bb7aa52 370 uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
emilmont 1:fdd22bb7aa52 371 q15_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
emilmont 1:fdd22bb7aa52 372 uint32_t numStages = S->numStages; /* number of stages */
emilmont 1:fdd22bb7aa52 373 q15_t *pState; /* State pointer */
emilmont 1:fdd22bb7aa52 374 q15_t *pStateCurnt; /* State current pointer */
emilmont 1:fdd22bb7aa52 375 q15_t out; /* Temporary variable for output */
emilmont 1:fdd22bb7aa52 376
emilmont 1:fdd22bb7aa52 377
emilmont 1:fdd22bb7aa52 378 blkCnt = blockSize;
emilmont 1:fdd22bb7aa52 379
emilmont 1:fdd22bb7aa52 380 pState = &S->pState[0];
emilmont 1:fdd22bb7aa52 381
emilmont 1:fdd22bb7aa52 382 /* Sample processing */
emilmont 1:fdd22bb7aa52 383 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 384 {
emilmont 1:fdd22bb7aa52 385 /* Read Sample from input buffer */
emilmont 1:fdd22bb7aa52 386 /* fN(n) = x(n) */
emilmont 1:fdd22bb7aa52 387 fcurr = *pSrc++;
emilmont 1:fdd22bb7aa52 388
emilmont 1:fdd22bb7aa52 389 /* Initialize state read pointer */
emilmont 1:fdd22bb7aa52 390 px1 = pState;
emilmont 1:fdd22bb7aa52 391 /* Initialize state write pointer */
emilmont 1:fdd22bb7aa52 392 px2 = pState;
emilmont 1:fdd22bb7aa52 393 /* Set accumulator to zero */
emilmont 1:fdd22bb7aa52 394 acc = 0;
emilmont 1:fdd22bb7aa52 395 /* Initialize Ladder coeff pointer */
emilmont 1:fdd22bb7aa52 396 pv = &S->pvCoeffs[0];
emilmont 1:fdd22bb7aa52 397 /* Initialize Reflection coeff pointer */
emilmont 1:fdd22bb7aa52 398 pk = &S->pkCoeffs[0];
emilmont 1:fdd22bb7aa52 399
emilmont 1:fdd22bb7aa52 400 tapCnt = numStages;
emilmont 1:fdd22bb7aa52 401
emilmont 1:fdd22bb7aa52 402 while(tapCnt > 0u)
emilmont 1:fdd22bb7aa52 403 {
emilmont 1:fdd22bb7aa52 404 gcurr = *px1++;
emilmont 1:fdd22bb7aa52 405 /* Process sample */
emilmont 1:fdd22bb7aa52 406 /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
emilmont 1:fdd22bb7aa52 407 fnext = fcurr - ((gcurr * (*pk)) >> 15);
emilmont 1:fdd22bb7aa52 408 fnext = __SSAT(fnext, 16);
emilmont 1:fdd22bb7aa52 409 /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
emilmont 1:fdd22bb7aa52 410 gnext = ((fnext * (*pk++)) >> 15) + gcurr;
emilmont 1:fdd22bb7aa52 411 gnext = __SSAT(gnext, 16);
emilmont 1:fdd22bb7aa52 412 /* Output samples */
emilmont 1:fdd22bb7aa52 413 /* y(n) += gN(n) * vN */
emilmont 1:fdd22bb7aa52 414 acc += (q31_t) ((gnext * (*pv++)));
emilmont 1:fdd22bb7aa52 415 /* write gN(n) into state for next sample processing */
emilmont 1:fdd22bb7aa52 416 *px2++ = (q15_t) gnext;
emilmont 1:fdd22bb7aa52 417 /* Update f values for next coefficient processing */
emilmont 1:fdd22bb7aa52 418 fcurr = fnext;
emilmont 1:fdd22bb7aa52 419
emilmont 1:fdd22bb7aa52 420 tapCnt--;
emilmont 1:fdd22bb7aa52 421 }
emilmont 1:fdd22bb7aa52 422
emilmont 1:fdd22bb7aa52 423 /* y(n) += g0(n) * v0 */
emilmont 1:fdd22bb7aa52 424 acc += (q31_t) ((fnext * (*pv++)));
emilmont 1:fdd22bb7aa52 425
emilmont 1:fdd22bb7aa52 426 out = (q15_t) __SSAT(acc >> 15, 16);
emilmont 1:fdd22bb7aa52 427 *px2++ = (q15_t) fnext;
emilmont 1:fdd22bb7aa52 428
emilmont 1:fdd22bb7aa52 429 /* write out into pDst */
emilmont 1:fdd22bb7aa52 430 *pDst++ = out;
emilmont 1:fdd22bb7aa52 431
emilmont 1:fdd22bb7aa52 432 /* Advance the state pointer by 1 to process the next group of samples */
emilmont 1:fdd22bb7aa52 433 pState = pState + 1u;
emilmont 1:fdd22bb7aa52 434 blkCnt--;
emilmont 1:fdd22bb7aa52 435
emilmont 1:fdd22bb7aa52 436 }
emilmont 1:fdd22bb7aa52 437
emilmont 1:fdd22bb7aa52 438 /* Processing is complete. Now copy last S->numStages samples to start of the buffer
emilmont 1:fdd22bb7aa52 439 for the preperation of next frame process */
emilmont 1:fdd22bb7aa52 440 /* Points to the start of the state buffer */
emilmont 1:fdd22bb7aa52 441 pStateCurnt = &S->pState[0];
emilmont 1:fdd22bb7aa52 442 pState = &S->pState[blockSize];
emilmont 1:fdd22bb7aa52 443
emilmont 1:fdd22bb7aa52 444 stgCnt = numStages;
emilmont 1:fdd22bb7aa52 445
emilmont 1:fdd22bb7aa52 446 /* copy data */
emilmont 1:fdd22bb7aa52 447 while(stgCnt > 0u)
emilmont 1:fdd22bb7aa52 448 {
emilmont 1:fdd22bb7aa52 449 *pStateCurnt++ = *pState++;
emilmont 1:fdd22bb7aa52 450
emilmont 1:fdd22bb7aa52 451 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 452 stgCnt--;
emilmont 1:fdd22bb7aa52 453 }
emilmont 1:fdd22bb7aa52 454
mbed_official 3:7a284390b0ce 455 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
emilmont 1:fdd22bb7aa52 456
emilmont 1:fdd22bb7aa52 457 }
emilmont 1:fdd22bb7aa52 458
emilmont 1:fdd22bb7aa52 459
emilmont 1:fdd22bb7aa52 460
emilmont 1:fdd22bb7aa52 461
emilmont 1:fdd22bb7aa52 462 /**
emilmont 1:fdd22bb7aa52 463 * @} end of IIR_Lattice group
emilmont 1:fdd22bb7aa52 464 */