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CMSIS DSP library

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cmsis_dsp/BasicMathFunctions/arm_shift_q31.c@5:3762170b6d4d, 2015-11-20 (annotated)

Committer:
mbed_official
Date:
Fri Nov 20 08:45:18 2015 +0000
Revision:
5:3762170b6d4d
Parent:
3:7a284390b0ce 
Synchronized with git revision 2eb940b9a73af188d3004a2575fdfbb05febe62b



Full URL: https://github.com/mbedmicro/mbed/commit/2eb940b9a73af188d3004a2575fdfbb05febe62b/



Added option to build rpc library. closes #1426

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 1:fdd22bb7aa52 1 /* ----------------------------------------------------------------------
mbed_official 5:3762170b6d4d 2 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
emilmont 1:fdd22bb7aa52 3 *
mbed_official 5:3762170b6d4d 4 * $Date: 19. March 2015
mbed_official 5:3762170b6d4d 5 * $Revision: V.1.4.5
emilmont 1:fdd22bb7aa52 6 *
emilmont 2:da51fb522205 7 * Project: CMSIS DSP Library
emilmont 2:da51fb522205 8 * Title: arm_shift_q31.c
emilmont 1:fdd22bb7aa52 9 *
emilmont 2:da51fb522205 10 * Description: Shifts the elements of a Q31 vector by a specified number of bits.
emilmont 1:fdd22bb7aa52 11 *
emilmont 1:fdd22bb7aa52 12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emilmont 1:fdd22bb7aa52 13 *
mbed_official 3:7a284390b0ce 14 * Redistribution and use in source and binary forms, with or without
mbed_official 3:7a284390b0ce 15 * modification, are permitted provided that the following conditions
mbed_official 3:7a284390b0ce 16 * are met:
mbed_official 3:7a284390b0ce 17 * - Redistributions of source code must retain the above copyright
mbed_official 3:7a284390b0ce 18 * notice, this list of conditions and the following disclaimer.
mbed_official 3:7a284390b0ce 19 * - Redistributions in binary form must reproduce the above copyright
mbed_official 3:7a284390b0ce 20 * notice, this list of conditions and the following disclaimer in
mbed_official 3:7a284390b0ce 21 * the documentation and/or other materials provided with the
mbed_official 3:7a284390b0ce 22 * distribution.
mbed_official 3:7a284390b0ce 23 * - Neither the name of ARM LIMITED nor the names of its contributors
mbed_official 3:7a284390b0ce 24 * may be used to endorse or promote products derived from this
mbed_official 3:7a284390b0ce 25 * software without specific prior written permission.
mbed_official 3:7a284390b0ce 26 *
mbed_official 3:7a284390b0ce 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
mbed_official 3:7a284390b0ce 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
mbed_official 3:7a284390b0ce 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
mbed_official 3:7a284390b0ce 30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
mbed_official 3:7a284390b0ce 31 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
mbed_official 3:7a284390b0ce 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
mbed_official 3:7a284390b0ce 33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 3:7a284390b0ce 34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 3:7a284390b0ce 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
mbed_official 3:7a284390b0ce 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 3:7a284390b0ce 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 3:7a284390b0ce 38 * POSSIBILITY OF SUCH DAMAGE.
emilmont 1:fdd22bb7aa52 39 * -------------------------------------------------------------------- */
emilmont 1:fdd22bb7aa52 40
emilmont 1:fdd22bb7aa52 41 #include "arm_math.h"
emilmont 1:fdd22bb7aa52 42
emilmont 1:fdd22bb7aa52 43 /**
emilmont 1:fdd22bb7aa52 44 * @ingroup groupMath
emilmont 1:fdd22bb7aa52 45 */
emilmont 1:fdd22bb7aa52 46 /**
emilmont 1:fdd22bb7aa52 47 * @defgroup shift Vector Shift
emilmont 1:fdd22bb7aa52 48 *
emilmont 1:fdd22bb7aa52 49 * Shifts the elements of a fixed-point vector by a specified number of bits.
emilmont 1:fdd22bb7aa52 50 * There are separate functions for Q7, Q15, and Q31 data types.
emilmont 1:fdd22bb7aa52 51 * The underlying algorithm used is:
emilmont 1:fdd22bb7aa52 52 *
emilmont 1:fdd22bb7aa52 53 * <pre>
emilmont 1:fdd22bb7aa52 54 * pDst[n] = pSrc[n] << shift, 0 <= n < blockSize.
emilmont 1:fdd22bb7aa52 55 * </pre>
emilmont 1:fdd22bb7aa52 56 *
emilmont 1:fdd22bb7aa52 57 * If <code>shift</code> is positive then the elements of the vector are shifted to the left.
emilmont 1:fdd22bb7aa52 58 * If <code>shift</code> is negative then the elements of the vector are shifted to the right.
mbed_official 3:7a284390b0ce 59 *
mbed_official 3:7a284390b0ce 60 * The functions support in-place computation allowing the source and destination
mbed_official 3:7a284390b0ce 61 * pointers to reference the same memory buffer.
emilmont 1:fdd22bb7aa52 62 */
emilmont 1:fdd22bb7aa52 63
emilmont 1:fdd22bb7aa52 64 /**
emilmont 1:fdd22bb7aa52 65 * @addtogroup shift
emilmont 1:fdd22bb7aa52 66 * @{
emilmont 1:fdd22bb7aa52 67 */
emilmont 1:fdd22bb7aa52 68
emilmont 1:fdd22bb7aa52 69 /**
emilmont 1:fdd22bb7aa52 70 * @brief Shifts the elements of a Q31 vector a specified number of bits.
emilmont 1:fdd22bb7aa52 71 * @param[in] *pSrc points to the input vector
emilmont 1:fdd22bb7aa52 72 * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
emilmont 1:fdd22bb7aa52 73 * @param[out] *pDst points to the output vector
emilmont 1:fdd22bb7aa52 74 * @param[in] blockSize number of samples in the vector
emilmont 1:fdd22bb7aa52 75 * @return none.
emilmont 1:fdd22bb7aa52 76 *
emilmont 1:fdd22bb7aa52 77 *
emilmont 1:fdd22bb7aa52 78 * <b>Scaling and Overflow Behavior:</b>
emilmont 1:fdd22bb7aa52 79 * \par
emilmont 1:fdd22bb7aa52 80 * The function uses saturating arithmetic.
emilmont 1:fdd22bb7aa52 81 * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
emilmont 1:fdd22bb7aa52 82 */
emilmont 1:fdd22bb7aa52 83
emilmont 1:fdd22bb7aa52 84 void arm_shift_q31(
emilmont 1:fdd22bb7aa52 85 q31_t * pSrc,
emilmont 1:fdd22bb7aa52 86 int8_t shiftBits,
emilmont 1:fdd22bb7aa52 87 q31_t * pDst,
emilmont 1:fdd22bb7aa52 88 uint32_t blockSize)
emilmont 1:fdd22bb7aa52 89 {
emilmont 1:fdd22bb7aa52 90 uint32_t blkCnt; /* loop counter */
emilmont 1:fdd22bb7aa52 91 uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */
emilmont 1:fdd22bb7aa52 92
mbed_official 3:7a284390b0ce 93 #ifndef ARM_MATH_CM0_FAMILY
emilmont 1:fdd22bb7aa52 94
emilmont 1:fdd22bb7aa52 95 q31_t in1, in2, in3, in4; /* Temporary input variables */
emilmont 1:fdd22bb7aa52 96 q31_t out1, out2, out3, out4; /* Temporary output variables */
emilmont 1:fdd22bb7aa52 97
emilmont 1:fdd22bb7aa52 98 /*loop Unrolling */
emilmont 1:fdd22bb7aa52 99 blkCnt = blockSize >> 2u;
emilmont 1:fdd22bb7aa52 100
emilmont 1:fdd22bb7aa52 101
emilmont 1:fdd22bb7aa52 102 if(sign == 0u)
emilmont 1:fdd22bb7aa52 103 {
emilmont 1:fdd22bb7aa52 104 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
emilmont 1:fdd22bb7aa52 105 ** a second loop below computes the remaining 1 to 3 samples. */
emilmont 1:fdd22bb7aa52 106 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 107 {
emilmont 1:fdd22bb7aa52 108 /* C = A << shiftBits */
emilmont 1:fdd22bb7aa52 109 /* Shift the input and then store the results in the destination buffer. */
emilmont 1:fdd22bb7aa52 110 in1 = *pSrc;
emilmont 1:fdd22bb7aa52 111 in2 = *(pSrc + 1);
emilmont 1:fdd22bb7aa52 112 out1 = in1 << shiftBits;
emilmont 1:fdd22bb7aa52 113 in3 = *(pSrc + 2);
emilmont 1:fdd22bb7aa52 114 out2 = in2 << shiftBits;
emilmont 1:fdd22bb7aa52 115 in4 = *(pSrc + 3);
emilmont 1:fdd22bb7aa52 116 if(in1 != (out1 >> shiftBits))
emilmont 1:fdd22bb7aa52 117 out1 = 0x7FFFFFFF ^ (in1 >> 31);
emilmont 1:fdd22bb7aa52 118
emilmont 1:fdd22bb7aa52 119 if(in2 != (out2 >> shiftBits))
emilmont 1:fdd22bb7aa52 120 out2 = 0x7FFFFFFF ^ (in2 >> 31);
emilmont 1:fdd22bb7aa52 121
emilmont 1:fdd22bb7aa52 122 *pDst = out1;
emilmont 1:fdd22bb7aa52 123 out3 = in3 << shiftBits;
emilmont 1:fdd22bb7aa52 124 *(pDst + 1) = out2;
emilmont 1:fdd22bb7aa52 125 out4 = in4 << shiftBits;
emilmont 1:fdd22bb7aa52 126
emilmont 1:fdd22bb7aa52 127 if(in3 != (out3 >> shiftBits))
emilmont 1:fdd22bb7aa52 128 out3 = 0x7FFFFFFF ^ (in3 >> 31);
emilmont 1:fdd22bb7aa52 129
emilmont 1:fdd22bb7aa52 130 if(in4 != (out4 >> shiftBits))
emilmont 1:fdd22bb7aa52 131 out4 = 0x7FFFFFFF ^ (in4 >> 31);
emilmont 1:fdd22bb7aa52 132
emilmont 1:fdd22bb7aa52 133 *(pDst + 2) = out3;
emilmont 1:fdd22bb7aa52 134 *(pDst + 3) = out4;
emilmont 1:fdd22bb7aa52 135
emilmont 1:fdd22bb7aa52 136 /* Update destination pointer to process next sampels */
emilmont 1:fdd22bb7aa52 137 pSrc += 4u;
emilmont 1:fdd22bb7aa52 138 pDst += 4u;
emilmont 1:fdd22bb7aa52 139
emilmont 1:fdd22bb7aa52 140 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 141 blkCnt--;
emilmont 1:fdd22bb7aa52 142 }
emilmont 1:fdd22bb7aa52 143 }
emilmont 1:fdd22bb7aa52 144 else
emilmont 1:fdd22bb7aa52 145 {
emilmont 1:fdd22bb7aa52 146
emilmont 1:fdd22bb7aa52 147 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
emilmont 1:fdd22bb7aa52 148 ** a second loop below computes the remaining 1 to 3 samples. */
emilmont 1:fdd22bb7aa52 149 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 150 {
emilmont 1:fdd22bb7aa52 151 /* C = A >> shiftBits */
emilmont 1:fdd22bb7aa52 152 /* Shift the input and then store the results in the destination buffer. */
emilmont 1:fdd22bb7aa52 153 in1 = *pSrc;
emilmont 1:fdd22bb7aa52 154 in2 = *(pSrc + 1);
emilmont 1:fdd22bb7aa52 155 in3 = *(pSrc + 2);
emilmont 1:fdd22bb7aa52 156 in4 = *(pSrc + 3);
emilmont 1:fdd22bb7aa52 157
emilmont 1:fdd22bb7aa52 158 *pDst = (in1 >> -shiftBits);
emilmont 1:fdd22bb7aa52 159 *(pDst + 1) = (in2 >> -shiftBits);
emilmont 1:fdd22bb7aa52 160 *(pDst + 2) = (in3 >> -shiftBits);
emilmont 1:fdd22bb7aa52 161 *(pDst + 3) = (in4 >> -shiftBits);
emilmont 1:fdd22bb7aa52 162
emilmont 1:fdd22bb7aa52 163
emilmont 1:fdd22bb7aa52 164 pSrc += 4u;
emilmont 1:fdd22bb7aa52 165 pDst += 4u;
emilmont 1:fdd22bb7aa52 166
emilmont 1:fdd22bb7aa52 167 blkCnt--;
emilmont 1:fdd22bb7aa52 168 }
emilmont 1:fdd22bb7aa52 169
emilmont 1:fdd22bb7aa52 170 }
emilmont 1:fdd22bb7aa52 171
emilmont 1:fdd22bb7aa52 172 /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
emilmont 1:fdd22bb7aa52 173 ** No loop unrolling is used. */
emilmont 1:fdd22bb7aa52 174 blkCnt = blockSize % 0x4u;
emilmont 1:fdd22bb7aa52 175
emilmont 1:fdd22bb7aa52 176 #else
emilmont 1:fdd22bb7aa52 177
emilmont 1:fdd22bb7aa52 178 /* Run the below code for Cortex-M0 */
emilmont 1:fdd22bb7aa52 179
emilmont 1:fdd22bb7aa52 180
emilmont 1:fdd22bb7aa52 181 /* Initialize blkCnt with number of samples */
emilmont 1:fdd22bb7aa52 182 blkCnt = blockSize;
emilmont 1:fdd22bb7aa52 183
mbed_official 3:7a284390b0ce 184 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
emilmont 1:fdd22bb7aa52 185
emilmont 1:fdd22bb7aa52 186
emilmont 1:fdd22bb7aa52 187 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 188 {
emilmont 1:fdd22bb7aa52 189 /* C = A (>> or <<) shiftBits */
emilmont 1:fdd22bb7aa52 190 /* Shift the input and then store the result in the destination buffer. */
emilmont 1:fdd22bb7aa52 191 *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) :
emilmont 1:fdd22bb7aa52 192 (*pSrc++ >> -shiftBits);
emilmont 1:fdd22bb7aa52 193
emilmont 1:fdd22bb7aa52 194 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 195 blkCnt--;
emilmont 1:fdd22bb7aa52 196 }
emilmont 1:fdd22bb7aa52 197
emilmont 1:fdd22bb7aa52 198
emilmont 1:fdd22bb7aa52 199 }
emilmont 1:fdd22bb7aa52 200
emilmont 1:fdd22bb7aa52 201 /**
emilmont 1:fdd22bb7aa52 202 * @} end of shift group
emilmont 1:fdd22bb7aa52 203 */