mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_clock.c@170:19eb464bc2be, 2017-08-03 (annotated)

Committer:
Kojto
Date:
Thu Aug 03 13:13:39 2017 +0100
Revision:
170:19eb464bc2be
Child:
178:79309dc6340a
This updates the lib to the mbed lib v 148

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 170:19eb464bc2be 1 /* mbed Microcontroller Library
Kojto 170:19eb464bc2be 2 * Copyright (c) 2006-2017 ARM Limited
Kojto 170:19eb464bc2be 3 *
Kojto 170:19eb464bc2be 4 * Licensed under the Apache License, Version 2.0 (the "License");
Kojto 170:19eb464bc2be 5 * you may not use this file except in compliance with the License.
Kojto 170:19eb464bc2be 6 * You may obtain a copy of the License at
Kojto 170:19eb464bc2be 7 *
Kojto 170:19eb464bc2be 8 * http://www.apache.org/licenses/LICENSE-2.0
Kojto 170:19eb464bc2be 9 *
Kojto 170:19eb464bc2be 10 * Unless required by applicable law or agreed to in writing, software
Kojto 170:19eb464bc2be 11 * distributed under the License is distributed on an "AS IS" BASIS,
Kojto 170:19eb464bc2be 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Kojto 170:19eb464bc2be 13 * See the License for the specific language governing permissions and
Kojto 170:19eb464bc2be 14 * limitations under the License.
Kojto 170:19eb464bc2be 15 */
Kojto 170:19eb464bc2be 16
Kojto 170:19eb464bc2be 17 /**
Kojto 170:19eb464bc2be 18 * This file configures the system clock as follows:
Kojto 170:19eb464bc2be 19 *-----------------------------------------------------------------
Kojto 170:19eb464bc2be 20 * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
Kojto 170:19eb464bc2be 21 * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
Kojto 170:19eb464bc2be 22 * | 3- USE_PLL_HSI (internal 16 MHz)
Kojto 170:19eb464bc2be 23 *-----------------------------------------------------------------
Kojto 170:19eb464bc2be 24 * SYSCLK(MHz) | 32
Kojto 170:19eb464bc2be 25 * AHBCLK (MHz) | 32
Kojto 170:19eb464bc2be 26 * APB1CLK (MHz) | 32
Kojto 170:19eb464bc2be 27 * USB capable | YES
Kojto 170:19eb464bc2be 28 *-----------------------------------------------------------------
Kojto 170:19eb464bc2be 29 */
Kojto 170:19eb464bc2be 30
Kojto 170:19eb464bc2be 31 #include "stm32l0xx.h"
Kojto 170:19eb464bc2be 32 #include "mbed_assert.h"
Kojto 170:19eb464bc2be 33
Kojto 170:19eb464bc2be 34 /*!< Uncomment the following line if you need to relocate your vector Table in
Kojto 170:19eb464bc2be 35 Internal SRAM. */
Kojto 170:19eb464bc2be 36 /* #define VECT_TAB_SRAM */
Kojto 170:19eb464bc2be 37 #define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
Kojto 170:19eb464bc2be 38 This value must be a multiple of 0x100. */
Kojto 170:19eb464bc2be 39
Kojto 170:19eb464bc2be 40 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
Kojto 170:19eb464bc2be 41 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
Kojto 170:19eb464bc2be 42 #define USE_PLL_HSI 0x2 // Use HSI internal clock
Kojto 170:19eb464bc2be 43
Kojto 170:19eb464bc2be 44 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
Kojto 170:19eb464bc2be 45 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
Kojto 170:19eb464bc2be 46 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
Kojto 170:19eb464bc2be 47
Kojto 170:19eb464bc2be 48 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
Kojto 170:19eb464bc2be 49 uint8_t SetSysClock_PLL_HSI(void);
Kojto 170:19eb464bc2be 50 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
Kojto 170:19eb464bc2be 51
Kojto 170:19eb464bc2be 52
Kojto 170:19eb464bc2be 53 /**
Kojto 170:19eb464bc2be 54 * @brief Setup the microcontroller system.
Kojto 170:19eb464bc2be 55 * @param None
Kojto 170:19eb464bc2be 56 * @retval None
Kojto 170:19eb464bc2be 57 */
Kojto 170:19eb464bc2be 58 void SystemInit (void)
Kojto 170:19eb464bc2be 59 {
Kojto 170:19eb464bc2be 60 /*!< Set MSION bit */
Kojto 170:19eb464bc2be 61 RCC->CR |= (uint32_t)0x00000100U;
Kojto 170:19eb464bc2be 62
Kojto 170:19eb464bc2be 63 /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
Kojto 170:19eb464bc2be 64 RCC->CFGR &= (uint32_t) 0x88FF400CU;
Kojto 170:19eb464bc2be 65
Kojto 170:19eb464bc2be 66 /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
Kojto 170:19eb464bc2be 67 RCC->CR &= (uint32_t)0xFEF6FFF6U;
Kojto 170:19eb464bc2be 68
Kojto 170:19eb464bc2be 69 /*!< Reset HSI48ON bit */
Kojto 170:19eb464bc2be 70 RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
Kojto 170:19eb464bc2be 71
Kojto 170:19eb464bc2be 72 /*!< Reset HSEBYP bit */
Kojto 170:19eb464bc2be 73 RCC->CR &= (uint32_t)0xFFFBFFFFU;
Kojto 170:19eb464bc2be 74
Kojto 170:19eb464bc2be 75 /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
Kojto 170:19eb464bc2be 76 RCC->CFGR &= (uint32_t)0xFF02FFFFU;
Kojto 170:19eb464bc2be 77
Kojto 170:19eb464bc2be 78 /*!< Disable all interrupts */
Kojto 170:19eb464bc2be 79 RCC->CIER = 0x00000000U;
Kojto 170:19eb464bc2be 80
Kojto 170:19eb464bc2be 81 /* Configure the Vector Table location add offset address ------------------*/
Kojto 170:19eb464bc2be 82 #ifdef VECT_TAB_SRAM
Kojto 170:19eb464bc2be 83 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
Kojto 170:19eb464bc2be 84 #else
Kojto 170:19eb464bc2be 85 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
Kojto 170:19eb464bc2be 86 #endif
Kojto 170:19eb464bc2be 87
Kojto 170:19eb464bc2be 88 }
Kojto 170:19eb464bc2be 89
Kojto 170:19eb464bc2be 90 /**
Kojto 170:19eb464bc2be 91 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
Kojto 170:19eb464bc2be 92 * AHB/APBx prescalers and Flash settings
Kojto 170:19eb464bc2be 93 * @note This function should be called only once the RCC clock configuration
Kojto 170:19eb464bc2be 94 * is reset to the default reset state (done in SystemInit() function).
Kojto 170:19eb464bc2be 95 * @param None
Kojto 170:19eb464bc2be 96 * @retval None
Kojto 170:19eb464bc2be 97 */
Kojto 170:19eb464bc2be 98 void SetSysClock(void)
Kojto 170:19eb464bc2be 99 {
Kojto 170:19eb464bc2be 100 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
Kojto 170:19eb464bc2be 101 /* 1- Try to start with HSE and external clock */
Kojto 170:19eb464bc2be 102 if (SetSysClock_PLL_HSE(1) == 0)
Kojto 170:19eb464bc2be 103 #endif
Kojto 170:19eb464bc2be 104 {
Kojto 170:19eb464bc2be 105 #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
Kojto 170:19eb464bc2be 106 /* 2- If fail try to start with HSE and external xtal */
Kojto 170:19eb464bc2be 107 if (SetSysClock_PLL_HSE(0) == 0)
Kojto 170:19eb464bc2be 108 #endif
Kojto 170:19eb464bc2be 109 {
Kojto 170:19eb464bc2be 110 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
Kojto 170:19eb464bc2be 111 /* 3- If fail start with HSI clock */
Kojto 170:19eb464bc2be 112 if (SetSysClock_PLL_HSI() == 0)
Kojto 170:19eb464bc2be 113 #endif
Kojto 170:19eb464bc2be 114 {
Kojto 170:19eb464bc2be 115 while(1) {
Kojto 170:19eb464bc2be 116 MBED_ASSERT(1);
Kojto 170:19eb464bc2be 117 }
Kojto 170:19eb464bc2be 118 }
Kojto 170:19eb464bc2be 119 }
Kojto 170:19eb464bc2be 120 }
Kojto 170:19eb464bc2be 121
Kojto 170:19eb464bc2be 122 /* Output clock on MCO1 pin(PA8) for debugging purpose */
Kojto 170:19eb464bc2be 123 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
Kojto 170:19eb464bc2be 124 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
Kojto 170:19eb464bc2be 125 }
Kojto 170:19eb464bc2be 126
Kojto 170:19eb464bc2be 127 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
Kojto 170:19eb464bc2be 128 /******************************************************************************/
Kojto 170:19eb464bc2be 129 /* PLL (clocked by HSE) used as System clock source */
Kojto 170:19eb464bc2be 130 /******************************************************************************/
Kojto 170:19eb464bc2be 131 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
Kojto 170:19eb464bc2be 132 {
Kojto 170:19eb464bc2be 133 RCC_ClkInitTypeDef RCC_ClkInitStruct;
Kojto 170:19eb464bc2be 134 RCC_OscInitTypeDef RCC_OscInitStruct;
Kojto 170:19eb464bc2be 135 RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
Kojto 170:19eb464bc2be 136
Kojto 170:19eb464bc2be 137 /* Used to gain time after DeepSleep in case HSI is used */
Kojto 170:19eb464bc2be 138 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
Kojto 170:19eb464bc2be 139 return 0;
Kojto 170:19eb464bc2be 140 }
Kojto 170:19eb464bc2be 141
Kojto 170:19eb464bc2be 142 /* The voltage scaling allows optimizing the power consumption when the device is
Kojto 170:19eb464bc2be 143 clocked below the maximum system frequency, to update the voltage scaling value
Kojto 170:19eb464bc2be 144 regarding system frequency refer to product datasheet. */
Kojto 170:19eb464bc2be 145 __PWR_CLK_ENABLE();
Kojto 170:19eb464bc2be 146 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
Kojto 170:19eb464bc2be 147
Kojto 170:19eb464bc2be 148 /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
Kojto 170:19eb464bc2be 149 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_HSI48;
Kojto 170:19eb464bc2be 150 if (bypass == 0) {
Kojto 170:19eb464bc2be 151 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
Kojto 170:19eb464bc2be 152 } else {
Kojto 170:19eb464bc2be 153 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
Kojto 170:19eb464bc2be 154 }
Kojto 170:19eb464bc2be 155 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
Kojto 170:19eb464bc2be 156 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
Kojto 170:19eb464bc2be 157 // PLLCLK = (8 MHz * 8)/2 = 32 MHz
Kojto 170:19eb464bc2be 158 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Kojto 170:19eb464bc2be 159 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
Kojto 170:19eb464bc2be 160 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_8;
Kojto 170:19eb464bc2be 161 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
Kojto 170:19eb464bc2be 162 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Kojto 170:19eb464bc2be 163 return 0; // FAIL
Kojto 170:19eb464bc2be 164 }
Kojto 170:19eb464bc2be 165
Kojto 170:19eb464bc2be 166 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
Kojto 170:19eb464bc2be 167 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
Kojto 170:19eb464bc2be 168 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
Kojto 170:19eb464bc2be 169 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
Kojto 170:19eb464bc2be 170 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
Kojto 170:19eb464bc2be 171 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
Kojto 170:19eb464bc2be 172 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
Kojto 170:19eb464bc2be 173 return 0; // FAIL
Kojto 170:19eb464bc2be 174 }
Kojto 170:19eb464bc2be 175
Kojto 170:19eb464bc2be 176 RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
Kojto 170:19eb464bc2be 177 RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
Kojto 170:19eb464bc2be 178 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
Kojto 170:19eb464bc2be 179 return 0; // FAIL
Kojto 170:19eb464bc2be 180 }
Kojto 170:19eb464bc2be 181
Kojto 170:19eb464bc2be 182 /* Output clock on MCO1 pin(PA8) for debugging purpose */
Kojto 170:19eb464bc2be 183 //if (bypass == 0)
Kojto 170:19eb464bc2be 184 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
Kojto 170:19eb464bc2be 185 //else
Kojto 170:19eb464bc2be 186 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
Kojto 170:19eb464bc2be 187
Kojto 170:19eb464bc2be 188 return 1; // OK
Kojto 170:19eb464bc2be 189 }
Kojto 170:19eb464bc2be 190 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
Kojto 170:19eb464bc2be 191
Kojto 170:19eb464bc2be 192 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
Kojto 170:19eb464bc2be 193 /******************************************************************************/
Kojto 170:19eb464bc2be 194 /* PLL (clocked by HSI) used as System clock source */
Kojto 170:19eb464bc2be 195 /******************************************************************************/
Kojto 170:19eb464bc2be 196 uint8_t SetSysClock_PLL_HSI(void)
Kojto 170:19eb464bc2be 197 {
Kojto 170:19eb464bc2be 198 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
Kojto 170:19eb464bc2be 199 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
Kojto 170:19eb464bc2be 200 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
Kojto 170:19eb464bc2be 201 RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
Kojto 170:19eb464bc2be 202
Kojto 170:19eb464bc2be 203 /* The voltage scaling allows optimizing the power consumption when the device is
Kojto 170:19eb464bc2be 204 clocked below the maximum system frequency, to update the voltage scaling value
Kojto 170:19eb464bc2be 205 regarding system frequency refer to product datasheet. */
Kojto 170:19eb464bc2be 206 __HAL_RCC_PWR_CLK_ENABLE();
Kojto 170:19eb464bc2be 207 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
Kojto 170:19eb464bc2be 208 __HAL_RCC_PWR_CLK_DISABLE();
Kojto 170:19eb464bc2be 209
Kojto 170:19eb464bc2be 210 /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
Kojto 170:19eb464bc2be 211 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
Kojto 170:19eb464bc2be 212 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
Kojto 170:19eb464bc2be 213 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
Kojto 170:19eb464bc2be 214 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
Kojto 170:19eb464bc2be 215 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
Kojto 170:19eb464bc2be 216 // PLLCLK = (16 MHz * 6)/3 = 32 MHz
Kojto 170:19eb464bc2be 217 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Kojto 170:19eb464bc2be 218 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
Kojto 170:19eb464bc2be 219 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_6;
Kojto 170:19eb464bc2be 220 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_3;
Kojto 170:19eb464bc2be 221 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Kojto 170:19eb464bc2be 222 return 0; // FAIL
Kojto 170:19eb464bc2be 223 }
Kojto 170:19eb464bc2be 224
Kojto 170:19eb464bc2be 225 /* Select HSI48 as USB clock source */
Kojto 170:19eb464bc2be 226 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
Kojto 170:19eb464bc2be 227 PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
Kojto 170:19eb464bc2be 228 HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
Kojto 170:19eb464bc2be 229
Kojto 170:19eb464bc2be 230 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
Kojto 170:19eb464bc2be 231 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
Kojto 170:19eb464bc2be 232 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
Kojto 170:19eb464bc2be 233 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
Kojto 170:19eb464bc2be 234 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
Kojto 170:19eb464bc2be 235 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
Kojto 170:19eb464bc2be 236 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
Kojto 170:19eb464bc2be 237 return 0; // FAIL
Kojto 170:19eb464bc2be 238 }
Kojto 170:19eb464bc2be 239
Kojto 170:19eb464bc2be 240 /* Configure the clock recovery system (CRS) ********************************/
Kojto 170:19eb464bc2be 241 /* Enable CRS Clock */
Kojto 170:19eb464bc2be 242 __HAL_RCC_CRS_CLK_ENABLE();
Kojto 170:19eb464bc2be 243 /* Default Synchro Signal division factor (not divided) */
Kojto 170:19eb464bc2be 244 RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
Kojto 170:19eb464bc2be 245 /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
Kojto 170:19eb464bc2be 246 RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
Kojto 170:19eb464bc2be 247 /* HSI48 is synchronized with USB SOF at 1KHz rate */
Kojto 170:19eb464bc2be 248 RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
Kojto 170:19eb464bc2be 249 RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
Kojto 170:19eb464bc2be 250 /* Set the TRIM[5:0] to the default value */
Kojto 170:19eb464bc2be 251 RCC_CRSInitStruct.HSI48CalibrationValue = 0x20;
Kojto 170:19eb464bc2be 252 /* Start automatic synchronization */
Kojto 170:19eb464bc2be 253 HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
Kojto 170:19eb464bc2be 254
Kojto 170:19eb464bc2be 255 /* Output clock on MCO1 pin(PA8) for debugging purpose */
Kojto 170:19eb464bc2be 256 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
Kojto 170:19eb464bc2be 257
Kojto 170:19eb464bc2be 258 return 1; // OK
Kojto 170:19eb464bc2be 259 }
Kojto 170:19eb464bc2be 260 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */