Diff: targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c

Revision:

173:e131a1973e81

Parent:

167:e84263d55307

Child:

174:b96e65c34a4d

--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c	Thu Aug 31 17:27:04 2017 +0100
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c	Fri Sep 15 14:59:18 2017 +0100
@@ -14,26 +14,39 @@
  * limitations under the License.
  */
 #include "rtl8195a.h"
-#include "system_8195a.h"
-#if   defined ( __CC_ARM )                                            /* ARM Compiler 4/5 */
-extern uint8_t Image$$RW_IRAM1$$ZI$$Base[];
-#define __bss_start__ Image$$RW_IRAM1$$ZI$$Base
-extern uint8_t Image$$RW_IRAM1$$ZI$$Limit[];
-#define __bss_end__ Image$$RW_IRAM1$$ZI$$Limit
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)       /* ARM Compiler 6 */
-extern uint8_t Image$$RW_IRAM1$$ZI$$Base[];
-#define __bss_start__ Image$$RW_IRAM1$$ZI$$Base
-extern uint8_t Image$$RW_IRAM1$$ZI$$Limit[];
-#define __bss_end__ Image$$RW_IRAM1$$ZI$$Limit
+
+#if defined(__CC_ARM)
+#include "cmsis_armcc.h"
+#elif defined(__GNUC__)
+#include "cmsis_gcc.h"
+#else
+#include <cmsis_iar.h>
+#endif
+
+
+#if defined(__CC_ARM) || \
+    (defined (__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050)
 
-#elif defined ( __ICCARM__ )
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
+extern uint8_t Image$$RW_IRAM2$$ZI$$Base[];
+extern uint8_t Image$$RW_IRAM2$$ZI$$Limit[];
+extern uint8_t Image$$TCM_OVERLAY$$ZI$$Base[];
+extern uint8_t Image$$TCM_OVERLAY$$ZI$$Limit[];
+extern uint8_t Image$$RW_DRAM2$$ZI$$Base[];
+extern uint8_t Image$$RW_DRAM2$$ZI$$Limit[];
+#define __bss_sram_start__ Image$$RW_IRAM2$$ZI$$Base
+#define __bss_sram_end__   Image$$RW_IRAM2$$ZI$$Limit
+#define __bss_dtcm_start__ Image$$TCM_OVERLAY$$ZI$$Base
+#define __bss_dtcm_end__   Image$$TCM_OVERLAY$$ZI$$Limit
+#define __bss_dram_start__ Image$$RW_DRAM2$$ZI$$Base
+#define __bss_dram_end__   Image$$RW_DRAM2$$ZI$$Limit
+#define __stackp           Image$$ARM_LIB_STACK$$ZI$$Limit
+
+#elif defined (__ICCARM__)
+
 #pragma section=".ram.bss"
-#pragma section=".rom.bss"
-#pragma section=".ram.start.table"
-#pragma section=".ram_image1.bss"
-#pragma section=".image2.start.table1"
-#pragma section=".image2.start.table2"
 
+extern uint32_t CSTACK$$Limit;
 uint8_t *__bss_start__;
 uint8_t *__bss_end__;
 
@@ -42,30 +55,34 @@
     __bss_start__ = (uint8_t *)__section_begin(".ram.bss");
     __bss_end__   = (uint8_t *)__section_end(".ram.bss");
 }
+#define __stackp           CSTACK$$Limit
+
 #else
-extern uint8_t __bss_start__[];
-extern uint8_t __bss_end__[];
-extern uint8_t __image1_bss_start__[];
-extern uint8_t __image1_bss_end__[];
-extern uint8_t __image2_entry_func__[];
-extern uint8_t __image2_validate_code__[];
+
+extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
+extern uint8_t __bss_sram_start__[];
+extern uint8_t __bss_sram_end__[];
+extern uint8_t __bss_dtcm_start__[];
+extern uint8_t __bss_dtcm_end__[];
+extern uint8_t __bss_dram_start__[];
+extern uint8_t __bss_dram_end__[];
+
+#define __stackp           __StackTop
 #endif
 
 extern VECTOR_Func NewVectorTable[];
 extern void SystemCoreClockUpdate(void);
 extern void PLAT_Start(void);
 extern void PLAT_Main(void);
-extern HAL_TIMER_OP HalTimerOp;
- 
-IMAGE2_START_RAM_FUN_SECTION const RAM_START_FUNCTION gImage2EntryFun0 = {
+
+IMAGE2_START_RAM_FUN_SECTION
+const RAM_START_FUNCTION gImage2EntryFun0 = {
     PLAT_Start
 };
 
-IMAGE1_VALID_PATTEN_SECTION const uint8_t RAM_IMG1_VALID_PATTEN[] = {
-    0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff
-};
-
-IMAGE2_VALID_PATTEN_SECTION const uint8_t RAM_IMG2_VALID_PATTEN[20] = {
+IMAGE2_VALID_PATTEN_SECTION
+const uint8_t IMAGE2_SIGNATURE[20] = {
     'R', 'T', 'K', 'W', 'i', 'n', 0x0, 0xff,
     (FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff),
     (FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff),
@@ -93,7 +110,7 @@
 #endif
 }
 
-#if defined ( __ICCARM__ )
+#if defined (__ICCARM__)
 void __TRAP_HardFaultHandler_Patch(uint32_t addr)
 {
     uint32_t cfsr;
@@ -118,9 +135,9 @@
              * Otherwise it will keep hitting MemMange Fault on the same assembly code.
              *
              * To step to next command, we need parse the assembly code to check if
-	     * it is 16-bit or 32-bit command.
+         * it is 16-bit or 32-bit command.
              * Ref: ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
-	     * Chapter A6 - Thumb Instruction Set Encoding
+         * Chapter A6 - Thumb Instruction Set Encoding
              *
              * However, the fault assembly code (Ex. LDR or ADR) is not actually executed,
              * So the register value is un-predictable.
@@ -154,96 +171,63 @@
 }
 #endif
 
-// Override original Interrupt Vector Table
-INFRA_START_SECTION void TRAP_OverrideTable(uint32_t stackp)
-{
-    // Override NMI Handler
-    NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
-
-    #if defined ( __ICCARM__ )
-    NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch;
-    #endif
-}
-
-INFRA_START_SECTION void PLAT_Init(void)
+extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
+// Image2 Entry Function
+void PLAT_Start(void)
 {
     uint32_t val;
 
-    //Set SPS lower voltage
+#if defined (__ICCARM__)
+    __iar_data_init_app();
+#endif
+
+    // Clear RAM BSS
+#if defined (__ICCARM__)
+    __rtl_memset_v1_00((void *)__bss_start__, 0, __bss_end__ - __bss_start__);
+#else
+    __rtl_memset_v1_00((void *)__bss_sram_start__, 0, __bss_sram_end__ - __bss_sram_start__);
+    __rtl_memset_v1_00((void *)__bss_dtcm_start__, 0, __bss_dtcm_end__ - __bss_dtcm_start__);
+    __rtl_memset_v1_00((void *)__bss_dram_start__, 0, __bss_dram_end__ - __bss_dram_start__);
+#endif
+
+    // Set MSP
+    __set_MSP((uint32_t)&__stackp - 0x100);
+    // Overwrite vector table
+    NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
+#if defined ( __ICCARM__ )
+    NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch;
+#endif
+
+    extern HAL_TIMER_OP_EXT HalTimerOpExt;
+    __rtl_memset_v1_00((void *)&HalTimerOpExt, 0, sizeof(HalTimerOpExt));
+    __rtl_memset_v1_00((void *)&HalTimerOp, 0, sizeof(HalTimerOp));
+
+    HalTimerOpInit_Patch(&HalTimerOp);
+    SystemCoreClockUpdate();
+
+    // Set SPS lower voltage
     val = __RTK_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0);
     val &= 0xf0ffffff;
     val |= 0x6000000;
     __RTK_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0, val);
-
-    //xtal buffer driving current
+    
+    // xtal buffer driving current
     val = __RTK_CTRL_READ32(REG_SYS_XTAL_CTRL1);
     val &= ~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1);
     val |= BIT_SYS_XTAL_DRV_RF1(1);
     __RTK_CTRL_WRITE32(REG_SYS_XTAL_CTRL1, val);
-}
 
-//3 Image 2
-extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
-
-//extern uint32_t mbed_stack_isr_start;
-//extern uint32_t mbed_stack_isr_size;
-INFRA_START_SECTION void PLAT_Start(void)
-{
-	u8 isFlashEn;
-#if defined ( __ICCARM__ )
-    __iar_data_init_app();
-#endif
-    // Clear RAM BSS
-    __rtl_memset_v1_00((void *)__bss_start__, 0, __bss_end__ - __bss_start__);
-
-    TRAP_OverrideTable(0x1FFFFFFC);
-/* add by Ian --for mbed isr stack address setting */
-		__set_MSP(0x1fffffbc);
-
-
-#ifdef CONFIG_SPIC_MODULE 
-	if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN) != 0) {
-		isFlashEn = 1;
-	} else {
-		isFlashEn = 0;
-	}
-#endif
+    // Initialize SPIC, then disable it for power saving.
+    if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN) != 0) {
+        SpicNVMCalLoadAll();
+        SpicReadIDRtl8195A();
+        SpicDisableRtl8195A();
+    }
 
 #ifdef CONFIG_TIMER_MODULE
-    HalTimerOpInit_Patch(&HalTimerOp);
+    Calibration32k();
 #endif
 
-	//DBG_8195A("===== Enter Image 2 ====\n");
-
-
-    SystemCoreClockUpdate();
-
-	if (isFlashEn) {
-#if CONFIG_SPIC_EN && SPIC_CALIBRATION_IN_NVM
-		SpicNVMCalLoadAll();
-#endif
-		SpicReadIDRtl8195A();
-		// turn off SPIC for power saving
-		SpicDisableRtl8195A();	
-	}
-
-
-    PLAT_Init();
-#ifdef CONFIG_TIMER_MODULE
-	Calibration32k();
-		
-#ifdef CONFIG_WDG
-#ifdef CONFIG_WDG_TEST
-		WDGInit();
-#endif  //CONFIG_WDG_TEST
-#endif  //CONFIG_WDG
-#endif  //CONFIG_TIMER_MODULE
-
-#ifdef CONFIG_SOC_PS_MODULE
-    //InitSoCPM();
-#endif    
-    /* GPIOA_7 does not pull high at power on. It causes SDIO Device
-     * hardware to enable automatically and occupy GPIOA[7:0] */
 #ifndef CONFIG_SDIO_DEVICE_EN
     SDIO_DEV_Disable();
 #endif
@@ -256,37 +240,41 @@
 extern void PendSV_Handler(void);
 extern void SysTick_Handler(void);
 
+// The Main App entry point
 #if defined (__CC_ARM)
 __asm void ARM_PLAT_Main(void)
 {
-	IMPORT  SystemInit
-	IMPORT  __main
-   	BL	SystemInit
-	BL  __main
+    IMPORT  SystemInit
+    IMPORT  __main
+    BL      SystemInit
+    BL  __main
+}
+#elif defined (__ICCARM__)
+extern void __iar_program_start(void);
+
+void IAR_PLAT_Main(void)
+{
+    SystemInit();
+    __iar_program_start();
 }
 #endif
 
-extern void __iar_program_start( void );
-// The Main App entry point
 void PLAT_Main(void)
 {
     TRAP_Init((void *)SVC_Handler, (void *)PendSV_Handler, (void *)SysTick_Handler);
 
-#if defined (__ICCARM__)
-	//IAR_PLAT_Main();
-	SystemInit();
-    __iar_program_start();
-#elif defined (__CC_ARM)
-	ARM_PLAT_Main();
-
-#elif defined (__GNUC__)
-    __asm (
-    		"ldr	r0,	=SystemInit	\n"
+#if defined (__CC_ARM)
+    ARM_PLAT_Main();
+#elif defined (__ICCARM__)
+    IAR_PLAT_Main();
+#else
+    __asm ("ldr  r0, =SystemInit   \n"
            "blx  r0                \n"
            "ldr  r0, =_start       \n"
            "bx   r0                \n"
     );
 #endif
+
     // Never reached
-    for(;;);
+    for (;;);
 }