mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/stm_spi_api.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 *******************************************************************************
<> 149:156823d33999 3 * Copyright (c) 2015, STMicroelectronics
<> 149:156823d33999 4 * All rights reserved.
<> 149:156823d33999 5 *
<> 149:156823d33999 6 * Redistribution and use in source and binary forms, with or without
<> 149:156823d33999 7 * modification, are permitted provided that the following conditions are met:
<> 149:156823d33999 8 *
<> 149:156823d33999 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 10 * this list of conditions and the following disclaimer.
<> 149:156823d33999 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 12 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 13 * and/or other materials provided with the distribution.
<> 149:156823d33999 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 15 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 16 * without specific prior written permission.
<> 149:156823d33999 17 *
<> 149:156823d33999 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 28 *******************************************************************************
<> 149:156823d33999 29 */
<> 149:156823d33999 30 #include "mbed_assert.h"
<> 149:156823d33999 31 #include "mbed_error.h"
AnnaBridge 179:b0033dcd6934 32 #include "mbed_debug.h"
<> 149:156823d33999 33 #include "spi_api.h"
<> 149:156823d33999 34
<> 149:156823d33999 35 #if DEVICE_SPI
<> 149:156823d33999 36 #include <stdbool.h>
<> 149:156823d33999 37 #include <math.h>
<> 149:156823d33999 38 #include <string.h>
<> 149:156823d33999 39 #include "cmsis.h"
<> 149:156823d33999 40 #include "pinmap.h"
<> 149:156823d33999 41 #include "PeripheralPins.h"
AnnaBridge 168:9672193075cf 42 #include "spi_device.h"
<> 149:156823d33999 43
<> 149:156823d33999 44 #if DEVICE_SPI_ASYNCH
AnnaBridge 187:0387e8f68319 45 #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi.spi))
<> 149:156823d33999 46 #else
AnnaBridge 187:0387e8f68319 47 #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi))
<> 149:156823d33999 48 #endif
<> 149:156823d33999 49
<> 149:156823d33999 50 #if DEVICE_SPI_ASYNCH
AnnaBridge 187:0387e8f68319 51 #define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
<> 149:156823d33999 52 #else
AnnaBridge 187:0387e8f68319 53 #define SPI_S(obj) (( struct spi_s *)(obj))
<> 149:156823d33999 54 #endif
<> 149:156823d33999 55
<> 149:156823d33999 56 #ifndef DEBUG_STDIO
<> 149:156823d33999 57 # define DEBUG_STDIO 0
<> 149:156823d33999 58 #endif
<> 149:156823d33999 59
<> 149:156823d33999 60 #if DEBUG_STDIO
<> 149:156823d33999 61 # include <stdio.h>
<> 149:156823d33999 62 # define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
<> 149:156823d33999 63 #else
<> 149:156823d33999 64 # define DEBUG_PRINTF(...) {}
<> 149:156823d33999 65 #endif
<> 149:156823d33999 66
AnnaBridge 173:e131a1973e81 67 /* Consider 10ms as the default timeout for sending/receving 1 byte */
AnnaBridge 173:e131a1973e81 68 #define TIMEOUT_1_BYTE 10
AnnaBridge 173:e131a1973e81 69
Anna Bridge 186:707f6e361f3e 70 #if defined(SPI_FLAG_FRLVL) // STM32F0 STM32F3 STM32F7 STM32L4
Anna Bridge 186:707f6e361f3e 71 extern HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
Anna Bridge 186:707f6e361f3e 72 #endif
Anna Bridge 186:707f6e361f3e 73
<> 149:156823d33999 74 void init_spi(spi_t *obj)
<> 149:156823d33999 75 {
<> 149:156823d33999 76 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 77 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 78
<> 149:156823d33999 79 __HAL_SPI_DISABLE(handle);
<> 149:156823d33999 80
<> 149:156823d33999 81 DEBUG_PRINTF("init_spi: instance=0x%8X\r\n", (int)handle->Instance);
<> 149:156823d33999 82 if (HAL_SPI_Init(handle) != HAL_OK) {
<> 149:156823d33999 83 error("Cannot initialize SPI");
<> 149:156823d33999 84 }
AnnaBridge 173:e131a1973e81 85 /* In case of standard 4 wires SPI,PI can be kept enabled all time
AnnaBridge 173:e131a1973e81 86 * and SCK will only be generated during the write operations. But in case
AnnaBridge 173:e131a1973e81 87 * of 3 wires, it should be only enabled during rd/wr unitary operations,
AnnaBridge 173:e131a1973e81 88 * which is handled inside STM32 HAL layer.
AnnaBridge 173:e131a1973e81 89 */
AnnaBridge 173:e131a1973e81 90 if (handle->Init.Direction == SPI_DIRECTION_2LINES) {
AnnaBridge 173:e131a1973e81 91 __HAL_SPI_ENABLE(handle);
AnnaBridge 173:e131a1973e81 92 }
<> 149:156823d33999 93 }
<> 149:156823d33999 94
<> 149:156823d33999 95 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
<> 149:156823d33999 96 {
<> 149:156823d33999 97 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 98 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 99
<> 149:156823d33999 100 // Determine the SPI to use
<> 149:156823d33999 101 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
<> 149:156823d33999 102 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
<> 149:156823d33999 103 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
<> 149:156823d33999 104 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
<> 149:156823d33999 105
<> 149:156823d33999 106 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
<> 149:156823d33999 107 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
<> 149:156823d33999 108
<> 149:156823d33999 109 spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
<> 149:156823d33999 110 MBED_ASSERT(spiobj->spi != (SPIName)NC);
<> 149:156823d33999 111
<> 149:156823d33999 112 #if defined SPI1_BASE
<> 149:156823d33999 113 // Enable SPI clock
<> 149:156823d33999 114 if (spiobj->spi == SPI_1) {
<> 149:156823d33999 115 __HAL_RCC_SPI1_CLK_ENABLE();
<> 149:156823d33999 116 spiobj->spiIRQ = SPI1_IRQn;
<> 149:156823d33999 117 }
<> 149:156823d33999 118 #endif
<> 149:156823d33999 119
<> 149:156823d33999 120 #if defined SPI2_BASE
<> 149:156823d33999 121 if (spiobj->spi == SPI_2) {
<> 149:156823d33999 122 __HAL_RCC_SPI2_CLK_ENABLE();
<> 149:156823d33999 123 spiobj->spiIRQ = SPI2_IRQn;
<> 149:156823d33999 124 }
<> 149:156823d33999 125 #endif
<> 149:156823d33999 126
<> 149:156823d33999 127 #if defined SPI3_BASE
<> 149:156823d33999 128 if (spiobj->spi == SPI_3) {
<> 149:156823d33999 129 __HAL_RCC_SPI3_CLK_ENABLE();
<> 149:156823d33999 130 spiobj->spiIRQ = SPI3_IRQn;
<> 149:156823d33999 131 }
<> 149:156823d33999 132 #endif
<> 149:156823d33999 133
<> 149:156823d33999 134 #if defined SPI4_BASE
<> 149:156823d33999 135 if (spiobj->spi == SPI_4) {
<> 149:156823d33999 136 __HAL_RCC_SPI4_CLK_ENABLE();
<> 149:156823d33999 137 spiobj->spiIRQ = SPI4_IRQn;
<> 149:156823d33999 138 }
<> 149:156823d33999 139 #endif
<> 149:156823d33999 140
<> 149:156823d33999 141 #if defined SPI5_BASE
<> 149:156823d33999 142 if (spiobj->spi == SPI_5) {
<> 149:156823d33999 143 __HAL_RCC_SPI5_CLK_ENABLE();
<> 149:156823d33999 144 spiobj->spiIRQ = SPI5_IRQn;
<> 149:156823d33999 145 }
<> 149:156823d33999 146 #endif
<> 149:156823d33999 147
<> 149:156823d33999 148 #if defined SPI6_BASE
<> 149:156823d33999 149 if (spiobj->spi == SPI_6) {
<> 149:156823d33999 150 __HAL_RCC_SPI6_CLK_ENABLE();
<> 149:156823d33999 151 spiobj->spiIRQ = SPI6_IRQn;
<> 149:156823d33999 152 }
<> 149:156823d33999 153 #endif
<> 149:156823d33999 154
<> 149:156823d33999 155 // Configure the SPI pins
<> 149:156823d33999 156 pinmap_pinout(mosi, PinMap_SPI_MOSI);
<> 149:156823d33999 157 pinmap_pinout(miso, PinMap_SPI_MISO);
<> 149:156823d33999 158 pinmap_pinout(sclk, PinMap_SPI_SCLK);
<> 149:156823d33999 159 spiobj->pin_miso = miso;
<> 149:156823d33999 160 spiobj->pin_mosi = mosi;
<> 149:156823d33999 161 spiobj->pin_sclk = sclk;
<> 149:156823d33999 162 spiobj->pin_ssel = ssel;
<> 149:156823d33999 163 if (ssel != NC) {
<> 149:156823d33999 164 pinmap_pinout(ssel, PinMap_SPI_SSEL);
Anna Bridge 186:707f6e361f3e 165 handle->Init.NSS = SPI_NSS_HARD_OUTPUT;
<> 149:156823d33999 166 } else {
<> 149:156823d33999 167 handle->Init.NSS = SPI_NSS_SOFT;
<> 149:156823d33999 168 }
<> 149:156823d33999 169
<> 149:156823d33999 170 /* Fill default value */
<> 149:156823d33999 171 handle->Instance = SPI_INST(obj);
<> 149:156823d33999 172 handle->Init.Mode = SPI_MODE_MASTER;
<> 149:156823d33999 173 handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
AnnaBridge 173:e131a1973e81 174
AnnaBridge 173:e131a1973e81 175 if (miso != NC) {
AnnaBridge 173:e131a1973e81 176 handle->Init.Direction = SPI_DIRECTION_2LINES;
AnnaBridge 173:e131a1973e81 177 } else {
AnnaBridge 187:0387e8f68319 178 handle->Init.Direction = SPI_DIRECTION_1LINE;
AnnaBridge 173:e131a1973e81 179 }
AnnaBridge 173:e131a1973e81 180
<> 149:156823d33999 181 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
<> 149:156823d33999 182 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
AnnaBridge 165:e614a9f1c9e2 183 handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
<> 149:156823d33999 184 handle->Init.CRCPolynomial = 7;
<> 149:156823d33999 185 handle->Init.DataSize = SPI_DATASIZE_8BIT;
<> 149:156823d33999 186 handle->Init.FirstBit = SPI_FIRSTBIT_MSB;
AnnaBridge 165:e614a9f1c9e2 187 handle->Init.TIMode = SPI_TIMODE_DISABLE;
<> 149:156823d33999 188
AnnaBridge 189:f392fc9709a3 189 #if TARGET_STM32H7
AnnaBridge 189:f392fc9709a3 190 handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
AnnaBridge 189:f392fc9709a3 191 handle->Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ENABLE;
AnnaBridge 189:f392fc9709a3 192 handle->Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
AnnaBridge 189:f392fc9709a3 193 #endif
AnnaBridge 189:f392fc9709a3 194
<> 149:156823d33999 195 init_spi(obj);
<> 149:156823d33999 196 }
<> 149:156823d33999 197
<> 149:156823d33999 198 void spi_free(spi_t *obj)
<> 149:156823d33999 199 {
<> 149:156823d33999 200 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 201 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 202
<> 149:156823d33999 203 DEBUG_PRINTF("spi_free\r\n");
<> 149:156823d33999 204
<> 149:156823d33999 205 __HAL_SPI_DISABLE(handle);
<> 149:156823d33999 206 HAL_SPI_DeInit(handle);
<> 149:156823d33999 207
<> 149:156823d33999 208 #if defined SPI1_BASE
<> 149:156823d33999 209 // Reset SPI and disable clock
<> 149:156823d33999 210 if (spiobj->spi == SPI_1) {
<> 149:156823d33999 211 __HAL_RCC_SPI1_FORCE_RESET();
<> 149:156823d33999 212 __HAL_RCC_SPI1_RELEASE_RESET();
<> 149:156823d33999 213 __HAL_RCC_SPI1_CLK_DISABLE();
<> 149:156823d33999 214 }
<> 149:156823d33999 215 #endif
<> 149:156823d33999 216 #if defined SPI2_BASE
<> 149:156823d33999 217 if (spiobj->spi == SPI_2) {
<> 149:156823d33999 218 __HAL_RCC_SPI2_FORCE_RESET();
<> 149:156823d33999 219 __HAL_RCC_SPI2_RELEASE_RESET();
<> 149:156823d33999 220 __HAL_RCC_SPI2_CLK_DISABLE();
<> 149:156823d33999 221 }
<> 149:156823d33999 222 #endif
<> 149:156823d33999 223
<> 149:156823d33999 224 #if defined SPI3_BASE
<> 149:156823d33999 225 if (spiobj->spi == SPI_3) {
<> 149:156823d33999 226 __HAL_RCC_SPI3_FORCE_RESET();
<> 149:156823d33999 227 __HAL_RCC_SPI3_RELEASE_RESET();
<> 149:156823d33999 228 __HAL_RCC_SPI3_CLK_DISABLE();
<> 149:156823d33999 229 }
<> 149:156823d33999 230 #endif
<> 149:156823d33999 231
<> 149:156823d33999 232 #if defined SPI4_BASE
<> 149:156823d33999 233 if (spiobj->spi == SPI_4) {
<> 149:156823d33999 234 __HAL_RCC_SPI4_FORCE_RESET();
<> 149:156823d33999 235 __HAL_RCC_SPI4_RELEASE_RESET();
<> 149:156823d33999 236 __HAL_RCC_SPI4_CLK_DISABLE();
<> 149:156823d33999 237 }
<> 149:156823d33999 238 #endif
<> 149:156823d33999 239
<> 149:156823d33999 240 #if defined SPI5_BASE
<> 149:156823d33999 241 if (spiobj->spi == SPI_5) {
<> 149:156823d33999 242 __HAL_RCC_SPI5_FORCE_RESET();
<> 149:156823d33999 243 __HAL_RCC_SPI5_RELEASE_RESET();
<> 149:156823d33999 244 __HAL_RCC_SPI5_CLK_DISABLE();
<> 149:156823d33999 245 }
<> 149:156823d33999 246 #endif
<> 149:156823d33999 247
<> 149:156823d33999 248 #if defined SPI6_BASE
<> 149:156823d33999 249 if (spiobj->spi == SPI_6) {
<> 149:156823d33999 250 __HAL_RCC_SPI6_FORCE_RESET();
<> 149:156823d33999 251 __HAL_RCC_SPI6_RELEASE_RESET();
<> 149:156823d33999 252 __HAL_RCC_SPI6_CLK_DISABLE();
<> 149:156823d33999 253 }
<> 149:156823d33999 254 #endif
<> 149:156823d33999 255
<> 149:156823d33999 256 // Configure GPIOs
<> 149:156823d33999 257 pin_function(spiobj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 258 pin_function(spiobj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 259 pin_function(spiobj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 260 if (handle->Init.NSS != SPI_NSS_SOFT) {
<> 149:156823d33999 261 pin_function(spiobj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 262 }
<> 149:156823d33999 263 }
<> 149:156823d33999 264
<> 149:156823d33999 265 void spi_format(spi_t *obj, int bits, int mode, int slave)
<> 149:156823d33999 266 {
<> 149:156823d33999 267 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 268 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 269
<> 149:156823d33999 270 DEBUG_PRINTF("spi_format, bits:%d, mode:%d, slave?:%d\r\n", bits, mode, slave);
<> 149:156823d33999 271
<> 149:156823d33999 272 // Save new values
<> 149:156823d33999 273 handle->Init.DataSize = (bits == 16) ? SPI_DATASIZE_16BIT : SPI_DATASIZE_8BIT;
<> 149:156823d33999 274
<> 149:156823d33999 275 switch (mode) {
<> 149:156823d33999 276 case 0:
<> 149:156823d33999 277 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
<> 149:156823d33999 278 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
<> 149:156823d33999 279 break;
<> 149:156823d33999 280 case 1:
<> 149:156823d33999 281 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
<> 149:156823d33999 282 handle->Init.CLKPhase = SPI_PHASE_2EDGE;
<> 149:156823d33999 283 break;
<> 149:156823d33999 284 case 2:
<> 149:156823d33999 285 handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
<> 149:156823d33999 286 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
<> 149:156823d33999 287 break;
<> 149:156823d33999 288 default:
<> 149:156823d33999 289 handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
<> 149:156823d33999 290 handle->Init.CLKPhase = SPI_PHASE_2EDGE;
<> 149:156823d33999 291 break;
<> 149:156823d33999 292 }
<> 149:156823d33999 293
<> 149:156823d33999 294 if (handle->Init.NSS != SPI_NSS_SOFT) {
<> 149:156823d33999 295 handle->Init.NSS = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
<> 149:156823d33999 296 }
<> 149:156823d33999 297
<> 149:156823d33999 298 handle->Init.Mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
<> 149:156823d33999 299
AnnaBridge 179:b0033dcd6934 300 if (slave && (handle->Init.Direction == SPI_DIRECTION_1LINE)) {
AnnaBridge 179:b0033dcd6934 301 /* SPI slave implemtation in MBED does not support the 3 wires SPI.
AnnaBridge 179:b0033dcd6934 302 * (e.g. when MISO is not connected). So we're forcing slave in
AnnaBridge 179:b0033dcd6934 303 * 2LINES mode. As MISO is not connected, slave will only read
AnnaBridge 179:b0033dcd6934 304 * from master, and cannot write to it. Inform user.
AnnaBridge 179:b0033dcd6934 305 */
AnnaBridge 179:b0033dcd6934 306 debug("3 wires SPI slave not supported - slave will only read\r\n");
AnnaBridge 179:b0033dcd6934 307 handle->Init.Direction = SPI_DIRECTION_2LINES;
AnnaBridge 179:b0033dcd6934 308 }
AnnaBridge 179:b0033dcd6934 309
<> 149:156823d33999 310 init_spi(obj);
<> 149:156823d33999 311 }
<> 149:156823d33999 312
<> 149:156823d33999 313 /*
<> 149:156823d33999 314 * Only the IP clock input is family dependant so it computed
<> 149:156823d33999 315 * separately in spi_get_clock_freq
<> 149:156823d33999 316 */
<> 149:156823d33999 317 extern int spi_get_clock_freq(spi_t *obj);
<> 149:156823d33999 318
AnnaBridge 189:f392fc9709a3 319 static const uint32_t baudrate_prescaler_table[] = {SPI_BAUDRATEPRESCALER_2,
AnnaBridge 187:0387e8f68319 320 SPI_BAUDRATEPRESCALER_4,
AnnaBridge 187:0387e8f68319 321 SPI_BAUDRATEPRESCALER_8,
AnnaBridge 187:0387e8f68319 322 SPI_BAUDRATEPRESCALER_16,
AnnaBridge 187:0387e8f68319 323 SPI_BAUDRATEPRESCALER_32,
AnnaBridge 187:0387e8f68319 324 SPI_BAUDRATEPRESCALER_64,
AnnaBridge 187:0387e8f68319 325 SPI_BAUDRATEPRESCALER_128,
AnnaBridge 187:0387e8f68319 326 SPI_BAUDRATEPRESCALER_256
AnnaBridge 187:0387e8f68319 327 };
<> 149:156823d33999 328
AnnaBridge 187:0387e8f68319 329 void spi_frequency(spi_t *obj, int hz)
AnnaBridge 187:0387e8f68319 330 {
<> 149:156823d33999 331 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 332 int spi_hz = 0;
<> 149:156823d33999 333 uint8_t prescaler_rank = 0;
AnnaBridge 187:0387e8f68319 334 uint8_t last_index = (sizeof(baudrate_prescaler_table) / sizeof(baudrate_prescaler_table[0])) - 1;
<> 149:156823d33999 335 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 336
<> 159:612c381a210f 337 /* Calculate the spi clock for prescaler_rank 0: SPI_BAUDRATEPRESCALER_2 */
<> 159:612c381a210f 338 spi_hz = spi_get_clock_freq(obj) / 2;
<> 149:156823d33999 339
<> 149:156823d33999 340 /* Define pre-scaler in order to get highest available frequency below requested frequency */
<> 159:612c381a210f 341 while ((spi_hz > hz) && (prescaler_rank < last_index)) {
<> 149:156823d33999 342 spi_hz = spi_hz / 2;
<> 149:156823d33999 343 prescaler_rank++;
<> 149:156823d33999 344 }
<> 149:156823d33999 345
<> 159:612c381a210f 346 /* Use the best fit pre-scaler */
<> 159:612c381a210f 347 handle->Init.BaudRatePrescaler = baudrate_prescaler_table[prescaler_rank];
<> 159:612c381a210f 348
<> 159:612c381a210f 349 /* In case maximum pre-scaler still gives too high freq, raise an error */
<> 159:612c381a210f 350 if (spi_hz > hz) {
<> 160:d5399cc887bb 351 DEBUG_PRINTF("WARNING: lowest SPI freq (%d) higher than requested (%d)\r\n", spi_hz, hz);
<> 149:156823d33999 352 }
<> 149:156823d33999 353
<> 159:612c381a210f 354 DEBUG_PRINTF("spi_frequency, request:%d, select:%d\r\n", hz, spi_hz);
<> 159:612c381a210f 355
<> 149:156823d33999 356 init_spi(obj);
<> 149:156823d33999 357 }
<> 149:156823d33999 358
<> 149:156823d33999 359 static inline int ssp_readable(spi_t *obj)
<> 149:156823d33999 360 {
<> 149:156823d33999 361 int status;
<> 149:156823d33999 362 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 363 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 364
<> 149:156823d33999 365 // Check if data is received
<> 149:156823d33999 366 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
<> 149:156823d33999 367 return status;
<> 149:156823d33999 368 }
<> 149:156823d33999 369
<> 149:156823d33999 370 static inline int ssp_writeable(spi_t *obj)
<> 149:156823d33999 371 {
<> 149:156823d33999 372 int status;
<> 149:156823d33999 373 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 374 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 375
<> 149:156823d33999 376 // Check if data is transmitted
<> 149:156823d33999 377 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
<> 149:156823d33999 378 return status;
<> 149:156823d33999 379 }
<> 149:156823d33999 380
<> 149:156823d33999 381 static inline int ssp_busy(spi_t *obj)
<> 149:156823d33999 382 {
<> 149:156823d33999 383 int status;
<> 149:156823d33999 384 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 385 SPI_HandleTypeDef *handle = &(spiobj->handle);
AnnaBridge 189:f392fc9709a3 386 #if TARGET_STM32H7
AnnaBridge 189:f392fc9709a3 387 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_RXWNE) != RESET) ? 1 : 0);
AnnaBridge 189:f392fc9709a3 388 #else /* TARGET_STM32H7 */
<> 149:156823d33999 389 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
AnnaBridge 189:f392fc9709a3 390 #endif /* TARGET_STM32H7 */
<> 149:156823d33999 391 return status;
<> 149:156823d33999 392 }
<> 149:156823d33999 393
<> 149:156823d33999 394 int spi_master_write(spi_t *obj, int value)
<> 149:156823d33999 395 {
<> 149:156823d33999 396 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 397 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 398
AnnaBridge 173:e131a1973e81 399 if (handle->Init.Direction == SPI_DIRECTION_1LINE) {
AnnaBridge 187:0387e8f68319 400 return HAL_SPI_Transmit(handle, (uint8_t *)&value, 1, TIMEOUT_1_BYTE);
AnnaBridge 173:e131a1973e81 401 }
AnnaBridge 173:e131a1973e81 402
AnnaBridge 168:9672193075cf 403 #if defined(LL_SPI_RX_FIFO_TH_HALF)
AnnaBridge 168:9672193075cf 404 /* Configure the default data size */
AnnaBridge 168:9672193075cf 405 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
AnnaBridge 168:9672193075cf 406 LL_SPI_SetRxFIFOThreshold(SPI_INST(obj), LL_SPI_RX_FIFO_TH_HALF);
AnnaBridge 168:9672193075cf 407 } else {
AnnaBridge 168:9672193075cf 408 LL_SPI_SetRxFIFOThreshold(SPI_INST(obj), LL_SPI_RX_FIFO_TH_QUARTER);
AnnaBridge 168:9672193075cf 409 }
AnnaBridge 168:9672193075cf 410 #endif
<> 149:156823d33999 411
AnnaBridge 168:9672193075cf 412 /* Here we're using LL which means direct registers access
AnnaBridge 168:9672193075cf 413 * There is no error management, so we may end up looping
AnnaBridge 189:f392fc9709a3 414 * infinitely here in case of faulty device for instance,
AnnaBridge 168:9672193075cf 415 * but this will increase performances significantly
AnnaBridge 168:9672193075cf 416 */
<> 149:156823d33999 417
AnnaBridge 189:f392fc9709a3 418 #if TARGET_STM32H7
AnnaBridge 189:f392fc9709a3 419 /* Master transfer start */
AnnaBridge 189:f392fc9709a3 420 LL_SPI_StartMasterTransfer(SPI_INST(obj));
AnnaBridge 189:f392fc9709a3 421
AnnaBridge 189:f392fc9709a3 422 /* Wait TXP flag to transmit data */
AnnaBridge 189:f392fc9709a3 423 while (!LL_SPI_IsActiveFlag_TXP(SPI_INST(obj)));
AnnaBridge 189:f392fc9709a3 424 #else
AnnaBridge 168:9672193075cf 425 /* Wait TXE flag to transmit data */
AnnaBridge 168:9672193075cf 426 while (!LL_SPI_IsActiveFlag_TXE(SPI_INST(obj)));
AnnaBridge 168:9672193075cf 427
AnnaBridge 189:f392fc9709a3 428 #endif /* TARGET_STM32H7 */
AnnaBridge 189:f392fc9709a3 429
AnnaBridge 189:f392fc9709a3 430 /* Transmit data */
AnnaBridge 168:9672193075cf 431 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
AnnaBridge 189:f392fc9709a3 432 LL_SPI_TransmitData16(SPI_INST(obj), (uint16_t)value);
<> 149:156823d33999 433 } else {
AnnaBridge 189:f392fc9709a3 434 LL_SPI_TransmitData8(SPI_INST(obj), (uint8_t)value);
AnnaBridge 168:9672193075cf 435 }
AnnaBridge 168:9672193075cf 436
AnnaBridge 189:f392fc9709a3 437 #if TARGET_STM32H7
AnnaBridge 189:f392fc9709a3 438 /* Wait for RXP or end of Transfer */
AnnaBridge 189:f392fc9709a3 439 while (!LL_SPI_IsActiveFlag_RXP(SPI_INST(obj)));
AnnaBridge 189:f392fc9709a3 440 #else /* TARGET_STM32H7 */
AnnaBridge 189:f392fc9709a3 441 /* Wait for RXNE flag before reading */
AnnaBridge 168:9672193075cf 442 while (!LL_SPI_IsActiveFlag_RXNE(SPI_INST(obj)));
AnnaBridge 189:f392fc9709a3 443 #endif /* TARGET_STM32H7 */
AnnaBridge 168:9672193075cf 444
AnnaBridge 189:f392fc9709a3 445 /* Read received data */
AnnaBridge 168:9672193075cf 446 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
AnnaBridge 168:9672193075cf 447 return LL_SPI_ReceiveData16(SPI_INST(obj));
AnnaBridge 168:9672193075cf 448 } else {
AnnaBridge 168:9672193075cf 449 return LL_SPI_ReceiveData8(SPI_INST(obj));
<> 149:156823d33999 450 }
<> 149:156823d33999 451 }
<> 149:156823d33999 452
Kojto 170:19eb464bc2be 453 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
Kojto 170:19eb464bc2be 454 char *rx_buffer, int rx_length, char write_fill)
AnnaBridge 167:e84263d55307 455 {
AnnaBridge 173:e131a1973e81 456 struct spi_s *spiobj = SPI_S(obj);
AnnaBridge 173:e131a1973e81 457 SPI_HandleTypeDef *handle = &(spiobj->handle);
AnnaBridge 167:e84263d55307 458 int total = (tx_length > rx_length) ? tx_length : rx_length;
AnnaBridge 173:e131a1973e81 459 int i = 0;
AnnaBridge 173:e131a1973e81 460 if (handle->Init.Direction == SPI_DIRECTION_2LINES) {
AnnaBridge 173:e131a1973e81 461 for (i = 0; i < total; i++) {
AnnaBridge 173:e131a1973e81 462 char out = (i < tx_length) ? tx_buffer[i] : write_fill;
AnnaBridge 173:e131a1973e81 463 char in = spi_master_write(obj, out);
AnnaBridge 173:e131a1973e81 464 if (i < rx_length) {
AnnaBridge 173:e131a1973e81 465 rx_buffer[i] = in;
AnnaBridge 173:e131a1973e81 466 }
AnnaBridge 173:e131a1973e81 467 }
AnnaBridge 173:e131a1973e81 468 } else {
AnnaBridge 173:e131a1973e81 469 /* In case of 1 WIRE only, first handle TX, then Rx */
AnnaBridge 173:e131a1973e81 470 if (tx_length != 0) {
AnnaBridge 187:0387e8f68319 471 if (HAL_OK != HAL_SPI_Transmit(handle, (uint8_t *)tx_buffer, tx_length, tx_length * TIMEOUT_1_BYTE)) {
AnnaBridge 173:e131a1973e81 472 /* report an error */
AnnaBridge 173:e131a1973e81 473 total = 0;
AnnaBridge 173:e131a1973e81 474 }
AnnaBridge 173:e131a1973e81 475 }
AnnaBridge 173:e131a1973e81 476 if (rx_length != 0) {
AnnaBridge 187:0387e8f68319 477 if (HAL_OK != HAL_SPI_Receive(handle, (uint8_t *)rx_buffer, rx_length, rx_length * TIMEOUT_1_BYTE)) {
AnnaBridge 173:e131a1973e81 478 /* report an error */
AnnaBridge 173:e131a1973e81 479 total = 0;
AnnaBridge 173:e131a1973e81 480 }
AnnaBridge 167:e84263d55307 481 }
AnnaBridge 167:e84263d55307 482 }
AnnaBridge 167:e84263d55307 483
AnnaBridge 167:e84263d55307 484 return total;
AnnaBridge 167:e84263d55307 485 }
AnnaBridge 167:e84263d55307 486
<> 149:156823d33999 487 int spi_slave_receive(spi_t *obj)
<> 149:156823d33999 488 {
<> 149:156823d33999 489 return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
<> 149:156823d33999 490 };
<> 149:156823d33999 491
<> 149:156823d33999 492 int spi_slave_read(spi_t *obj)
<> 149:156823d33999 493 {
<> 149:156823d33999 494 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 495 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 496 while (!ssp_readable(obj));
AnnaBridge 173:e131a1973e81 497 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
AnnaBridge 173:e131a1973e81 498 return LL_SPI_ReceiveData16(SPI_INST(obj));
<> 149:156823d33999 499 } else {
AnnaBridge 173:e131a1973e81 500 return LL_SPI_ReceiveData8(SPI_INST(obj));
<> 149:156823d33999 501 }
<> 149:156823d33999 502 }
<> 149:156823d33999 503
<> 149:156823d33999 504 void spi_slave_write(spi_t *obj, int value)
<> 149:156823d33999 505 {
<> 149:156823d33999 506 SPI_TypeDef *spi = SPI_INST(obj);
<> 149:156823d33999 507 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 508 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 509 while (!ssp_writeable(obj));
<> 149:156823d33999 510 if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
<> 149:156823d33999 511 // Force 8-bit access to the data register
<> 149:156823d33999 512 uint8_t *p_spi_dr = 0;
AnnaBridge 189:f392fc9709a3 513 #if TARGET_STM32H7
AnnaBridge 189:f392fc9709a3 514 p_spi_dr = (uint8_t *) & (spi->TXDR);
AnnaBridge 189:f392fc9709a3 515 #else /* TARGET_STM32H7 */
<> 149:156823d33999 516 p_spi_dr = (uint8_t *) & (spi->DR);
AnnaBridge 189:f392fc9709a3 517 #endif /* TARGET_STM32H7 */
<> 149:156823d33999 518 *p_spi_dr = (uint8_t)value;
<> 149:156823d33999 519 } else { // SPI_DATASIZE_16BIT
AnnaBridge 189:f392fc9709a3 520 #if TARGET_STM32H7
AnnaBridge 189:f392fc9709a3 521 spi->TXDR = (uint16_t)value;
AnnaBridge 189:f392fc9709a3 522 #else /* TARGET_STM32H7 */
<> 149:156823d33999 523 spi->DR = (uint16_t)value;
AnnaBridge 189:f392fc9709a3 524 #endif /* TARGET_STM32H7 */
<> 149:156823d33999 525 }
<> 149:156823d33999 526 }
<> 149:156823d33999 527
<> 149:156823d33999 528 int spi_busy(spi_t *obj)
<> 149:156823d33999 529 {
<> 149:156823d33999 530 return ssp_busy(obj);
<> 149:156823d33999 531 }
<> 149:156823d33999 532
AnnaBridge 189:f392fc9709a3 533 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 534 typedef enum {
<> 149:156823d33999 535 SPI_TRANSFER_TYPE_NONE = 0,
<> 149:156823d33999 536 SPI_TRANSFER_TYPE_TX = 1,
<> 149:156823d33999 537 SPI_TRANSFER_TYPE_RX = 2,
<> 149:156823d33999 538 SPI_TRANSFER_TYPE_TXRX = 3,
<> 149:156823d33999 539 } transfer_type_t;
<> 149:156823d33999 540
<> 149:156823d33999 541
<> 149:156823d33999 542 /// @returns the number of bytes transferred, or `0` if nothing transferred
<> 149:156823d33999 543 static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer_type, const void *tx, void *rx, size_t length)
<> 149:156823d33999 544 {
<> 149:156823d33999 545 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 546 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 547 bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
<> 149:156823d33999 548 // the HAL expects number of transfers instead of number of bytes
<> 149:156823d33999 549 // so for 16 bit transfer width the count needs to be halved
<> 149:156823d33999 550 size_t words;
<> 149:156823d33999 551
<> 149:156823d33999 552 DEBUG_PRINTF("SPI inst=0x%8X Start: %u, %u\r\n", (int)handle->Instance, transfer_type, length);
<> 149:156823d33999 553
<> 149:156823d33999 554 obj->spi.transfer_type = transfer_type;
<> 149:156823d33999 555
<> 149:156823d33999 556 if (is16bit) {
<> 149:156823d33999 557 words = length / 2;
<> 149:156823d33999 558 } else {
<> 149:156823d33999 559 words = length;
<> 149:156823d33999 560 }
<> 149:156823d33999 561
<> 149:156823d33999 562 // enable the interrupt
<> 149:156823d33999 563 IRQn_Type irq_n = spiobj->spiIRQ;
<> 153:fa9ff456f731 564 NVIC_DisableIRQ(irq_n);
<> 149:156823d33999 565 NVIC_ClearPendingIRQ(irq_n);
<> 149:156823d33999 566 NVIC_SetPriority(irq_n, 1);
<> 149:156823d33999 567 NVIC_EnableIRQ(irq_n);
<> 149:156823d33999 568
AnnaBridge 181:57724642e740 569 // flush FIFO
AnnaBridge 181:57724642e740 570 #if defined(SPI_FLAG_FRLVL) // STM32F0 STM32F3 STM32F7 STM32L4
AnnaBridge 181:57724642e740 571 HAL_SPIEx_FlushRxFifo(handle);
AnnaBridge 181:57724642e740 572 #endif
AnnaBridge 181:57724642e740 573
<> 149:156823d33999 574 // enable the right hal transfer
<> 149:156823d33999 575 int rc = 0;
AnnaBridge 187:0387e8f68319 576 switch (transfer_type) {
<> 149:156823d33999 577 case SPI_TRANSFER_TYPE_TXRX:
AnnaBridge 187:0387e8f68319 578 rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t *)tx, (uint8_t *)rx, words);
<> 149:156823d33999 579 break;
<> 149:156823d33999 580 case SPI_TRANSFER_TYPE_TX:
AnnaBridge 187:0387e8f68319 581 rc = HAL_SPI_Transmit_IT(handle, (uint8_t *)tx, words);
<> 149:156823d33999 582 break;
<> 149:156823d33999 583 case SPI_TRANSFER_TYPE_RX:
<> 149:156823d33999 584 // the receive function also "transmits" the receive buffer so in order
<> 149:156823d33999 585 // to guarantee that 0xff is on the line, we explicitly memset it here
<> 149:156823d33999 586 memset(rx, SPI_FILL_WORD, length);
AnnaBridge 187:0387e8f68319 587 rc = HAL_SPI_Receive_IT(handle, (uint8_t *)rx, words);
<> 149:156823d33999 588 break;
<> 149:156823d33999 589 default:
<> 149:156823d33999 590 length = 0;
<> 149:156823d33999 591 }
<> 149:156823d33999 592
<> 149:156823d33999 593 if (rc) {
<> 149:156823d33999 594 DEBUG_PRINTF("SPI: RC=%u\n", rc);
<> 149:156823d33999 595 length = 0;
<> 149:156823d33999 596 }
<> 149:156823d33999 597
<> 149:156823d33999 598 return length;
<> 149:156823d33999 599 }
<> 149:156823d33999 600
<> 149:156823d33999 601 // asynchronous API
<> 149:156823d33999 602 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
<> 149:156823d33999 603 {
<> 149:156823d33999 604 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 605 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 606
<> 149:156823d33999 607 // TODO: DMA usage is currently ignored
<> 149:156823d33999 608 (void) hint;
<> 149:156823d33999 609
<> 149:156823d33999 610 // check which use-case we have
<> 149:156823d33999 611 bool use_tx = (tx != NULL && tx_length > 0);
<> 149:156823d33999 612 bool use_rx = (rx != NULL && rx_length > 0);
<> 149:156823d33999 613 bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
<> 149:156823d33999 614
<> 149:156823d33999 615 // don't do anything, if the buffers aren't valid
AnnaBridge 187:0387e8f68319 616 if (!use_tx && !use_rx) {
<> 149:156823d33999 617 return;
AnnaBridge 187:0387e8f68319 618 }
<> 149:156823d33999 619
<> 149:156823d33999 620 // copy the buffers to the SPI object
<> 149:156823d33999 621 obj->tx_buff.buffer = (void *) tx;
<> 149:156823d33999 622 obj->tx_buff.length = tx_length;
<> 149:156823d33999 623 obj->tx_buff.pos = 0;
<> 149:156823d33999 624 obj->tx_buff.width = is16bit ? 16 : 8;
<> 149:156823d33999 625
<> 149:156823d33999 626 obj->rx_buff.buffer = rx;
<> 149:156823d33999 627 obj->rx_buff.length = rx_length;
<> 149:156823d33999 628 obj->rx_buff.pos = 0;
<> 149:156823d33999 629 obj->rx_buff.width = obj->tx_buff.width;
<> 149:156823d33999 630
<> 149:156823d33999 631 obj->spi.event = event;
<> 149:156823d33999 632
<> 149:156823d33999 633 DEBUG_PRINTF("SPI: Transfer: %u, %u\n", tx_length, rx_length);
<> 149:156823d33999 634
<> 149:156823d33999 635 // register the thunking handler
<> 149:156823d33999 636 IRQn_Type irq_n = spiobj->spiIRQ;
<> 149:156823d33999 637 NVIC_SetVector(irq_n, (uint32_t)handler);
<> 149:156823d33999 638
<> 149:156823d33999 639 // enable the right hal transfer
<> 149:156823d33999 640 if (use_tx && use_rx) {
<> 149:156823d33999 641 // we cannot manage different rx / tx sizes, let's use smaller one
AnnaBridge 187:0387e8f68319 642 size_t size = (tx_length < rx_length) ? tx_length : rx_length;
AnnaBridge 187:0387e8f68319 643 if (tx_length != rx_length) {
<> 149:156823d33999 644 DEBUG_PRINTF("SPI: Full duplex transfer only 1 size: %d\n", size);
<> 149:156823d33999 645 obj->tx_buff.length = size;
<> 149:156823d33999 646 obj->rx_buff.length = size;
<> 149:156823d33999 647 }
<> 149:156823d33999 648 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TXRX, tx, rx, size);
<> 149:156823d33999 649 } else if (use_tx) {
<> 149:156823d33999 650 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TX, tx, NULL, tx_length);
<> 149:156823d33999 651 } else if (use_rx) {
<> 149:156823d33999 652 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_RX, NULL, rx, rx_length);
<> 149:156823d33999 653 }
<> 149:156823d33999 654 }
<> 149:156823d33999 655
<> 153:fa9ff456f731 656 inline uint32_t spi_irq_handler_asynch(spi_t *obj)
<> 149:156823d33999 657 {
<> 149:156823d33999 658 int event = 0;
<> 149:156823d33999 659
<> 149:156823d33999 660 // call the CubeF4 handler, this will update the handle
<> 153:fa9ff456f731 661 HAL_SPI_IRQHandler(&obj->spi.handle);
<> 149:156823d33999 662
<> 153:fa9ff456f731 663 if (obj->spi.handle.State == HAL_SPI_STATE_READY) {
<> 149:156823d33999 664 // When HAL SPI is back to READY state, check if there was an error
<> 153:fa9ff456f731 665 int error = obj->spi.handle.ErrorCode;
AnnaBridge 187:0387e8f68319 666 if (error != HAL_SPI_ERROR_NONE) {
<> 149:156823d33999 667 // something went wrong and the transfer has definitely completed
<> 149:156823d33999 668 event = SPI_EVENT_ERROR | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
<> 149:156823d33999 669
<> 149:156823d33999 670 if (error & HAL_SPI_ERROR_OVR) {
<> 149:156823d33999 671 // buffer overrun
<> 149:156823d33999 672 event |= SPI_EVENT_RX_OVERFLOW;
<> 149:156823d33999 673 }
<> 149:156823d33999 674 } else {
<> 149:156823d33999 675 // else we're done
<> 149:156823d33999 676 event = SPI_EVENT_COMPLETE | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
AnnaBridge 187:0387e8f68319 677 }
AnnaBridge 187:0387e8f68319 678 // enable the interrupt
AnnaBridge 187:0387e8f68319 679 NVIC_DisableIRQ(obj->spi.spiIRQ);
AnnaBridge 187:0387e8f68319 680 NVIC_ClearPendingIRQ(obj->spi.spiIRQ);
<> 149:156823d33999 681 }
<> 149:156823d33999 682
<> 149:156823d33999 683
<> 149:156823d33999 684 return (event & (obj->spi.event | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE));
<> 149:156823d33999 685 }
<> 149:156823d33999 686
<> 149:156823d33999 687 uint8_t spi_active(spi_t *obj)
<> 149:156823d33999 688 {
<> 149:156823d33999 689 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 690 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 691 HAL_SPI_StateTypeDef state = HAL_SPI_GetState(handle);
<> 149:156823d33999 692
AnnaBridge 187:0387e8f68319 693 switch (state) {
<> 149:156823d33999 694 case HAL_SPI_STATE_RESET:
<> 149:156823d33999 695 case HAL_SPI_STATE_READY:
<> 149:156823d33999 696 case HAL_SPI_STATE_ERROR:
<> 149:156823d33999 697 return 0;
<> 149:156823d33999 698 default:
<> 149:156823d33999 699 return 1;
<> 149:156823d33999 700 }
<> 149:156823d33999 701 }
<> 149:156823d33999 702
<> 149:156823d33999 703 void spi_abort_asynch(spi_t *obj)
<> 149:156823d33999 704 {
<> 149:156823d33999 705 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 706 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 707
<> 149:156823d33999 708 // disable interrupt
<> 149:156823d33999 709 IRQn_Type irq_n = spiobj->spiIRQ;
<> 149:156823d33999 710 NVIC_ClearPendingIRQ(irq_n);
<> 149:156823d33999 711 NVIC_DisableIRQ(irq_n);
<> 149:156823d33999 712
<> 149:156823d33999 713 // clean-up
<> 149:156823d33999 714 __HAL_SPI_DISABLE(handle);
<> 149:156823d33999 715 HAL_SPI_DeInit(handle);
<> 149:156823d33999 716 HAL_SPI_Init(handle);
<> 149:156823d33999 717 __HAL_SPI_ENABLE(handle);
<> 149:156823d33999 718 }
<> 149:156823d33999 719
<> 149:156823d33999 720 #endif //DEVICE_SPI_ASYNCH
<> 149:156823d33999 721
<> 149:156823d33999 722 #endif