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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_clock.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 170:19eb464bc2be 1 /* mbed Microcontroller Library
Kojto 170:19eb464bc2be 2 * Copyright (c) 2006-2017 ARM Limited
Kojto 170:19eb464bc2be 3 *
Kojto 170:19eb464bc2be 4 * Licensed under the Apache License, Version 2.0 (the "License");
Kojto 170:19eb464bc2be 5 * you may not use this file except in compliance with the License.
Kojto 170:19eb464bc2be 6 * You may obtain a copy of the License at
Kojto 170:19eb464bc2be 7 *
Kojto 170:19eb464bc2be 8 * http://www.apache.org/licenses/LICENSE-2.0
Kojto 170:19eb464bc2be 9 *
Kojto 170:19eb464bc2be 10 * Unless required by applicable law or agreed to in writing, software
Kojto 170:19eb464bc2be 11 * distributed under the License is distributed on an "AS IS" BASIS,
Kojto 170:19eb464bc2be 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Kojto 170:19eb464bc2be 13 * See the License for the specific language governing permissions and
Kojto 170:19eb464bc2be 14 * limitations under the License.
Kojto 170:19eb464bc2be 15 */
Kojto 170:19eb464bc2be 16
Kojto 170:19eb464bc2be 17 /**
Kojto 170:19eb464bc2be 18 * This file configures the system clock as follows:
Kojto 170:19eb464bc2be 19 *--------------------------------------------------------------------
Kojto 170:19eb464bc2be 20 * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
Kojto 170:19eb464bc2be 21 * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
Kojto 170:19eb464bc2be 22 * | 3- USE_PLL_HSI (internal 16 MHz clock)
Kojto 170:19eb464bc2be 23 *--------------------------------------------------------------------
Kojto 170:19eb464bc2be 24 * SYSCLK(MHz) | 216
Kojto 170:19eb464bc2be 25 * AHBCLK (MHz) | 216
Kojto 170:19eb464bc2be 26 * APB1CLK (MHz) | 54
Kojto 170:19eb464bc2be 27 * APB2CLK (MHz) | 108
Kojto 170:19eb464bc2be 28 * USB capable (48 MHz) | YES
Kojto 170:19eb464bc2be 29 *--------------------------------------------------------------------
Kojto 170:19eb464bc2be 30 **/
Kojto 170:19eb464bc2be 31
Kojto 170:19eb464bc2be 32 #include "stm32f7xx.h"
AnnaBridge 181:57724642e740 33 #include "nvic_addr.h"
AnnaBridge 187:0387e8f68319 34 #include "mbed_error.h"
Kojto 170:19eb464bc2be 35
Kojto 170:19eb464bc2be 36 /*!< Uncomment the following line if you need to relocate your vector Table in
Kojto 170:19eb464bc2be 37 Internal SRAM. */
Kojto 170:19eb464bc2be 38 /* #define VECT_TAB_SRAM */
Kojto 170:19eb464bc2be 39 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
Kojto 170:19eb464bc2be 40 This value must be a multiple of 0x200. */
Kojto 170:19eb464bc2be 41
Kojto 170:19eb464bc2be 42 // clock source is selected with CLOCK_SOURCE in json config
Kojto 170:19eb464bc2be 43 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
Kojto 170:19eb464bc2be 44 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
Kojto 170:19eb464bc2be 45 #define USE_PLL_HSI 0x2 // Use HSI internal clock
Kojto 170:19eb464bc2be 46
Kojto 170:19eb464bc2be 47 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
Kojto 170:19eb464bc2be 48 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
Kojto 170:19eb464bc2be 49 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
Kojto 170:19eb464bc2be 50
Kojto 170:19eb464bc2be 51 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
Kojto 170:19eb464bc2be 52 uint8_t SetSysClock_PLL_HSI(void);
Kojto 170:19eb464bc2be 53 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
Kojto 170:19eb464bc2be 54
Kojto 170:19eb464bc2be 55
Kojto 170:19eb464bc2be 56 /**
Kojto 170:19eb464bc2be 57 * @brief Setup the microcontroller system
Kojto 170:19eb464bc2be 58 * Initialize the Embedded Flash Interface, the PLL and update the
Kojto 170:19eb464bc2be 59 * SystemFrequency variable.
Kojto 170:19eb464bc2be 60 * @param None
Kojto 170:19eb464bc2be 61 * @retval None
Kojto 170:19eb464bc2be 62 */
Kojto 170:19eb464bc2be 63 void SystemInit(void)
Kojto 170:19eb464bc2be 64 {
Kojto 170:19eb464bc2be 65 /* FPU settings ------------------------------------------------------------*/
Kojto 170:19eb464bc2be 66 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 187:0387e8f68319 67 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
Kojto 170:19eb464bc2be 68 #endif
Kojto 170:19eb464bc2be 69 /* Reset the RCC clock configuration to the default reset state ------------*/
Kojto 170:19eb464bc2be 70 /* Set HSION bit */
Kojto 170:19eb464bc2be 71 RCC->CR |= (uint32_t)0x00000001;
Kojto 170:19eb464bc2be 72
Kojto 170:19eb464bc2be 73 /* Reset CFGR register */
Kojto 170:19eb464bc2be 74 RCC->CFGR = 0x00000000;
Kojto 170:19eb464bc2be 75
Kojto 170:19eb464bc2be 76 /* Reset HSEON, CSSON and PLLON bits */
Kojto 170:19eb464bc2be 77 RCC->CR &= (uint32_t)0xFEF6FFFF;
Kojto 170:19eb464bc2be 78
Kojto 170:19eb464bc2be 79 /* Reset PLLCFGR register */
Kojto 170:19eb464bc2be 80 RCC->PLLCFGR = 0x24003010;
Kojto 170:19eb464bc2be 81
Kojto 170:19eb464bc2be 82 /* Reset HSEBYP bit */
Kojto 170:19eb464bc2be 83 RCC->CR &= (uint32_t)0xFFFBFFFF;
Kojto 170:19eb464bc2be 84
Kojto 170:19eb464bc2be 85 /* Disable all interrupts */
Kojto 170:19eb464bc2be 86 RCC->CIR = 0x00000000;
Kojto 170:19eb464bc2be 87
Kojto 170:19eb464bc2be 88 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
Kojto 170:19eb464bc2be 89 SystemInit_ExtMemCtl();
Kojto 170:19eb464bc2be 90 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
Kojto 170:19eb464bc2be 91
Kojto 170:19eb464bc2be 92 /* Configure the Vector Table location add offset address ------------------*/
Kojto 170:19eb464bc2be 93 #ifdef VECT_TAB_SRAM
Kojto 170:19eb464bc2be 94 SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
Kojto 170:19eb464bc2be 95 #else
AnnaBridge 181:57724642e740 96 SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
Kojto 170:19eb464bc2be 97 #endif
Kojto 170:19eb464bc2be 98
Kojto 170:19eb464bc2be 99 }
Kojto 170:19eb464bc2be 100
Kojto 170:19eb464bc2be 101 /**
Kojto 170:19eb464bc2be 102 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
Kojto 170:19eb464bc2be 103 * AHB/APBx prescalers and Flash settings
Kojto 170:19eb464bc2be 104 * @note This function should be called only once the RCC clock configuration
Kojto 170:19eb464bc2be 105 * is reset to the default reset state (done in SystemInit() function).
Kojto 170:19eb464bc2be 106 * @param None
Kojto 170:19eb464bc2be 107 * @retval None
Kojto 170:19eb464bc2be 108 */
Kojto 170:19eb464bc2be 109
Kojto 170:19eb464bc2be 110 void SetSysClock(void)
Kojto 170:19eb464bc2be 111 {
Kojto 170:19eb464bc2be 112 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
Kojto 170:19eb464bc2be 113 /* 1- Try to start with HSE and external clock */
Kojto 170:19eb464bc2be 114 if (SetSysClock_PLL_HSE(1) == 0)
Kojto 170:19eb464bc2be 115 #endif
Kojto 170:19eb464bc2be 116 {
Kojto 170:19eb464bc2be 117 #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
Kojto 170:19eb464bc2be 118 /* 2- If fail try to start with HSE and external xtal */
Kojto 170:19eb464bc2be 119 if (SetSysClock_PLL_HSE(0) == 0)
Kojto 170:19eb464bc2be 120 #endif
Kojto 170:19eb464bc2be 121 {
Kojto 170:19eb464bc2be 122 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
Kojto 170:19eb464bc2be 123 /* 3- If fail start with HSI clock */
Kojto 170:19eb464bc2be 124 if (SetSysClock_PLL_HSI() == 0)
Kojto 170:19eb464bc2be 125 #endif
Kojto 170:19eb464bc2be 126 {
AnnaBridge 187:0387e8f68319 127 {
AnnaBridge 187:0387e8f68319 128 error("SetSysClock failed\n");
Kojto 170:19eb464bc2be 129 }
Kojto 170:19eb464bc2be 130 }
Kojto 170:19eb464bc2be 131 }
Kojto 170:19eb464bc2be 132 }
Kojto 170:19eb464bc2be 133
Kojto 170:19eb464bc2be 134 // Output clock on MCO2 pin(PC9) for debugging purpose
Kojto 170:19eb464bc2be 135 // Can be visualized on CN8 connector pin 4
Kojto 170:19eb464bc2be 136 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
Kojto 170:19eb464bc2be 137 }
Kojto 170:19eb464bc2be 138
Kojto 170:19eb464bc2be 139 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
Kojto 170:19eb464bc2be 140 /******************************************************************************/
Kojto 170:19eb464bc2be 141 /* PLL (clocked by HSE) used as System clock source */
Kojto 170:19eb464bc2be 142 /******************************************************************************/
Kojto 170:19eb464bc2be 143 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
Kojto 170:19eb464bc2be 144 {
Kojto 170:19eb464bc2be 145 RCC_ClkInitTypeDef RCC_ClkInitStruct;
Kojto 170:19eb464bc2be 146 RCC_OscInitTypeDef RCC_OscInitStruct;
Kojto 170:19eb464bc2be 147 RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct;
Kojto 170:19eb464bc2be 148
Kojto 170:19eb464bc2be 149 // Enable power clock
Kojto 170:19eb464bc2be 150 __PWR_CLK_ENABLE();
Kojto 170:19eb464bc2be 151 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
Kojto 170:19eb464bc2be 152
Kojto 170:19eb464bc2be 153 // Enable HSE oscillator and activate PLL with HSE as source
Kojto 170:19eb464bc2be 154 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
Kojto 170:19eb464bc2be 155 if (bypass == 0) {
Kojto 170:19eb464bc2be 156 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
Kojto 170:19eb464bc2be 157 } else {
Kojto 170:19eb464bc2be 158 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External clock on OSC_IN */
Kojto 170:19eb464bc2be 159 }
Kojto 170:19eb464bc2be 160 // Warning: this configuration is for a 8 MHz xtal clock only
Kojto 170:19eb464bc2be 161 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Kojto 170:19eb464bc2be 162 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
Kojto 170:19eb464bc2be 163 RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
Kojto 170:19eb464bc2be 164 RCC_OscInitStruct.PLL.PLLN = 216; // VCO output clock = 432 MHz (2 MHz * 216)
Kojto 170:19eb464bc2be 165 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
Kojto 170:19eb464bc2be 166 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
Kojto 170:19eb464bc2be 167 RCC_OscInitStruct.PLL.PLLR = 2; // I2S clock
Kojto 170:19eb464bc2be 168
Kojto 170:19eb464bc2be 169 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Kojto 170:19eb464bc2be 170 return 0; // FAIL
Kojto 170:19eb464bc2be 171 }
Kojto 170:19eb464bc2be 172
Kojto 170:19eb464bc2be 173 // Activate the OverDrive to reach the 216 MHz Frequency
Kojto 170:19eb464bc2be 174 if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
Kojto 170:19eb464bc2be 175 return 0; // FAIL
Kojto 170:19eb464bc2be 176 }
Kojto 170:19eb464bc2be 177
Kojto 170:19eb464bc2be 178 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
Kojto 170:19eb464bc2be 179 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
Kojto 170:19eb464bc2be 180 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
Kojto 170:19eb464bc2be 181 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz
Kojto 170:19eb464bc2be 182 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz
Kojto 170:19eb464bc2be 183 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz
Kojto 170:19eb464bc2be 184
Kojto 170:19eb464bc2be 185 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
Kojto 170:19eb464bc2be 186 return 0; // FAIL
Kojto 170:19eb464bc2be 187 }
Kojto 170:19eb464bc2be 188
Kojto 170:19eb464bc2be 189 RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
Kojto 170:19eb464bc2be 190 RCC_PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
Kojto 170:19eb464bc2be 191 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) {
Kojto 170:19eb464bc2be 192 return 0; // FAIL
Kojto 170:19eb464bc2be 193 }
Kojto 170:19eb464bc2be 194
Kojto 170:19eb464bc2be 195 return 1; // OK
Kojto 170:19eb464bc2be 196 }
Kojto 170:19eb464bc2be 197 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
Kojto 170:19eb464bc2be 198
Kojto 170:19eb464bc2be 199 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
Kojto 170:19eb464bc2be 200 /******************************************************************************/
Kojto 170:19eb464bc2be 201 /* PLL (clocked by HSI) used as System clock source */
Kojto 170:19eb464bc2be 202 /******************************************************************************/
Kojto 170:19eb464bc2be 203 uint8_t SetSysClock_PLL_HSI(void)
Kojto 170:19eb464bc2be 204 {
Kojto 170:19eb464bc2be 205 RCC_ClkInitTypeDef RCC_ClkInitStruct;
Kojto 170:19eb464bc2be 206 RCC_OscInitTypeDef RCC_OscInitStruct;
Kojto 170:19eb464bc2be 207 RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct;
Kojto 170:19eb464bc2be 208
Kojto 170:19eb464bc2be 209 // Enable power clock
Kojto 170:19eb464bc2be 210 __PWR_CLK_ENABLE();
Kojto 170:19eb464bc2be 211
Kojto 170:19eb464bc2be 212 // Enable HSI oscillator and activate PLL with HSI as source
Kojto 170:19eb464bc2be 213 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
Kojto 170:19eb464bc2be 214 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
Kojto 170:19eb464bc2be 215 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
AnnaBridge 182:a56a73fd2a6f 216 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
Kojto 170:19eb464bc2be 217 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Kojto 170:19eb464bc2be 218 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
Kojto 170:19eb464bc2be 219 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
Kojto 170:19eb464bc2be 220 RCC_OscInitStruct.PLL.PLLN = 216; // VCO output clock = 432 MHz (2 MHz * 216)
Kojto 170:19eb464bc2be 221 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
Kojto 170:19eb464bc2be 222 RCC_OscInitStruct.PLL.PLLQ = 9;
Kojto 170:19eb464bc2be 223 RCC_OscInitStruct.PLL.PLLR = 2; // I2S clock
Kojto 170:19eb464bc2be 224
Kojto 170:19eb464bc2be 225 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Kojto 170:19eb464bc2be 226 return 0; // FAIL
Kojto 170:19eb464bc2be 227 }
Kojto 170:19eb464bc2be 228
Kojto 170:19eb464bc2be 229 // Activate the OverDrive to reach the 216 MHz Frequency
Kojto 170:19eb464bc2be 230 if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
Kojto 170:19eb464bc2be 231 return 0; // FAIL
Kojto 170:19eb464bc2be 232 }
Kojto 170:19eb464bc2be 233
Kojto 170:19eb464bc2be 234 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
Kojto 170:19eb464bc2be 235 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
Kojto 170:19eb464bc2be 236 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
Kojto 170:19eb464bc2be 237 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz
Kojto 170:19eb464bc2be 238 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz
Kojto 170:19eb464bc2be 239 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz
Kojto 170:19eb464bc2be 240
Kojto 170:19eb464bc2be 241 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
Kojto 170:19eb464bc2be 242 return 0; // FAIL
Kojto 170:19eb464bc2be 243 }
Kojto 170:19eb464bc2be 244
Kojto 170:19eb464bc2be 245 RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
Kojto 170:19eb464bc2be 246 RCC_PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
Kojto 170:19eb464bc2be 247 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) {
Kojto 170:19eb464bc2be 248 return 0; // FAIL
Kojto 170:19eb464bc2be 249 }
Kojto 170:19eb464bc2be 250
Kojto 170:19eb464bc2be 251 return 1; // OK
Kojto 170:19eb464bc2be 252 }
Kojto 170:19eb464bc2be 253 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */