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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_wwdg.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 156:95d6b41a828b 1 /**
<> 156:95d6b41a828b 2 ******************************************************************************
<> 156:95d6b41a828b 3 * @file stm32f0xx_ll_wwdg.h
<> 156:95d6b41a828b 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @brief Header file of WWDG LL module.
<> 156:95d6b41a828b 6 ******************************************************************************
<> 156:95d6b41a828b 7 * @attention
<> 156:95d6b41a828b 8 *
<> 156:95d6b41a828b 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 156:95d6b41a828b 10 *
<> 156:95d6b41a828b 11 * Redistribution and use in source and binary forms, with or without modification,
<> 156:95d6b41a828b 12 * are permitted provided that the following conditions are met:
<> 156:95d6b41a828b 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 156:95d6b41a828b 14 * this list of conditions and the following disclaimer.
<> 156:95d6b41a828b 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 156:95d6b41a828b 16 * this list of conditions and the following disclaimer in the documentation
<> 156:95d6b41a828b 17 * and/or other materials provided with the distribution.
<> 156:95d6b41a828b 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 156:95d6b41a828b 19 * may be used to endorse or promote products derived from this software
<> 156:95d6b41a828b 20 * without specific prior written permission.
<> 156:95d6b41a828b 21 *
<> 156:95d6b41a828b 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 156:95d6b41a828b 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 156:95d6b41a828b 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 156:95d6b41a828b 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 156:95d6b41a828b 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 156:95d6b41a828b 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 156:95d6b41a828b 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 156:95d6b41a828b 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 156:95d6b41a828b 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 156:95d6b41a828b 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 156:95d6b41a828b 32 *
<> 156:95d6b41a828b 33 ******************************************************************************
<> 156:95d6b41a828b 34 */
<> 156:95d6b41a828b 35
<> 156:95d6b41a828b 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 156:95d6b41a828b 37 #ifndef __STM32F0xx_LL_WWDG_H
<> 156:95d6b41a828b 38 #define __STM32F0xx_LL_WWDG_H
<> 156:95d6b41a828b 39
<> 156:95d6b41a828b 40 #ifdef __cplusplus
<> 156:95d6b41a828b 41 extern "C" {
<> 156:95d6b41a828b 42 #endif
<> 156:95d6b41a828b 43
<> 156:95d6b41a828b 44 /* Includes ------------------------------------------------------------------*/
<> 156:95d6b41a828b 45 #include "stm32f0xx.h"
<> 156:95d6b41a828b 46
<> 156:95d6b41a828b 47 /** @addtogroup STM32F0xx_LL_Driver
<> 156:95d6b41a828b 48 * @{
<> 156:95d6b41a828b 49 */
<> 156:95d6b41a828b 50
<> 156:95d6b41a828b 51 #if defined (WWDG)
<> 156:95d6b41a828b 52
<> 156:95d6b41a828b 53 /** @defgroup WWDG_LL WWDG
<> 156:95d6b41a828b 54 * @{
<> 156:95d6b41a828b 55 */
<> 156:95d6b41a828b 56
<> 156:95d6b41a828b 57 /* Private types -------------------------------------------------------------*/
<> 156:95d6b41a828b 58 /* Private variables ---------------------------------------------------------*/
<> 156:95d6b41a828b 59
<> 156:95d6b41a828b 60 /* Private constants ---------------------------------------------------------*/
<> 156:95d6b41a828b 61
<> 156:95d6b41a828b 62 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 63
<> 156:95d6b41a828b 64 /* Exported types ------------------------------------------------------------*/
<> 156:95d6b41a828b 65 /* Exported constants --------------------------------------------------------*/
<> 156:95d6b41a828b 66 /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
<> 156:95d6b41a828b 67 * @{
<> 156:95d6b41a828b 68 */
<> 156:95d6b41a828b 69
<> 156:95d6b41a828b 70
<> 156:95d6b41a828b 71 /** @defgroup WWDG_LL_EC_IT IT Defines
<> 156:95d6b41a828b 72 * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
<> 156:95d6b41a828b 73 * @{
<> 156:95d6b41a828b 74 */
<> 156:95d6b41a828b 75 #define LL_WWDG_CFR_EWI WWDG_CFR_EWI
<> 156:95d6b41a828b 76 /**
<> 156:95d6b41a828b 77 * @}
<> 156:95d6b41a828b 78 */
<> 156:95d6b41a828b 79
<> 156:95d6b41a828b 80 /** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
<> 156:95d6b41a828b 81 * @{
<> 156:95d6b41a828b 82 */
Anna Bridge 180:96ed750bd169 83 #define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
<> 156:95d6b41a828b 84 #define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
<> 156:95d6b41a828b 85 #define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
<> 156:95d6b41a828b 86 #define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
<> 156:95d6b41a828b 87 /**
<> 156:95d6b41a828b 88 * @}
<> 156:95d6b41a828b 89 */
<> 156:95d6b41a828b 90
<> 156:95d6b41a828b 91 /**
<> 156:95d6b41a828b 92 * @}
<> 156:95d6b41a828b 93 */
<> 156:95d6b41a828b 94
<> 156:95d6b41a828b 95 /* Exported macro ------------------------------------------------------------*/
<> 156:95d6b41a828b 96 /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
<> 156:95d6b41a828b 97 * @{
<> 156:95d6b41a828b 98 */
<> 156:95d6b41a828b 99 /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
<> 156:95d6b41a828b 100 * @{
<> 156:95d6b41a828b 101 */
<> 156:95d6b41a828b 102 /**
<> 156:95d6b41a828b 103 * @brief Write a value in WWDG register
<> 156:95d6b41a828b 104 * @param __INSTANCE__ WWDG Instance
<> 156:95d6b41a828b 105 * @param __REG__ Register to be written
<> 156:95d6b41a828b 106 * @param __VALUE__ Value to be written in the register
<> 156:95d6b41a828b 107 * @retval None
<> 156:95d6b41a828b 108 */
<> 156:95d6b41a828b 109 #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 156:95d6b41a828b 110
<> 156:95d6b41a828b 111 /**
<> 156:95d6b41a828b 112 * @brief Read a value in WWDG register
<> 156:95d6b41a828b 113 * @param __INSTANCE__ WWDG Instance
<> 156:95d6b41a828b 114 * @param __REG__ Register to be read
<> 156:95d6b41a828b 115 * @retval Register value
<> 156:95d6b41a828b 116 */
<> 156:95d6b41a828b 117 #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 156:95d6b41a828b 118 /**
<> 156:95d6b41a828b 119 * @}
<> 156:95d6b41a828b 120 */
<> 156:95d6b41a828b 121
<> 156:95d6b41a828b 122
<> 156:95d6b41a828b 123 /**
<> 156:95d6b41a828b 124 * @}
<> 156:95d6b41a828b 125 */
<> 156:95d6b41a828b 126
<> 156:95d6b41a828b 127 /* Exported functions --------------------------------------------------------*/
<> 156:95d6b41a828b 128 /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
<> 156:95d6b41a828b 129 * @{
<> 156:95d6b41a828b 130 */
<> 156:95d6b41a828b 131
<> 156:95d6b41a828b 132 /** @defgroup WWDG_LL_EF_Configuration Configuration
<> 156:95d6b41a828b 133 * @{
<> 156:95d6b41a828b 134 */
<> 156:95d6b41a828b 135 /**
<> 156:95d6b41a828b 136 * @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
<> 156:95d6b41a828b 137 * @note It is enabled by setting the WDGA bit in the WWDG_CR register,
<> 156:95d6b41a828b 138 * then it cannot be disabled again except by a reset.
<> 156:95d6b41a828b 139 * This bit is set by software and only cleared by hardware after a reset.
<> 156:95d6b41a828b 140 * When WDGA = 1, the watchdog can generate a reset.
<> 156:95d6b41a828b 141 * @rmtoll CR WDGA LL_WWDG_Enable
<> 156:95d6b41a828b 142 * @param WWDGx WWDG Instance
<> 156:95d6b41a828b 143 * @retval None
<> 156:95d6b41a828b 144 */
<> 156:95d6b41a828b 145 __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
<> 156:95d6b41a828b 146 {
<> 156:95d6b41a828b 147 SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
<> 156:95d6b41a828b 148 }
<> 156:95d6b41a828b 149
<> 156:95d6b41a828b 150 /**
<> 156:95d6b41a828b 151 * @brief Checks if Window Watchdog is enabled
<> 156:95d6b41a828b 152 * @rmtoll CR WDGA LL_WWDG_IsEnabled
<> 156:95d6b41a828b 153 * @param WWDGx WWDG Instance
<> 156:95d6b41a828b 154 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 155 */
<> 156:95d6b41a828b 156 __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
<> 156:95d6b41a828b 157 {
<> 156:95d6b41a828b 158 return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
<> 156:95d6b41a828b 159 }
<> 156:95d6b41a828b 160
<> 156:95d6b41a828b 161 /**
<> 156:95d6b41a828b 162 * @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
<> 156:95d6b41a828b 163 * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
<> 156:95d6b41a828b 164 * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
<> 156:95d6b41a828b 165 * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
<> 156:95d6b41a828b 166 * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
<> 156:95d6b41a828b 167 * @rmtoll CR T LL_WWDG_SetCounter
<> 156:95d6b41a828b 168 * @param WWDGx WWDG Instance
<> 156:95d6b41a828b 169 * @param Counter 0..0x7F (7 bit counter value)
<> 156:95d6b41a828b 170 * @retval None
<> 156:95d6b41a828b 171 */
<> 156:95d6b41a828b 172 __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
<> 156:95d6b41a828b 173 {
<> 156:95d6b41a828b 174 MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
<> 156:95d6b41a828b 175 }
<> 156:95d6b41a828b 176
<> 156:95d6b41a828b 177 /**
<> 156:95d6b41a828b 178 * @brief Return current Watchdog Counter Value (7 bits counter value)
<> 156:95d6b41a828b 179 * @rmtoll CR T LL_WWDG_GetCounter
<> 156:95d6b41a828b 180 * @param WWDGx WWDG Instance
<> 156:95d6b41a828b 181 * @retval 7 bit Watchdog Counter value
<> 156:95d6b41a828b 182 */
<> 156:95d6b41a828b 183 __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
<> 156:95d6b41a828b 184 {
<> 156:95d6b41a828b 185 return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
<> 156:95d6b41a828b 186 }
<> 156:95d6b41a828b 187
<> 156:95d6b41a828b 188 /**
<> 156:95d6b41a828b 189 * @brief Set the time base of the prescaler (WDGTB).
<> 156:95d6b41a828b 190 * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
<> 156:95d6b41a828b 191 * is decremented every (4096 x 2expWDGTB) PCLK cycles
<> 156:95d6b41a828b 192 * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
<> 156:95d6b41a828b 193 * @param WWDGx WWDG Instance
<> 156:95d6b41a828b 194 * @param Prescaler This parameter can be one of the following values:
<> 156:95d6b41a828b 195 * @arg @ref LL_WWDG_PRESCALER_1
<> 156:95d6b41a828b 196 * @arg @ref LL_WWDG_PRESCALER_2
<> 156:95d6b41a828b 197 * @arg @ref LL_WWDG_PRESCALER_4
<> 156:95d6b41a828b 198 * @arg @ref LL_WWDG_PRESCALER_8
<> 156:95d6b41a828b 199 * @retval None
<> 156:95d6b41a828b 200 */
<> 156:95d6b41a828b 201 __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
<> 156:95d6b41a828b 202 {
<> 156:95d6b41a828b 203 MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
<> 156:95d6b41a828b 204 }
<> 156:95d6b41a828b 205
<> 156:95d6b41a828b 206 /**
<> 156:95d6b41a828b 207 * @brief Return current Watchdog Prescaler Value
<> 156:95d6b41a828b 208 * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
<> 156:95d6b41a828b 209 * @param WWDGx WWDG Instance
<> 156:95d6b41a828b 210 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 211 * @arg @ref LL_WWDG_PRESCALER_1
<> 156:95d6b41a828b 212 * @arg @ref LL_WWDG_PRESCALER_2
<> 156:95d6b41a828b 213 * @arg @ref LL_WWDG_PRESCALER_4
<> 156:95d6b41a828b 214 * @arg @ref LL_WWDG_PRESCALER_8
<> 156:95d6b41a828b 215 */
<> 156:95d6b41a828b 216 __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
<> 156:95d6b41a828b 217 {
<> 156:95d6b41a828b 218 return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
<> 156:95d6b41a828b 219 }
<> 156:95d6b41a828b 220
<> 156:95d6b41a828b 221 /**
<> 156:95d6b41a828b 222 * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
<> 156:95d6b41a828b 223 * @note This window value defines when write in the WWDG_CR register
<> 156:95d6b41a828b 224 * to program Watchdog counter is allowed.
<> 156:95d6b41a828b 225 * Watchdog counter value update must occur only when the counter value
<> 156:95d6b41a828b 226 * is lower than the Watchdog window register value.
<> 156:95d6b41a828b 227 * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
<> 156:95d6b41a828b 228 * (in the control register) is refreshed before the downcounter has reached
<> 156:95d6b41a828b 229 * the watchdog window register value.
<> 156:95d6b41a828b 230 * Physically is possible to set the Window lower then 0x40 but it is not recommended.
<> 156:95d6b41a828b 231 * To generate an immediate reset, it is possible to set the Counter lower than 0x40.
<> 156:95d6b41a828b 232 * @rmtoll CFR W LL_WWDG_SetWindow
<> 156:95d6b41a828b 233 * @param WWDGx WWDG Instance
<> 156:95d6b41a828b 234 * @param Window 0x00..0x7F (7 bit Window value)
<> 156:95d6b41a828b 235 * @retval None
<> 156:95d6b41a828b 236 */
<> 156:95d6b41a828b 237 __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
<> 156:95d6b41a828b 238 {
<> 156:95d6b41a828b 239 MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
<> 156:95d6b41a828b 240 }
<> 156:95d6b41a828b 241
<> 156:95d6b41a828b 242 /**
<> 156:95d6b41a828b 243 * @brief Return current Watchdog Window Value (7 bits value)
<> 156:95d6b41a828b 244 * @rmtoll CFR W LL_WWDG_GetWindow
<> 156:95d6b41a828b 245 * @param WWDGx WWDG Instance
<> 156:95d6b41a828b 246 * @retval 7 bit Watchdog Window value
<> 156:95d6b41a828b 247 */
<> 156:95d6b41a828b 248 __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
<> 156:95d6b41a828b 249 {
<> 156:95d6b41a828b 250 return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
<> 156:95d6b41a828b 251 }
<> 156:95d6b41a828b 252
<> 156:95d6b41a828b 253 /**
<> 156:95d6b41a828b 254 * @}
<> 156:95d6b41a828b 255 */
<> 156:95d6b41a828b 256
<> 156:95d6b41a828b 257 /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
<> 156:95d6b41a828b 258 * @{
<> 156:95d6b41a828b 259 */
<> 156:95d6b41a828b 260 /**
<> 156:95d6b41a828b 261 * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
<> 156:95d6b41a828b 262 * @note This bit is set by hardware when the counter has reached the value 0x40.
<> 156:95d6b41a828b 263 * It must be cleared by software by writing 0.
<> 156:95d6b41a828b 264 * A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
<> 156:95d6b41a828b 265 * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
<> 156:95d6b41a828b 266 * @param WWDGx WWDG Instance
<> 156:95d6b41a828b 267 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 268 */
<> 156:95d6b41a828b 269 __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
<> 156:95d6b41a828b 270 {
<> 156:95d6b41a828b 271 return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
<> 156:95d6b41a828b 272 }
<> 156:95d6b41a828b 273
<> 156:95d6b41a828b 274 /**
<> 156:95d6b41a828b 275 * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
<> 156:95d6b41a828b 276 * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
<> 156:95d6b41a828b 277 * @param WWDGx WWDG Instance
<> 156:95d6b41a828b 278 * @retval None
<> 156:95d6b41a828b 279 */
<> 156:95d6b41a828b 280 __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
<> 156:95d6b41a828b 281 {
<> 156:95d6b41a828b 282 WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
<> 156:95d6b41a828b 283 }
<> 156:95d6b41a828b 284
<> 156:95d6b41a828b 285 /**
<> 156:95d6b41a828b 286 * @}
<> 156:95d6b41a828b 287 */
<> 156:95d6b41a828b 288
<> 156:95d6b41a828b 289 /** @defgroup WWDG_LL_EF_IT_Management IT_Management
<> 156:95d6b41a828b 290 * @{
<> 156:95d6b41a828b 291 */
<> 156:95d6b41a828b 292 /**
<> 156:95d6b41a828b 293 * @brief Enable the Early Wakeup Interrupt.
<> 156:95d6b41a828b 294 * @note When set, an interrupt occurs whenever the counter reaches value 0x40.
<> 156:95d6b41a828b 295 * This interrupt is only cleared by hardware after a reset
<> 156:95d6b41a828b 296 * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
<> 156:95d6b41a828b 297 * @param WWDGx WWDG Instance
<> 156:95d6b41a828b 298 * @retval None
<> 156:95d6b41a828b 299 */
<> 156:95d6b41a828b 300 __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
<> 156:95d6b41a828b 301 {
<> 156:95d6b41a828b 302 SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
<> 156:95d6b41a828b 303 }
<> 156:95d6b41a828b 304
<> 156:95d6b41a828b 305 /**
<> 156:95d6b41a828b 306 * @brief Check if Early Wakeup Interrupt is enabled
<> 156:95d6b41a828b 307 * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
<> 156:95d6b41a828b 308 * @param WWDGx WWDG Instance
<> 156:95d6b41a828b 309 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 310 */
<> 156:95d6b41a828b 311 __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
<> 156:95d6b41a828b 312 {
<> 156:95d6b41a828b 313 return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
<> 156:95d6b41a828b 314 }
<> 156:95d6b41a828b 315
<> 156:95d6b41a828b 316 /**
<> 156:95d6b41a828b 317 * @}
<> 156:95d6b41a828b 318 */
<> 156:95d6b41a828b 319
<> 156:95d6b41a828b 320 /**
<> 156:95d6b41a828b 321 * @}
<> 156:95d6b41a828b 322 */
<> 156:95d6b41a828b 323
<> 156:95d6b41a828b 324 /**
<> 156:95d6b41a828b 325 * @}
<> 156:95d6b41a828b 326 */
<> 156:95d6b41a828b 327
<> 156:95d6b41a828b 328 #endif /* WWDG */
<> 156:95d6b41a828b 329
<> 156:95d6b41a828b 330 /**
<> 156:95d6b41a828b 331 * @}
<> 156:95d6b41a828b 332 */
<> 156:95d6b41a828b 333
<> 156:95d6b41a828b 334 #ifdef __cplusplus
<> 156:95d6b41a828b 335 }
<> 156:95d6b41a828b 336 #endif
<> 156:95d6b41a828b 337
<> 156:95d6b41a828b 338 #endif /* __STM32F0xx_LL_WWDG_H */
<> 156:95d6b41a828b 339
<> 156:95d6b41a828b 340 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/