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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_utils.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 156:95d6b41a828b 1 /**
<> 156:95d6b41a828b 2 ******************************************************************************
<> 156:95d6b41a828b 3 * @file stm32f0xx_ll_utils.h
<> 156:95d6b41a828b 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @brief Header file of UTILS LL module.
<> 156:95d6b41a828b 6 @verbatim
<> 156:95d6b41a828b 7 ==============================================================================
<> 156:95d6b41a828b 8 ##### How to use this driver #####
<> 156:95d6b41a828b 9 ==============================================================================
<> 156:95d6b41a828b 10 [..]
<> 156:95d6b41a828b 11 The LL UTILS driver contains a set of generic APIs that can be
<> 156:95d6b41a828b 12 used by user:
<> 156:95d6b41a828b 13 (+) Device electronic signature
<> 156:95d6b41a828b 14 (+) Timing functions
<> 156:95d6b41a828b 15 (+) PLL configuration functions
<> 156:95d6b41a828b 16
<> 156:95d6b41a828b 17 @endverbatim
<> 156:95d6b41a828b 18 ******************************************************************************
<> 156:95d6b41a828b 19 * @attention
<> 156:95d6b41a828b 20 *
<> 156:95d6b41a828b 21 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 156:95d6b41a828b 22 *
<> 156:95d6b41a828b 23 * Redistribution and use in source and binary forms, with or without modification,
<> 156:95d6b41a828b 24 * are permitted provided that the following conditions are met:
<> 156:95d6b41a828b 25 * 1. Redistributions of source code must retain the above copyright notice,
<> 156:95d6b41a828b 26 * this list of conditions and the following disclaimer.
<> 156:95d6b41a828b 27 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 156:95d6b41a828b 28 * this list of conditions and the following disclaimer in the documentation
<> 156:95d6b41a828b 29 * and/or other materials provided with the distribution.
<> 156:95d6b41a828b 30 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 156:95d6b41a828b 31 * may be used to endorse or promote products derived from this software
<> 156:95d6b41a828b 32 * without specific prior written permission.
<> 156:95d6b41a828b 33 *
<> 156:95d6b41a828b 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 156:95d6b41a828b 35 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 156:95d6b41a828b 36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 156:95d6b41a828b 37 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 156:95d6b41a828b 38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 156:95d6b41a828b 39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 156:95d6b41a828b 40 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 156:95d6b41a828b 41 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 156:95d6b41a828b 42 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 156:95d6b41a828b 43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 156:95d6b41a828b 44 *
<> 156:95d6b41a828b 45 ******************************************************************************
<> 156:95d6b41a828b 46 */
<> 156:95d6b41a828b 47
<> 156:95d6b41a828b 48 /* Define to prevent recursive inclusion -------------------------------------*/
<> 156:95d6b41a828b 49 #ifndef __STM32F0xx_LL_UTILS_H
<> 156:95d6b41a828b 50 #define __STM32F0xx_LL_UTILS_H
<> 156:95d6b41a828b 51
<> 156:95d6b41a828b 52 #ifdef __cplusplus
<> 156:95d6b41a828b 53 extern "C" {
<> 156:95d6b41a828b 54 #endif
<> 156:95d6b41a828b 55
<> 156:95d6b41a828b 56 /* Includes ------------------------------------------------------------------*/
<> 156:95d6b41a828b 57 #include "stm32f0xx.h"
<> 156:95d6b41a828b 58
<> 156:95d6b41a828b 59 /** @addtogroup STM32F0xx_LL_Driver
<> 156:95d6b41a828b 60 * @{
<> 156:95d6b41a828b 61 */
<> 156:95d6b41a828b 62
<> 156:95d6b41a828b 63 /** @defgroup UTILS_LL UTILS
<> 156:95d6b41a828b 64 * @{
<> 156:95d6b41a828b 65 */
<> 156:95d6b41a828b 66
<> 156:95d6b41a828b 67 /* Private types -------------------------------------------------------------*/
<> 156:95d6b41a828b 68 /* Private variables ---------------------------------------------------------*/
<> 156:95d6b41a828b 69
<> 156:95d6b41a828b 70 /* Private constants ---------------------------------------------------------*/
<> 156:95d6b41a828b 71 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
<> 156:95d6b41a828b 72 * @{
<> 156:95d6b41a828b 73 */
<> 156:95d6b41a828b 74
<> 156:95d6b41a828b 75 /* Max delay can be used in LL_mDelay */
Anna Bridge 180:96ed750bd169 76 #define LL_MAX_DELAY 0xFFFFFFFFU
<> 156:95d6b41a828b 77
<> 156:95d6b41a828b 78 /**
<> 156:95d6b41a828b 79 * @brief Unique device ID register base address
<> 156:95d6b41a828b 80 */
<> 156:95d6b41a828b 81 #define UID_BASE_ADDRESS UID_BASE
<> 156:95d6b41a828b 82
<> 156:95d6b41a828b 83 /**
<> 156:95d6b41a828b 84 * @brief Flash size data register base address
<> 156:95d6b41a828b 85 */
<> 156:95d6b41a828b 86 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
<> 156:95d6b41a828b 87
<> 156:95d6b41a828b 88 /**
<> 156:95d6b41a828b 89 * @}
<> 156:95d6b41a828b 90 */
<> 156:95d6b41a828b 91
<> 156:95d6b41a828b 92 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 93 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
<> 156:95d6b41a828b 94 * @{
<> 156:95d6b41a828b 95 */
<> 156:95d6b41a828b 96 /**
<> 156:95d6b41a828b 97 * @}
<> 156:95d6b41a828b 98 */
<> 156:95d6b41a828b 99 /* Exported types ------------------------------------------------------------*/
<> 156:95d6b41a828b 100 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
<> 156:95d6b41a828b 101 * @{
<> 156:95d6b41a828b 102 */
<> 156:95d6b41a828b 103 /**
<> 156:95d6b41a828b 104 * @brief UTILS PLL structure definition
<> 156:95d6b41a828b 105 */
<> 156:95d6b41a828b 106 typedef struct
<> 156:95d6b41a828b 107 {
<> 156:95d6b41a828b 108 uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
<> 156:95d6b41a828b 109 This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
<> 156:95d6b41a828b 110
<> 156:95d6b41a828b 111 This feature can be modified afterwards using unitary function
<> 156:95d6b41a828b 112 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
<> 156:95d6b41a828b 113
<> 156:95d6b41a828b 114 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
<> 156:95d6b41a828b 115 uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock.
<> 156:95d6b41a828b 116 This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
<> 156:95d6b41a828b 117
<> 156:95d6b41a828b 118 This feature can be modified afterwards using unitary function
<> 156:95d6b41a828b 119 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
<> 156:95d6b41a828b 120 #else
<> 156:95d6b41a828b 121 uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
<> 156:95d6b41a828b 122 This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
<> 156:95d6b41a828b 123
<> 156:95d6b41a828b 124 This feature can be modified afterwards using unitary function
<> 156:95d6b41a828b 125 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
<> 156:95d6b41a828b 126 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
<> 156:95d6b41a828b 127 } LL_UTILS_PLLInitTypeDef;
<> 156:95d6b41a828b 128
<> 156:95d6b41a828b 129 /**
<> 156:95d6b41a828b 130 * @brief UTILS System, AHB and APB buses clock configuration structure definition
<> 156:95d6b41a828b 131 */
<> 156:95d6b41a828b 132 typedef struct
<> 156:95d6b41a828b 133 {
<> 156:95d6b41a828b 134 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
<> 156:95d6b41a828b 135 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
<> 156:95d6b41a828b 136
<> 156:95d6b41a828b 137 This feature can be modified afterwards using unitary function
<> 156:95d6b41a828b 138 @ref LL_RCC_SetAHBPrescaler(). */
<> 156:95d6b41a828b 139
<> 156:95d6b41a828b 140 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
<> 156:95d6b41a828b 141 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
<> 156:95d6b41a828b 142
<> 156:95d6b41a828b 143 This feature can be modified afterwards using unitary function
<> 156:95d6b41a828b 144 @ref LL_RCC_SetAPB1Prescaler(). */
<> 156:95d6b41a828b 145 } LL_UTILS_ClkInitTypeDef;
<> 156:95d6b41a828b 146
<> 156:95d6b41a828b 147 /**
<> 156:95d6b41a828b 148 * @}
<> 156:95d6b41a828b 149 */
<> 156:95d6b41a828b 150
<> 156:95d6b41a828b 151 /* Exported constants --------------------------------------------------------*/
<> 156:95d6b41a828b 152 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
<> 156:95d6b41a828b 153 * @{
<> 156:95d6b41a828b 154 */
<> 156:95d6b41a828b 155
<> 156:95d6b41a828b 156 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
<> 156:95d6b41a828b 157 * @{
<> 156:95d6b41a828b 158 */
Anna Bridge 180:96ed750bd169 159 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
Anna Bridge 180:96ed750bd169 160 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
<> 156:95d6b41a828b 161 /**
<> 156:95d6b41a828b 162 * @}
<> 156:95d6b41a828b 163 */
<> 156:95d6b41a828b 164
<> 156:95d6b41a828b 165 /**
<> 156:95d6b41a828b 166 * @}
<> 156:95d6b41a828b 167 */
<> 156:95d6b41a828b 168
<> 156:95d6b41a828b 169 /* Exported macro ------------------------------------------------------------*/
<> 156:95d6b41a828b 170
<> 156:95d6b41a828b 171 /* Exported functions --------------------------------------------------------*/
<> 156:95d6b41a828b 172 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
<> 156:95d6b41a828b 173 * @{
<> 156:95d6b41a828b 174 */
<> 156:95d6b41a828b 175
<> 156:95d6b41a828b 176 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
<> 156:95d6b41a828b 177 * @{
<> 156:95d6b41a828b 178 */
<> 156:95d6b41a828b 179
<> 156:95d6b41a828b 180 /**
<> 156:95d6b41a828b 181 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
<> 156:95d6b41a828b 182 * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
<> 156:95d6b41a828b 183 */
<> 156:95d6b41a828b 184 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
<> 156:95d6b41a828b 185 {
<> 156:95d6b41a828b 186 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
<> 156:95d6b41a828b 187 }
<> 156:95d6b41a828b 188
<> 156:95d6b41a828b 189 /**
<> 156:95d6b41a828b 190 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
<> 156:95d6b41a828b 191 * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
<> 156:95d6b41a828b 192 */
<> 156:95d6b41a828b 193 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
<> 156:95d6b41a828b 194 {
<> 156:95d6b41a828b 195 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
<> 156:95d6b41a828b 196 }
<> 156:95d6b41a828b 197
<> 156:95d6b41a828b 198 /**
<> 156:95d6b41a828b 199 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
<> 156:95d6b41a828b 200 * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
<> 156:95d6b41a828b 201 */
<> 156:95d6b41a828b 202 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
<> 156:95d6b41a828b 203 {
<> 156:95d6b41a828b 204 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
<> 156:95d6b41a828b 205 }
<> 156:95d6b41a828b 206
<> 156:95d6b41a828b 207 /**
<> 156:95d6b41a828b 208 * @brief Get Flash memory size
<> 156:95d6b41a828b 209 * @note This bitfield indicates the size of the device Flash memory expressed in
<> 156:95d6b41a828b 210 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
<> 156:95d6b41a828b 211 * @retval FLASH_SIZE[15:0]: Flash memory size
<> 156:95d6b41a828b 212 */
<> 156:95d6b41a828b 213 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
<> 156:95d6b41a828b 214 {
<> 156:95d6b41a828b 215 return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
<> 156:95d6b41a828b 216 }
<> 156:95d6b41a828b 217
Anna Bridge 180:96ed750bd169 218
<> 156:95d6b41a828b 219 /**
<> 156:95d6b41a828b 220 * @}
<> 156:95d6b41a828b 221 */
<> 156:95d6b41a828b 222
<> 156:95d6b41a828b 223 /** @defgroup UTILS_LL_EF_DELAY DELAY
<> 156:95d6b41a828b 224 * @{
<> 156:95d6b41a828b 225 */
<> 156:95d6b41a828b 226
<> 156:95d6b41a828b 227 /**
<> 156:95d6b41a828b 228 * @brief This function configures the Cortex-M SysTick source of the time base.
<> 156:95d6b41a828b 229 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
<> 156:95d6b41a828b 230 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
<> 156:95d6b41a828b 231 * configuration by calling this function, for a delay use rather osDelay RTOS service.
<> 156:95d6b41a828b 232 * @param Ticks Number of ticks
<> 156:95d6b41a828b 233 * @retval None
<> 156:95d6b41a828b 234 */
<> 156:95d6b41a828b 235 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
<> 156:95d6b41a828b 236 {
<> 156:95d6b41a828b 237 /* Configure the SysTick to have interrupt in 1ms time base */
<> 156:95d6b41a828b 238 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
<> 156:95d6b41a828b 239 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 156:95d6b41a828b 240 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 156:95d6b41a828b 241 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
<> 156:95d6b41a828b 242 }
<> 156:95d6b41a828b 243
<> 156:95d6b41a828b 244 void LL_Init1msTick(uint32_t HCLKFrequency);
<> 156:95d6b41a828b 245 void LL_mDelay(uint32_t Delay);
<> 156:95d6b41a828b 246
<> 156:95d6b41a828b 247 /**
<> 156:95d6b41a828b 248 * @}
<> 156:95d6b41a828b 249 */
<> 156:95d6b41a828b 250
<> 156:95d6b41a828b 251 /** @defgroup UTILS_EF_SYSTEM SYSTEM
<> 156:95d6b41a828b 252 * @{
<> 156:95d6b41a828b 253 */
<> 156:95d6b41a828b 254
<> 156:95d6b41a828b 255 void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
<> 156:95d6b41a828b 256 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
<> 156:95d6b41a828b 257 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
<> 156:95d6b41a828b 258 #if defined(RCC_CFGR_SW_HSI48)
<> 156:95d6b41a828b 259 ErrorStatus LL_PLL_ConfigSystemClock_HSI48(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
<> 156:95d6b41a828b 260 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
<> 156:95d6b41a828b 261 #endif /*RCC_CFGR_SW_HSI48*/
<> 156:95d6b41a828b 262 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
<> 156:95d6b41a828b 263 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
<> 156:95d6b41a828b 264
<> 156:95d6b41a828b 265 /**
<> 156:95d6b41a828b 266 * @}
<> 156:95d6b41a828b 267 */
<> 156:95d6b41a828b 268
<> 156:95d6b41a828b 269 /**
<> 156:95d6b41a828b 270 * @}
<> 156:95d6b41a828b 271 */
<> 156:95d6b41a828b 272
<> 156:95d6b41a828b 273 /**
<> 156:95d6b41a828b 274 * @}
<> 156:95d6b41a828b 275 */
<> 156:95d6b41a828b 276
<> 156:95d6b41a828b 277 /**
<> 156:95d6b41a828b 278 * @}
<> 156:95d6b41a828b 279 */
<> 156:95d6b41a828b 280
<> 156:95d6b41a828b 281 #ifdef __cplusplus
<> 156:95d6b41a828b 282 }
<> 156:95d6b41a828b 283 #endif
<> 156:95d6b41a828b 284
<> 156:95d6b41a828b 285 #endif /* __STM32F0xx_LL_UTILS_H */
<> 156:95d6b41a828b 286
<> 156:95d6b41a828b 287 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/