mbed-dev - mbed library sources. Supersedes mbed-src.

Users » mbed_official » Code » mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_tim.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 180:96ed750bd169

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	156:95d6b41a828b	1	/**
<>	156:95d6b41a828b	2	******************************************************************************
<>	156:95d6b41a828b	3	* @file stm32f0xx_ll_tim.h
<>	156:95d6b41a828b	4	* @author MCD Application Team
<>	156:95d6b41a828b	5	* @brief Header file of TIM LL module.
<>	156:95d6b41a828b	6	******************************************************************************
<>	156:95d6b41a828b	7	* @attention
<>	156:95d6b41a828b	8	*
<>	156:95d6b41a828b	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	156:95d6b41a828b	10	*
<>	156:95d6b41a828b	11	* Redistribution and use in source and binary forms, with or without modification,
<>	156:95d6b41a828b	12	* are permitted provided that the following conditions are met:
<>	156:95d6b41a828b	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	156:95d6b41a828b	14	* this list of conditions and the following disclaimer.
<>	156:95d6b41a828b	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	156:95d6b41a828b	16	* this list of conditions and the following disclaimer in the documentation
<>	156:95d6b41a828b	17	* and/or other materials provided with the distribution.
<>	156:95d6b41a828b	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	156:95d6b41a828b	19	* may be used to endorse or promote products derived from this software
<>	156:95d6b41a828b	20	* without specific prior written permission.
<>	156:95d6b41a828b	21	*
<>	156:95d6b41a828b	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	156:95d6b41a828b	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	156:95d6b41a828b	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	156:95d6b41a828b	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	156:95d6b41a828b	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	156:95d6b41a828b	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	156:95d6b41a828b	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	156:95d6b41a828b	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	156:95d6b41a828b	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	156:95d6b41a828b	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	156:95d6b41a828b	32	*
<>	156:95d6b41a828b	33	******************************************************************************
<>	156:95d6b41a828b	34	*/
<>	156:95d6b41a828b	35
<>	156:95d6b41a828b	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	156:95d6b41a828b	37	#ifndef __STM32F0xx_LL_TIM_H
<>	156:95d6b41a828b	38	#define __STM32F0xx_LL_TIM_H
<>	156:95d6b41a828b	39
<>	156:95d6b41a828b	40	#ifdef __cplusplus
<>	156:95d6b41a828b	41	extern "C" {
<>	156:95d6b41a828b	42	#endif
<>	156:95d6b41a828b	43
<>	156:95d6b41a828b	44	/* Includes ------------------------------------------------------------------*/
<>	156:95d6b41a828b	45	#include "stm32f0xx.h"
<>	156:95d6b41a828b	46
<>	156:95d6b41a828b	47	/** @addtogroup STM32F0xx_LL_Driver
<>	156:95d6b41a828b	48	* @{
<>	156:95d6b41a828b	49	*/
<>	156:95d6b41a828b	50
<>	156:95d6b41a828b	51	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM14) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17) \|\| defined (TIM6) \|\| defined (TIM7)
<>	156:95d6b41a828b	52
<>	156:95d6b41a828b	53	/** @defgroup TIM_LL TIM
<>	156:95d6b41a828b	54	* @{
<>	156:95d6b41a828b	55	*/
<>	156:95d6b41a828b	56
<>	156:95d6b41a828b	57	/* Private types -------------------------------------------------------------*/
<>	156:95d6b41a828b	58	/* Private variables ---------------------------------------------------------*/
<>	156:95d6b41a828b	59	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
<>	156:95d6b41a828b	60	* @{
<>	156:95d6b41a828b	61	*/
<>	156:95d6b41a828b	62	static const uint8_t OFFSET_TAB_CCMRx[] =
<>	156:95d6b41a828b	63	{
<>	156:95d6b41a828b	64	0x00U, /* 0: TIMx_CH1 */
<>	156:95d6b41a828b	65	0x00U, /* 1: TIMx_CH1N */
<>	156:95d6b41a828b	66	0x00U, /* 2: TIMx_CH2 */
<>	156:95d6b41a828b	67	0x00U, /* 3: TIMx_CH2N */
<>	156:95d6b41a828b	68	0x04U, /* 4: TIMx_CH3 */
<>	156:95d6b41a828b	69	0x04U, /* 5: TIMx_CH3N */
<>	156:95d6b41a828b	70	0x04U /* 6: TIMx_CH4 */
<>	156:95d6b41a828b	71	};
<>	156:95d6b41a828b	72
<>	156:95d6b41a828b	73	static const uint8_t SHIFT_TAB_OCxx[] =
<>	156:95d6b41a828b	74	{
<>	156:95d6b41a828b	75	0U, /* 0: OC1M, OC1FE, OC1PE */
<>	156:95d6b41a828b	76	0U, /* 1: - NA */
<>	156:95d6b41a828b	77	8U, /* 2: OC2M, OC2FE, OC2PE */
<>	156:95d6b41a828b	78	0U, /* 3: - NA */
<>	156:95d6b41a828b	79	0U, /* 4: OC3M, OC3FE, OC3PE */
<>	156:95d6b41a828b	80	0U, /* 5: - NA */
<>	156:95d6b41a828b	81	8U /* 6: OC4M, OC4FE, OC4PE */
<>	156:95d6b41a828b	82	};
<>	156:95d6b41a828b	83
<>	156:95d6b41a828b	84	static const uint8_t SHIFT_TAB_ICxx[] =
<>	156:95d6b41a828b	85	{
<>	156:95d6b41a828b	86	0U, /* 0: CC1S, IC1PSC, IC1F */
<>	156:95d6b41a828b	87	0U, /* 1: - NA */
<>	156:95d6b41a828b	88	8U, /* 2: CC2S, IC2PSC, IC2F */
<>	156:95d6b41a828b	89	0U, /* 3: - NA */
<>	156:95d6b41a828b	90	0U, /* 4: CC3S, IC3PSC, IC3F */
<>	156:95d6b41a828b	91	0U, /* 5: - NA */
<>	156:95d6b41a828b	92	8U /* 6: CC4S, IC4PSC, IC4F */
<>	156:95d6b41a828b	93	};
<>	156:95d6b41a828b	94
<>	156:95d6b41a828b	95	static const uint8_t SHIFT_TAB_CCxP[] =
<>	156:95d6b41a828b	96	{
<>	156:95d6b41a828b	97	0U, /* 0: CC1P */
<>	156:95d6b41a828b	98	2U, /* 1: CC1NP */
<>	156:95d6b41a828b	99	4U, /* 2: CC2P */
<>	156:95d6b41a828b	100	6U, /* 3: CC2NP */
<>	156:95d6b41a828b	101	8U, /* 4: CC3P */
<>	156:95d6b41a828b	102	10U, /* 5: CC3NP */
<>	156:95d6b41a828b	103	12U /* 6: CC4P */
<>	156:95d6b41a828b	104	};
<>	156:95d6b41a828b	105
<>	156:95d6b41a828b	106	static const uint8_t SHIFT_TAB_OISx[] =
<>	156:95d6b41a828b	107	{
<>	156:95d6b41a828b	108	0U, /* 0: OIS1 */
<>	156:95d6b41a828b	109	1U, /* 1: OIS1N */
<>	156:95d6b41a828b	110	2U, /* 2: OIS2 */
<>	156:95d6b41a828b	111	3U, /* 3: OIS2N */
<>	156:95d6b41a828b	112	4U, /* 4: OIS3 */
<>	156:95d6b41a828b	113	5U, /* 5: OIS3N */
<>	156:95d6b41a828b	114	6U /* 6: OIS4 */
<>	156:95d6b41a828b	115	};
<>	156:95d6b41a828b	116	/**
<>	156:95d6b41a828b	117	* @}
<>	156:95d6b41a828b	118	*/
<>	156:95d6b41a828b	119
<>	156:95d6b41a828b	120
<>	156:95d6b41a828b	121	/* Private constants ---------------------------------------------------------*/
<>	156:95d6b41a828b	122	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
<>	156:95d6b41a828b	123	* @{
<>	156:95d6b41a828b	124	*/
<>	156:95d6b41a828b	125
<>	156:95d6b41a828b	126
Anna Bridge	180:96ed750bd169	127	#define TIMx_OR_RMP_SHIFT 16U
Anna Bridge	180:96ed750bd169	128	#define TIMx_OR_RMP_MASK 0x0000FFFFU
Anna Bridge	180:96ed750bd169	129	#define TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
<>	156:95d6b41a828b	130
<>	156:95d6b41a828b	131	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
<>	156:95d6b41a828b	132	#define DT_DELAY_1 ((uint8_t)0x7FU)
<>	156:95d6b41a828b	133	#define DT_DELAY_2 ((uint8_t)0x3FU)
<>	156:95d6b41a828b	134	#define DT_DELAY_3 ((uint8_t)0x1FU)
<>	156:95d6b41a828b	135	#define DT_DELAY_4 ((uint8_t)0x1FU)
<>	156:95d6b41a828b	136
<>	156:95d6b41a828b	137	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
<>	156:95d6b41a828b	138	#define DT_RANGE_1 ((uint8_t)0x00U)
<>	156:95d6b41a828b	139	#define DT_RANGE_2 ((uint8_t)0x80U)
<>	156:95d6b41a828b	140	#define DT_RANGE_3 ((uint8_t)0xC0U)
<>	156:95d6b41a828b	141	#define DT_RANGE_4 ((uint8_t)0xE0U)
<>	156:95d6b41a828b	142
<>	156:95d6b41a828b	143
<>	156:95d6b41a828b	144	/**
<>	156:95d6b41a828b	145	* @}
<>	156:95d6b41a828b	146	*/
<>	156:95d6b41a828b	147
<>	156:95d6b41a828b	148	/* Private macros ------------------------------------------------------------*/
<>	156:95d6b41a828b	149	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
<>	156:95d6b41a828b	150	* @{
<>	156:95d6b41a828b	151	*/
<>	156:95d6b41a828b	152	/** @brief Convert channel id into channel index.
<>	156:95d6b41a828b	153	* @param __CHANNEL__ This parameter can be one of the following values:
<>	156:95d6b41a828b	154	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	155	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	156:95d6b41a828b	156	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	157	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	156:95d6b41a828b	158	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	159	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	156:95d6b41a828b	160	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	161	* @retval none
<>	156:95d6b41a828b	162	*/
<>	156:95d6b41a828b	163	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
<>	156:95d6b41a828b	164	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
<>	156:95d6b41a828b	165	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
<>	156:95d6b41a828b	166	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
<>	156:95d6b41a828b	167	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
<>	156:95d6b41a828b	168	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
<>	156:95d6b41a828b	169	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
<>	156:95d6b41a828b	170
<>	156:95d6b41a828b	171	/** @brief Calculate the deadtime sampling period(in ps).
<>	156:95d6b41a828b	172	* @param __TIMCLK__ timer input clock frequency (in Hz).
<>	156:95d6b41a828b	173	* @param __CKD__ This parameter can be one of the following values:
<>	156:95d6b41a828b	174	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	156:95d6b41a828b	175	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	156:95d6b41a828b	176	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	156:95d6b41a828b	177	* @retval none
<>	156:95d6b41a828b	178	*/
<>	156:95d6b41a828b	179	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
<>	156:95d6b41a828b	180	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
<>	156:95d6b41a828b	181	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
<>	156:95d6b41a828b	182	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
<>	156:95d6b41a828b	183	/**
<>	156:95d6b41a828b	184	* @}
<>	156:95d6b41a828b	185	*/
<>	156:95d6b41a828b	186
<>	156:95d6b41a828b	187
<>	156:95d6b41a828b	188	/* Exported types ------------------------------------------------------------*/
<>	156:95d6b41a828b	189	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	190	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
<>	156:95d6b41a828b	191	* @{
<>	156:95d6b41a828b	192	*/
<>	156:95d6b41a828b	193
<>	156:95d6b41a828b	194	/**
<>	156:95d6b41a828b	195	* @brief TIM Time Base configuration structure definition.
<>	156:95d6b41a828b	196	*/
<>	156:95d6b41a828b	197	typedef struct
<>	156:95d6b41a828b	198	{
<>	156:95d6b41a828b	199	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
<>	156:95d6b41a828b	200	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
<>	156:95d6b41a828b	201
<>	156:95d6b41a828b	202	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
<>	156:95d6b41a828b	203
<>	156:95d6b41a828b	204	uint32_t CounterMode; /*!< Specifies the counter mode.
<>	156:95d6b41a828b	205	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
<>	156:95d6b41a828b	206
<>	156:95d6b41a828b	207	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
<>	156:95d6b41a828b	208
Anna Bridge	180:96ed750bd169	209	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
<>	156:95d6b41a828b	210	Auto-Reload Register at the next update event.
<>	156:95d6b41a828b	211	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
<>	156:95d6b41a828b	212	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
<>	156:95d6b41a828b	213
<>	156:95d6b41a828b	214	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
<>	156:95d6b41a828b	215
<>	156:95d6b41a828b	216	uint32_t ClockDivision; /*!< Specifies the clock division.
<>	156:95d6b41a828b	217	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
<>	156:95d6b41a828b	218
<>	156:95d6b41a828b	219	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
<>	156:95d6b41a828b	220
<>	156:95d6b41a828b	221	uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
<>	156:95d6b41a828b	222	reaches zero, an update event is generated and counting restarts
<>	156:95d6b41a828b	223	from the RCR value (N).
<>	156:95d6b41a828b	224	This means in PWM mode that (N+1) corresponds to:
<>	156:95d6b41a828b	225	- the number of PWM periods in edge-aligned mode
<>	156:95d6b41a828b	226	- the number of half PWM period in center-aligned mode
<>	156:95d6b41a828b	227	This parameter must be a number between 0x00 and 0xFF.
<>	156:95d6b41a828b	228
<>	156:95d6b41a828b	229	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
<>	156:95d6b41a828b	230	} LL_TIM_InitTypeDef;
<>	156:95d6b41a828b	231
<>	156:95d6b41a828b	232	/**
<>	156:95d6b41a828b	233	* @brief TIM Output Compare configuration structure definition.
<>	156:95d6b41a828b	234	*/
<>	156:95d6b41a828b	235	typedef struct
<>	156:95d6b41a828b	236	{
<>	156:95d6b41a828b	237	uint32_t OCMode; /*!< Specifies the output mode.
<>	156:95d6b41a828b	238	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
<>	156:95d6b41a828b	239
<>	156:95d6b41a828b	240	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
<>	156:95d6b41a828b	241
<>	156:95d6b41a828b	242	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
<>	156:95d6b41a828b	243	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
<>	156:95d6b41a828b	244
<>	156:95d6b41a828b	245	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
<>	156:95d6b41a828b	246
<>	156:95d6b41a828b	247	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
<>	156:95d6b41a828b	248	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
<>	156:95d6b41a828b	249
<>	156:95d6b41a828b	250	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
<>	156:95d6b41a828b	251
<>	156:95d6b41a828b	252	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
<>	156:95d6b41a828b	253	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
<>	156:95d6b41a828b	254
<>	156:95d6b41a828b	255	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
<>	156:95d6b41a828b	256
<>	156:95d6b41a828b	257	uint32_t OCPolarity; /*!< Specifies the output polarity.
<>	156:95d6b41a828b	258	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
<>	156:95d6b41a828b	259
<>	156:95d6b41a828b	260	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
<>	156:95d6b41a828b	261
<>	156:95d6b41a828b	262	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
<>	156:95d6b41a828b	263	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
<>	156:95d6b41a828b	264
<>	156:95d6b41a828b	265	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
<>	156:95d6b41a828b	266
Anna Bridge	180:96ed750bd169	267
<>	156:95d6b41a828b	268	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	156:95d6b41a828b	269	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
<>	156:95d6b41a828b	270
<>	156:95d6b41a828b	271	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
<>	156:95d6b41a828b	272
<>	156:95d6b41a828b	273	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	156:95d6b41a828b	274	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
<>	156:95d6b41a828b	275
<>	156:95d6b41a828b	276	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
<>	156:95d6b41a828b	277	} LL_TIM_OC_InitTypeDef;
<>	156:95d6b41a828b	278
<>	156:95d6b41a828b	279	/**
<>	156:95d6b41a828b	280	* @brief TIM Input Capture configuration structure definition.
<>	156:95d6b41a828b	281	*/
<>	156:95d6b41a828b	282
<>	156:95d6b41a828b	283	typedef struct
<>	156:95d6b41a828b	284	{
<>	156:95d6b41a828b	285
<>	156:95d6b41a828b	286	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<>	156:95d6b41a828b	287	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	156:95d6b41a828b	288
<>	156:95d6b41a828b	289	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	156:95d6b41a828b	290
<>	156:95d6b41a828b	291	uint32_t ICActiveInput; /*!< Specifies the input.
<>	156:95d6b41a828b	292	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<>	156:95d6b41a828b	293
<>	156:95d6b41a828b	294	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<>	156:95d6b41a828b	295
<>	156:95d6b41a828b	296	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
<>	156:95d6b41a828b	297	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	156:95d6b41a828b	298
<>	156:95d6b41a828b	299	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	156:95d6b41a828b	300
<>	156:95d6b41a828b	301	uint32_t ICFilter; /*!< Specifies the input capture filter.
<>	156:95d6b41a828b	302	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	156:95d6b41a828b	303
<>	156:95d6b41a828b	304	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	156:95d6b41a828b	305	} LL_TIM_IC_InitTypeDef;
<>	156:95d6b41a828b	306
<>	156:95d6b41a828b	307
<>	156:95d6b41a828b	308	/**
<>	156:95d6b41a828b	309	* @brief TIM Encoder interface configuration structure definition.
<>	156:95d6b41a828b	310	*/
<>	156:95d6b41a828b	311	typedef struct
<>	156:95d6b41a828b	312	{
<>	156:95d6b41a828b	313	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
<>	156:95d6b41a828b	314	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
<>	156:95d6b41a828b	315
<>	156:95d6b41a828b	316	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
<>	156:95d6b41a828b	317
<>	156:95d6b41a828b	318	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
<>	156:95d6b41a828b	319	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	156:95d6b41a828b	320
<>	156:95d6b41a828b	321	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	156:95d6b41a828b	322
<>	156:95d6b41a828b	323	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
<>	156:95d6b41a828b	324	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<>	156:95d6b41a828b	325
<>	156:95d6b41a828b	326	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<>	156:95d6b41a828b	327
<>	156:95d6b41a828b	328	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
<>	156:95d6b41a828b	329	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	156:95d6b41a828b	330
<>	156:95d6b41a828b	331	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	156:95d6b41a828b	332
<>	156:95d6b41a828b	333	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
<>	156:95d6b41a828b	334	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	156:95d6b41a828b	335
<>	156:95d6b41a828b	336	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	156:95d6b41a828b	337
<>	156:95d6b41a828b	338	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
<>	156:95d6b41a828b	339	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	156:95d6b41a828b	340
<>	156:95d6b41a828b	341	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	156:95d6b41a828b	342
<>	156:95d6b41a828b	343	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
<>	156:95d6b41a828b	344	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<>	156:95d6b41a828b	345
<>	156:95d6b41a828b	346	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<>	156:95d6b41a828b	347
<>	156:95d6b41a828b	348	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
<>	156:95d6b41a828b	349	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	156:95d6b41a828b	350
<>	156:95d6b41a828b	351	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	156:95d6b41a828b	352
<>	156:95d6b41a828b	353	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
<>	156:95d6b41a828b	354	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	156:95d6b41a828b	355
<>	156:95d6b41a828b	356	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	156:95d6b41a828b	357
<>	156:95d6b41a828b	358	} LL_TIM_ENCODER_InitTypeDef;
<>	156:95d6b41a828b	359
<>	156:95d6b41a828b	360	/**
<>	156:95d6b41a828b	361	* @brief TIM Hall sensor interface configuration structure definition.
<>	156:95d6b41a828b	362	*/
<>	156:95d6b41a828b	363	typedef struct
<>	156:95d6b41a828b	364	{
<>	156:95d6b41a828b	365
<>	156:95d6b41a828b	366	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
<>	156:95d6b41a828b	367	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	156:95d6b41a828b	368
<>	156:95d6b41a828b	369	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	156:95d6b41a828b	370
<>	156:95d6b41a828b	371	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
<>	156:95d6b41a828b	372	Prescaler must be set to get a maximum counter period longer than the
<>	156:95d6b41a828b	373	time interval between 2 consecutive changes on the Hall inputs.
<>	156:95d6b41a828b	374	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	156:95d6b41a828b	375
<>	156:95d6b41a828b	376	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	156:95d6b41a828b	377
<>	156:95d6b41a828b	378	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
<>	156:95d6b41a828b	379	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	156:95d6b41a828b	380
<>	156:95d6b41a828b	381	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	156:95d6b41a828b	382
<>	156:95d6b41a828b	383	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
<>	156:95d6b41a828b	384	A positive pulse (TRGO event) is generated with a programmable delay every time
<>	156:95d6b41a828b	385	a change occurs on the Hall inputs.
<>	156:95d6b41a828b	386	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
<>	156:95d6b41a828b	387
<>	156:95d6b41a828b	388	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
<>	156:95d6b41a828b	389	} LL_TIM_HALLSENSOR_InitTypeDef;
<>	156:95d6b41a828b	390
<>	156:95d6b41a828b	391	/**
Anna Bridge	180:96ed750bd169	392	* @brief BDTR (Break and Dead Time) structure definition
Anna Bridge	180:96ed750bd169	393	*/
Anna Bridge	180:96ed750bd169	394	typedef struct
Anna Bridge	180:96ed750bd169	395	{
Anna Bridge	180:96ed750bd169	396	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
Anna Bridge	180:96ed750bd169	397	This parameter can be a value of @ref TIM_LL_EC_OSSR
Anna Bridge	180:96ed750bd169	398
Anna Bridge	180:96ed750bd169	399	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
Anna Bridge	180:96ed750bd169	400
Anna Bridge	180:96ed750bd169	401	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
Anna Bridge	180:96ed750bd169	402
Anna Bridge	180:96ed750bd169	403	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
Anna Bridge	180:96ed750bd169	404	This parameter can be a value of @ref TIM_LL_EC_OSSI
Anna Bridge	180:96ed750bd169	405
Anna Bridge	180:96ed750bd169	406	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
Anna Bridge	180:96ed750bd169	407
Anna Bridge	180:96ed750bd169	408	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
Anna Bridge	180:96ed750bd169	409
Anna Bridge	180:96ed750bd169	410	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
Anna Bridge	180:96ed750bd169	411	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
Anna Bridge	180:96ed750bd169	412
Anna Bridge	180:96ed750bd169	413	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
Anna Bridge	180:96ed750bd169	414	has been written, their content is frozen until the next reset.*/
Anna Bridge	180:96ed750bd169	415
Anna Bridge	180:96ed750bd169	416	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
Anna Bridge	180:96ed750bd169	417	switching-on of the outputs.
Anna Bridge	180:96ed750bd169	418	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
Anna Bridge	180:96ed750bd169	419
Anna Bridge	180:96ed750bd169	420	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
Anna Bridge	180:96ed750bd169	421
Anna Bridge	180:96ed750bd169	422	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
Anna Bridge	180:96ed750bd169	423
Anna Bridge	180:96ed750bd169	424	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
Anna Bridge	180:96ed750bd169	425	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
Anna Bridge	180:96ed750bd169	426
Anna Bridge	180:96ed750bd169	427	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
Anna Bridge	180:96ed750bd169	428
Anna Bridge	180:96ed750bd169	429	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
Anna Bridge	180:96ed750bd169	430
Anna Bridge	180:96ed750bd169	431	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
Anna Bridge	180:96ed750bd169	432	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
Anna Bridge	180:96ed750bd169	433
Anna Bridge	180:96ed750bd169	434	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
Anna Bridge	180:96ed750bd169	435
Anna Bridge	180:96ed750bd169	436	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
Anna Bridge	180:96ed750bd169	437
Anna Bridge	180:96ed750bd169	438	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
Anna Bridge	180:96ed750bd169	439	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
Anna Bridge	180:96ed750bd169	440
Anna Bridge	180:96ed750bd169	441	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
Anna Bridge	180:96ed750bd169	442
Anna Bridge	180:96ed750bd169	443	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
Anna Bridge	180:96ed750bd169	444	} LL_TIM_BDTR_InitTypeDef;
Anna Bridge	180:96ed750bd169	445
Anna Bridge	180:96ed750bd169	446	/**
<>	156:95d6b41a828b	447	* @}
<>	156:95d6b41a828b	448	*/
<>	156:95d6b41a828b	449	#endif /* USE_FULL_LL_DRIVER */
<>	156:95d6b41a828b	450
<>	156:95d6b41a828b	451	/* Exported constants --------------------------------------------------------*/
<>	156:95d6b41a828b	452	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
<>	156:95d6b41a828b	453	* @{
<>	156:95d6b41a828b	454	*/
<>	156:95d6b41a828b	455
<>	156:95d6b41a828b	456	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
<>	156:95d6b41a828b	457	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
<>	156:95d6b41a828b	458	* @{
<>	156:95d6b41a828b	459	*/
<>	156:95d6b41a828b	460	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
<>	156:95d6b41a828b	461	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
<>	156:95d6b41a828b	462	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
<>	156:95d6b41a828b	463	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
<>	156:95d6b41a828b	464	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
<>	156:95d6b41a828b	465	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
<>	156:95d6b41a828b	466	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
<>	156:95d6b41a828b	467	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
<>	156:95d6b41a828b	468	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
<>	156:95d6b41a828b	469	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
<>	156:95d6b41a828b	470	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
<>	156:95d6b41a828b	471	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
<>	156:95d6b41a828b	472	/**
<>	156:95d6b41a828b	473	* @}
<>	156:95d6b41a828b	474	*/
<>	156:95d6b41a828b	475
Anna Bridge	180:96ed750bd169	476	#if defined(USE_FULL_LL_DRIVER)
Anna Bridge	180:96ed750bd169	477	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
Anna Bridge	180:96ed750bd169	478	* @{
Anna Bridge	180:96ed750bd169	479	*/
Anna Bridge	180:96ed750bd169	480	#define LL_TIM_BREAK_DISABLE 0x00000000U /!< Break function disabled /
Anna Bridge	180:96ed750bd169	481	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
Anna Bridge	180:96ed750bd169	482	/**
Anna Bridge	180:96ed750bd169	483	* @}
Anna Bridge	180:96ed750bd169	484	*/
Anna Bridge	180:96ed750bd169	485
Anna Bridge	180:96ed750bd169	486	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
Anna Bridge	180:96ed750bd169	487	* @{
Anna Bridge	180:96ed750bd169	488	*/
Anna Bridge	180:96ed750bd169	489	#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
Anna Bridge	180:96ed750bd169	490	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
Anna Bridge	180:96ed750bd169	491	/**
Anna Bridge	180:96ed750bd169	492	* @}
Anna Bridge	180:96ed750bd169	493	*/
Anna Bridge	180:96ed750bd169	494	#endif /* USE_FULL_LL_DRIVER */
Anna Bridge	180:96ed750bd169	495
<>	156:95d6b41a828b	496	/** @defgroup TIM_LL_EC_IT IT Defines
<>	156:95d6b41a828b	497	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
<>	156:95d6b41a828b	498	* @{
<>	156:95d6b41a828b	499	*/
<>	156:95d6b41a828b	500	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
<>	156:95d6b41a828b	501	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
<>	156:95d6b41a828b	502	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
<>	156:95d6b41a828b	503	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
<>	156:95d6b41a828b	504	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
<>	156:95d6b41a828b	505	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
<>	156:95d6b41a828b	506	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
<>	156:95d6b41a828b	507	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
<>	156:95d6b41a828b	508	/**
<>	156:95d6b41a828b	509	* @}
<>	156:95d6b41a828b	510	*/
<>	156:95d6b41a828b	511
<>	156:95d6b41a828b	512	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
<>	156:95d6b41a828b	513	* @{
<>	156:95d6b41a828b	514	*/
Anna Bridge	180:96ed750bd169	515	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
Anna Bridge	180:96ed750bd169	516	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
<>	156:95d6b41a828b	517	/**
<>	156:95d6b41a828b	518	* @}
<>	156:95d6b41a828b	519	*/
<>	156:95d6b41a828b	520
<>	156:95d6b41a828b	521	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
<>	156:95d6b41a828b	522	* @{
<>	156:95d6b41a828b	523	*/
Anna Bridge	180:96ed750bd169	524	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
Anna Bridge	180:96ed750bd169	525	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
<>	156:95d6b41a828b	526	/**
<>	156:95d6b41a828b	527	* @}
<>	156:95d6b41a828b	528	*/
<>	156:95d6b41a828b	529
<>	156:95d6b41a828b	530	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
<>	156:95d6b41a828b	531	* @{
<>	156:95d6b41a828b	532	*/
Anna Bridge	180:96ed750bd169	533	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
Anna Bridge	180:96ed750bd169	534	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
Anna Bridge	180:96ed750bd169	535	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
Anna Bridge	180:96ed750bd169	536	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
Anna Bridge	180:96ed750bd169	537	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
<>	156:95d6b41a828b	538	/**
<>	156:95d6b41a828b	539	* @}
<>	156:95d6b41a828b	540	*/
<>	156:95d6b41a828b	541
<>	156:95d6b41a828b	542	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
<>	156:95d6b41a828b	543	* @{
<>	156:95d6b41a828b	544	*/
Anna Bridge	180:96ed750bd169	545	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
Anna Bridge	180:96ed750bd169	546	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
Anna Bridge	180:96ed750bd169	547	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
<>	156:95d6b41a828b	548	/**
<>	156:95d6b41a828b	549	* @}
<>	156:95d6b41a828b	550	*/
<>	156:95d6b41a828b	551
<>	156:95d6b41a828b	552	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
<>	156:95d6b41a828b	553	* @{
<>	156:95d6b41a828b	554	*/
Anna Bridge	180:96ed750bd169	555	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
Anna Bridge	180:96ed750bd169	556	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
<>	156:95d6b41a828b	557	/**
<>	156:95d6b41a828b	558	* @}
<>	156:95d6b41a828b	559	*/
<>	156:95d6b41a828b	560
<>	156:95d6b41a828b	561	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
<>	156:95d6b41a828b	562	* @{
<>	156:95d6b41a828b	563	*/
Anna Bridge	180:96ed750bd169	564	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
Anna Bridge	180:96ed750bd169	565	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
<>	156:95d6b41a828b	566	/**
<>	156:95d6b41a828b	567	* @}
<>	156:95d6b41a828b	568	*/
<>	156:95d6b41a828b	569
<>	156:95d6b41a828b	570	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
<>	156:95d6b41a828b	571	* @{
<>	156:95d6b41a828b	572	*/
Anna Bridge	180:96ed750bd169	573	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
Anna Bridge	180:96ed750bd169	574	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
<>	156:95d6b41a828b	575	/**
<>	156:95d6b41a828b	576	* @}
<>	156:95d6b41a828b	577	*/
<>	156:95d6b41a828b	578
<>	156:95d6b41a828b	579	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
<>	156:95d6b41a828b	580	* @{
<>	156:95d6b41a828b	581	*/
Anna Bridge	180:96ed750bd169	582	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
Anna Bridge	180:96ed750bd169	583	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
Anna Bridge	180:96ed750bd169	584	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
Anna Bridge	180:96ed750bd169	585	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
<>	156:95d6b41a828b	586	/**
<>	156:95d6b41a828b	587	* @}
<>	156:95d6b41a828b	588	*/
<>	156:95d6b41a828b	589
<>	156:95d6b41a828b	590	/** @defgroup TIM_LL_EC_CHANNEL Channel
<>	156:95d6b41a828b	591	* @{
<>	156:95d6b41a828b	592	*/
<>	156:95d6b41a828b	593	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
<>	156:95d6b41a828b	594	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
<>	156:95d6b41a828b	595	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
<>	156:95d6b41a828b	596	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
<>	156:95d6b41a828b	597	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
<>	156:95d6b41a828b	598	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
<>	156:95d6b41a828b	599	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
<>	156:95d6b41a828b	600	/**
<>	156:95d6b41a828b	601	* @}
<>	156:95d6b41a828b	602	*/
<>	156:95d6b41a828b	603
<>	156:95d6b41a828b	604	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	605	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
<>	156:95d6b41a828b	606	* @{
<>	156:95d6b41a828b	607	*/
Anna Bridge	180:96ed750bd169	608	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
<>	156:95d6b41a828b	609	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
<>	156:95d6b41a828b	610	/**
<>	156:95d6b41a828b	611	* @}
<>	156:95d6b41a828b	612	*/
<>	156:95d6b41a828b	613	#endif /* USE_FULL_LL_DRIVER */
<>	156:95d6b41a828b	614
<>	156:95d6b41a828b	615	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
<>	156:95d6b41a828b	616	* @{
<>	156:95d6b41a828b	617	*/
Anna Bridge	180:96ed750bd169	618	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
<>	156:95d6b41a828b	619	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
<>	156:95d6b41a828b	620	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
<>	156:95d6b41a828b	621	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
Anna Bridge	180:96ed750bd169	622	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
<>	156:95d6b41a828b	623	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
<>	156:95d6b41a828b	624	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
<>	156:95d6b41a828b	625	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
<>	156:95d6b41a828b	626	/**
<>	156:95d6b41a828b	627	* @}
<>	156:95d6b41a828b	628	*/
<>	156:95d6b41a828b	629
<>	156:95d6b41a828b	630	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
<>	156:95d6b41a828b	631	* @{
<>	156:95d6b41a828b	632	*/
Anna Bridge	180:96ed750bd169	633	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
<>	156:95d6b41a828b	634	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
<>	156:95d6b41a828b	635	/**
<>	156:95d6b41a828b	636	* @}
<>	156:95d6b41a828b	637	*/
<>	156:95d6b41a828b	638
<>	156:95d6b41a828b	639	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
<>	156:95d6b41a828b	640	* @{
<>	156:95d6b41a828b	641	*/
Anna Bridge	180:96ed750bd169	642	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
<>	156:95d6b41a828b	643	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
<>	156:95d6b41a828b	644	/**
<>	156:95d6b41a828b	645	* @}
<>	156:95d6b41a828b	646	*/
<>	156:95d6b41a828b	647
<>	156:95d6b41a828b	648
<>	156:95d6b41a828b	649	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
<>	156:95d6b41a828b	650	* @{
<>	156:95d6b41a828b	651	*/
Anna Bridge	180:96ed750bd169	652	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
Anna Bridge	180:96ed750bd169	653	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
Anna Bridge	180:96ed750bd169	654	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
<>	156:95d6b41a828b	655	/**
<>	156:95d6b41a828b	656	* @}
<>	156:95d6b41a828b	657	*/
<>	156:95d6b41a828b	658
<>	156:95d6b41a828b	659	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
<>	156:95d6b41a828b	660	* @{
<>	156:95d6b41a828b	661	*/
Anna Bridge	180:96ed750bd169	662	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
Anna Bridge	180:96ed750bd169	663	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
Anna Bridge	180:96ed750bd169	664	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
Anna Bridge	180:96ed750bd169	665	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
<>	156:95d6b41a828b	666	/**
<>	156:95d6b41a828b	667	* @}
<>	156:95d6b41a828b	668	*/
<>	156:95d6b41a828b	669
<>	156:95d6b41a828b	670	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
<>	156:95d6b41a828b	671	* @{
<>	156:95d6b41a828b	672	*/
Anna Bridge	180:96ed750bd169	673	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
Anna Bridge	180:96ed750bd169	674	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
Anna Bridge	180:96ed750bd169	675	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
Anna Bridge	180:96ed750bd169	676	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
Anna Bridge	180:96ed750bd169	677	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
Anna Bridge	180:96ed750bd169	678	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
Anna Bridge	180:96ed750bd169	679	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
Anna Bridge	180:96ed750bd169	680	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
Anna Bridge	180:96ed750bd169	681	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
Anna Bridge	180:96ed750bd169	682	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
Anna Bridge	180:96ed750bd169	683	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
Anna Bridge	180:96ed750bd169	684	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
Anna Bridge	180:96ed750bd169	685	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
Anna Bridge	180:96ed750bd169	686	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
Anna Bridge	180:96ed750bd169	687	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
Anna Bridge	180:96ed750bd169	688	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
<>	156:95d6b41a828b	689	/**
<>	156:95d6b41a828b	690	* @}
<>	156:95d6b41a828b	691	*/
<>	156:95d6b41a828b	692
<>	156:95d6b41a828b	693	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
<>	156:95d6b41a828b	694	* @{
<>	156:95d6b41a828b	695	*/
Anna Bridge	180:96ed750bd169	696	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
<>	156:95d6b41a828b	697	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
<>	156:95d6b41a828b	698	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
<>	156:95d6b41a828b	699	/**
<>	156:95d6b41a828b	700	* @}
<>	156:95d6b41a828b	701	*/
<>	156:95d6b41a828b	702
<>	156:95d6b41a828b	703	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
<>	156:95d6b41a828b	704	* @{
<>	156:95d6b41a828b	705	*/
Anna Bridge	180:96ed750bd169	706	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
Anna Bridge	180:96ed750bd169	707	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected inpu t/
Anna Bridge	180:96ed750bd169	708	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
<>	156:95d6b41a828b	709	/**
<>	156:95d6b41a828b	710	* @}
<>	156:95d6b41a828b	711	*/
<>	156:95d6b41a828b	712
<>	156:95d6b41a828b	713	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
<>	156:95d6b41a828b	714	* @{
<>	156:95d6b41a828b	715	*/
<>	156:95d6b41a828b	716	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
<>	156:95d6b41a828b	717	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
<>	156:95d6b41a828b	718	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l /
<>	156:95d6b41a828b	719	/**
<>	156:95d6b41a828b	720	* @}
<>	156:95d6b41a828b	721	*/
<>	156:95d6b41a828b	722
<>	156:95d6b41a828b	723	/** @defgroup TIM_LL_EC_TRGO Trigger Output
<>	156:95d6b41a828b	724	* @{
<>	156:95d6b41a828b	725	*/
Anna Bridge	180:96ed750bd169	726	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
<>	156:95d6b41a828b	727	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
<>	156:95d6b41a828b	728	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
<>	156:95d6b41a828b	729	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
<>	156:95d6b41a828b	730	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
<>	156:95d6b41a828b	731	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
<>	156:95d6b41a828b	732	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
<>	156:95d6b41a828b	733	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
<>	156:95d6b41a828b	734	/**
<>	156:95d6b41a828b	735	* @}
<>	156:95d6b41a828b	736	*/
<>	156:95d6b41a828b	737
<>	156:95d6b41a828b	738
<>	156:95d6b41a828b	739	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
<>	156:95d6b41a828b	740	* @{
<>	156:95d6b41a828b	741	*/
Anna Bridge	180:96ed750bd169	742	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
<>	156:95d6b41a828b	743	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
<>	156:95d6b41a828b	744	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
<>	156:95d6b41a828b	745	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
<>	156:95d6b41a828b	746	/**
<>	156:95d6b41a828b	747	* @}
<>	156:95d6b41a828b	748	*/
<>	156:95d6b41a828b	749
<>	156:95d6b41a828b	750	/** @defgroup TIM_LL_EC_TS Trigger Selection
<>	156:95d6b41a828b	751	* @{
<>	156:95d6b41a828b	752	*/
Anna Bridge	180:96ed750bd169	753	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
Anna Bridge	180:96ed750bd169	754	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
Anna Bridge	180:96ed750bd169	755	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
Anna Bridge	180:96ed750bd169	756	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
Anna Bridge	180:96ed750bd169	757	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
Anna Bridge	180:96ed750bd169	758	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
Anna Bridge	180:96ed750bd169	759	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
Anna Bridge	180:96ed750bd169	760	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
<>	156:95d6b41a828b	761	/**
<>	156:95d6b41a828b	762	* @}
<>	156:95d6b41a828b	763	*/
<>	156:95d6b41a828b	764
<>	156:95d6b41a828b	765	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
<>	156:95d6b41a828b	766	* @{
<>	156:95d6b41a828b	767	*/
Anna Bridge	180:96ed750bd169	768	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
<>	156:95d6b41a828b	769	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
<>	156:95d6b41a828b	770	/**
<>	156:95d6b41a828b	771	* @}
<>	156:95d6b41a828b	772	*/
<>	156:95d6b41a828b	773
<>	156:95d6b41a828b	774	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
<>	156:95d6b41a828b	775	* @{
<>	156:95d6b41a828b	776	*/
Anna Bridge	180:96ed750bd169	777	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
<>	156:95d6b41a828b	778	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
<>	156:95d6b41a828b	779	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
<>	156:95d6b41a828b	780	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
<>	156:95d6b41a828b	781	/**
<>	156:95d6b41a828b	782	* @}
<>	156:95d6b41a828b	783	*/
<>	156:95d6b41a828b	784
<>	156:95d6b41a828b	785	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
<>	156:95d6b41a828b	786	* @{
<>	156:95d6b41a828b	787	*/
Anna Bridge	180:96ed750bd169	788	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
<>	156:95d6b41a828b	789	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
<>	156:95d6b41a828b	790	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
<>	156:95d6b41a828b	791	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
<>	156:95d6b41a828b	792	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
<>	156:95d6b41a828b	793	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
Anna Bridge	180:96ed750bd169	794	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
<>	156:95d6b41a828b	795	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
<>	156:95d6b41a828b	796	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
<>	156:95d6b41a828b	797	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
Anna Bridge	180:96ed750bd169	798	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
<>	156:95d6b41a828b	799	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
Anna Bridge	180:96ed750bd169	800	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
Anna Bridge	180:96ed750bd169	801	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
Anna Bridge	180:96ed750bd169	802	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
<>	156:95d6b41a828b	803	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
<>	156:95d6b41a828b	804	/**
<>	156:95d6b41a828b	805	* @}
<>	156:95d6b41a828b	806	*/
<>	156:95d6b41a828b	807
<>	156:95d6b41a828b	808
<>	156:95d6b41a828b	809	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
<>	156:95d6b41a828b	810	* @{
<>	156:95d6b41a828b	811	*/
Anna Bridge	180:96ed750bd169	812	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
<>	156:95d6b41a828b	813	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
<>	156:95d6b41a828b	814	/**
<>	156:95d6b41a828b	815	* @}
<>	156:95d6b41a828b	816	*/
<>	156:95d6b41a828b	817
<>	156:95d6b41a828b	818
<>	156:95d6b41a828b	819
<>	156:95d6b41a828b	820
<>	156:95d6b41a828b	821	/** @defgroup TIM_LL_EC_OSSI OSSI
<>	156:95d6b41a828b	822	* @{
<>	156:95d6b41a828b	823	*/
Anna Bridge	180:96ed750bd169	824	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
<>	156:95d6b41a828b	825	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
<>	156:95d6b41a828b	826	/**
<>	156:95d6b41a828b	827	* @}
<>	156:95d6b41a828b	828	*/
<>	156:95d6b41a828b	829
<>	156:95d6b41a828b	830	/** @defgroup TIM_LL_EC_OSSR OSSR
<>	156:95d6b41a828b	831	* @{
<>	156:95d6b41a828b	832	*/
Anna Bridge	180:96ed750bd169	833	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
<>	156:95d6b41a828b	834	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
<>	156:95d6b41a828b	835	/**
<>	156:95d6b41a828b	836	* @}
<>	156:95d6b41a828b	837	*/
<>	156:95d6b41a828b	838
<>	156:95d6b41a828b	839
<>	156:95d6b41a828b	840	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
<>	156:95d6b41a828b	841	* @{
<>	156:95d6b41a828b	842	*/
Anna Bridge	180:96ed750bd169	843	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
<>	156:95d6b41a828b	844	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
<>	156:95d6b41a828b	845	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
<>	156:95d6b41a828b	846	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
<>	156:95d6b41a828b	847	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
<>	156:95d6b41a828b	848	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
<>	156:95d6b41a828b	849	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
<>	156:95d6b41a828b	850	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
<>	156:95d6b41a828b	851	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
<>	156:95d6b41a828b	852	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
<>	156:95d6b41a828b	853	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
<>	156:95d6b41a828b	854	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
<>	156:95d6b41a828b	855	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
<>	156:95d6b41a828b	856	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
<>	156:95d6b41a828b	857	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
<>	156:95d6b41a828b	858	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
<>	156:95d6b41a828b	859	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
<>	156:95d6b41a828b	860	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
<>	156:95d6b41a828b	861
<>	156:95d6b41a828b	862
<>	156:95d6b41a828b	863	/**
<>	156:95d6b41a828b	864	* @}
<>	156:95d6b41a828b	865	*/
<>	156:95d6b41a828b	866
<>	156:95d6b41a828b	867	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
<>	156:95d6b41a828b	868	* @{
<>	156:95d6b41a828b	869	*/
Anna Bridge	180:96ed750bd169	870	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
<>	156:95d6b41a828b	871	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
<>	156:95d6b41a828b	872	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
<>	156:95d6b41a828b	873	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
<>	156:95d6b41a828b	874	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
<>	156:95d6b41a828b	875	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
<>	156:95d6b41a828b	876	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
<>	156:95d6b41a828b	877	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
<>	156:95d6b41a828b	878	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
<>	156:95d6b41a828b	879	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
<>	156:95d6b41a828b	880	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
<>	156:95d6b41a828b	881	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
<>	156:95d6b41a828b	882	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
<>	156:95d6b41a828b	883	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
<>	156:95d6b41a828b	884	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
<>	156:95d6b41a828b	885	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
<>	156:95d6b41a828b	886	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
<>	156:95d6b41a828b	887	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
<>	156:95d6b41a828b	888	/**
<>	156:95d6b41a828b	889	* @}
<>	156:95d6b41a828b	890	*/
<>	156:95d6b41a828b	891
<>	156:95d6b41a828b	892
Anna Bridge	180:96ed750bd169	893	#define LL_TIM_TIM14_TI1_RMP_GPIO TIM14_OR_RMP_MASK /!< TIM14_TI1 is connected to Ored GPIO /
<>	156:95d6b41a828b	894	#define LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to RTC clock /
<>	156:95d6b41a828b	895	#define LL_TIM_TIM14_TI1_RMP_HSE (TIM14_OR_TI1_RMP_1 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to HSE/32 clock /
<>	156:95d6b41a828b	896	#define LL_TIM_TIM14_TI1_RMP_MCO (TIM14_OR_TI1_RMP_0 \| TIM14_OR_TI1_RMP_1 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to MCO /
<>	156:95d6b41a828b	897
<>	156:95d6b41a828b	898
<>	156:95d6b41a828b	899	/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
<>	156:95d6b41a828b	900	* @{
<>	156:95d6b41a828b	901	*/
Anna Bridge	180:96ed750bd169	902	#define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /!< OCREF_CLR_INT is connected to the OCREF_CLR input /
Anna Bridge	180:96ed750bd169	903	#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /!< OCREF_CLR_INT is connected to ETRF /
<>	156:95d6b41a828b	904	/**
<>	156:95d6b41a828b	905	* @}
<>	156:95d6b41a828b	906	*/
<>	156:95d6b41a828b	907
<>	156:95d6b41a828b	908	/**
<>	156:95d6b41a828b	909	* @}
<>	156:95d6b41a828b	910	*/
<>	156:95d6b41a828b	911
<>	156:95d6b41a828b	912	/* Exported macro ------------------------------------------------------------*/
<>	156:95d6b41a828b	913	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
<>	156:95d6b41a828b	914	* @{
<>	156:95d6b41a828b	915	*/
<>	156:95d6b41a828b	916
<>	156:95d6b41a828b	917	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
<>	156:95d6b41a828b	918	* @{
<>	156:95d6b41a828b	919	*/
<>	156:95d6b41a828b	920	/**
<>	156:95d6b41a828b	921	* @brief Write a value in TIM register.
<>	156:95d6b41a828b	922	* @param __INSTANCE__ TIM Instance
<>	156:95d6b41a828b	923	* @param __REG__ Register to be written
<>	156:95d6b41a828b	924	* @param __VALUE__ Value to be written in the register
<>	156:95d6b41a828b	925	* @retval None
<>	156:95d6b41a828b	926	*/
<>	156:95d6b41a828b	927	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	156:95d6b41a828b	928
<>	156:95d6b41a828b	929	/**
<>	156:95d6b41a828b	930	* @brief Read a value in TIM register.
<>	156:95d6b41a828b	931	* @param __INSTANCE__ TIM Instance
<>	156:95d6b41a828b	932	* @param __REG__ Register to be read
<>	156:95d6b41a828b	933	* @retval Register value
<>	156:95d6b41a828b	934	*/
<>	156:95d6b41a828b	935	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	156:95d6b41a828b	936	/**
<>	156:95d6b41a828b	937	* @}
<>	156:95d6b41a828b	938	*/
<>	156:95d6b41a828b	939
<>	156:95d6b41a828b	940	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
<>	156:95d6b41a828b	941	* @{
<>	156:95d6b41a828b	942	*/
<>	156:95d6b41a828b	943
<>	156:95d6b41a828b	944	/**
<>	156:95d6b41a828b	945	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
<>	156:95d6b41a828b	946	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
<>	156:95d6b41a828b	947	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	156:95d6b41a828b	948	* @param __CKD__ This parameter can be one of the following values:
<>	156:95d6b41a828b	949	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	156:95d6b41a828b	950	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	156:95d6b41a828b	951	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	156:95d6b41a828b	952	* @param __DT__ deadtime duration (in ns)
<>	156:95d6b41a828b	953	* @retval DTG[0:7]
<>	156:95d6b41a828b	954	*/
<>	156:95d6b41a828b	955	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
<>	156:95d6b41a828b	956	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
<>	156:95d6b41a828b	957	(((uint64_t)((__DT__)1000U)) < (64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
<>	156:95d6b41a828b	958	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
<>	156:95d6b41a828b	959	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
<>	156:95d6b41a828b	960	0U)
<>	156:95d6b41a828b	961
<>	156:95d6b41a828b	962	/**
<>	156:95d6b41a828b	963	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
<>	156:95d6b41a828b	964	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
<>	156:95d6b41a828b	965	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	156:95d6b41a828b	966	* @param __CNTCLK__ counter clock frequency (in Hz)
<>	156:95d6b41a828b	967	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
<>	156:95d6b41a828b	968	*/
<>	156:95d6b41a828b	969	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
<>	156:95d6b41a828b	970	((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
<>	156:95d6b41a828b	971
<>	156:95d6b41a828b	972	/**
<>	156:95d6b41a828b	973	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
<>	156:95d6b41a828b	974	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
<>	156:95d6b41a828b	975	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	156:95d6b41a828b	976	* @param __PSC__ prescaler
<>	156:95d6b41a828b	977	* @param __FREQ__ output signal frequency (in Hz)
<>	156:95d6b41a828b	978	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
<>	156:95d6b41a828b	979	*/
<>	156:95d6b41a828b	980	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
<>	156:95d6b41a828b	981	(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
<>	156:95d6b41a828b	982
<>	156:95d6b41a828b	983	/**
<>	156:95d6b41a828b	984	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
<>	156:95d6b41a828b	985	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
<>	156:95d6b41a828b	986	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	156:95d6b41a828b	987	* @param __PSC__ prescaler
<>	156:95d6b41a828b	988	* @param __DELAY__ timer output compare active/inactive delay (in us)
<>	156:95d6b41a828b	989	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
<>	156:95d6b41a828b	990	*/
<>	156:95d6b41a828b	991	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
<>	156:95d6b41a828b	992	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
<>	156:95d6b41a828b	993	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
<>	156:95d6b41a828b	994
<>	156:95d6b41a828b	995	/**
<>	156:95d6b41a828b	996	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
<>	156:95d6b41a828b	997	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
<>	156:95d6b41a828b	998	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	156:95d6b41a828b	999	* @param __PSC__ prescaler
<>	156:95d6b41a828b	1000	* @param __DELAY__ timer output compare active/inactive delay (in us)
<>	156:95d6b41a828b	1001	* @param __PULSE__ pulse duration (in us)
<>	156:95d6b41a828b	1002	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
<>	156:95d6b41a828b	1003	*/
<>	156:95d6b41a828b	1004	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
<>	156:95d6b41a828b	1005	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
<>	156:95d6b41a828b	1006	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
<>	156:95d6b41a828b	1007
<>	156:95d6b41a828b	1008	/**
<>	156:95d6b41a828b	1009	* @brief HELPER macro retrieving the ratio of the input capture prescaler
<>	156:95d6b41a828b	1010	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
<>	156:95d6b41a828b	1011	* @param __ICPSC__ This parameter can be one of the following values:
<>	156:95d6b41a828b	1012	* @arg @ref LL_TIM_ICPSC_DIV1
<>	156:95d6b41a828b	1013	* @arg @ref LL_TIM_ICPSC_DIV2
<>	156:95d6b41a828b	1014	* @arg @ref LL_TIM_ICPSC_DIV4
<>	156:95d6b41a828b	1015	* @arg @ref LL_TIM_ICPSC_DIV8
<>	156:95d6b41a828b	1016	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
<>	156:95d6b41a828b	1017	*/
<>	156:95d6b41a828b	1018	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
Anna Bridge	180:96ed750bd169	1019	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
<>	156:95d6b41a828b	1020
<>	156:95d6b41a828b	1021
<>	156:95d6b41a828b	1022	/**
<>	156:95d6b41a828b	1023	* @}
<>	156:95d6b41a828b	1024	*/
<>	156:95d6b41a828b	1025
<>	156:95d6b41a828b	1026
<>	156:95d6b41a828b	1027	/**
<>	156:95d6b41a828b	1028	* @}
<>	156:95d6b41a828b	1029	*/
<>	156:95d6b41a828b	1030
<>	156:95d6b41a828b	1031	/* Exported functions --------------------------------------------------------*/
<>	156:95d6b41a828b	1032	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
<>	156:95d6b41a828b	1033	* @{
<>	156:95d6b41a828b	1034	*/
<>	156:95d6b41a828b	1035
<>	156:95d6b41a828b	1036	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
<>	156:95d6b41a828b	1037	* @{
<>	156:95d6b41a828b	1038	*/
<>	156:95d6b41a828b	1039	/**
<>	156:95d6b41a828b	1040	* @brief Enable timer counter.
<>	156:95d6b41a828b	1041	* @rmtoll CR1 CEN LL_TIM_EnableCounter
<>	156:95d6b41a828b	1042	* @param TIMx Timer instance
<>	156:95d6b41a828b	1043	* @retval None
<>	156:95d6b41a828b	1044	*/
<>	156:95d6b41a828b	1045	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1046	{
<>	156:95d6b41a828b	1047	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
<>	156:95d6b41a828b	1048	}
<>	156:95d6b41a828b	1049
<>	156:95d6b41a828b	1050	/**
<>	156:95d6b41a828b	1051	* @brief Disable timer counter.
<>	156:95d6b41a828b	1052	* @rmtoll CR1 CEN LL_TIM_DisableCounter
<>	156:95d6b41a828b	1053	* @param TIMx Timer instance
<>	156:95d6b41a828b	1054	* @retval None
<>	156:95d6b41a828b	1055	*/
<>	156:95d6b41a828b	1056	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1057	{
<>	156:95d6b41a828b	1058	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
<>	156:95d6b41a828b	1059	}
<>	156:95d6b41a828b	1060
<>	156:95d6b41a828b	1061	/**
<>	156:95d6b41a828b	1062	* @brief Indicates whether the timer counter is enabled.
<>	156:95d6b41a828b	1063	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
<>	156:95d6b41a828b	1064	* @param TIMx Timer instance
<>	156:95d6b41a828b	1065	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1066	*/
<>	156:95d6b41a828b	1067	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1068	{
<>	156:95d6b41a828b	1069	return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
<>	156:95d6b41a828b	1070	}
<>	156:95d6b41a828b	1071
<>	156:95d6b41a828b	1072	/**
<>	156:95d6b41a828b	1073	* @brief Enable update event generation.
<>	156:95d6b41a828b	1074	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
<>	156:95d6b41a828b	1075	* @param TIMx Timer instance
<>	156:95d6b41a828b	1076	* @retval None
<>	156:95d6b41a828b	1077	*/
<>	156:95d6b41a828b	1078	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1079	{
Anna Bridge	180:96ed750bd169	1080	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
<>	156:95d6b41a828b	1081	}
<>	156:95d6b41a828b	1082
<>	156:95d6b41a828b	1083	/**
<>	156:95d6b41a828b	1084	* @brief Disable update event generation.
<>	156:95d6b41a828b	1085	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
<>	156:95d6b41a828b	1086	* @param TIMx Timer instance
<>	156:95d6b41a828b	1087	* @retval None
<>	156:95d6b41a828b	1088	*/
<>	156:95d6b41a828b	1089	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1090	{
Anna Bridge	180:96ed750bd169	1091	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
<>	156:95d6b41a828b	1092	}
<>	156:95d6b41a828b	1093
<>	156:95d6b41a828b	1094	/**
<>	156:95d6b41a828b	1095	* @brief Indicates whether update event generation is enabled.
<>	156:95d6b41a828b	1096	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
<>	156:95d6b41a828b	1097	* @param TIMx Timer instance
Anna Bridge	180:96ed750bd169	1098	* @retval Inverted state of bit (0 or 1).
<>	156:95d6b41a828b	1099	*/
<>	156:95d6b41a828b	1100	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1101	{
Anna Bridge	180:96ed750bd169	1102	return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET);
<>	156:95d6b41a828b	1103	}
<>	156:95d6b41a828b	1104
<>	156:95d6b41a828b	1105	/**
<>	156:95d6b41a828b	1106	* @brief Set update event source
<>	156:95d6b41a828b	1107	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
<>	156:95d6b41a828b	1108	* generate an update interrupt or DMA request if enabled:
<>	156:95d6b41a828b	1109	* - Counter overflow/underflow
<>	156:95d6b41a828b	1110	* - Setting the UG bit
<>	156:95d6b41a828b	1111	* - Update generation through the slave mode controller
<>	156:95d6b41a828b	1112	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
<>	156:95d6b41a828b	1113	* overflow/underflow generates an update interrupt or DMA request if enabled.
<>	156:95d6b41a828b	1114	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
<>	156:95d6b41a828b	1115	* @param TIMx Timer instance
<>	156:95d6b41a828b	1116	* @param UpdateSource This parameter can be one of the following values:
<>	156:95d6b41a828b	1117	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
<>	156:95d6b41a828b	1118	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
<>	156:95d6b41a828b	1119	* @retval None
<>	156:95d6b41a828b	1120	*/
<>	156:95d6b41a828b	1121	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
<>	156:95d6b41a828b	1122	{
<>	156:95d6b41a828b	1123	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
<>	156:95d6b41a828b	1124	}
<>	156:95d6b41a828b	1125
<>	156:95d6b41a828b	1126	/**
<>	156:95d6b41a828b	1127	* @brief Get actual event update source
<>	156:95d6b41a828b	1128	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
<>	156:95d6b41a828b	1129	* @param TIMx Timer instance
<>	156:95d6b41a828b	1130	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1131	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
<>	156:95d6b41a828b	1132	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
<>	156:95d6b41a828b	1133	*/
<>	156:95d6b41a828b	1134	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1135	{
<>	156:95d6b41a828b	1136	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
<>	156:95d6b41a828b	1137	}
<>	156:95d6b41a828b	1138
<>	156:95d6b41a828b	1139	/**
<>	156:95d6b41a828b	1140	* @brief Set one pulse mode (one shot v.s. repetitive).
<>	156:95d6b41a828b	1141	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
<>	156:95d6b41a828b	1142	* @param TIMx Timer instance
<>	156:95d6b41a828b	1143	* @param OnePulseMode This parameter can be one of the following values:
<>	156:95d6b41a828b	1144	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
<>	156:95d6b41a828b	1145	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
<>	156:95d6b41a828b	1146	* @retval None
<>	156:95d6b41a828b	1147	*/
<>	156:95d6b41a828b	1148	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
<>	156:95d6b41a828b	1149	{
<>	156:95d6b41a828b	1150	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
<>	156:95d6b41a828b	1151	}
<>	156:95d6b41a828b	1152
<>	156:95d6b41a828b	1153	/**
<>	156:95d6b41a828b	1154	* @brief Get actual one pulse mode.
<>	156:95d6b41a828b	1155	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
<>	156:95d6b41a828b	1156	* @param TIMx Timer instance
<>	156:95d6b41a828b	1157	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1158	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
<>	156:95d6b41a828b	1159	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
<>	156:95d6b41a828b	1160	*/
<>	156:95d6b41a828b	1161	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1162	{
<>	156:95d6b41a828b	1163	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
<>	156:95d6b41a828b	1164	}
<>	156:95d6b41a828b	1165
<>	156:95d6b41a828b	1166	/**
<>	156:95d6b41a828b	1167	* @brief Set the timer counter counting mode.
<>	156:95d6b41a828b	1168	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
<>	156:95d6b41a828b	1169	* check whether or not the counter mode selection feature is supported
<>	156:95d6b41a828b	1170	* by a timer instance.
<>	156:95d6b41a828b	1171	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
<>	156:95d6b41a828b	1172	* CR1 CMS LL_TIM_SetCounterMode
<>	156:95d6b41a828b	1173	* @param TIMx Timer instance
<>	156:95d6b41a828b	1174	* @param CounterMode This parameter can be one of the following values:
<>	156:95d6b41a828b	1175	* @arg @ref LL_TIM_COUNTERMODE_UP
<>	156:95d6b41a828b	1176	* @arg @ref LL_TIM_COUNTERMODE_DOWN
<>	156:95d6b41a828b	1177	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
<>	156:95d6b41a828b	1178	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
<>	156:95d6b41a828b	1179	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
<>	156:95d6b41a828b	1180	* @retval None
<>	156:95d6b41a828b	1181	*/
<>	156:95d6b41a828b	1182	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
<>	156:95d6b41a828b	1183	{
<>	156:95d6b41a828b	1184	MODIFY_REG(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS, CounterMode);
<>	156:95d6b41a828b	1185	}
<>	156:95d6b41a828b	1186
<>	156:95d6b41a828b	1187	/**
<>	156:95d6b41a828b	1188	* @brief Get actual counter mode.
<>	156:95d6b41a828b	1189	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
<>	156:95d6b41a828b	1190	* check whether or not the counter mode selection feature is supported
<>	156:95d6b41a828b	1191	* by a timer instance.
<>	156:95d6b41a828b	1192	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
<>	156:95d6b41a828b	1193	* CR1 CMS LL_TIM_GetCounterMode
<>	156:95d6b41a828b	1194	* @param TIMx Timer instance
<>	156:95d6b41a828b	1195	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1196	* @arg @ref LL_TIM_COUNTERMODE_UP
<>	156:95d6b41a828b	1197	* @arg @ref LL_TIM_COUNTERMODE_DOWN
<>	156:95d6b41a828b	1198	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
<>	156:95d6b41a828b	1199	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
<>	156:95d6b41a828b	1200	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
<>	156:95d6b41a828b	1201	*/
<>	156:95d6b41a828b	1202	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1203	{
<>	156:95d6b41a828b	1204	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
<>	156:95d6b41a828b	1205	}
<>	156:95d6b41a828b	1206
<>	156:95d6b41a828b	1207	/**
<>	156:95d6b41a828b	1208	* @brief Enable auto-reload (ARR) preload.
<>	156:95d6b41a828b	1209	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
<>	156:95d6b41a828b	1210	* @param TIMx Timer instance
<>	156:95d6b41a828b	1211	* @retval None
<>	156:95d6b41a828b	1212	*/
<>	156:95d6b41a828b	1213	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1214	{
<>	156:95d6b41a828b	1215	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
<>	156:95d6b41a828b	1216	}
<>	156:95d6b41a828b	1217
<>	156:95d6b41a828b	1218	/**
<>	156:95d6b41a828b	1219	* @brief Disable auto-reload (ARR) preload.
<>	156:95d6b41a828b	1220	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
<>	156:95d6b41a828b	1221	* @param TIMx Timer instance
<>	156:95d6b41a828b	1222	* @retval None
<>	156:95d6b41a828b	1223	*/
<>	156:95d6b41a828b	1224	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1225	{
<>	156:95d6b41a828b	1226	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
<>	156:95d6b41a828b	1227	}
<>	156:95d6b41a828b	1228
<>	156:95d6b41a828b	1229	/**
<>	156:95d6b41a828b	1230	* @brief Indicates whether auto-reload (ARR) preload is enabled.
<>	156:95d6b41a828b	1231	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
<>	156:95d6b41a828b	1232	* @param TIMx Timer instance
<>	156:95d6b41a828b	1233	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1234	*/
<>	156:95d6b41a828b	1235	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1236	{
<>	156:95d6b41a828b	1237	return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
<>	156:95d6b41a828b	1238	}
<>	156:95d6b41a828b	1239
<>	156:95d6b41a828b	1240	/**
<>	156:95d6b41a828b	1241	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
<>	156:95d6b41a828b	1242	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	1243	* whether or not the clock division feature is supported by the timer
<>	156:95d6b41a828b	1244	* instance.
<>	156:95d6b41a828b	1245	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
<>	156:95d6b41a828b	1246	* @param TIMx Timer instance
<>	156:95d6b41a828b	1247	* @param ClockDivision This parameter can be one of the following values:
<>	156:95d6b41a828b	1248	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	156:95d6b41a828b	1249	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	156:95d6b41a828b	1250	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	156:95d6b41a828b	1251	* @retval None
<>	156:95d6b41a828b	1252	*/
<>	156:95d6b41a828b	1253	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
<>	156:95d6b41a828b	1254	{
<>	156:95d6b41a828b	1255	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
<>	156:95d6b41a828b	1256	}
<>	156:95d6b41a828b	1257
<>	156:95d6b41a828b	1258	/**
<>	156:95d6b41a828b	1259	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
<>	156:95d6b41a828b	1260	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	1261	* whether or not the clock division feature is supported by the timer
<>	156:95d6b41a828b	1262	* instance.
<>	156:95d6b41a828b	1263	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
<>	156:95d6b41a828b	1264	* @param TIMx Timer instance
<>	156:95d6b41a828b	1265	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1266	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	156:95d6b41a828b	1267	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	156:95d6b41a828b	1268	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	156:95d6b41a828b	1269	*/
<>	156:95d6b41a828b	1270	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1271	{
<>	156:95d6b41a828b	1272	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
<>	156:95d6b41a828b	1273	}
<>	156:95d6b41a828b	1274
<>	156:95d6b41a828b	1275	/**
<>	156:95d6b41a828b	1276	* @brief Set the counter value.
<>	156:95d6b41a828b	1277	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	1278	* whether or not a timer instance supports a 32 bits counter.
<>	156:95d6b41a828b	1279	* @rmtoll CNT CNT LL_TIM_SetCounter
<>	156:95d6b41a828b	1280	* @param TIMx Timer instance
<>	156:95d6b41a828b	1281	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
<>	156:95d6b41a828b	1282	* @retval None
<>	156:95d6b41a828b	1283	*/
<>	156:95d6b41a828b	1284	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
<>	156:95d6b41a828b	1285	{
<>	156:95d6b41a828b	1286	WRITE_REG(TIMx->CNT, Counter);
<>	156:95d6b41a828b	1287	}
<>	156:95d6b41a828b	1288
<>	156:95d6b41a828b	1289	/**
<>	156:95d6b41a828b	1290	* @brief Get the counter value.
<>	156:95d6b41a828b	1291	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	1292	* whether or not a timer instance supports a 32 bits counter.
<>	156:95d6b41a828b	1293	* @rmtoll CNT CNT LL_TIM_GetCounter
<>	156:95d6b41a828b	1294	* @param TIMx Timer instance
<>	156:95d6b41a828b	1295	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
<>	156:95d6b41a828b	1296	*/
<>	156:95d6b41a828b	1297	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1298	{
<>	156:95d6b41a828b	1299	return (uint32_t)(READ_REG(TIMx->CNT));
<>	156:95d6b41a828b	1300	}
<>	156:95d6b41a828b	1301
<>	156:95d6b41a828b	1302	/**
<>	156:95d6b41a828b	1303	* @brief Get the current direction of the counter
<>	156:95d6b41a828b	1304	* @rmtoll CR1 DIR LL_TIM_GetDirection
<>	156:95d6b41a828b	1305	* @param TIMx Timer instance
<>	156:95d6b41a828b	1306	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1307	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
<>	156:95d6b41a828b	1308	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
<>	156:95d6b41a828b	1309	*/
<>	156:95d6b41a828b	1310	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1311	{
<>	156:95d6b41a828b	1312	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
<>	156:95d6b41a828b	1313	}
<>	156:95d6b41a828b	1314
<>	156:95d6b41a828b	1315	/**
<>	156:95d6b41a828b	1316	* @brief Set the prescaler value.
<>	156:95d6b41a828b	1317	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
<>	156:95d6b41a828b	1318	* @note The prescaler can be changed on the fly as this control register is buffered. The new
<>	156:95d6b41a828b	1319	* prescaler ratio is taken into account at the next update event.
<>	156:95d6b41a828b	1320	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
<>	156:95d6b41a828b	1321	* @rmtoll PSC PSC LL_TIM_SetPrescaler
<>	156:95d6b41a828b	1322	* @param TIMx Timer instance
<>	156:95d6b41a828b	1323	* @param Prescaler between Min_Data=0 and Max_Data=65535
<>	156:95d6b41a828b	1324	* @retval None
<>	156:95d6b41a828b	1325	*/
<>	156:95d6b41a828b	1326	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
<>	156:95d6b41a828b	1327	{
<>	156:95d6b41a828b	1328	WRITE_REG(TIMx->PSC, Prescaler);
<>	156:95d6b41a828b	1329	}
<>	156:95d6b41a828b	1330
<>	156:95d6b41a828b	1331	/**
<>	156:95d6b41a828b	1332	* @brief Get the prescaler value.
<>	156:95d6b41a828b	1333	* @rmtoll PSC PSC LL_TIM_GetPrescaler
<>	156:95d6b41a828b	1334	* @param TIMx Timer instance
<>	156:95d6b41a828b	1335	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
<>	156:95d6b41a828b	1336	*/
<>	156:95d6b41a828b	1337	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1338	{
<>	156:95d6b41a828b	1339	return (uint32_t)(READ_REG(TIMx->PSC));
<>	156:95d6b41a828b	1340	}
<>	156:95d6b41a828b	1341
<>	156:95d6b41a828b	1342	/**
<>	156:95d6b41a828b	1343	* @brief Set the auto-reload value.
<>	156:95d6b41a828b	1344	* @note The counter is blocked while the auto-reload value is null.
<>	156:95d6b41a828b	1345	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	1346	* whether or not a timer instance supports a 32 bits counter.
<>	156:95d6b41a828b	1347	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
<>	156:95d6b41a828b	1348	* @rmtoll ARR ARR LL_TIM_SetAutoReload
<>	156:95d6b41a828b	1349	* @param TIMx Timer instance
<>	156:95d6b41a828b	1350	* @param AutoReload between Min_Data=0 and Max_Data=65535
<>	156:95d6b41a828b	1351	* @retval None
<>	156:95d6b41a828b	1352	*/
<>	156:95d6b41a828b	1353	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
<>	156:95d6b41a828b	1354	{
<>	156:95d6b41a828b	1355	WRITE_REG(TIMx->ARR, AutoReload);
<>	156:95d6b41a828b	1356	}
<>	156:95d6b41a828b	1357
<>	156:95d6b41a828b	1358	/**
<>	156:95d6b41a828b	1359	* @brief Get the auto-reload value.
<>	156:95d6b41a828b	1360	* @rmtoll ARR ARR LL_TIM_GetAutoReload
<>	156:95d6b41a828b	1361	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	1362	* whether or not a timer instance supports a 32 bits counter.
<>	156:95d6b41a828b	1363	* @param TIMx Timer instance
<>	156:95d6b41a828b	1364	* @retval Auto-reload value
<>	156:95d6b41a828b	1365	*/
<>	156:95d6b41a828b	1366	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1367	{
<>	156:95d6b41a828b	1368	return (uint32_t)(READ_REG(TIMx->ARR));
<>	156:95d6b41a828b	1369	}
<>	156:95d6b41a828b	1370
<>	156:95d6b41a828b	1371	/**
<>	156:95d6b41a828b	1372	* @brief Set the repetition counter value.
<>	156:95d6b41a828b	1373	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	1374	* whether or not a timer instance supports a repetition counter.
<>	156:95d6b41a828b	1375	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
<>	156:95d6b41a828b	1376	* @param TIMx Timer instance
<>	156:95d6b41a828b	1377	* @param RepetitionCounter between Min_Data=0 and Max_Data=255
<>	156:95d6b41a828b	1378	* @retval None
<>	156:95d6b41a828b	1379	*/
<>	156:95d6b41a828b	1380	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
<>	156:95d6b41a828b	1381	{
<>	156:95d6b41a828b	1382	WRITE_REG(TIMx->RCR, RepetitionCounter);
<>	156:95d6b41a828b	1383	}
<>	156:95d6b41a828b	1384
<>	156:95d6b41a828b	1385	/**
<>	156:95d6b41a828b	1386	* @brief Get the repetition counter value.
<>	156:95d6b41a828b	1387	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	1388	* whether or not a timer instance supports a repetition counter.
<>	156:95d6b41a828b	1389	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
<>	156:95d6b41a828b	1390	* @param TIMx Timer instance
<>	156:95d6b41a828b	1391	* @retval Repetition counter value
<>	156:95d6b41a828b	1392	*/
<>	156:95d6b41a828b	1393	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1394	{
<>	156:95d6b41a828b	1395	return (uint32_t)(READ_REG(TIMx->RCR));
<>	156:95d6b41a828b	1396	}
<>	156:95d6b41a828b	1397
<>	156:95d6b41a828b	1398	/**
<>	156:95d6b41a828b	1399	* @}
<>	156:95d6b41a828b	1400	*/
<>	156:95d6b41a828b	1401
<>	156:95d6b41a828b	1402	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
<>	156:95d6b41a828b	1403	* @{
<>	156:95d6b41a828b	1404	*/
<>	156:95d6b41a828b	1405	/**
<>	156:95d6b41a828b	1406	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
<>	156:95d6b41a828b	1407	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
<>	156:95d6b41a828b	1408	* they are updated only when a commutation event (COM) occurs.
<>	156:95d6b41a828b	1409	* @note Only on channels that have a complementary output.
<>	156:95d6b41a828b	1410	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	1411	* whether or not a timer instance is able to generate a commutation event.
<>	156:95d6b41a828b	1412	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
<>	156:95d6b41a828b	1413	* @param TIMx Timer instance
<>	156:95d6b41a828b	1414	* @retval None
<>	156:95d6b41a828b	1415	*/
<>	156:95d6b41a828b	1416	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1417	{
<>	156:95d6b41a828b	1418	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
<>	156:95d6b41a828b	1419	}
<>	156:95d6b41a828b	1420
<>	156:95d6b41a828b	1421	/**
<>	156:95d6b41a828b	1422	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
<>	156:95d6b41a828b	1423	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	1424	* whether or not a timer instance is able to generate a commutation event.
<>	156:95d6b41a828b	1425	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
<>	156:95d6b41a828b	1426	* @param TIMx Timer instance
<>	156:95d6b41a828b	1427	* @retval None
<>	156:95d6b41a828b	1428	*/
<>	156:95d6b41a828b	1429	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1430	{
<>	156:95d6b41a828b	1431	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
<>	156:95d6b41a828b	1432	}
<>	156:95d6b41a828b	1433
<>	156:95d6b41a828b	1434	/**
<>	156:95d6b41a828b	1435	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
<>	156:95d6b41a828b	1436	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	1437	* whether or not a timer instance is able to generate a commutation event.
<>	156:95d6b41a828b	1438	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
<>	156:95d6b41a828b	1439	* @param TIMx Timer instance
<>	156:95d6b41a828b	1440	* @param CCUpdateSource This parameter can be one of the following values:
<>	156:95d6b41a828b	1441	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
<>	156:95d6b41a828b	1442	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
<>	156:95d6b41a828b	1443	* @retval None
<>	156:95d6b41a828b	1444	*/
<>	156:95d6b41a828b	1445	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
<>	156:95d6b41a828b	1446	{
<>	156:95d6b41a828b	1447	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
<>	156:95d6b41a828b	1448	}
<>	156:95d6b41a828b	1449
<>	156:95d6b41a828b	1450	/**
<>	156:95d6b41a828b	1451	* @brief Set the trigger of the capture/compare DMA request.
<>	156:95d6b41a828b	1452	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
<>	156:95d6b41a828b	1453	* @param TIMx Timer instance
<>	156:95d6b41a828b	1454	* @param DMAReqTrigger This parameter can be one of the following values:
<>	156:95d6b41a828b	1455	* @arg @ref LL_TIM_CCDMAREQUEST_CC
<>	156:95d6b41a828b	1456	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
<>	156:95d6b41a828b	1457	* @retval None
<>	156:95d6b41a828b	1458	*/
<>	156:95d6b41a828b	1459	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
<>	156:95d6b41a828b	1460	{
<>	156:95d6b41a828b	1461	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
<>	156:95d6b41a828b	1462	}
<>	156:95d6b41a828b	1463
<>	156:95d6b41a828b	1464	/**
<>	156:95d6b41a828b	1465	* @brief Get actual trigger of the capture/compare DMA request.
<>	156:95d6b41a828b	1466	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
<>	156:95d6b41a828b	1467	* @param TIMx Timer instance
<>	156:95d6b41a828b	1468	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1469	* @arg @ref LL_TIM_CCDMAREQUEST_CC
<>	156:95d6b41a828b	1470	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
<>	156:95d6b41a828b	1471	*/
<>	156:95d6b41a828b	1472	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	1473	{
<>	156:95d6b41a828b	1474	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
<>	156:95d6b41a828b	1475	}
<>	156:95d6b41a828b	1476
<>	156:95d6b41a828b	1477	/**
<>	156:95d6b41a828b	1478	* @brief Set the lock level to freeze the
<>	156:95d6b41a828b	1479	* configuration of several capture/compare parameters.
<>	156:95d6b41a828b	1480	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	1481	* the lock mechanism is supported by a timer instance.
<>	156:95d6b41a828b	1482	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
<>	156:95d6b41a828b	1483	* @param TIMx Timer instance
<>	156:95d6b41a828b	1484	* @param LockLevel This parameter can be one of the following values:
<>	156:95d6b41a828b	1485	* @arg @ref LL_TIM_LOCKLEVEL_OFF
<>	156:95d6b41a828b	1486	* @arg @ref LL_TIM_LOCKLEVEL_1
<>	156:95d6b41a828b	1487	* @arg @ref LL_TIM_LOCKLEVEL_2
<>	156:95d6b41a828b	1488	* @arg @ref LL_TIM_LOCKLEVEL_3
<>	156:95d6b41a828b	1489	* @retval None
<>	156:95d6b41a828b	1490	*/
<>	156:95d6b41a828b	1491	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
<>	156:95d6b41a828b	1492	{
<>	156:95d6b41a828b	1493	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
<>	156:95d6b41a828b	1494	}
<>	156:95d6b41a828b	1495
<>	156:95d6b41a828b	1496	/**
<>	156:95d6b41a828b	1497	* @brief Enable capture/compare channels.
<>	156:95d6b41a828b	1498	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
<>	156:95d6b41a828b	1499	* CCER CC1NE LL_TIM_CC_EnableChannel\n
<>	156:95d6b41a828b	1500	* CCER CC2E LL_TIM_CC_EnableChannel\n
<>	156:95d6b41a828b	1501	* CCER CC2NE LL_TIM_CC_EnableChannel\n
<>	156:95d6b41a828b	1502	* CCER CC3E LL_TIM_CC_EnableChannel\n
<>	156:95d6b41a828b	1503	* CCER CC3NE LL_TIM_CC_EnableChannel\n
<>	156:95d6b41a828b	1504	* CCER CC4E LL_TIM_CC_EnableChannel
<>	156:95d6b41a828b	1505	* @param TIMx Timer instance
<>	156:95d6b41a828b	1506	* @param Channels This parameter can be a combination of the following values:
<>	156:95d6b41a828b	1507	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1508	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	156:95d6b41a828b	1509	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1510	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	156:95d6b41a828b	1511	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1512	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	156:95d6b41a828b	1513	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1514	* @retval None
<>	156:95d6b41a828b	1515	*/
<>	156:95d6b41a828b	1516	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
<>	156:95d6b41a828b	1517	{
<>	156:95d6b41a828b	1518	SET_BIT(TIMx->CCER, Channels);
<>	156:95d6b41a828b	1519	}
<>	156:95d6b41a828b	1520
<>	156:95d6b41a828b	1521	/**
<>	156:95d6b41a828b	1522	* @brief Disable capture/compare channels.
<>	156:95d6b41a828b	1523	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
<>	156:95d6b41a828b	1524	* CCER CC1NE LL_TIM_CC_DisableChannel\n
<>	156:95d6b41a828b	1525	* CCER CC2E LL_TIM_CC_DisableChannel\n
<>	156:95d6b41a828b	1526	* CCER CC2NE LL_TIM_CC_DisableChannel\n
<>	156:95d6b41a828b	1527	* CCER CC3E LL_TIM_CC_DisableChannel\n
<>	156:95d6b41a828b	1528	* CCER CC3NE LL_TIM_CC_DisableChannel\n
<>	156:95d6b41a828b	1529	* CCER CC4E LL_TIM_CC_DisableChannel
<>	156:95d6b41a828b	1530	* @param TIMx Timer instance
<>	156:95d6b41a828b	1531	* @param Channels This parameter can be a combination of the following values:
<>	156:95d6b41a828b	1532	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1533	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	156:95d6b41a828b	1534	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1535	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	156:95d6b41a828b	1536	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1537	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	156:95d6b41a828b	1538	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1539	* @retval None
<>	156:95d6b41a828b	1540	*/
<>	156:95d6b41a828b	1541	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
<>	156:95d6b41a828b	1542	{
<>	156:95d6b41a828b	1543	CLEAR_BIT(TIMx->CCER, Channels);
<>	156:95d6b41a828b	1544	}
<>	156:95d6b41a828b	1545
<>	156:95d6b41a828b	1546	/**
<>	156:95d6b41a828b	1547	* @brief Indicate whether channel(s) is(are) enabled.
<>	156:95d6b41a828b	1548	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
<>	156:95d6b41a828b	1549	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
<>	156:95d6b41a828b	1550	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
<>	156:95d6b41a828b	1551	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
<>	156:95d6b41a828b	1552	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
<>	156:95d6b41a828b	1553	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
<>	156:95d6b41a828b	1554	* CCER CC4E LL_TIM_CC_IsEnabledChannel
<>	156:95d6b41a828b	1555	* @param TIMx Timer instance
<>	156:95d6b41a828b	1556	* @param Channels This parameter can be a combination of the following values:
<>	156:95d6b41a828b	1557	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1558	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	156:95d6b41a828b	1559	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1560	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	156:95d6b41a828b	1561	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1562	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	156:95d6b41a828b	1563	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1564	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1565	*/
<>	156:95d6b41a828b	1566	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
<>	156:95d6b41a828b	1567	{
<>	156:95d6b41a828b	1568	return (READ_BIT(TIMx->CCER, Channels) == (Channels));
<>	156:95d6b41a828b	1569	}
<>	156:95d6b41a828b	1570
<>	156:95d6b41a828b	1571	/**
<>	156:95d6b41a828b	1572	* @}
<>	156:95d6b41a828b	1573	*/
<>	156:95d6b41a828b	1574
<>	156:95d6b41a828b	1575	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
<>	156:95d6b41a828b	1576	* @{
<>	156:95d6b41a828b	1577	*/
<>	156:95d6b41a828b	1578	/**
<>	156:95d6b41a828b	1579	* @brief Configure an output channel.
<>	156:95d6b41a828b	1580	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
<>	156:95d6b41a828b	1581	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
<>	156:95d6b41a828b	1582	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
<>	156:95d6b41a828b	1583	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
<>	156:95d6b41a828b	1584	* CCER CC1P LL_TIM_OC_ConfigOutput\n
<>	156:95d6b41a828b	1585	* CCER CC2P LL_TIM_OC_ConfigOutput\n
<>	156:95d6b41a828b	1586	* CCER CC3P LL_TIM_OC_ConfigOutput\n
<>	156:95d6b41a828b	1587	* CCER CC4P LL_TIM_OC_ConfigOutput\n
<>	156:95d6b41a828b	1588	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
<>	156:95d6b41a828b	1589	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
<>	156:95d6b41a828b	1590	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
<>	156:95d6b41a828b	1591	* CR2 OIS4 LL_TIM_OC_ConfigOutput
<>	156:95d6b41a828b	1592	* @param TIMx Timer instance
<>	156:95d6b41a828b	1593	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1594	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1595	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1596	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1597	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1598	* @param Configuration This parameter must be a combination of all the following values:
<>	156:95d6b41a828b	1599	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
<>	156:95d6b41a828b	1600	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
<>	156:95d6b41a828b	1601	* @retval None
<>	156:95d6b41a828b	1602	*/
<>	156:95d6b41a828b	1603	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
<>	156:95d6b41a828b	1604	{
<>	156:95d6b41a828b	1605	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	1606	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	1607	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
<>	156:95d6b41a828b	1608	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
<>	156:95d6b41a828b	1609	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
<>	156:95d6b41a828b	1610	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
<>	156:95d6b41a828b	1611	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
<>	156:95d6b41a828b	1612	}
<>	156:95d6b41a828b	1613
<>	156:95d6b41a828b	1614	/**
<>	156:95d6b41a828b	1615	* @brief Define the behavior of the output reference signal OCxREF from which
<>	156:95d6b41a828b	1616	* OCx and OCxN (when relevant) are derived.
<>	156:95d6b41a828b	1617	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
<>	156:95d6b41a828b	1618	* CCMR1 OC2M LL_TIM_OC_SetMode\n
<>	156:95d6b41a828b	1619	* CCMR2 OC3M LL_TIM_OC_SetMode\n
<>	156:95d6b41a828b	1620	* CCMR2 OC4M LL_TIM_OC_SetMode
<>	156:95d6b41a828b	1621	* @param TIMx Timer instance
<>	156:95d6b41a828b	1622	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1623	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1624	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1625	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1626	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1627	* @param Mode This parameter can be one of the following values:
<>	156:95d6b41a828b	1628	* @arg @ref LL_TIM_OCMODE_FROZEN
<>	156:95d6b41a828b	1629	* @arg @ref LL_TIM_OCMODE_ACTIVE
<>	156:95d6b41a828b	1630	* @arg @ref LL_TIM_OCMODE_INACTIVE
<>	156:95d6b41a828b	1631	* @arg @ref LL_TIM_OCMODE_TOGGLE
<>	156:95d6b41a828b	1632	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
<>	156:95d6b41a828b	1633	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
<>	156:95d6b41a828b	1634	* @arg @ref LL_TIM_OCMODE_PWM1
<>	156:95d6b41a828b	1635	* @arg @ref LL_TIM_OCMODE_PWM2
<>	156:95d6b41a828b	1636	* @retval None
<>	156:95d6b41a828b	1637	*/
<>	156:95d6b41a828b	1638	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
<>	156:95d6b41a828b	1639	{
<>	156:95d6b41a828b	1640	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	1641	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	1642	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
<>	156:95d6b41a828b	1643	}
<>	156:95d6b41a828b	1644
<>	156:95d6b41a828b	1645	/**
<>	156:95d6b41a828b	1646	* @brief Get the output compare mode of an output channel.
<>	156:95d6b41a828b	1647	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
<>	156:95d6b41a828b	1648	* CCMR1 OC2M LL_TIM_OC_GetMode\n
<>	156:95d6b41a828b	1649	* CCMR2 OC3M LL_TIM_OC_GetMode\n
<>	156:95d6b41a828b	1650	* CCMR2 OC4M LL_TIM_OC_GetMode
<>	156:95d6b41a828b	1651	* @param TIMx Timer instance
<>	156:95d6b41a828b	1652	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1653	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1654	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1655	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1656	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1657	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1658	* @arg @ref LL_TIM_OCMODE_FROZEN
<>	156:95d6b41a828b	1659	* @arg @ref LL_TIM_OCMODE_ACTIVE
<>	156:95d6b41a828b	1660	* @arg @ref LL_TIM_OCMODE_INACTIVE
<>	156:95d6b41a828b	1661	* @arg @ref LL_TIM_OCMODE_TOGGLE
<>	156:95d6b41a828b	1662	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
<>	156:95d6b41a828b	1663	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
<>	156:95d6b41a828b	1664	* @arg @ref LL_TIM_OCMODE_PWM1
<>	156:95d6b41a828b	1665	* @arg @ref LL_TIM_OCMODE_PWM2
<>	156:95d6b41a828b	1666	*/
<>	156:95d6b41a828b	1667	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
<>	156:95d6b41a828b	1668	{
<>	156:95d6b41a828b	1669	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	1670	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	1671	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
<>	156:95d6b41a828b	1672	}
<>	156:95d6b41a828b	1673
<>	156:95d6b41a828b	1674	/**
<>	156:95d6b41a828b	1675	* @brief Set the polarity of an output channel.
<>	156:95d6b41a828b	1676	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
<>	156:95d6b41a828b	1677	* CCER CC1NP LL_TIM_OC_SetPolarity\n
<>	156:95d6b41a828b	1678	* CCER CC2P LL_TIM_OC_SetPolarity\n
<>	156:95d6b41a828b	1679	* CCER CC2NP LL_TIM_OC_SetPolarity\n
<>	156:95d6b41a828b	1680	* CCER CC3P LL_TIM_OC_SetPolarity\n
<>	156:95d6b41a828b	1681	* CCER CC3NP LL_TIM_OC_SetPolarity\n
<>	156:95d6b41a828b	1682	* CCER CC4P LL_TIM_OC_SetPolarity
<>	156:95d6b41a828b	1683	* @param TIMx Timer instance
<>	156:95d6b41a828b	1684	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1685	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1686	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	156:95d6b41a828b	1687	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1688	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	156:95d6b41a828b	1689	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1690	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	156:95d6b41a828b	1691	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1692	* @param Polarity This parameter can be one of the following values:
<>	156:95d6b41a828b	1693	* @arg @ref LL_TIM_OCPOLARITY_HIGH
<>	156:95d6b41a828b	1694	* @arg @ref LL_TIM_OCPOLARITY_LOW
<>	156:95d6b41a828b	1695	* @retval None
<>	156:95d6b41a828b	1696	*/
<>	156:95d6b41a828b	1697	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
<>	156:95d6b41a828b	1698	{
<>	156:95d6b41a828b	1699	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	1700	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
<>	156:95d6b41a828b	1701	}
<>	156:95d6b41a828b	1702
<>	156:95d6b41a828b	1703	/**
<>	156:95d6b41a828b	1704	* @brief Get the polarity of an output channel.
<>	156:95d6b41a828b	1705	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
<>	156:95d6b41a828b	1706	* CCER CC1NP LL_TIM_OC_GetPolarity\n
<>	156:95d6b41a828b	1707	* CCER CC2P LL_TIM_OC_GetPolarity\n
<>	156:95d6b41a828b	1708	* CCER CC2NP LL_TIM_OC_GetPolarity\n
<>	156:95d6b41a828b	1709	* CCER CC3P LL_TIM_OC_GetPolarity\n
<>	156:95d6b41a828b	1710	* CCER CC3NP LL_TIM_OC_GetPolarity\n
<>	156:95d6b41a828b	1711	* CCER CC4P LL_TIM_OC_GetPolarity
<>	156:95d6b41a828b	1712	* @param TIMx Timer instance
<>	156:95d6b41a828b	1713	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1714	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1715	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	156:95d6b41a828b	1716	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1717	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	156:95d6b41a828b	1718	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1719	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	156:95d6b41a828b	1720	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1721	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1722	* @arg @ref LL_TIM_OCPOLARITY_HIGH
<>	156:95d6b41a828b	1723	* @arg @ref LL_TIM_OCPOLARITY_LOW
<>	156:95d6b41a828b	1724	*/
<>	156:95d6b41a828b	1725	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
<>	156:95d6b41a828b	1726	{
<>	156:95d6b41a828b	1727	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	1728	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
<>	156:95d6b41a828b	1729	}
<>	156:95d6b41a828b	1730
<>	156:95d6b41a828b	1731	/**
<>	156:95d6b41a828b	1732	* @brief Set the IDLE state of an output channel
<>	156:95d6b41a828b	1733	* @note This function is significant only for the timer instances
<>	156:95d6b41a828b	1734	* supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
<>	156:95d6b41a828b	1735	* can be used to check whether or not a timer instance provides
<>	156:95d6b41a828b	1736	* a break input.
<>	156:95d6b41a828b	1737	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
<>	156:95d6b41a828b	1738	* CR2 OIS1N LL_TIM_OC_SetIdleState\n
<>	156:95d6b41a828b	1739	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
<>	156:95d6b41a828b	1740	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
<>	156:95d6b41a828b	1741	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
<>	156:95d6b41a828b	1742	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
<>	156:95d6b41a828b	1743	* CR2 OIS4 LL_TIM_OC_SetIdleState
<>	156:95d6b41a828b	1744	* @param TIMx Timer instance
<>	156:95d6b41a828b	1745	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1746	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1747	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	156:95d6b41a828b	1748	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1749	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	156:95d6b41a828b	1750	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1751	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	156:95d6b41a828b	1752	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1753	* @param IdleState This parameter can be one of the following values:
<>	156:95d6b41a828b	1754	* @arg @ref LL_TIM_OCIDLESTATE_LOW
<>	156:95d6b41a828b	1755	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
<>	156:95d6b41a828b	1756	* @retval None
<>	156:95d6b41a828b	1757	*/
<>	156:95d6b41a828b	1758	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
<>	156:95d6b41a828b	1759	{
<>	156:95d6b41a828b	1760	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	1761	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
<>	156:95d6b41a828b	1762	}
<>	156:95d6b41a828b	1763
<>	156:95d6b41a828b	1764	/**
<>	156:95d6b41a828b	1765	* @brief Get the IDLE state of an output channel
<>	156:95d6b41a828b	1766	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
<>	156:95d6b41a828b	1767	* CR2 OIS1N LL_TIM_OC_GetIdleState\n
<>	156:95d6b41a828b	1768	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
<>	156:95d6b41a828b	1769	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
<>	156:95d6b41a828b	1770	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
<>	156:95d6b41a828b	1771	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
<>	156:95d6b41a828b	1772	* CR2 OIS4 LL_TIM_OC_GetIdleState
<>	156:95d6b41a828b	1773	* @param TIMx Timer instance
<>	156:95d6b41a828b	1774	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1775	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1776	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	156:95d6b41a828b	1777	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1778	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	156:95d6b41a828b	1779	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1780	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	156:95d6b41a828b	1781	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1782	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1783	* @arg @ref LL_TIM_OCIDLESTATE_LOW
<>	156:95d6b41a828b	1784	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
<>	156:95d6b41a828b	1785	*/
<>	156:95d6b41a828b	1786	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
<>	156:95d6b41a828b	1787	{
<>	156:95d6b41a828b	1788	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	1789	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
<>	156:95d6b41a828b	1790	}
<>	156:95d6b41a828b	1791
<>	156:95d6b41a828b	1792	/**
<>	156:95d6b41a828b	1793	* @brief Enable fast mode for the output channel.
<>	156:95d6b41a828b	1794	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
<>	156:95d6b41a828b	1795	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
<>	156:95d6b41a828b	1796	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
<>	156:95d6b41a828b	1797	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
<>	156:95d6b41a828b	1798	* CCMR2 OC4FE LL_TIM_OC_EnableFast
<>	156:95d6b41a828b	1799	* @param TIMx Timer instance
<>	156:95d6b41a828b	1800	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1801	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1802	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1803	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1804	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1805	* @retval None
<>	156:95d6b41a828b	1806	*/
<>	156:95d6b41a828b	1807	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
<>	156:95d6b41a828b	1808	{
<>	156:95d6b41a828b	1809	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	1810	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	1811	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
<>	156:95d6b41a828b	1812
<>	156:95d6b41a828b	1813	}
<>	156:95d6b41a828b	1814
<>	156:95d6b41a828b	1815	/**
<>	156:95d6b41a828b	1816	* @brief Disable fast mode for the output channel.
<>	156:95d6b41a828b	1817	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
<>	156:95d6b41a828b	1818	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
<>	156:95d6b41a828b	1819	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
<>	156:95d6b41a828b	1820	* CCMR2 OC4FE LL_TIM_OC_DisableFast
<>	156:95d6b41a828b	1821	* @param TIMx Timer instance
<>	156:95d6b41a828b	1822	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1823	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1824	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1825	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1826	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1827	* @retval None
<>	156:95d6b41a828b	1828	*/
<>	156:95d6b41a828b	1829	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
<>	156:95d6b41a828b	1830	{
<>	156:95d6b41a828b	1831	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	1832	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	1833	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
<>	156:95d6b41a828b	1834
<>	156:95d6b41a828b	1835	}
<>	156:95d6b41a828b	1836
<>	156:95d6b41a828b	1837	/**
<>	156:95d6b41a828b	1838	* @brief Indicates whether fast mode is enabled for the output channel.
<>	156:95d6b41a828b	1839	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
<>	156:95d6b41a828b	1840	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
<>	156:95d6b41a828b	1841	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
<>	156:95d6b41a828b	1842	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
<>	156:95d6b41a828b	1843	* @param TIMx Timer instance
<>	156:95d6b41a828b	1844	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1845	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1846	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1847	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1848	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1849	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1850	*/
<>	156:95d6b41a828b	1851	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
<>	156:95d6b41a828b	1852	{
<>	156:95d6b41a828b	1853	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	1854	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	1855	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
<>	156:95d6b41a828b	1856	return (READ_BIT(*pReg, bitfield) == bitfield);
<>	156:95d6b41a828b	1857	}
<>	156:95d6b41a828b	1858
<>	156:95d6b41a828b	1859	/**
<>	156:95d6b41a828b	1860	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
<>	156:95d6b41a828b	1861	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
<>	156:95d6b41a828b	1862	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
<>	156:95d6b41a828b	1863	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
<>	156:95d6b41a828b	1864	* CCMR2 OC4PE LL_TIM_OC_EnablePreload
<>	156:95d6b41a828b	1865	* @param TIMx Timer instance
<>	156:95d6b41a828b	1866	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1867	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1868	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1869	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1870	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1871	* @retval None
<>	156:95d6b41a828b	1872	*/
<>	156:95d6b41a828b	1873	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
<>	156:95d6b41a828b	1874	{
<>	156:95d6b41a828b	1875	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	1876	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	1877	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
<>	156:95d6b41a828b	1878	}
<>	156:95d6b41a828b	1879
<>	156:95d6b41a828b	1880	/**
<>	156:95d6b41a828b	1881	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
<>	156:95d6b41a828b	1882	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
<>	156:95d6b41a828b	1883	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
<>	156:95d6b41a828b	1884	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
<>	156:95d6b41a828b	1885	* CCMR2 OC4PE LL_TIM_OC_DisablePreload
<>	156:95d6b41a828b	1886	* @param TIMx Timer instance
<>	156:95d6b41a828b	1887	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1888	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1889	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1890	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1891	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1892	* @retval None
<>	156:95d6b41a828b	1893	*/
<>	156:95d6b41a828b	1894	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
<>	156:95d6b41a828b	1895	{
<>	156:95d6b41a828b	1896	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	1897	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	1898	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
<>	156:95d6b41a828b	1899	}
<>	156:95d6b41a828b	1900
<>	156:95d6b41a828b	1901	/**
<>	156:95d6b41a828b	1902	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
<>	156:95d6b41a828b	1903	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
<>	156:95d6b41a828b	1904	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
<>	156:95d6b41a828b	1905	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
<>	156:95d6b41a828b	1906	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
<>	156:95d6b41a828b	1907	* @param TIMx Timer instance
<>	156:95d6b41a828b	1908	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1909	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1910	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1911	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1912	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1913	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1914	*/
<>	156:95d6b41a828b	1915	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
<>	156:95d6b41a828b	1916	{
<>	156:95d6b41a828b	1917	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	1918	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	1919	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
<>	156:95d6b41a828b	1920	return (READ_BIT(*pReg, bitfield) == bitfield);
<>	156:95d6b41a828b	1921	}
<>	156:95d6b41a828b	1922
<>	156:95d6b41a828b	1923	/**
<>	156:95d6b41a828b	1924	* @brief Enable clearing the output channel on an external event.
<>	156:95d6b41a828b	1925	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
<>	156:95d6b41a828b	1926	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<>	156:95d6b41a828b	1927	* or not a timer instance can clear the OCxREF signal on an external event.
<>	156:95d6b41a828b	1928	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
<>	156:95d6b41a828b	1929	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
<>	156:95d6b41a828b	1930	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
<>	156:95d6b41a828b	1931	* CCMR2 OC4CE LL_TIM_OC_EnableClear
<>	156:95d6b41a828b	1932	* @param TIMx Timer instance
<>	156:95d6b41a828b	1933	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1934	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1935	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1936	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1937	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1938	* @retval None
<>	156:95d6b41a828b	1939	*/
<>	156:95d6b41a828b	1940	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
<>	156:95d6b41a828b	1941	{
<>	156:95d6b41a828b	1942	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	1943	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	1944	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
<>	156:95d6b41a828b	1945	}
<>	156:95d6b41a828b	1946
<>	156:95d6b41a828b	1947	/**
<>	156:95d6b41a828b	1948	* @brief Disable clearing the output channel on an external event.
<>	156:95d6b41a828b	1949	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<>	156:95d6b41a828b	1950	* or not a timer instance can clear the OCxREF signal on an external event.
<>	156:95d6b41a828b	1951	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
<>	156:95d6b41a828b	1952	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
<>	156:95d6b41a828b	1953	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
<>	156:95d6b41a828b	1954	* CCMR2 OC4CE LL_TIM_OC_DisableClear
<>	156:95d6b41a828b	1955	* @param TIMx Timer instance
<>	156:95d6b41a828b	1956	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1957	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1958	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1959	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1960	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1961	* @retval None
<>	156:95d6b41a828b	1962	*/
<>	156:95d6b41a828b	1963	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
<>	156:95d6b41a828b	1964	{
<>	156:95d6b41a828b	1965	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	1966	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	1967	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
<>	156:95d6b41a828b	1968	}
<>	156:95d6b41a828b	1969
<>	156:95d6b41a828b	1970	/**
<>	156:95d6b41a828b	1971	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
<>	156:95d6b41a828b	1972	* @note This function enables clearing the output channel on an external event.
<>	156:95d6b41a828b	1973	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
<>	156:95d6b41a828b	1974	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<>	156:95d6b41a828b	1975	* or not a timer instance can clear the OCxREF signal on an external event.
<>	156:95d6b41a828b	1976	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
<>	156:95d6b41a828b	1977	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
<>	156:95d6b41a828b	1978	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
<>	156:95d6b41a828b	1979	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
<>	156:95d6b41a828b	1980	* @param TIMx Timer instance
<>	156:95d6b41a828b	1981	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1982	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	1983	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	1984	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	1985	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	1986	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1987	*/
<>	156:95d6b41a828b	1988	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
<>	156:95d6b41a828b	1989	{
<>	156:95d6b41a828b	1990	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	1991	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	1992	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
<>	156:95d6b41a828b	1993	return (READ_BIT(*pReg, bitfield) == bitfield);
<>	156:95d6b41a828b	1994	}
<>	156:95d6b41a828b	1995
<>	156:95d6b41a828b	1996	/**
<>	156:95d6b41a828b	1997	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
<>	156:95d6b41a828b	1998	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	1999	* dead-time insertion feature is supported by a timer instance.
<>	156:95d6b41a828b	2000	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
<>	156:95d6b41a828b	2001	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
<>	156:95d6b41a828b	2002	* @param TIMx Timer instance
<>	156:95d6b41a828b	2003	* @param DeadTime between Min_Data=0 and Max_Data=255
<>	156:95d6b41a828b	2004	* @retval None
<>	156:95d6b41a828b	2005	*/
<>	156:95d6b41a828b	2006	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
<>	156:95d6b41a828b	2007	{
<>	156:95d6b41a828b	2008	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
<>	156:95d6b41a828b	2009	}
<>	156:95d6b41a828b	2010
<>	156:95d6b41a828b	2011	/**
<>	156:95d6b41a828b	2012	* @brief Set compare value for output channel 1 (TIMx_CCR1).
<>	156:95d6b41a828b	2013	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	156:95d6b41a828b	2014	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2015	* whether or not a timer instance supports a 32 bits counter.
<>	156:95d6b41a828b	2016	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2017	* output channel 1 is supported by a timer instance.
<>	156:95d6b41a828b	2018	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
<>	156:95d6b41a828b	2019	* @param TIMx Timer instance
<>	156:95d6b41a828b	2020	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	156:95d6b41a828b	2021	* @retval None
<>	156:95d6b41a828b	2022	*/
<>	156:95d6b41a828b	2023	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	156:95d6b41a828b	2024	{
<>	156:95d6b41a828b	2025	WRITE_REG(TIMx->CCR1, CompareValue);
<>	156:95d6b41a828b	2026	}
<>	156:95d6b41a828b	2027
<>	156:95d6b41a828b	2028	/**
<>	156:95d6b41a828b	2029	* @brief Set compare value for output channel 2 (TIMx_CCR2).
<>	156:95d6b41a828b	2030	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	156:95d6b41a828b	2031	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2032	* whether or not a timer instance supports a 32 bits counter.
<>	156:95d6b41a828b	2033	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2034	* output channel 2 is supported by a timer instance.
<>	156:95d6b41a828b	2035	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
<>	156:95d6b41a828b	2036	* @param TIMx Timer instance
<>	156:95d6b41a828b	2037	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	156:95d6b41a828b	2038	* @retval None
<>	156:95d6b41a828b	2039	*/
<>	156:95d6b41a828b	2040	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	156:95d6b41a828b	2041	{
<>	156:95d6b41a828b	2042	WRITE_REG(TIMx->CCR2, CompareValue);
<>	156:95d6b41a828b	2043	}
<>	156:95d6b41a828b	2044
<>	156:95d6b41a828b	2045	/**
<>	156:95d6b41a828b	2046	* @brief Set compare value for output channel 3 (TIMx_CCR3).
<>	156:95d6b41a828b	2047	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	156:95d6b41a828b	2048	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2049	* whether or not a timer instance supports a 32 bits counter.
<>	156:95d6b41a828b	2050	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2051	* output channel is supported by a timer instance.
<>	156:95d6b41a828b	2052	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
<>	156:95d6b41a828b	2053	* @param TIMx Timer instance
<>	156:95d6b41a828b	2054	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	156:95d6b41a828b	2055	* @retval None
<>	156:95d6b41a828b	2056	*/
<>	156:95d6b41a828b	2057	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	156:95d6b41a828b	2058	{
<>	156:95d6b41a828b	2059	WRITE_REG(TIMx->CCR3, CompareValue);
<>	156:95d6b41a828b	2060	}
<>	156:95d6b41a828b	2061
<>	156:95d6b41a828b	2062	/**
<>	156:95d6b41a828b	2063	* @brief Set compare value for output channel 4 (TIMx_CCR4).
<>	156:95d6b41a828b	2064	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	156:95d6b41a828b	2065	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2066	* whether or not a timer instance supports a 32 bits counter.
<>	156:95d6b41a828b	2067	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2068	* output channel 4 is supported by a timer instance.
<>	156:95d6b41a828b	2069	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
<>	156:95d6b41a828b	2070	* @param TIMx Timer instance
<>	156:95d6b41a828b	2071	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	156:95d6b41a828b	2072	* @retval None
<>	156:95d6b41a828b	2073	*/
<>	156:95d6b41a828b	2074	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	156:95d6b41a828b	2075	{
<>	156:95d6b41a828b	2076	WRITE_REG(TIMx->CCR4, CompareValue);
<>	156:95d6b41a828b	2077	}
<>	156:95d6b41a828b	2078
<>	156:95d6b41a828b	2079	/**
<>	156:95d6b41a828b	2080	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
<>	156:95d6b41a828b	2081	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	156:95d6b41a828b	2082	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2083	* whether or not a timer instance supports a 32 bits counter.
<>	156:95d6b41a828b	2084	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2085	* output channel 1 is supported by a timer instance.
<>	156:95d6b41a828b	2086	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
<>	156:95d6b41a828b	2087	* @param TIMx Timer instance
<>	156:95d6b41a828b	2088	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	156:95d6b41a828b	2089	*/
<>	156:95d6b41a828b	2090	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2091	{
<>	156:95d6b41a828b	2092	return (uint32_t)(READ_REG(TIMx->CCR1));
<>	156:95d6b41a828b	2093	}
<>	156:95d6b41a828b	2094
<>	156:95d6b41a828b	2095	/**
<>	156:95d6b41a828b	2096	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
<>	156:95d6b41a828b	2097	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	156:95d6b41a828b	2098	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2099	* whether or not a timer instance supports a 32 bits counter.
<>	156:95d6b41a828b	2100	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2101	* output channel 2 is supported by a timer instance.
<>	156:95d6b41a828b	2102	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
<>	156:95d6b41a828b	2103	* @param TIMx Timer instance
<>	156:95d6b41a828b	2104	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	156:95d6b41a828b	2105	*/
<>	156:95d6b41a828b	2106	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2107	{
<>	156:95d6b41a828b	2108	return (uint32_t)(READ_REG(TIMx->CCR2));
<>	156:95d6b41a828b	2109	}
<>	156:95d6b41a828b	2110
<>	156:95d6b41a828b	2111	/**
<>	156:95d6b41a828b	2112	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
<>	156:95d6b41a828b	2113	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	156:95d6b41a828b	2114	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2115	* whether or not a timer instance supports a 32 bits counter.
<>	156:95d6b41a828b	2116	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2117	* output channel 3 is supported by a timer instance.
<>	156:95d6b41a828b	2118	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
<>	156:95d6b41a828b	2119	* @param TIMx Timer instance
<>	156:95d6b41a828b	2120	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	156:95d6b41a828b	2121	*/
<>	156:95d6b41a828b	2122	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2123	{
<>	156:95d6b41a828b	2124	return (uint32_t)(READ_REG(TIMx->CCR3));
<>	156:95d6b41a828b	2125	}
<>	156:95d6b41a828b	2126
<>	156:95d6b41a828b	2127	/**
<>	156:95d6b41a828b	2128	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
<>	156:95d6b41a828b	2129	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	156:95d6b41a828b	2130	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2131	* whether or not a timer instance supports a 32 bits counter.
<>	156:95d6b41a828b	2132	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2133	* output channel 4 is supported by a timer instance.
<>	156:95d6b41a828b	2134	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
<>	156:95d6b41a828b	2135	* @param TIMx Timer instance
<>	156:95d6b41a828b	2136	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	156:95d6b41a828b	2137	*/
<>	156:95d6b41a828b	2138	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2139	{
<>	156:95d6b41a828b	2140	return (uint32_t)(READ_REG(TIMx->CCR4));
<>	156:95d6b41a828b	2141	}
<>	156:95d6b41a828b	2142
<>	156:95d6b41a828b	2143	/**
<>	156:95d6b41a828b	2144	* @}
<>	156:95d6b41a828b	2145	*/
<>	156:95d6b41a828b	2146
<>	156:95d6b41a828b	2147	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
<>	156:95d6b41a828b	2148	* @{
<>	156:95d6b41a828b	2149	*/
<>	156:95d6b41a828b	2150	/**
<>	156:95d6b41a828b	2151	* @brief Configure input channel.
<>	156:95d6b41a828b	2152	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2153	* CCMR1 IC1PSC LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2154	* CCMR1 IC1F LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2155	* CCMR1 CC2S LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2156	* CCMR1 IC2PSC LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2157	* CCMR1 IC2F LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2158	* CCMR2 CC3S LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2159	* CCMR2 IC3PSC LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2160	* CCMR2 IC3F LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2161	* CCMR2 CC4S LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2162	* CCMR2 IC4PSC LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2163	* CCMR2 IC4F LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2164	* CCER CC1P LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2165	* CCER CC1NP LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2166	* CCER CC2P LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2167	* CCER CC2NP LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2168	* CCER CC3P LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2169	* CCER CC3NP LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2170	* CCER CC4P LL_TIM_IC_Config\n
<>	156:95d6b41a828b	2171	* CCER CC4NP LL_TIM_IC_Config
<>	156:95d6b41a828b	2172	* @param TIMx Timer instance
<>	156:95d6b41a828b	2173	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	2174	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	2175	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	2176	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	2177	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	2178	* @param Configuration This parameter must be a combination of all the following values:
<>	156:95d6b41a828b	2179	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
<>	156:95d6b41a828b	2180	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
<>	156:95d6b41a828b	2181	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
<>	156:95d6b41a828b	2182	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
<>	156:95d6b41a828b	2183	* @retval None
<>	156:95d6b41a828b	2184	*/
<>	156:95d6b41a828b	2185	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
<>	156:95d6b41a828b	2186	{
<>	156:95d6b41a828b	2187	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	2188	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	2189	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
<>	156:95d6b41a828b	2190	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
<>	156:95d6b41a828b	2191	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
<>	156:95d6b41a828b	2192	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
<>	156:95d6b41a828b	2193	}
<>	156:95d6b41a828b	2194
<>	156:95d6b41a828b	2195	/**
<>	156:95d6b41a828b	2196	* @brief Set the active input.
<>	156:95d6b41a828b	2197	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
<>	156:95d6b41a828b	2198	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
<>	156:95d6b41a828b	2199	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
<>	156:95d6b41a828b	2200	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
<>	156:95d6b41a828b	2201	* @param TIMx Timer instance
<>	156:95d6b41a828b	2202	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	2203	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	2204	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	2205	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	2206	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	2207	* @param ICActiveInput This parameter can be one of the following values:
<>	156:95d6b41a828b	2208	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
<>	156:95d6b41a828b	2209	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
<>	156:95d6b41a828b	2210	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
<>	156:95d6b41a828b	2211	* @retval None
<>	156:95d6b41a828b	2212	*/
<>	156:95d6b41a828b	2213	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
<>	156:95d6b41a828b	2214	{
<>	156:95d6b41a828b	2215	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	2216	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	2217	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<>	156:95d6b41a828b	2218	}
<>	156:95d6b41a828b	2219
<>	156:95d6b41a828b	2220	/**
<>	156:95d6b41a828b	2221	* @brief Get the current active input.
<>	156:95d6b41a828b	2222	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
<>	156:95d6b41a828b	2223	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
<>	156:95d6b41a828b	2224	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
<>	156:95d6b41a828b	2225	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
<>	156:95d6b41a828b	2226	* @param TIMx Timer instance
<>	156:95d6b41a828b	2227	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	2228	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	2229	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	2230	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	2231	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	2232	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	2233	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
<>	156:95d6b41a828b	2234	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
<>	156:95d6b41a828b	2235	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
<>	156:95d6b41a828b	2236	*/
<>	156:95d6b41a828b	2237	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
<>	156:95d6b41a828b	2238	{
<>	156:95d6b41a828b	2239	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	2240	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	2241	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<>	156:95d6b41a828b	2242	}
<>	156:95d6b41a828b	2243
<>	156:95d6b41a828b	2244	/**
<>	156:95d6b41a828b	2245	* @brief Set the prescaler of input channel.
<>	156:95d6b41a828b	2246	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
<>	156:95d6b41a828b	2247	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
<>	156:95d6b41a828b	2248	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
<>	156:95d6b41a828b	2249	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
<>	156:95d6b41a828b	2250	* @param TIMx Timer instance
<>	156:95d6b41a828b	2251	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	2252	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	2253	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	2254	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	2255	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	2256	* @param ICPrescaler This parameter can be one of the following values:
<>	156:95d6b41a828b	2257	* @arg @ref LL_TIM_ICPSC_DIV1
<>	156:95d6b41a828b	2258	* @arg @ref LL_TIM_ICPSC_DIV2
<>	156:95d6b41a828b	2259	* @arg @ref LL_TIM_ICPSC_DIV4
<>	156:95d6b41a828b	2260	* @arg @ref LL_TIM_ICPSC_DIV8
<>	156:95d6b41a828b	2261	* @retval None
<>	156:95d6b41a828b	2262	*/
<>	156:95d6b41a828b	2263	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
<>	156:95d6b41a828b	2264	{
<>	156:95d6b41a828b	2265	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	2266	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	2267	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<>	156:95d6b41a828b	2268	}
<>	156:95d6b41a828b	2269
<>	156:95d6b41a828b	2270	/**
<>	156:95d6b41a828b	2271	* @brief Get the current prescaler value acting on an input channel.
<>	156:95d6b41a828b	2272	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
<>	156:95d6b41a828b	2273	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
<>	156:95d6b41a828b	2274	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
<>	156:95d6b41a828b	2275	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
<>	156:95d6b41a828b	2276	* @param TIMx Timer instance
<>	156:95d6b41a828b	2277	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	2278	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	2279	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	2280	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	2281	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	2282	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	2283	* @arg @ref LL_TIM_ICPSC_DIV1
<>	156:95d6b41a828b	2284	* @arg @ref LL_TIM_ICPSC_DIV2
<>	156:95d6b41a828b	2285	* @arg @ref LL_TIM_ICPSC_DIV4
<>	156:95d6b41a828b	2286	* @arg @ref LL_TIM_ICPSC_DIV8
<>	156:95d6b41a828b	2287	*/
<>	156:95d6b41a828b	2288	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
<>	156:95d6b41a828b	2289	{
<>	156:95d6b41a828b	2290	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	2291	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	2292	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<>	156:95d6b41a828b	2293	}
<>	156:95d6b41a828b	2294
<>	156:95d6b41a828b	2295	/**
<>	156:95d6b41a828b	2296	* @brief Set the input filter duration.
<>	156:95d6b41a828b	2297	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
<>	156:95d6b41a828b	2298	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
<>	156:95d6b41a828b	2299	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
<>	156:95d6b41a828b	2300	* CCMR2 IC4F LL_TIM_IC_SetFilter
<>	156:95d6b41a828b	2301	* @param TIMx Timer instance
<>	156:95d6b41a828b	2302	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	2303	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	2304	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	2305	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	2306	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	2307	* @param ICFilter This parameter can be one of the following values:
<>	156:95d6b41a828b	2308	* @arg @ref LL_TIM_IC_FILTER_FDIV1
<>	156:95d6b41a828b	2309	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
<>	156:95d6b41a828b	2310	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
<>	156:95d6b41a828b	2311	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
<>	156:95d6b41a828b	2312	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
<>	156:95d6b41a828b	2313	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
<>	156:95d6b41a828b	2314	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
<>	156:95d6b41a828b	2315	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
<>	156:95d6b41a828b	2316	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
<>	156:95d6b41a828b	2317	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
<>	156:95d6b41a828b	2318	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
<>	156:95d6b41a828b	2319	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
<>	156:95d6b41a828b	2320	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
<>	156:95d6b41a828b	2321	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
<>	156:95d6b41a828b	2322	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
<>	156:95d6b41a828b	2323	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
<>	156:95d6b41a828b	2324	* @retval None
<>	156:95d6b41a828b	2325	*/
<>	156:95d6b41a828b	2326	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
<>	156:95d6b41a828b	2327	{
<>	156:95d6b41a828b	2328	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	2329	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	2330	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<>	156:95d6b41a828b	2331	}
<>	156:95d6b41a828b	2332
<>	156:95d6b41a828b	2333	/**
<>	156:95d6b41a828b	2334	* @brief Get the input filter duration.
<>	156:95d6b41a828b	2335	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
<>	156:95d6b41a828b	2336	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
<>	156:95d6b41a828b	2337	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
<>	156:95d6b41a828b	2338	* CCMR2 IC4F LL_TIM_IC_GetFilter
<>	156:95d6b41a828b	2339	* @param TIMx Timer instance
<>	156:95d6b41a828b	2340	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	2341	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	2342	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	2343	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	2344	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	2345	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	2346	* @arg @ref LL_TIM_IC_FILTER_FDIV1
<>	156:95d6b41a828b	2347	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
<>	156:95d6b41a828b	2348	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
<>	156:95d6b41a828b	2349	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
<>	156:95d6b41a828b	2350	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
<>	156:95d6b41a828b	2351	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
<>	156:95d6b41a828b	2352	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
<>	156:95d6b41a828b	2353	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
<>	156:95d6b41a828b	2354	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
<>	156:95d6b41a828b	2355	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
<>	156:95d6b41a828b	2356	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
<>	156:95d6b41a828b	2357	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
<>	156:95d6b41a828b	2358	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
<>	156:95d6b41a828b	2359	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
<>	156:95d6b41a828b	2360	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
<>	156:95d6b41a828b	2361	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
<>	156:95d6b41a828b	2362	*/
<>	156:95d6b41a828b	2363	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
<>	156:95d6b41a828b	2364	{
<>	156:95d6b41a828b	2365	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	2366	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	156:95d6b41a828b	2367	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<>	156:95d6b41a828b	2368	}
<>	156:95d6b41a828b	2369
<>	156:95d6b41a828b	2370	/**
<>	156:95d6b41a828b	2371	* @brief Set the input channel polarity.
<>	156:95d6b41a828b	2372	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
<>	156:95d6b41a828b	2373	* CCER CC1NP LL_TIM_IC_SetPolarity\n
<>	156:95d6b41a828b	2374	* CCER CC2P LL_TIM_IC_SetPolarity\n
<>	156:95d6b41a828b	2375	* CCER CC2NP LL_TIM_IC_SetPolarity\n
<>	156:95d6b41a828b	2376	* CCER CC3P LL_TIM_IC_SetPolarity\n
<>	156:95d6b41a828b	2377	* CCER CC3NP LL_TIM_IC_SetPolarity\n
<>	156:95d6b41a828b	2378	* CCER CC4P LL_TIM_IC_SetPolarity\n
<>	156:95d6b41a828b	2379	* CCER CC4NP LL_TIM_IC_SetPolarity
<>	156:95d6b41a828b	2380	* @param TIMx Timer instance
<>	156:95d6b41a828b	2381	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	2382	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	2383	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	2384	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	2385	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	2386	* @param ICPolarity This parameter can be one of the following values:
<>	156:95d6b41a828b	2387	* @arg @ref LL_TIM_IC_POLARITY_RISING
<>	156:95d6b41a828b	2388	* @arg @ref LL_TIM_IC_POLARITY_FALLING
<>	156:95d6b41a828b	2389	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
<>	156:95d6b41a828b	2390	* @retval None
<>	156:95d6b41a828b	2391	*/
<>	156:95d6b41a828b	2392	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
<>	156:95d6b41a828b	2393	{
<>	156:95d6b41a828b	2394	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	2395	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
<>	156:95d6b41a828b	2396	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
<>	156:95d6b41a828b	2397	}
<>	156:95d6b41a828b	2398
<>	156:95d6b41a828b	2399	/**
<>	156:95d6b41a828b	2400	* @brief Get the current input channel polarity.
<>	156:95d6b41a828b	2401	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
<>	156:95d6b41a828b	2402	* CCER CC1NP LL_TIM_IC_GetPolarity\n
<>	156:95d6b41a828b	2403	* CCER CC2P LL_TIM_IC_GetPolarity\n
<>	156:95d6b41a828b	2404	* CCER CC2NP LL_TIM_IC_GetPolarity\n
<>	156:95d6b41a828b	2405	* CCER CC3P LL_TIM_IC_GetPolarity\n
<>	156:95d6b41a828b	2406	* CCER CC3NP LL_TIM_IC_GetPolarity\n
<>	156:95d6b41a828b	2407	* CCER CC4P LL_TIM_IC_GetPolarity\n
<>	156:95d6b41a828b	2408	* CCER CC4NP LL_TIM_IC_GetPolarity
<>	156:95d6b41a828b	2409	* @param TIMx Timer instance
<>	156:95d6b41a828b	2410	* @param Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	2411	* @arg @ref LL_TIM_CHANNEL_CH1
<>	156:95d6b41a828b	2412	* @arg @ref LL_TIM_CHANNEL_CH2
<>	156:95d6b41a828b	2413	* @arg @ref LL_TIM_CHANNEL_CH3
<>	156:95d6b41a828b	2414	* @arg @ref LL_TIM_CHANNEL_CH4
<>	156:95d6b41a828b	2415	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	2416	* @arg @ref LL_TIM_IC_POLARITY_RISING
<>	156:95d6b41a828b	2417	* @arg @ref LL_TIM_IC_POLARITY_FALLING
<>	156:95d6b41a828b	2418	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
<>	156:95d6b41a828b	2419	*/
<>	156:95d6b41a828b	2420	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
<>	156:95d6b41a828b	2421	{
<>	156:95d6b41a828b	2422	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	156:95d6b41a828b	2423	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
<>	156:95d6b41a828b	2424	SHIFT_TAB_CCxP[iChannel]);
<>	156:95d6b41a828b	2425	}
<>	156:95d6b41a828b	2426
<>	156:95d6b41a828b	2427	/**
<>	156:95d6b41a828b	2428	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
<>	156:95d6b41a828b	2429	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2430	* a timer instance provides an XOR input.
<>	156:95d6b41a828b	2431	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
<>	156:95d6b41a828b	2432	* @param TIMx Timer instance
<>	156:95d6b41a828b	2433	* @retval None
<>	156:95d6b41a828b	2434	*/
<>	156:95d6b41a828b	2435	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2436	{
<>	156:95d6b41a828b	2437	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
<>	156:95d6b41a828b	2438	}
<>	156:95d6b41a828b	2439
<>	156:95d6b41a828b	2440	/**
<>	156:95d6b41a828b	2441	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
<>	156:95d6b41a828b	2442	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2443	* a timer instance provides an XOR input.
<>	156:95d6b41a828b	2444	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
<>	156:95d6b41a828b	2445	* @param TIMx Timer instance
<>	156:95d6b41a828b	2446	* @retval None
<>	156:95d6b41a828b	2447	*/
<>	156:95d6b41a828b	2448	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2449	{
<>	156:95d6b41a828b	2450	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
<>	156:95d6b41a828b	2451	}
<>	156:95d6b41a828b	2452
<>	156:95d6b41a828b	2453	/**
<>	156:95d6b41a828b	2454	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
<>	156:95d6b41a828b	2455	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2456	* a timer instance provides an XOR input.
<>	156:95d6b41a828b	2457	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
<>	156:95d6b41a828b	2458	* @param TIMx Timer instance
<>	156:95d6b41a828b	2459	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2460	*/
<>	156:95d6b41a828b	2461	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2462	{
<>	156:95d6b41a828b	2463	return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
<>	156:95d6b41a828b	2464	}
<>	156:95d6b41a828b	2465
<>	156:95d6b41a828b	2466	/**
<>	156:95d6b41a828b	2467	* @brief Get captured value for input channel 1.
<>	156:95d6b41a828b	2468	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	156:95d6b41a828b	2469	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2470	* whether or not a timer instance supports a 32 bits counter.
<>	156:95d6b41a828b	2471	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2472	* input channel 1 is supported by a timer instance.
<>	156:95d6b41a828b	2473	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
<>	156:95d6b41a828b	2474	* @param TIMx Timer instance
<>	156:95d6b41a828b	2475	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	156:95d6b41a828b	2476	*/
<>	156:95d6b41a828b	2477	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2478	{
<>	156:95d6b41a828b	2479	return (uint32_t)(READ_REG(TIMx->CCR1));
<>	156:95d6b41a828b	2480	}
<>	156:95d6b41a828b	2481
<>	156:95d6b41a828b	2482	/**
<>	156:95d6b41a828b	2483	* @brief Get captured value for input channel 2.
<>	156:95d6b41a828b	2484	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	156:95d6b41a828b	2485	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2486	* whether or not a timer instance supports a 32 bits counter.
<>	156:95d6b41a828b	2487	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2488	* input channel 2 is supported by a timer instance.
<>	156:95d6b41a828b	2489	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
<>	156:95d6b41a828b	2490	* @param TIMx Timer instance
<>	156:95d6b41a828b	2491	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	156:95d6b41a828b	2492	*/
<>	156:95d6b41a828b	2493	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2494	{
<>	156:95d6b41a828b	2495	return (uint32_t)(READ_REG(TIMx->CCR2));
<>	156:95d6b41a828b	2496	}
<>	156:95d6b41a828b	2497
<>	156:95d6b41a828b	2498	/**
<>	156:95d6b41a828b	2499	* @brief Get captured value for input channel 3.
<>	156:95d6b41a828b	2500	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	156:95d6b41a828b	2501	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2502	* whether or not a timer instance supports a 32 bits counter.
<>	156:95d6b41a828b	2503	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2504	* input channel 3 is supported by a timer instance.
<>	156:95d6b41a828b	2505	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
<>	156:95d6b41a828b	2506	* @param TIMx Timer instance
<>	156:95d6b41a828b	2507	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	156:95d6b41a828b	2508	*/
<>	156:95d6b41a828b	2509	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2510	{
<>	156:95d6b41a828b	2511	return (uint32_t)(READ_REG(TIMx->CCR3));
<>	156:95d6b41a828b	2512	}
<>	156:95d6b41a828b	2513
<>	156:95d6b41a828b	2514	/**
<>	156:95d6b41a828b	2515	* @brief Get captured value for input channel 4.
<>	156:95d6b41a828b	2516	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	156:95d6b41a828b	2517	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2518	* whether or not a timer instance supports a 32 bits counter.
<>	156:95d6b41a828b	2519	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2520	* input channel 4 is supported by a timer instance.
<>	156:95d6b41a828b	2521	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
<>	156:95d6b41a828b	2522	* @param TIMx Timer instance
<>	156:95d6b41a828b	2523	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	156:95d6b41a828b	2524	*/
<>	156:95d6b41a828b	2525	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2526	{
<>	156:95d6b41a828b	2527	return (uint32_t)(READ_REG(TIMx->CCR4));
<>	156:95d6b41a828b	2528	}
<>	156:95d6b41a828b	2529
<>	156:95d6b41a828b	2530	/**
<>	156:95d6b41a828b	2531	* @}
<>	156:95d6b41a828b	2532	*/
<>	156:95d6b41a828b	2533
<>	156:95d6b41a828b	2534	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
<>	156:95d6b41a828b	2535	* @{
<>	156:95d6b41a828b	2536	*/
<>	156:95d6b41a828b	2537	/**
<>	156:95d6b41a828b	2538	* @brief Enable external clock mode 2.
<>	156:95d6b41a828b	2539	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
<>	156:95d6b41a828b	2540	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2541	* whether or not a timer instance supports external clock mode2.
<>	156:95d6b41a828b	2542	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
<>	156:95d6b41a828b	2543	* @param TIMx Timer instance
<>	156:95d6b41a828b	2544	* @retval None
<>	156:95d6b41a828b	2545	*/
<>	156:95d6b41a828b	2546	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2547	{
<>	156:95d6b41a828b	2548	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
<>	156:95d6b41a828b	2549	}
<>	156:95d6b41a828b	2550
<>	156:95d6b41a828b	2551	/**
<>	156:95d6b41a828b	2552	* @brief Disable external clock mode 2.
<>	156:95d6b41a828b	2553	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2554	* whether or not a timer instance supports external clock mode2.
<>	156:95d6b41a828b	2555	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
<>	156:95d6b41a828b	2556	* @param TIMx Timer instance
<>	156:95d6b41a828b	2557	* @retval None
<>	156:95d6b41a828b	2558	*/
<>	156:95d6b41a828b	2559	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2560	{
<>	156:95d6b41a828b	2561	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
<>	156:95d6b41a828b	2562	}
<>	156:95d6b41a828b	2563
<>	156:95d6b41a828b	2564	/**
<>	156:95d6b41a828b	2565	* @brief Indicate whether external clock mode 2 is enabled.
<>	156:95d6b41a828b	2566	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2567	* whether or not a timer instance supports external clock mode2.
<>	156:95d6b41a828b	2568	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
<>	156:95d6b41a828b	2569	* @param TIMx Timer instance
<>	156:95d6b41a828b	2570	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2571	*/
<>	156:95d6b41a828b	2572	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2573	{
<>	156:95d6b41a828b	2574	return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
<>	156:95d6b41a828b	2575	}
<>	156:95d6b41a828b	2576
<>	156:95d6b41a828b	2577	/**
<>	156:95d6b41a828b	2578	* @brief Set the clock source of the counter clock.
<>	156:95d6b41a828b	2579	* @note when selected clock source is external clock mode 1, the timer input
<>	156:95d6b41a828b	2580	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
<>	156:95d6b41a828b	2581	* function. This timer input must be configured by calling
<>	156:95d6b41a828b	2582	* the @ref LL_TIM_IC_Config() function.
<>	156:95d6b41a828b	2583	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2584	* whether or not a timer instance supports external clock mode1.
<>	156:95d6b41a828b	2585	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2586	* whether or not a timer instance supports external clock mode2.
<>	156:95d6b41a828b	2587	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
<>	156:95d6b41a828b	2588	* SMCR ECE LL_TIM_SetClockSource
<>	156:95d6b41a828b	2589	* @param TIMx Timer instance
<>	156:95d6b41a828b	2590	* @param ClockSource This parameter can be one of the following values:
<>	156:95d6b41a828b	2591	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
<>	156:95d6b41a828b	2592	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
<>	156:95d6b41a828b	2593	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
<>	156:95d6b41a828b	2594	* @retval None
<>	156:95d6b41a828b	2595	*/
<>	156:95d6b41a828b	2596	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
<>	156:95d6b41a828b	2597	{
<>	156:95d6b41a828b	2598	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
<>	156:95d6b41a828b	2599	}
<>	156:95d6b41a828b	2600
<>	156:95d6b41a828b	2601	/**
<>	156:95d6b41a828b	2602	* @brief Set the encoder interface mode.
<>	156:95d6b41a828b	2603	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2604	* whether or not a timer instance supports the encoder mode.
<>	156:95d6b41a828b	2605	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
<>	156:95d6b41a828b	2606	* @param TIMx Timer instance
<>	156:95d6b41a828b	2607	* @param EncoderMode This parameter can be one of the following values:
<>	156:95d6b41a828b	2608	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
<>	156:95d6b41a828b	2609	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
<>	156:95d6b41a828b	2610	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
<>	156:95d6b41a828b	2611	* @retval None
<>	156:95d6b41a828b	2612	*/
<>	156:95d6b41a828b	2613	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
<>	156:95d6b41a828b	2614	{
<>	156:95d6b41a828b	2615	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
<>	156:95d6b41a828b	2616	}
<>	156:95d6b41a828b	2617
<>	156:95d6b41a828b	2618	/**
<>	156:95d6b41a828b	2619	* @}
<>	156:95d6b41a828b	2620	*/
<>	156:95d6b41a828b	2621
<>	156:95d6b41a828b	2622	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
<>	156:95d6b41a828b	2623	* @{
<>	156:95d6b41a828b	2624	*/
<>	156:95d6b41a828b	2625	/**
<>	156:95d6b41a828b	2626	* @brief Set the trigger output (TRGO) used for timer synchronization .
<>	156:95d6b41a828b	2627	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
<>	156:95d6b41a828b	2628	* whether or not a timer instance can operate as a master timer.
<>	156:95d6b41a828b	2629	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
<>	156:95d6b41a828b	2630	* @param TIMx Timer instance
<>	156:95d6b41a828b	2631	* @param TimerSynchronization This parameter can be one of the following values:
<>	156:95d6b41a828b	2632	* @arg @ref LL_TIM_TRGO_RESET
<>	156:95d6b41a828b	2633	* @arg @ref LL_TIM_TRGO_ENABLE
<>	156:95d6b41a828b	2634	* @arg @ref LL_TIM_TRGO_UPDATE
<>	156:95d6b41a828b	2635	* @arg @ref LL_TIM_TRGO_CC1IF
<>	156:95d6b41a828b	2636	* @arg @ref LL_TIM_TRGO_OC1REF
<>	156:95d6b41a828b	2637	* @arg @ref LL_TIM_TRGO_OC2REF
<>	156:95d6b41a828b	2638	* @arg @ref LL_TIM_TRGO_OC3REF
<>	156:95d6b41a828b	2639	* @arg @ref LL_TIM_TRGO_OC4REF
<>	156:95d6b41a828b	2640	* @retval None
<>	156:95d6b41a828b	2641	*/
<>	156:95d6b41a828b	2642	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
<>	156:95d6b41a828b	2643	{
<>	156:95d6b41a828b	2644	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
<>	156:95d6b41a828b	2645	}
<>	156:95d6b41a828b	2646
<>	156:95d6b41a828b	2647	/**
<>	156:95d6b41a828b	2648	* @brief Set the synchronization mode of a slave timer.
<>	156:95d6b41a828b	2649	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2650	* a timer instance can operate as a slave timer.
<>	156:95d6b41a828b	2651	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
<>	156:95d6b41a828b	2652	* @param TIMx Timer instance
<>	156:95d6b41a828b	2653	* @param SlaveMode This parameter can be one of the following values:
<>	156:95d6b41a828b	2654	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
<>	156:95d6b41a828b	2655	* @arg @ref LL_TIM_SLAVEMODE_RESET
<>	156:95d6b41a828b	2656	* @arg @ref LL_TIM_SLAVEMODE_GATED
<>	156:95d6b41a828b	2657	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
<>	156:95d6b41a828b	2658	* @retval None
<>	156:95d6b41a828b	2659	*/
<>	156:95d6b41a828b	2660	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
<>	156:95d6b41a828b	2661	{
<>	156:95d6b41a828b	2662	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
<>	156:95d6b41a828b	2663	}
<>	156:95d6b41a828b	2664
<>	156:95d6b41a828b	2665	/**
<>	156:95d6b41a828b	2666	* @brief Set the selects the trigger input to be used to synchronize the counter.
<>	156:95d6b41a828b	2667	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2668	* a timer instance can operate as a slave timer.
<>	156:95d6b41a828b	2669	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
<>	156:95d6b41a828b	2670	* @param TIMx Timer instance
<>	156:95d6b41a828b	2671	* @param TriggerInput This parameter can be one of the following values:
<>	156:95d6b41a828b	2672	* @arg @ref LL_TIM_TS_ITR0
<>	156:95d6b41a828b	2673	* @arg @ref LL_TIM_TS_ITR1
<>	156:95d6b41a828b	2674	* @arg @ref LL_TIM_TS_ITR2
<>	156:95d6b41a828b	2675	* @arg @ref LL_TIM_TS_ITR3
<>	156:95d6b41a828b	2676	* @arg @ref LL_TIM_TS_TI1F_ED
<>	156:95d6b41a828b	2677	* @arg @ref LL_TIM_TS_TI1FP1
<>	156:95d6b41a828b	2678	* @arg @ref LL_TIM_TS_TI2FP2
<>	156:95d6b41a828b	2679	* @arg @ref LL_TIM_TS_ETRF
<>	156:95d6b41a828b	2680	* @retval None
<>	156:95d6b41a828b	2681	*/
<>	156:95d6b41a828b	2682	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
<>	156:95d6b41a828b	2683	{
<>	156:95d6b41a828b	2684	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
<>	156:95d6b41a828b	2685	}
<>	156:95d6b41a828b	2686
<>	156:95d6b41a828b	2687	/**
<>	156:95d6b41a828b	2688	* @brief Enable the Master/Slave mode.
<>	156:95d6b41a828b	2689	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2690	* a timer instance can operate as a slave timer.
<>	156:95d6b41a828b	2691	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
<>	156:95d6b41a828b	2692	* @param TIMx Timer instance
<>	156:95d6b41a828b	2693	* @retval None
<>	156:95d6b41a828b	2694	*/
<>	156:95d6b41a828b	2695	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2696	{
<>	156:95d6b41a828b	2697	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
<>	156:95d6b41a828b	2698	}
<>	156:95d6b41a828b	2699
<>	156:95d6b41a828b	2700	/**
<>	156:95d6b41a828b	2701	* @brief Disable the Master/Slave mode.
<>	156:95d6b41a828b	2702	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2703	* a timer instance can operate as a slave timer.
<>	156:95d6b41a828b	2704	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
<>	156:95d6b41a828b	2705	* @param TIMx Timer instance
<>	156:95d6b41a828b	2706	* @retval None
<>	156:95d6b41a828b	2707	*/
<>	156:95d6b41a828b	2708	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2709	{
<>	156:95d6b41a828b	2710	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
<>	156:95d6b41a828b	2711	}
<>	156:95d6b41a828b	2712
<>	156:95d6b41a828b	2713	/**
<>	156:95d6b41a828b	2714	* @brief Indicates whether the Master/Slave mode is enabled.
<>	156:95d6b41a828b	2715	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2716	* a timer instance can operate as a slave timer.
<>	156:95d6b41a828b	2717	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
<>	156:95d6b41a828b	2718	* @param TIMx Timer instance
<>	156:95d6b41a828b	2719	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2720	*/
<>	156:95d6b41a828b	2721	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2722	{
<>	156:95d6b41a828b	2723	return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
<>	156:95d6b41a828b	2724	}
<>	156:95d6b41a828b	2725
<>	156:95d6b41a828b	2726	/**
<>	156:95d6b41a828b	2727	* @brief Configure the external trigger (ETR) input.
<>	156:95d6b41a828b	2728	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2729	* a timer instance provides an external trigger input.
<>	156:95d6b41a828b	2730	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
<>	156:95d6b41a828b	2731	* SMCR ETPS LL_TIM_ConfigETR\n
<>	156:95d6b41a828b	2732	* SMCR ETF LL_TIM_ConfigETR
<>	156:95d6b41a828b	2733	* @param TIMx Timer instance
<>	156:95d6b41a828b	2734	* @param ETRPolarity This parameter can be one of the following values:
<>	156:95d6b41a828b	2735	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
<>	156:95d6b41a828b	2736	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
<>	156:95d6b41a828b	2737	* @param ETRPrescaler This parameter can be one of the following values:
<>	156:95d6b41a828b	2738	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
<>	156:95d6b41a828b	2739	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
<>	156:95d6b41a828b	2740	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
<>	156:95d6b41a828b	2741	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
<>	156:95d6b41a828b	2742	* @param ETRFilter This parameter can be one of the following values:
<>	156:95d6b41a828b	2743	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
<>	156:95d6b41a828b	2744	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
<>	156:95d6b41a828b	2745	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
<>	156:95d6b41a828b	2746	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
<>	156:95d6b41a828b	2747	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
<>	156:95d6b41a828b	2748	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
<>	156:95d6b41a828b	2749	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
<>	156:95d6b41a828b	2750	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
<>	156:95d6b41a828b	2751	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
<>	156:95d6b41a828b	2752	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
<>	156:95d6b41a828b	2753	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
<>	156:95d6b41a828b	2754	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
<>	156:95d6b41a828b	2755	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
<>	156:95d6b41a828b	2756	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
<>	156:95d6b41a828b	2757	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
<>	156:95d6b41a828b	2758	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
<>	156:95d6b41a828b	2759	* @retval None
<>	156:95d6b41a828b	2760	*/
<>	156:95d6b41a828b	2761	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
<>	156:95d6b41a828b	2762	uint32_t ETRFilter)
<>	156:95d6b41a828b	2763	{
<>	156:95d6b41a828b	2764	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
<>	156:95d6b41a828b	2765	}
<>	156:95d6b41a828b	2766
<>	156:95d6b41a828b	2767	/**
<>	156:95d6b41a828b	2768	* @}
<>	156:95d6b41a828b	2769	*/
<>	156:95d6b41a828b	2770
<>	156:95d6b41a828b	2771	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
<>	156:95d6b41a828b	2772	* @{
<>	156:95d6b41a828b	2773	*/
<>	156:95d6b41a828b	2774	/**
<>	156:95d6b41a828b	2775	* @brief Enable the break function.
<>	156:95d6b41a828b	2776	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2777	* a timer instance provides a break input.
<>	156:95d6b41a828b	2778	* @rmtoll BDTR BKE LL_TIM_EnableBRK
<>	156:95d6b41a828b	2779	* @param TIMx Timer instance
<>	156:95d6b41a828b	2780	* @retval None
<>	156:95d6b41a828b	2781	*/
<>	156:95d6b41a828b	2782	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2783	{
Anna Bridge	180:96ed750bd169	2784	__IO uint32_t tmpreg;
Anna Bridge	180:96ed750bd169	2785
<>	156:95d6b41a828b	2786	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
Anna Bridge	180:96ed750bd169	2787
Anna Bridge	180:96ed750bd169	2788	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
Anna Bridge	180:96ed750bd169	2789	tmpreg = READ_REG(TIMx->BDTR);
Anna Bridge	180:96ed750bd169	2790	(void)(tmpreg);
<>	156:95d6b41a828b	2791	}
<>	156:95d6b41a828b	2792
<>	156:95d6b41a828b	2793	/**
<>	156:95d6b41a828b	2794	* @brief Disable the break function.
<>	156:95d6b41a828b	2795	* @rmtoll BDTR BKE LL_TIM_DisableBRK
<>	156:95d6b41a828b	2796	* @param TIMx Timer instance
<>	156:95d6b41a828b	2797	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2798	* a timer instance provides a break input.
<>	156:95d6b41a828b	2799	* @retval None
<>	156:95d6b41a828b	2800	*/
<>	156:95d6b41a828b	2801	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2802	{
Anna Bridge	180:96ed750bd169	2803	__IO uint32_t tmpreg;
Anna Bridge	180:96ed750bd169	2804
<>	156:95d6b41a828b	2805	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
Anna Bridge	180:96ed750bd169	2806
Anna Bridge	180:96ed750bd169	2807	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
Anna Bridge	180:96ed750bd169	2808	tmpreg = READ_REG(TIMx->BDTR);
Anna Bridge	180:96ed750bd169	2809	(void)(tmpreg);
<>	156:95d6b41a828b	2810	}
<>	156:95d6b41a828b	2811
<>	156:95d6b41a828b	2812	/**
<>	156:95d6b41a828b	2813	* @brief Configure the break input.
<>	156:95d6b41a828b	2814	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2815	* a timer instance provides a break input.
<>	156:95d6b41a828b	2816	* @rmtoll BDTR BKP LL_TIM_ConfigBRK
<>	156:95d6b41a828b	2817	* @param TIMx Timer instance
<>	156:95d6b41a828b	2818	* @param BreakPolarity This parameter can be one of the following values:
<>	156:95d6b41a828b	2819	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
<>	156:95d6b41a828b	2820	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
<>	156:95d6b41a828b	2821	* @retval None
<>	156:95d6b41a828b	2822	*/
<>	156:95d6b41a828b	2823	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
<>	156:95d6b41a828b	2824	{
Anna Bridge	180:96ed750bd169	2825	__IO uint32_t tmpreg;
Anna Bridge	180:96ed750bd169	2826
<>	156:95d6b41a828b	2827	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
Anna Bridge	180:96ed750bd169	2828
Anna Bridge	180:96ed750bd169	2829	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
Anna Bridge	180:96ed750bd169	2830	tmpreg = READ_REG(TIMx->BDTR);
Anna Bridge	180:96ed750bd169	2831	(void)(tmpreg);
<>	156:95d6b41a828b	2832	}
<>	156:95d6b41a828b	2833
<>	156:95d6b41a828b	2834	/**
<>	156:95d6b41a828b	2835	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
<>	156:95d6b41a828b	2836	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2837	* a timer instance provides a break input.
<>	156:95d6b41a828b	2838	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
<>	156:95d6b41a828b	2839	* BDTR OSSR LL_TIM_SetOffStates
<>	156:95d6b41a828b	2840	* @param TIMx Timer instance
<>	156:95d6b41a828b	2841	* @param OffStateIdle This parameter can be one of the following values:
<>	156:95d6b41a828b	2842	* @arg @ref LL_TIM_OSSI_DISABLE
<>	156:95d6b41a828b	2843	* @arg @ref LL_TIM_OSSI_ENABLE
<>	156:95d6b41a828b	2844	* @param OffStateRun This parameter can be one of the following values:
<>	156:95d6b41a828b	2845	* @arg @ref LL_TIM_OSSR_DISABLE
<>	156:95d6b41a828b	2846	* @arg @ref LL_TIM_OSSR_ENABLE
<>	156:95d6b41a828b	2847	* @retval None
<>	156:95d6b41a828b	2848	*/
<>	156:95d6b41a828b	2849	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
<>	156:95d6b41a828b	2850	{
<>	156:95d6b41a828b	2851	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
<>	156:95d6b41a828b	2852	}
<>	156:95d6b41a828b	2853
<>	156:95d6b41a828b	2854	/**
<>	156:95d6b41a828b	2855	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
<>	156:95d6b41a828b	2856	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2857	* a timer instance provides a break input.
<>	156:95d6b41a828b	2858	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
<>	156:95d6b41a828b	2859	* @param TIMx Timer instance
<>	156:95d6b41a828b	2860	* @retval None
<>	156:95d6b41a828b	2861	*/
<>	156:95d6b41a828b	2862	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2863	{
<>	156:95d6b41a828b	2864	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
<>	156:95d6b41a828b	2865	}
<>	156:95d6b41a828b	2866
<>	156:95d6b41a828b	2867	/**
<>	156:95d6b41a828b	2868	* @brief Disable automatic output (MOE can be set only by software).
<>	156:95d6b41a828b	2869	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2870	* a timer instance provides a break input.
<>	156:95d6b41a828b	2871	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
<>	156:95d6b41a828b	2872	* @param TIMx Timer instance
<>	156:95d6b41a828b	2873	* @retval None
<>	156:95d6b41a828b	2874	*/
<>	156:95d6b41a828b	2875	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2876	{
<>	156:95d6b41a828b	2877	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
<>	156:95d6b41a828b	2878	}
<>	156:95d6b41a828b	2879
<>	156:95d6b41a828b	2880	/**
<>	156:95d6b41a828b	2881	* @brief Indicate whether automatic output is enabled.
<>	156:95d6b41a828b	2882	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2883	* a timer instance provides a break input.
<>	156:95d6b41a828b	2884	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
<>	156:95d6b41a828b	2885	* @param TIMx Timer instance
<>	156:95d6b41a828b	2886	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2887	*/
<>	156:95d6b41a828b	2888	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2889	{
<>	156:95d6b41a828b	2890	return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
<>	156:95d6b41a828b	2891	}
<>	156:95d6b41a828b	2892
<>	156:95d6b41a828b	2893	/**
<>	156:95d6b41a828b	2894	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
<>	156:95d6b41a828b	2895	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
<>	156:95d6b41a828b	2896	* software and is reset in case of break or break2 event
<>	156:95d6b41a828b	2897	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2898	* a timer instance provides a break input.
<>	156:95d6b41a828b	2899	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
<>	156:95d6b41a828b	2900	* @param TIMx Timer instance
<>	156:95d6b41a828b	2901	* @retval None
<>	156:95d6b41a828b	2902	*/
<>	156:95d6b41a828b	2903	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2904	{
<>	156:95d6b41a828b	2905	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
<>	156:95d6b41a828b	2906	}
<>	156:95d6b41a828b	2907
<>	156:95d6b41a828b	2908	/**
<>	156:95d6b41a828b	2909	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
<>	156:95d6b41a828b	2910	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
<>	156:95d6b41a828b	2911	* software and is reset in case of break or break2 event.
<>	156:95d6b41a828b	2912	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2913	* a timer instance provides a break input.
<>	156:95d6b41a828b	2914	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
<>	156:95d6b41a828b	2915	* @param TIMx Timer instance
<>	156:95d6b41a828b	2916	* @retval None
<>	156:95d6b41a828b	2917	*/
<>	156:95d6b41a828b	2918	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2919	{
<>	156:95d6b41a828b	2920	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
<>	156:95d6b41a828b	2921	}
<>	156:95d6b41a828b	2922
<>	156:95d6b41a828b	2923	/**
<>	156:95d6b41a828b	2924	* @brief Indicates whether outputs are enabled.
<>	156:95d6b41a828b	2925	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	2926	* a timer instance provides a break input.
<>	156:95d6b41a828b	2927	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
<>	156:95d6b41a828b	2928	* @param TIMx Timer instance
<>	156:95d6b41a828b	2929	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2930	*/
<>	156:95d6b41a828b	2931	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	2932	{
<>	156:95d6b41a828b	2933	return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
<>	156:95d6b41a828b	2934	}
<>	156:95d6b41a828b	2935
<>	156:95d6b41a828b	2936	/**
<>	156:95d6b41a828b	2937	* @}
<>	156:95d6b41a828b	2938	*/
<>	156:95d6b41a828b	2939
<>	156:95d6b41a828b	2940	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
<>	156:95d6b41a828b	2941	* @{
<>	156:95d6b41a828b	2942	*/
<>	156:95d6b41a828b	2943	/**
<>	156:95d6b41a828b	2944	* @brief Configures the timer DMA burst feature.
<>	156:95d6b41a828b	2945	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
<>	156:95d6b41a828b	2946	* not a timer instance supports the DMA burst mode.
<>	156:95d6b41a828b	2947	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
<>	156:95d6b41a828b	2948	* DCR DBA LL_TIM_ConfigDMABurst
<>	156:95d6b41a828b	2949	* @param TIMx Timer instance
<>	156:95d6b41a828b	2950	* @param DMABurstBaseAddress This parameter can be one of the following values:
<>	156:95d6b41a828b	2951	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
<>	156:95d6b41a828b	2952	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
<>	156:95d6b41a828b	2953	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
<>	156:95d6b41a828b	2954	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
<>	156:95d6b41a828b	2955	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
<>	156:95d6b41a828b	2956	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
<>	156:95d6b41a828b	2957	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
<>	156:95d6b41a828b	2958	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
<>	156:95d6b41a828b	2959	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
<>	156:95d6b41a828b	2960	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
<>	156:95d6b41a828b	2961	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
<>	156:95d6b41a828b	2962	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
<>	156:95d6b41a828b	2963	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
<>	156:95d6b41a828b	2964	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
<>	156:95d6b41a828b	2965	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
<>	156:95d6b41a828b	2966	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
<>	156:95d6b41a828b	2967	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
<>	156:95d6b41a828b	2968	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
<>	156:95d6b41a828b	2969	* @param DMABurstLength This parameter can be one of the following values:
<>	156:95d6b41a828b	2970	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
<>	156:95d6b41a828b	2971	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
<>	156:95d6b41a828b	2972	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
<>	156:95d6b41a828b	2973	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
<>	156:95d6b41a828b	2974	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
<>	156:95d6b41a828b	2975	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
<>	156:95d6b41a828b	2976	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
<>	156:95d6b41a828b	2977	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
<>	156:95d6b41a828b	2978	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
<>	156:95d6b41a828b	2979	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
<>	156:95d6b41a828b	2980	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
<>	156:95d6b41a828b	2981	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
<>	156:95d6b41a828b	2982	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
<>	156:95d6b41a828b	2983	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
<>	156:95d6b41a828b	2984	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
<>	156:95d6b41a828b	2985	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
<>	156:95d6b41a828b	2986	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
<>	156:95d6b41a828b	2987	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
<>	156:95d6b41a828b	2988	* @retval None
<>	156:95d6b41a828b	2989	*/
<>	156:95d6b41a828b	2990	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
<>	156:95d6b41a828b	2991	{
<>	156:95d6b41a828b	2992	MODIFY_REG(TIMx->DCR, TIM_DCR_DBL \| TIM_DCR_DBA, DMABurstBaseAddress \| DMABurstLength);
<>	156:95d6b41a828b	2993	}
<>	156:95d6b41a828b	2994
<>	156:95d6b41a828b	2995	/**
<>	156:95d6b41a828b	2996	* @}
<>	156:95d6b41a828b	2997	*/
<>	156:95d6b41a828b	2998
<>	156:95d6b41a828b	2999	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
<>	156:95d6b41a828b	3000	* @{
<>	156:95d6b41a828b	3001	*/
<>	156:95d6b41a828b	3002	/**
<>	156:95d6b41a828b	3003	* @brief Remap TIM inputs (input channel, internal/external triggers).
<>	156:95d6b41a828b	3004	* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
<>	156:95d6b41a828b	3005	* a some timer inputs can be remapped.
<>	156:95d6b41a828b	3006	* @rmtoll TIM14_OR TI1_RMP LL_TIM_SetRemap
<>	156:95d6b41a828b	3007	* @param TIMx Timer instance
<>	156:95d6b41a828b	3008	* @param Remap This parameter can be one of the following values:
<>	156:95d6b41a828b	3009	* @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO
<>	156:95d6b41a828b	3010	* @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK
<>	156:95d6b41a828b	3011	* @arg @ref LL_TIM_TIM14_TI1_RMP_HSE
<>	156:95d6b41a828b	3012	* @arg @ref LL_TIM_TIM14_TI1_RMP_MCO
<>	156:95d6b41a828b	3013	*
<>	156:95d6b41a828b	3014	* @retval None
<>	156:95d6b41a828b	3015	*/
<>	156:95d6b41a828b	3016	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
<>	156:95d6b41a828b	3017	{
<>	156:95d6b41a828b	3018	MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
<>	156:95d6b41a828b	3019	}
<>	156:95d6b41a828b	3020
<>	156:95d6b41a828b	3021	/**
<>	156:95d6b41a828b	3022	* @}
<>	156:95d6b41a828b	3023	*/
<>	156:95d6b41a828b	3024
<>	156:95d6b41a828b	3025	/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
<>	156:95d6b41a828b	3026	* @{
<>	156:95d6b41a828b	3027	*/
<>	156:95d6b41a828b	3028	/**
Anna Bridge	180:96ed750bd169	3029	* @brief Set the OCREF clear input source
<>	156:95d6b41a828b	3030	* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
<>	156:95d6b41a828b	3031	* @note This function can only be used in Output compare and PWM modes.
Anna Bridge	180:96ed750bd169	3032	* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
<>	156:95d6b41a828b	3033	* @param TIMx Timer instance
<>	156:95d6b41a828b	3034	* @param OCRefClearInputSource This parameter can be one of the following values:
<>	156:95d6b41a828b	3035	* @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
<>	156:95d6b41a828b	3036	* @arg @ref LL_TIM_OCREF_CLR_INT_ETR
<>	156:95d6b41a828b	3037	* @retval None
<>	156:95d6b41a828b	3038	*/
<>	156:95d6b41a828b	3039	__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
<>	156:95d6b41a828b	3040	{
<>	156:95d6b41a828b	3041	MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
<>	156:95d6b41a828b	3042	}
<>	156:95d6b41a828b	3043	/**
<>	156:95d6b41a828b	3044	* @}
<>	156:95d6b41a828b	3045	*/
<>	156:95d6b41a828b	3046
<>	156:95d6b41a828b	3047	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
<>	156:95d6b41a828b	3048	* @{
<>	156:95d6b41a828b	3049	*/
<>	156:95d6b41a828b	3050	/**
<>	156:95d6b41a828b	3051	* @brief Clear the update interrupt flag (UIF).
<>	156:95d6b41a828b	3052	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
<>	156:95d6b41a828b	3053	* @param TIMx Timer instance
<>	156:95d6b41a828b	3054	* @retval None
<>	156:95d6b41a828b	3055	*/
<>	156:95d6b41a828b	3056	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3057	{
<>	156:95d6b41a828b	3058	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
<>	156:95d6b41a828b	3059	}
<>	156:95d6b41a828b	3060
<>	156:95d6b41a828b	3061	/**
<>	156:95d6b41a828b	3062	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
<>	156:95d6b41a828b	3063	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
<>	156:95d6b41a828b	3064	* @param TIMx Timer instance
<>	156:95d6b41a828b	3065	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3066	*/
<>	156:95d6b41a828b	3067	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3068	{
<>	156:95d6b41a828b	3069	return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
<>	156:95d6b41a828b	3070	}
<>	156:95d6b41a828b	3071
<>	156:95d6b41a828b	3072	/**
<>	156:95d6b41a828b	3073	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
<>	156:95d6b41a828b	3074	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
<>	156:95d6b41a828b	3075	* @param TIMx Timer instance
<>	156:95d6b41a828b	3076	* @retval None
<>	156:95d6b41a828b	3077	*/
<>	156:95d6b41a828b	3078	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3079	{
<>	156:95d6b41a828b	3080	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
<>	156:95d6b41a828b	3081	}
<>	156:95d6b41a828b	3082
<>	156:95d6b41a828b	3083	/**
<>	156:95d6b41a828b	3084	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
<>	156:95d6b41a828b	3085	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
<>	156:95d6b41a828b	3086	* @param TIMx Timer instance
<>	156:95d6b41a828b	3087	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3088	*/
<>	156:95d6b41a828b	3089	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3090	{
<>	156:95d6b41a828b	3091	return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
<>	156:95d6b41a828b	3092	}
<>	156:95d6b41a828b	3093
<>	156:95d6b41a828b	3094	/**
<>	156:95d6b41a828b	3095	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
<>	156:95d6b41a828b	3096	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
<>	156:95d6b41a828b	3097	* @param TIMx Timer instance
<>	156:95d6b41a828b	3098	* @retval None
<>	156:95d6b41a828b	3099	*/
<>	156:95d6b41a828b	3100	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3101	{
<>	156:95d6b41a828b	3102	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
<>	156:95d6b41a828b	3103	}
<>	156:95d6b41a828b	3104
<>	156:95d6b41a828b	3105	/**
<>	156:95d6b41a828b	3106	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
<>	156:95d6b41a828b	3107	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
<>	156:95d6b41a828b	3108	* @param TIMx Timer instance
<>	156:95d6b41a828b	3109	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3110	*/
<>	156:95d6b41a828b	3111	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3112	{
<>	156:95d6b41a828b	3113	return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
<>	156:95d6b41a828b	3114	}
<>	156:95d6b41a828b	3115
<>	156:95d6b41a828b	3116	/**
<>	156:95d6b41a828b	3117	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
<>	156:95d6b41a828b	3118	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
<>	156:95d6b41a828b	3119	* @param TIMx Timer instance
<>	156:95d6b41a828b	3120	* @retval None
<>	156:95d6b41a828b	3121	*/
<>	156:95d6b41a828b	3122	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3123	{
<>	156:95d6b41a828b	3124	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
<>	156:95d6b41a828b	3125	}
<>	156:95d6b41a828b	3126
<>	156:95d6b41a828b	3127	/**
<>	156:95d6b41a828b	3128	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
<>	156:95d6b41a828b	3129	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
<>	156:95d6b41a828b	3130	* @param TIMx Timer instance
<>	156:95d6b41a828b	3131	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3132	*/
<>	156:95d6b41a828b	3133	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3134	{
<>	156:95d6b41a828b	3135	return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
<>	156:95d6b41a828b	3136	}
<>	156:95d6b41a828b	3137
<>	156:95d6b41a828b	3138	/**
<>	156:95d6b41a828b	3139	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
<>	156:95d6b41a828b	3140	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
<>	156:95d6b41a828b	3141	* @param TIMx Timer instance
<>	156:95d6b41a828b	3142	* @retval None
<>	156:95d6b41a828b	3143	*/
<>	156:95d6b41a828b	3144	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3145	{
<>	156:95d6b41a828b	3146	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
<>	156:95d6b41a828b	3147	}
<>	156:95d6b41a828b	3148
<>	156:95d6b41a828b	3149	/**
<>	156:95d6b41a828b	3150	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
<>	156:95d6b41a828b	3151	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
<>	156:95d6b41a828b	3152	* @param TIMx Timer instance
<>	156:95d6b41a828b	3153	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3154	*/
<>	156:95d6b41a828b	3155	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3156	{
<>	156:95d6b41a828b	3157	return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
<>	156:95d6b41a828b	3158	}
<>	156:95d6b41a828b	3159
<>	156:95d6b41a828b	3160	/**
<>	156:95d6b41a828b	3161	* @brief Clear the commutation interrupt flag (COMIF).
<>	156:95d6b41a828b	3162	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
<>	156:95d6b41a828b	3163	* @param TIMx Timer instance
<>	156:95d6b41a828b	3164	* @retval None
<>	156:95d6b41a828b	3165	*/
<>	156:95d6b41a828b	3166	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3167	{
<>	156:95d6b41a828b	3168	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
<>	156:95d6b41a828b	3169	}
<>	156:95d6b41a828b	3170
<>	156:95d6b41a828b	3171	/**
<>	156:95d6b41a828b	3172	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
<>	156:95d6b41a828b	3173	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
<>	156:95d6b41a828b	3174	* @param TIMx Timer instance
<>	156:95d6b41a828b	3175	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3176	*/
<>	156:95d6b41a828b	3177	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3178	{
<>	156:95d6b41a828b	3179	return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
<>	156:95d6b41a828b	3180	}
<>	156:95d6b41a828b	3181
<>	156:95d6b41a828b	3182	/**
<>	156:95d6b41a828b	3183	* @brief Clear the trigger interrupt flag (TIF).
<>	156:95d6b41a828b	3184	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
<>	156:95d6b41a828b	3185	* @param TIMx Timer instance
<>	156:95d6b41a828b	3186	* @retval None
<>	156:95d6b41a828b	3187	*/
<>	156:95d6b41a828b	3188	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3189	{
<>	156:95d6b41a828b	3190	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
<>	156:95d6b41a828b	3191	}
<>	156:95d6b41a828b	3192
<>	156:95d6b41a828b	3193	/**
<>	156:95d6b41a828b	3194	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
<>	156:95d6b41a828b	3195	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
<>	156:95d6b41a828b	3196	* @param TIMx Timer instance
<>	156:95d6b41a828b	3197	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3198	*/
<>	156:95d6b41a828b	3199	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3200	{
<>	156:95d6b41a828b	3201	return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
<>	156:95d6b41a828b	3202	}
<>	156:95d6b41a828b	3203
<>	156:95d6b41a828b	3204	/**
<>	156:95d6b41a828b	3205	* @brief Clear the break interrupt flag (BIF).
<>	156:95d6b41a828b	3206	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
<>	156:95d6b41a828b	3207	* @param TIMx Timer instance
<>	156:95d6b41a828b	3208	* @retval None
<>	156:95d6b41a828b	3209	*/
<>	156:95d6b41a828b	3210	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3211	{
<>	156:95d6b41a828b	3212	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
<>	156:95d6b41a828b	3213	}
<>	156:95d6b41a828b	3214
<>	156:95d6b41a828b	3215	/**
<>	156:95d6b41a828b	3216	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
<>	156:95d6b41a828b	3217	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
<>	156:95d6b41a828b	3218	* @param TIMx Timer instance
<>	156:95d6b41a828b	3219	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3220	*/
<>	156:95d6b41a828b	3221	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3222	{
<>	156:95d6b41a828b	3223	return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
<>	156:95d6b41a828b	3224	}
<>	156:95d6b41a828b	3225
<>	156:95d6b41a828b	3226	/**
<>	156:95d6b41a828b	3227	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
<>	156:95d6b41a828b	3228	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
<>	156:95d6b41a828b	3229	* @param TIMx Timer instance
<>	156:95d6b41a828b	3230	* @retval None
<>	156:95d6b41a828b	3231	*/
<>	156:95d6b41a828b	3232	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3233	{
<>	156:95d6b41a828b	3234	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
<>	156:95d6b41a828b	3235	}
<>	156:95d6b41a828b	3236
<>	156:95d6b41a828b	3237	/**
<>	156:95d6b41a828b	3238	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
<>	156:95d6b41a828b	3239	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
<>	156:95d6b41a828b	3240	* @param TIMx Timer instance
<>	156:95d6b41a828b	3241	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3242	*/
<>	156:95d6b41a828b	3243	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3244	{
<>	156:95d6b41a828b	3245	return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
<>	156:95d6b41a828b	3246	}
<>	156:95d6b41a828b	3247
<>	156:95d6b41a828b	3248	/**
<>	156:95d6b41a828b	3249	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
<>	156:95d6b41a828b	3250	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
<>	156:95d6b41a828b	3251	* @param TIMx Timer instance
<>	156:95d6b41a828b	3252	* @retval None
<>	156:95d6b41a828b	3253	*/
<>	156:95d6b41a828b	3254	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3255	{
<>	156:95d6b41a828b	3256	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
<>	156:95d6b41a828b	3257	}
<>	156:95d6b41a828b	3258
<>	156:95d6b41a828b	3259	/**
<>	156:95d6b41a828b	3260	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
<>	156:95d6b41a828b	3261	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
<>	156:95d6b41a828b	3262	* @param TIMx Timer instance
<>	156:95d6b41a828b	3263	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3264	*/
<>	156:95d6b41a828b	3265	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3266	{
<>	156:95d6b41a828b	3267	return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
<>	156:95d6b41a828b	3268	}
<>	156:95d6b41a828b	3269
<>	156:95d6b41a828b	3270	/**
<>	156:95d6b41a828b	3271	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
<>	156:95d6b41a828b	3272	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
<>	156:95d6b41a828b	3273	* @param TIMx Timer instance
<>	156:95d6b41a828b	3274	* @retval None
<>	156:95d6b41a828b	3275	*/
<>	156:95d6b41a828b	3276	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3277	{
<>	156:95d6b41a828b	3278	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
<>	156:95d6b41a828b	3279	}
<>	156:95d6b41a828b	3280
<>	156:95d6b41a828b	3281	/**
<>	156:95d6b41a828b	3282	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
<>	156:95d6b41a828b	3283	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
<>	156:95d6b41a828b	3284	* @param TIMx Timer instance
<>	156:95d6b41a828b	3285	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3286	*/
<>	156:95d6b41a828b	3287	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3288	{
<>	156:95d6b41a828b	3289	return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
<>	156:95d6b41a828b	3290	}
<>	156:95d6b41a828b	3291
<>	156:95d6b41a828b	3292	/**
<>	156:95d6b41a828b	3293	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
<>	156:95d6b41a828b	3294	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
<>	156:95d6b41a828b	3295	* @param TIMx Timer instance
<>	156:95d6b41a828b	3296	* @retval None
<>	156:95d6b41a828b	3297	*/
<>	156:95d6b41a828b	3298	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3299	{
<>	156:95d6b41a828b	3300	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
<>	156:95d6b41a828b	3301	}
<>	156:95d6b41a828b	3302
<>	156:95d6b41a828b	3303	/**
<>	156:95d6b41a828b	3304	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
<>	156:95d6b41a828b	3305	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
<>	156:95d6b41a828b	3306	* @param TIMx Timer instance
<>	156:95d6b41a828b	3307	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3308	*/
<>	156:95d6b41a828b	3309	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3310	{
<>	156:95d6b41a828b	3311	return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
<>	156:95d6b41a828b	3312	}
<>	156:95d6b41a828b	3313
<>	156:95d6b41a828b	3314	/**
<>	156:95d6b41a828b	3315	* @}
<>	156:95d6b41a828b	3316	*/
<>	156:95d6b41a828b	3317
<>	156:95d6b41a828b	3318	/** @defgroup TIM_LL_EF_IT_Management IT-Management
<>	156:95d6b41a828b	3319	* @{
<>	156:95d6b41a828b	3320	*/
<>	156:95d6b41a828b	3321	/**
<>	156:95d6b41a828b	3322	* @brief Enable update interrupt (UIE).
<>	156:95d6b41a828b	3323	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
<>	156:95d6b41a828b	3324	* @param TIMx Timer instance
<>	156:95d6b41a828b	3325	* @retval None
<>	156:95d6b41a828b	3326	*/
<>	156:95d6b41a828b	3327	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3328	{
<>	156:95d6b41a828b	3329	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
<>	156:95d6b41a828b	3330	}
<>	156:95d6b41a828b	3331
<>	156:95d6b41a828b	3332	/**
<>	156:95d6b41a828b	3333	* @brief Disable update interrupt (UIE).
<>	156:95d6b41a828b	3334	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
<>	156:95d6b41a828b	3335	* @param TIMx Timer instance
<>	156:95d6b41a828b	3336	* @retval None
<>	156:95d6b41a828b	3337	*/
<>	156:95d6b41a828b	3338	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3339	{
<>	156:95d6b41a828b	3340	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
<>	156:95d6b41a828b	3341	}
<>	156:95d6b41a828b	3342
<>	156:95d6b41a828b	3343	/**
<>	156:95d6b41a828b	3344	* @brief Indicates whether the update interrupt (UIE) is enabled.
<>	156:95d6b41a828b	3345	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
<>	156:95d6b41a828b	3346	* @param TIMx Timer instance
<>	156:95d6b41a828b	3347	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3348	*/
<>	156:95d6b41a828b	3349	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3350	{
<>	156:95d6b41a828b	3351	return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
<>	156:95d6b41a828b	3352	}
<>	156:95d6b41a828b	3353
<>	156:95d6b41a828b	3354	/**
<>	156:95d6b41a828b	3355	* @brief Enable capture/compare 1 interrupt (CC1IE).
<>	156:95d6b41a828b	3356	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
<>	156:95d6b41a828b	3357	* @param TIMx Timer instance
<>	156:95d6b41a828b	3358	* @retval None
<>	156:95d6b41a828b	3359	*/
<>	156:95d6b41a828b	3360	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3361	{
<>	156:95d6b41a828b	3362	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
<>	156:95d6b41a828b	3363	}
<>	156:95d6b41a828b	3364
<>	156:95d6b41a828b	3365	/**
<>	156:95d6b41a828b	3366	* @brief Disable capture/compare 1 interrupt (CC1IE).
<>	156:95d6b41a828b	3367	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
<>	156:95d6b41a828b	3368	* @param TIMx Timer instance
<>	156:95d6b41a828b	3369	* @retval None
<>	156:95d6b41a828b	3370	*/
<>	156:95d6b41a828b	3371	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3372	{
<>	156:95d6b41a828b	3373	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
<>	156:95d6b41a828b	3374	}
<>	156:95d6b41a828b	3375
<>	156:95d6b41a828b	3376	/**
<>	156:95d6b41a828b	3377	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
<>	156:95d6b41a828b	3378	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
<>	156:95d6b41a828b	3379	* @param TIMx Timer instance
<>	156:95d6b41a828b	3380	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3381	*/
<>	156:95d6b41a828b	3382	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3383	{
<>	156:95d6b41a828b	3384	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
<>	156:95d6b41a828b	3385	}
<>	156:95d6b41a828b	3386
<>	156:95d6b41a828b	3387	/**
<>	156:95d6b41a828b	3388	* @brief Enable capture/compare 2 interrupt (CC2IE).
<>	156:95d6b41a828b	3389	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
<>	156:95d6b41a828b	3390	* @param TIMx Timer instance
<>	156:95d6b41a828b	3391	* @retval None
<>	156:95d6b41a828b	3392	*/
<>	156:95d6b41a828b	3393	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3394	{
<>	156:95d6b41a828b	3395	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
<>	156:95d6b41a828b	3396	}
<>	156:95d6b41a828b	3397
<>	156:95d6b41a828b	3398	/**
<>	156:95d6b41a828b	3399	* @brief Disable capture/compare 2 interrupt (CC2IE).
<>	156:95d6b41a828b	3400	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
<>	156:95d6b41a828b	3401	* @param TIMx Timer instance
<>	156:95d6b41a828b	3402	* @retval None
<>	156:95d6b41a828b	3403	*/
<>	156:95d6b41a828b	3404	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3405	{
<>	156:95d6b41a828b	3406	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
<>	156:95d6b41a828b	3407	}
<>	156:95d6b41a828b	3408
<>	156:95d6b41a828b	3409	/**
<>	156:95d6b41a828b	3410	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
<>	156:95d6b41a828b	3411	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
<>	156:95d6b41a828b	3412	* @param TIMx Timer instance
<>	156:95d6b41a828b	3413	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3414	*/
<>	156:95d6b41a828b	3415	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3416	{
<>	156:95d6b41a828b	3417	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
<>	156:95d6b41a828b	3418	}
<>	156:95d6b41a828b	3419
<>	156:95d6b41a828b	3420	/**
<>	156:95d6b41a828b	3421	* @brief Enable capture/compare 3 interrupt (CC3IE).
<>	156:95d6b41a828b	3422	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
<>	156:95d6b41a828b	3423	* @param TIMx Timer instance
<>	156:95d6b41a828b	3424	* @retval None
<>	156:95d6b41a828b	3425	*/
<>	156:95d6b41a828b	3426	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3427	{
<>	156:95d6b41a828b	3428	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
<>	156:95d6b41a828b	3429	}
<>	156:95d6b41a828b	3430
<>	156:95d6b41a828b	3431	/**
<>	156:95d6b41a828b	3432	* @brief Disable capture/compare 3 interrupt (CC3IE).
<>	156:95d6b41a828b	3433	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
<>	156:95d6b41a828b	3434	* @param TIMx Timer instance
<>	156:95d6b41a828b	3435	* @retval None
<>	156:95d6b41a828b	3436	*/
<>	156:95d6b41a828b	3437	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3438	{
<>	156:95d6b41a828b	3439	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
<>	156:95d6b41a828b	3440	}
<>	156:95d6b41a828b	3441
<>	156:95d6b41a828b	3442	/**
<>	156:95d6b41a828b	3443	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
<>	156:95d6b41a828b	3444	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
<>	156:95d6b41a828b	3445	* @param TIMx Timer instance
<>	156:95d6b41a828b	3446	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3447	*/
<>	156:95d6b41a828b	3448	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3449	{
<>	156:95d6b41a828b	3450	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
<>	156:95d6b41a828b	3451	}
<>	156:95d6b41a828b	3452
<>	156:95d6b41a828b	3453	/**
<>	156:95d6b41a828b	3454	* @brief Enable capture/compare 4 interrupt (CC4IE).
<>	156:95d6b41a828b	3455	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
<>	156:95d6b41a828b	3456	* @param TIMx Timer instance
<>	156:95d6b41a828b	3457	* @retval None
<>	156:95d6b41a828b	3458	*/
<>	156:95d6b41a828b	3459	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3460	{
<>	156:95d6b41a828b	3461	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
<>	156:95d6b41a828b	3462	}
<>	156:95d6b41a828b	3463
<>	156:95d6b41a828b	3464	/**
<>	156:95d6b41a828b	3465	* @brief Disable capture/compare 4 interrupt (CC4IE).
<>	156:95d6b41a828b	3466	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
<>	156:95d6b41a828b	3467	* @param TIMx Timer instance
<>	156:95d6b41a828b	3468	* @retval None
<>	156:95d6b41a828b	3469	*/
<>	156:95d6b41a828b	3470	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3471	{
<>	156:95d6b41a828b	3472	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
<>	156:95d6b41a828b	3473	}
<>	156:95d6b41a828b	3474
<>	156:95d6b41a828b	3475	/**
<>	156:95d6b41a828b	3476	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
<>	156:95d6b41a828b	3477	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
<>	156:95d6b41a828b	3478	* @param TIMx Timer instance
<>	156:95d6b41a828b	3479	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3480	*/
<>	156:95d6b41a828b	3481	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3482	{
<>	156:95d6b41a828b	3483	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
<>	156:95d6b41a828b	3484	}
<>	156:95d6b41a828b	3485
<>	156:95d6b41a828b	3486	/**
<>	156:95d6b41a828b	3487	* @brief Enable commutation interrupt (COMIE).
<>	156:95d6b41a828b	3488	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
<>	156:95d6b41a828b	3489	* @param TIMx Timer instance
<>	156:95d6b41a828b	3490	* @retval None
<>	156:95d6b41a828b	3491	*/
<>	156:95d6b41a828b	3492	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3493	{
<>	156:95d6b41a828b	3494	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
<>	156:95d6b41a828b	3495	}
<>	156:95d6b41a828b	3496
<>	156:95d6b41a828b	3497	/**
<>	156:95d6b41a828b	3498	* @brief Disable commutation interrupt (COMIE).
<>	156:95d6b41a828b	3499	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
<>	156:95d6b41a828b	3500	* @param TIMx Timer instance
<>	156:95d6b41a828b	3501	* @retval None
<>	156:95d6b41a828b	3502	*/
<>	156:95d6b41a828b	3503	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3504	{
<>	156:95d6b41a828b	3505	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
<>	156:95d6b41a828b	3506	}
<>	156:95d6b41a828b	3507
<>	156:95d6b41a828b	3508	/**
<>	156:95d6b41a828b	3509	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
<>	156:95d6b41a828b	3510	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
<>	156:95d6b41a828b	3511	* @param TIMx Timer instance
<>	156:95d6b41a828b	3512	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3513	*/
<>	156:95d6b41a828b	3514	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3515	{
<>	156:95d6b41a828b	3516	return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
<>	156:95d6b41a828b	3517	}
<>	156:95d6b41a828b	3518
<>	156:95d6b41a828b	3519	/**
<>	156:95d6b41a828b	3520	* @brief Enable trigger interrupt (TIE).
<>	156:95d6b41a828b	3521	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
<>	156:95d6b41a828b	3522	* @param TIMx Timer instance
<>	156:95d6b41a828b	3523	* @retval None
<>	156:95d6b41a828b	3524	*/
<>	156:95d6b41a828b	3525	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3526	{
<>	156:95d6b41a828b	3527	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
<>	156:95d6b41a828b	3528	}
<>	156:95d6b41a828b	3529
<>	156:95d6b41a828b	3530	/**
<>	156:95d6b41a828b	3531	* @brief Disable trigger interrupt (TIE).
<>	156:95d6b41a828b	3532	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
<>	156:95d6b41a828b	3533	* @param TIMx Timer instance
<>	156:95d6b41a828b	3534	* @retval None
<>	156:95d6b41a828b	3535	*/
<>	156:95d6b41a828b	3536	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3537	{
<>	156:95d6b41a828b	3538	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
<>	156:95d6b41a828b	3539	}
<>	156:95d6b41a828b	3540
<>	156:95d6b41a828b	3541	/**
<>	156:95d6b41a828b	3542	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
<>	156:95d6b41a828b	3543	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
<>	156:95d6b41a828b	3544	* @param TIMx Timer instance
<>	156:95d6b41a828b	3545	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3546	*/
<>	156:95d6b41a828b	3547	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3548	{
<>	156:95d6b41a828b	3549	return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
<>	156:95d6b41a828b	3550	}
<>	156:95d6b41a828b	3551
<>	156:95d6b41a828b	3552	/**
<>	156:95d6b41a828b	3553	* @brief Enable break interrupt (BIE).
<>	156:95d6b41a828b	3554	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
<>	156:95d6b41a828b	3555	* @param TIMx Timer instance
<>	156:95d6b41a828b	3556	* @retval None
<>	156:95d6b41a828b	3557	*/
<>	156:95d6b41a828b	3558	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3559	{
<>	156:95d6b41a828b	3560	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
<>	156:95d6b41a828b	3561	}
<>	156:95d6b41a828b	3562
<>	156:95d6b41a828b	3563	/**
<>	156:95d6b41a828b	3564	* @brief Disable break interrupt (BIE).
<>	156:95d6b41a828b	3565	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
<>	156:95d6b41a828b	3566	* @param TIMx Timer instance
<>	156:95d6b41a828b	3567	* @retval None
<>	156:95d6b41a828b	3568	*/
<>	156:95d6b41a828b	3569	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3570	{
<>	156:95d6b41a828b	3571	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
<>	156:95d6b41a828b	3572	}
<>	156:95d6b41a828b	3573
<>	156:95d6b41a828b	3574	/**
<>	156:95d6b41a828b	3575	* @brief Indicates whether the break interrupt (BIE) is enabled.
<>	156:95d6b41a828b	3576	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
<>	156:95d6b41a828b	3577	* @param TIMx Timer instance
<>	156:95d6b41a828b	3578	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3579	*/
<>	156:95d6b41a828b	3580	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3581	{
<>	156:95d6b41a828b	3582	return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
<>	156:95d6b41a828b	3583	}
<>	156:95d6b41a828b	3584
<>	156:95d6b41a828b	3585	/**
<>	156:95d6b41a828b	3586	* @}
<>	156:95d6b41a828b	3587	*/
<>	156:95d6b41a828b	3588
<>	156:95d6b41a828b	3589	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
<>	156:95d6b41a828b	3590	* @{
<>	156:95d6b41a828b	3591	*/
<>	156:95d6b41a828b	3592	/**
<>	156:95d6b41a828b	3593	* @brief Enable update DMA request (UDE).
<>	156:95d6b41a828b	3594	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
<>	156:95d6b41a828b	3595	* @param TIMx Timer instance
<>	156:95d6b41a828b	3596	* @retval None
<>	156:95d6b41a828b	3597	*/
<>	156:95d6b41a828b	3598	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3599	{
<>	156:95d6b41a828b	3600	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
<>	156:95d6b41a828b	3601	}
<>	156:95d6b41a828b	3602
<>	156:95d6b41a828b	3603	/**
<>	156:95d6b41a828b	3604	* @brief Disable update DMA request (UDE).
<>	156:95d6b41a828b	3605	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
<>	156:95d6b41a828b	3606	* @param TIMx Timer instance
<>	156:95d6b41a828b	3607	* @retval None
<>	156:95d6b41a828b	3608	*/
<>	156:95d6b41a828b	3609	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3610	{
<>	156:95d6b41a828b	3611	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
<>	156:95d6b41a828b	3612	}
<>	156:95d6b41a828b	3613
<>	156:95d6b41a828b	3614	/**
<>	156:95d6b41a828b	3615	* @brief Indicates whether the update DMA request (UDE) is enabled.
<>	156:95d6b41a828b	3616	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
<>	156:95d6b41a828b	3617	* @param TIMx Timer instance
<>	156:95d6b41a828b	3618	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3619	*/
<>	156:95d6b41a828b	3620	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3621	{
<>	156:95d6b41a828b	3622	return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
<>	156:95d6b41a828b	3623	}
<>	156:95d6b41a828b	3624
<>	156:95d6b41a828b	3625	/**
<>	156:95d6b41a828b	3626	* @brief Enable capture/compare 1 DMA request (CC1DE).
<>	156:95d6b41a828b	3627	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
<>	156:95d6b41a828b	3628	* @param TIMx Timer instance
<>	156:95d6b41a828b	3629	* @retval None
<>	156:95d6b41a828b	3630	*/
<>	156:95d6b41a828b	3631	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3632	{
<>	156:95d6b41a828b	3633	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
<>	156:95d6b41a828b	3634	}
<>	156:95d6b41a828b	3635
<>	156:95d6b41a828b	3636	/**
<>	156:95d6b41a828b	3637	* @brief Disable capture/compare 1 DMA request (CC1DE).
<>	156:95d6b41a828b	3638	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
<>	156:95d6b41a828b	3639	* @param TIMx Timer instance
<>	156:95d6b41a828b	3640	* @retval None
<>	156:95d6b41a828b	3641	*/
<>	156:95d6b41a828b	3642	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3643	{
<>	156:95d6b41a828b	3644	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
<>	156:95d6b41a828b	3645	}
<>	156:95d6b41a828b	3646
<>	156:95d6b41a828b	3647	/**
<>	156:95d6b41a828b	3648	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
<>	156:95d6b41a828b	3649	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
<>	156:95d6b41a828b	3650	* @param TIMx Timer instance
<>	156:95d6b41a828b	3651	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3652	*/
<>	156:95d6b41a828b	3653	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3654	{
<>	156:95d6b41a828b	3655	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
<>	156:95d6b41a828b	3656	}
<>	156:95d6b41a828b	3657
<>	156:95d6b41a828b	3658	/**
<>	156:95d6b41a828b	3659	* @brief Enable capture/compare 2 DMA request (CC2DE).
<>	156:95d6b41a828b	3660	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
<>	156:95d6b41a828b	3661	* @param TIMx Timer instance
<>	156:95d6b41a828b	3662	* @retval None
<>	156:95d6b41a828b	3663	*/
<>	156:95d6b41a828b	3664	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3665	{
<>	156:95d6b41a828b	3666	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
<>	156:95d6b41a828b	3667	}
<>	156:95d6b41a828b	3668
<>	156:95d6b41a828b	3669	/**
<>	156:95d6b41a828b	3670	* @brief Disable capture/compare 2 DMA request (CC2DE).
<>	156:95d6b41a828b	3671	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
<>	156:95d6b41a828b	3672	* @param TIMx Timer instance
<>	156:95d6b41a828b	3673	* @retval None
<>	156:95d6b41a828b	3674	*/
<>	156:95d6b41a828b	3675	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3676	{
<>	156:95d6b41a828b	3677	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
<>	156:95d6b41a828b	3678	}
<>	156:95d6b41a828b	3679
<>	156:95d6b41a828b	3680	/**
<>	156:95d6b41a828b	3681	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
<>	156:95d6b41a828b	3682	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
<>	156:95d6b41a828b	3683	* @param TIMx Timer instance
<>	156:95d6b41a828b	3684	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3685	*/
<>	156:95d6b41a828b	3686	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3687	{
<>	156:95d6b41a828b	3688	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
<>	156:95d6b41a828b	3689	}
<>	156:95d6b41a828b	3690
<>	156:95d6b41a828b	3691	/**
<>	156:95d6b41a828b	3692	* @brief Enable capture/compare 3 DMA request (CC3DE).
<>	156:95d6b41a828b	3693	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
<>	156:95d6b41a828b	3694	* @param TIMx Timer instance
<>	156:95d6b41a828b	3695	* @retval None
<>	156:95d6b41a828b	3696	*/
<>	156:95d6b41a828b	3697	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3698	{
<>	156:95d6b41a828b	3699	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
<>	156:95d6b41a828b	3700	}
<>	156:95d6b41a828b	3701
<>	156:95d6b41a828b	3702	/**
<>	156:95d6b41a828b	3703	* @brief Disable capture/compare 3 DMA request (CC3DE).
<>	156:95d6b41a828b	3704	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
<>	156:95d6b41a828b	3705	* @param TIMx Timer instance
<>	156:95d6b41a828b	3706	* @retval None
<>	156:95d6b41a828b	3707	*/
<>	156:95d6b41a828b	3708	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3709	{
<>	156:95d6b41a828b	3710	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
<>	156:95d6b41a828b	3711	}
<>	156:95d6b41a828b	3712
<>	156:95d6b41a828b	3713	/**
<>	156:95d6b41a828b	3714	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
<>	156:95d6b41a828b	3715	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
<>	156:95d6b41a828b	3716	* @param TIMx Timer instance
<>	156:95d6b41a828b	3717	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3718	*/
<>	156:95d6b41a828b	3719	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3720	{
<>	156:95d6b41a828b	3721	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
<>	156:95d6b41a828b	3722	}
<>	156:95d6b41a828b	3723
<>	156:95d6b41a828b	3724	/**
<>	156:95d6b41a828b	3725	* @brief Enable capture/compare 4 DMA request (CC4DE).
<>	156:95d6b41a828b	3726	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
<>	156:95d6b41a828b	3727	* @param TIMx Timer instance
<>	156:95d6b41a828b	3728	* @retval None
<>	156:95d6b41a828b	3729	*/
<>	156:95d6b41a828b	3730	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3731	{
<>	156:95d6b41a828b	3732	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
<>	156:95d6b41a828b	3733	}
<>	156:95d6b41a828b	3734
<>	156:95d6b41a828b	3735	/**
<>	156:95d6b41a828b	3736	* @brief Disable capture/compare 4 DMA request (CC4DE).
<>	156:95d6b41a828b	3737	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
<>	156:95d6b41a828b	3738	* @param TIMx Timer instance
<>	156:95d6b41a828b	3739	* @retval None
<>	156:95d6b41a828b	3740	*/
<>	156:95d6b41a828b	3741	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3742	{
<>	156:95d6b41a828b	3743	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
<>	156:95d6b41a828b	3744	}
<>	156:95d6b41a828b	3745
<>	156:95d6b41a828b	3746	/**
<>	156:95d6b41a828b	3747	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
<>	156:95d6b41a828b	3748	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
<>	156:95d6b41a828b	3749	* @param TIMx Timer instance
<>	156:95d6b41a828b	3750	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3751	*/
<>	156:95d6b41a828b	3752	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3753	{
<>	156:95d6b41a828b	3754	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
<>	156:95d6b41a828b	3755	}
<>	156:95d6b41a828b	3756
<>	156:95d6b41a828b	3757	/**
<>	156:95d6b41a828b	3758	* @brief Enable commutation DMA request (COMDE).
<>	156:95d6b41a828b	3759	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
<>	156:95d6b41a828b	3760	* @param TIMx Timer instance
<>	156:95d6b41a828b	3761	* @retval None
<>	156:95d6b41a828b	3762	*/
<>	156:95d6b41a828b	3763	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3764	{
<>	156:95d6b41a828b	3765	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
<>	156:95d6b41a828b	3766	}
<>	156:95d6b41a828b	3767
<>	156:95d6b41a828b	3768	/**
<>	156:95d6b41a828b	3769	* @brief Disable commutation DMA request (COMDE).
<>	156:95d6b41a828b	3770	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
<>	156:95d6b41a828b	3771	* @param TIMx Timer instance
<>	156:95d6b41a828b	3772	* @retval None
<>	156:95d6b41a828b	3773	*/
<>	156:95d6b41a828b	3774	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3775	{
<>	156:95d6b41a828b	3776	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
<>	156:95d6b41a828b	3777	}
<>	156:95d6b41a828b	3778
<>	156:95d6b41a828b	3779	/**
<>	156:95d6b41a828b	3780	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
<>	156:95d6b41a828b	3781	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
<>	156:95d6b41a828b	3782	* @param TIMx Timer instance
<>	156:95d6b41a828b	3783	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3784	*/
<>	156:95d6b41a828b	3785	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3786	{
<>	156:95d6b41a828b	3787	return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
<>	156:95d6b41a828b	3788	}
<>	156:95d6b41a828b	3789
<>	156:95d6b41a828b	3790	/**
<>	156:95d6b41a828b	3791	* @brief Enable trigger interrupt (TDE).
<>	156:95d6b41a828b	3792	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
<>	156:95d6b41a828b	3793	* @param TIMx Timer instance
<>	156:95d6b41a828b	3794	* @retval None
<>	156:95d6b41a828b	3795	*/
<>	156:95d6b41a828b	3796	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3797	{
<>	156:95d6b41a828b	3798	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
<>	156:95d6b41a828b	3799	}
<>	156:95d6b41a828b	3800
<>	156:95d6b41a828b	3801	/**
<>	156:95d6b41a828b	3802	* @brief Disable trigger interrupt (TDE).
<>	156:95d6b41a828b	3803	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
<>	156:95d6b41a828b	3804	* @param TIMx Timer instance
<>	156:95d6b41a828b	3805	* @retval None
<>	156:95d6b41a828b	3806	*/
<>	156:95d6b41a828b	3807	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3808	{
<>	156:95d6b41a828b	3809	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
<>	156:95d6b41a828b	3810	}
<>	156:95d6b41a828b	3811
<>	156:95d6b41a828b	3812	/**
<>	156:95d6b41a828b	3813	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
<>	156:95d6b41a828b	3814	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
<>	156:95d6b41a828b	3815	* @param TIMx Timer instance
<>	156:95d6b41a828b	3816	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3817	*/
<>	156:95d6b41a828b	3818	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3819	{
<>	156:95d6b41a828b	3820	return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
<>	156:95d6b41a828b	3821	}
<>	156:95d6b41a828b	3822
<>	156:95d6b41a828b	3823	/**
<>	156:95d6b41a828b	3824	* @}
<>	156:95d6b41a828b	3825	*/
<>	156:95d6b41a828b	3826
<>	156:95d6b41a828b	3827	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
<>	156:95d6b41a828b	3828	* @{
<>	156:95d6b41a828b	3829	*/
<>	156:95d6b41a828b	3830	/**
<>	156:95d6b41a828b	3831	* @brief Generate an update event.
<>	156:95d6b41a828b	3832	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
<>	156:95d6b41a828b	3833	* @param TIMx Timer instance
<>	156:95d6b41a828b	3834	* @retval None
<>	156:95d6b41a828b	3835	*/
<>	156:95d6b41a828b	3836	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3837	{
<>	156:95d6b41a828b	3838	SET_BIT(TIMx->EGR, TIM_EGR_UG);
<>	156:95d6b41a828b	3839	}
<>	156:95d6b41a828b	3840
<>	156:95d6b41a828b	3841	/**
<>	156:95d6b41a828b	3842	* @brief Generate Capture/Compare 1 event.
<>	156:95d6b41a828b	3843	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
<>	156:95d6b41a828b	3844	* @param TIMx Timer instance
<>	156:95d6b41a828b	3845	* @retval None
<>	156:95d6b41a828b	3846	*/
<>	156:95d6b41a828b	3847	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3848	{
<>	156:95d6b41a828b	3849	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
<>	156:95d6b41a828b	3850	}
<>	156:95d6b41a828b	3851
<>	156:95d6b41a828b	3852	/**
<>	156:95d6b41a828b	3853	* @brief Generate Capture/Compare 2 event.
<>	156:95d6b41a828b	3854	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
<>	156:95d6b41a828b	3855	* @param TIMx Timer instance
<>	156:95d6b41a828b	3856	* @retval None
<>	156:95d6b41a828b	3857	*/
<>	156:95d6b41a828b	3858	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3859	{
<>	156:95d6b41a828b	3860	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
<>	156:95d6b41a828b	3861	}
<>	156:95d6b41a828b	3862
<>	156:95d6b41a828b	3863	/**
<>	156:95d6b41a828b	3864	* @brief Generate Capture/Compare 3 event.
<>	156:95d6b41a828b	3865	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
<>	156:95d6b41a828b	3866	* @param TIMx Timer instance
<>	156:95d6b41a828b	3867	* @retval None
<>	156:95d6b41a828b	3868	*/
<>	156:95d6b41a828b	3869	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3870	{
<>	156:95d6b41a828b	3871	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
<>	156:95d6b41a828b	3872	}
<>	156:95d6b41a828b	3873
<>	156:95d6b41a828b	3874	/**
<>	156:95d6b41a828b	3875	* @brief Generate Capture/Compare 4 event.
<>	156:95d6b41a828b	3876	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
<>	156:95d6b41a828b	3877	* @param TIMx Timer instance
<>	156:95d6b41a828b	3878	* @retval None
<>	156:95d6b41a828b	3879	*/
<>	156:95d6b41a828b	3880	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3881	{
<>	156:95d6b41a828b	3882	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
<>	156:95d6b41a828b	3883	}
<>	156:95d6b41a828b	3884
<>	156:95d6b41a828b	3885	/**
<>	156:95d6b41a828b	3886	* @brief Generate commutation event.
<>	156:95d6b41a828b	3887	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
<>	156:95d6b41a828b	3888	* @param TIMx Timer instance
<>	156:95d6b41a828b	3889	* @retval None
<>	156:95d6b41a828b	3890	*/
<>	156:95d6b41a828b	3891	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3892	{
<>	156:95d6b41a828b	3893	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
<>	156:95d6b41a828b	3894	}
<>	156:95d6b41a828b	3895
<>	156:95d6b41a828b	3896	/**
<>	156:95d6b41a828b	3897	* @brief Generate trigger event.
<>	156:95d6b41a828b	3898	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
<>	156:95d6b41a828b	3899	* @param TIMx Timer instance
<>	156:95d6b41a828b	3900	* @retval None
<>	156:95d6b41a828b	3901	*/
<>	156:95d6b41a828b	3902	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3903	{
<>	156:95d6b41a828b	3904	SET_BIT(TIMx->EGR, TIM_EGR_TG);
<>	156:95d6b41a828b	3905	}
<>	156:95d6b41a828b	3906
<>	156:95d6b41a828b	3907	/**
<>	156:95d6b41a828b	3908	* @brief Generate break event.
<>	156:95d6b41a828b	3909	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
<>	156:95d6b41a828b	3910	* @param TIMx Timer instance
<>	156:95d6b41a828b	3911	* @retval None
<>	156:95d6b41a828b	3912	*/
<>	156:95d6b41a828b	3913	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
<>	156:95d6b41a828b	3914	{
<>	156:95d6b41a828b	3915	SET_BIT(TIMx->EGR, TIM_EGR_BG);
<>	156:95d6b41a828b	3916	}
<>	156:95d6b41a828b	3917
<>	156:95d6b41a828b	3918	/**
<>	156:95d6b41a828b	3919	* @}
<>	156:95d6b41a828b	3920	*/
<>	156:95d6b41a828b	3921
<>	156:95d6b41a828b	3922	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	3923	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
<>	156:95d6b41a828b	3924	* @{
<>	156:95d6b41a828b	3925	*/
<>	156:95d6b41a828b	3926
<>	156:95d6b41a828b	3927	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
<>	156:95d6b41a828b	3928	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
<>	156:95d6b41a828b	3929	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
<>	156:95d6b41a828b	3930	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
<>	156:95d6b41a828b	3931	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
<>	156:95d6b41a828b	3932	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
<>	156:95d6b41a828b	3933	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
<>	156:95d6b41a828b	3934	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
<>	156:95d6b41a828b	3935	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
<>	156:95d6b41a828b	3936	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
<>	156:95d6b41a828b	3937	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
Anna Bridge	180:96ed750bd169	3938	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
Anna Bridge	180:96ed750bd169	3939	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
<>	156:95d6b41a828b	3940	/**
<>	156:95d6b41a828b	3941	* @}
<>	156:95d6b41a828b	3942	*/
<>	156:95d6b41a828b	3943	#endif /* USE_FULL_LL_DRIVER */
<>	156:95d6b41a828b	3944
<>	156:95d6b41a828b	3945	/**
<>	156:95d6b41a828b	3946	* @}
<>	156:95d6b41a828b	3947	*/
<>	156:95d6b41a828b	3948
<>	156:95d6b41a828b	3949	/**
<>	156:95d6b41a828b	3950	* @}
<>	156:95d6b41a828b	3951	*/
<>	156:95d6b41a828b	3952
<>	156:95d6b41a828b	3953	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM14 \|\| TIM15 \|\| TIM16 \|\| TIM17 \|\| TIM6 \|\| TIM7 */
<>	156:95d6b41a828b	3954
<>	156:95d6b41a828b	3955	/**
<>	156:95d6b41a828b	3956	* @}
<>	156:95d6b41a828b	3957	*/
<>	156:95d6b41a828b	3958
<>	156:95d6b41a828b	3959	#ifdef __cplusplus
<>	156:95d6b41a828b	3960	}
<>	156:95d6b41a828b	3961	#endif
<>	156:95d6b41a828b	3962
<>	156:95d6b41a828b	3963	#endif /* __STM32F0xx_LL_TIM_H */
<>	156:95d6b41a828b	3964	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/