mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 180:96ed750bd169
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 156:95d6b41a828b | 1 | /** |
<> | 156:95d6b41a828b | 2 | ****************************************************************************** |
<> | 156:95d6b41a828b | 3 | * @file stm32f0xx_ll_pwr.h |
<> | 156:95d6b41a828b | 4 | * @author MCD Application Team |
<> | 156:95d6b41a828b | 5 | * @brief Header file of PWR LL module. |
<> | 156:95d6b41a828b | 6 | ****************************************************************************** |
<> | 156:95d6b41a828b | 7 | * @attention |
<> | 156:95d6b41a828b | 8 | * |
<> | 156:95d6b41a828b | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 156:95d6b41a828b | 10 | * |
<> | 156:95d6b41a828b | 11 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 156:95d6b41a828b | 12 | * are permitted provided that the following conditions are met: |
<> | 156:95d6b41a828b | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 156:95d6b41a828b | 14 | * this list of conditions and the following disclaimer. |
<> | 156:95d6b41a828b | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 156:95d6b41a828b | 16 | * this list of conditions and the following disclaimer in the documentation |
<> | 156:95d6b41a828b | 17 | * and/or other materials provided with the distribution. |
<> | 156:95d6b41a828b | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 156:95d6b41a828b | 19 | * may be used to endorse or promote products derived from this software |
<> | 156:95d6b41a828b | 20 | * without specific prior written permission. |
<> | 156:95d6b41a828b | 21 | * |
<> | 156:95d6b41a828b | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 156:95d6b41a828b | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 156:95d6b41a828b | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 156:95d6b41a828b | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 156:95d6b41a828b | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 156:95d6b41a828b | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 156:95d6b41a828b | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 156:95d6b41a828b | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 156:95d6b41a828b | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 156:95d6b41a828b | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 156:95d6b41a828b | 32 | * |
<> | 156:95d6b41a828b | 33 | ****************************************************************************** |
<> | 156:95d6b41a828b | 34 | */ |
<> | 156:95d6b41a828b | 35 | |
<> | 156:95d6b41a828b | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
<> | 156:95d6b41a828b | 37 | #ifndef __STM32F0xx_LL_PWR_H |
<> | 156:95d6b41a828b | 38 | #define __STM32F0xx_LL_PWR_H |
<> | 156:95d6b41a828b | 39 | |
<> | 156:95d6b41a828b | 40 | #ifdef __cplusplus |
<> | 156:95d6b41a828b | 41 | extern "C" { |
<> | 156:95d6b41a828b | 42 | #endif |
<> | 156:95d6b41a828b | 43 | |
<> | 156:95d6b41a828b | 44 | /* Includes ------------------------------------------------------------------*/ |
<> | 156:95d6b41a828b | 45 | #include "stm32f0xx.h" |
<> | 156:95d6b41a828b | 46 | |
<> | 156:95d6b41a828b | 47 | /** @addtogroup STM32F0xx_LL_Driver |
<> | 156:95d6b41a828b | 48 | * @{ |
<> | 156:95d6b41a828b | 49 | */ |
<> | 156:95d6b41a828b | 50 | |
<> | 156:95d6b41a828b | 51 | #if defined(PWR) |
<> | 156:95d6b41a828b | 52 | |
<> | 156:95d6b41a828b | 53 | /** @defgroup PWR_LL PWR |
<> | 156:95d6b41a828b | 54 | * @{ |
<> | 156:95d6b41a828b | 55 | */ |
<> | 156:95d6b41a828b | 56 | |
<> | 156:95d6b41a828b | 57 | /* Private types -------------------------------------------------------------*/ |
<> | 156:95d6b41a828b | 58 | /* Private variables ---------------------------------------------------------*/ |
<> | 156:95d6b41a828b | 59 | /* Private constants ---------------------------------------------------------*/ |
<> | 156:95d6b41a828b | 60 | /* Private macros ------------------------------------------------------------*/ |
<> | 156:95d6b41a828b | 61 | /* Exported types ------------------------------------------------------------*/ |
<> | 156:95d6b41a828b | 62 | /* Exported constants --------------------------------------------------------*/ |
<> | 156:95d6b41a828b | 63 | /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants |
<> | 156:95d6b41a828b | 64 | * @{ |
<> | 156:95d6b41a828b | 65 | */ |
<> | 156:95d6b41a828b | 66 | |
<> | 156:95d6b41a828b | 67 | /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines |
<> | 156:95d6b41a828b | 68 | * @brief Flags defines which can be used with LL_PWR_WriteReg function |
<> | 156:95d6b41a828b | 69 | * @{ |
<> | 156:95d6b41a828b | 70 | */ |
<> | 156:95d6b41a828b | 71 | #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ |
<> | 156:95d6b41a828b | 72 | #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ |
<> | 156:95d6b41a828b | 73 | /** |
<> | 156:95d6b41a828b | 74 | * @} |
<> | 156:95d6b41a828b | 75 | */ |
<> | 156:95d6b41a828b | 76 | |
<> | 156:95d6b41a828b | 77 | /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines |
<> | 156:95d6b41a828b | 78 | * @brief Flags defines which can be used with LL_PWR_ReadReg function |
<> | 156:95d6b41a828b | 79 | * @{ |
<> | 156:95d6b41a828b | 80 | */ |
<> | 156:95d6b41a828b | 81 | #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ |
<> | 156:95d6b41a828b | 82 | #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ |
Anna Bridge |
180:96ed750bd169 | 83 | #if defined(PWR_PVD_SUPPORT) |
<> | 156:95d6b41a828b | 84 | #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ |
Anna Bridge |
180:96ed750bd169 | 85 | #endif /* PWR_PVD_SUPPORT */ |
Anna Bridge |
180:96ed750bd169 | 86 | #if defined(PWR_CSR_VREFINTRDYF) |
<> | 156:95d6b41a828b | 87 | #define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */ |
Anna Bridge |
180:96ed750bd169 | 88 | #endif /* PWR_CSR_VREFINTRDYF */ |
<> | 156:95d6b41a828b | 89 | #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ |
<> | 156:95d6b41a828b | 90 | #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ |
Anna Bridge |
180:96ed750bd169 | 91 | #if defined(PWR_CSR_EWUP3) |
<> | 156:95d6b41a828b | 92 | #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ |
<> | 156:95d6b41a828b | 93 | #endif /* PWR_CSR_EWUP3 */ |
Anna Bridge |
180:96ed750bd169 | 94 | #if defined(PWR_CSR_EWUP4) |
<> | 156:95d6b41a828b | 95 | #define LL_PWR_CSR_EWUP4 PWR_CSR_EWUP4 /*!< Enable WKUP pin 4 */ |
<> | 156:95d6b41a828b | 96 | #endif /* PWR_CSR_EWUP4 */ |
Anna Bridge |
180:96ed750bd169 | 97 | #if defined(PWR_CSR_EWUP5) |
<> | 156:95d6b41a828b | 98 | #define LL_PWR_CSR_EWUP5 PWR_CSR_EWUP5 /*!< Enable WKUP pin 5 */ |
<> | 156:95d6b41a828b | 99 | #endif /* PWR_CSR_EWUP5 */ |
Anna Bridge |
180:96ed750bd169 | 100 | #if defined(PWR_CSR_EWUP6) |
<> | 156:95d6b41a828b | 101 | #define LL_PWR_CSR_EWUP6 PWR_CSR_EWUP6 /*!< Enable WKUP pin 6 */ |
<> | 156:95d6b41a828b | 102 | #endif /* PWR_CSR_EWUP6 */ |
Anna Bridge |
180:96ed750bd169 | 103 | #if defined(PWR_CSR_EWUP7) |
<> | 156:95d6b41a828b | 104 | #define LL_PWR_CSR_EWUP7 PWR_CSR_EWUP7 /*!< Enable WKUP pin 7 */ |
<> | 156:95d6b41a828b | 105 | #endif /* PWR_CSR_EWUP7 */ |
Anna Bridge |
180:96ed750bd169 | 106 | #if defined(PWR_CSR_EWUP8) |
<> | 156:95d6b41a828b | 107 | #define LL_PWR_CSR_EWUP8 PWR_CSR_EWUP8 /*!< Enable WKUP pin 8 */ |
<> | 156:95d6b41a828b | 108 | #endif /* PWR_CSR_EWUP8 */ |
<> | 156:95d6b41a828b | 109 | /** |
<> | 156:95d6b41a828b | 110 | * @} |
<> | 156:95d6b41a828b | 111 | */ |
<> | 156:95d6b41a828b | 112 | |
<> | 156:95d6b41a828b | 113 | |
<> | 156:95d6b41a828b | 114 | /** @defgroup PWR_LL_EC_MODE_PWR Mode Power |
<> | 156:95d6b41a828b | 115 | * @{ |
<> | 156:95d6b41a828b | 116 | */ |
Anna Bridge |
180:96ed750bd169 | 117 | #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ |
Anna Bridge |
180:96ed750bd169 | 118 | #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ |
Anna Bridge |
180:96ed750bd169 | 119 | #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ |
<> | 156:95d6b41a828b | 120 | /** |
<> | 156:95d6b41a828b | 121 | * @} |
<> | 156:95d6b41a828b | 122 | */ |
<> | 156:95d6b41a828b | 123 | |
<> | 156:95d6b41a828b | 124 | #if defined(PWR_CR_LPDS) |
<> | 156:95d6b41a828b | 125 | /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode |
<> | 156:95d6b41a828b | 126 | * @{ |
<> | 156:95d6b41a828b | 127 | */ |
Anna Bridge |
180:96ed750bd169 | 128 | #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ |
Anna Bridge |
180:96ed750bd169 | 129 | #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ |
<> | 156:95d6b41a828b | 130 | /** |
Anna Bridge |
180:96ed750bd169 | 131 | * @} |
Anna Bridge |
180:96ed750bd169 | 132 | */ |
<> | 156:95d6b41a828b | 133 | #endif /* PWR_CR_LPDS */ |
<> | 156:95d6b41a828b | 134 | |
Anna Bridge |
180:96ed750bd169 | 135 | #if defined(PWR_PVD_SUPPORT) |
<> | 156:95d6b41a828b | 136 | /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level |
<> | 156:95d6b41a828b | 137 | * @{ |
<> | 156:95d6b41a828b | 138 | */ |
<> | 156:95d6b41a828b | 139 | #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold 0 */ |
<> | 156:95d6b41a828b | 140 | #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold 1 */ |
<> | 156:95d6b41a828b | 141 | #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold 2 */ |
<> | 156:95d6b41a828b | 142 | #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold 3 */ |
<> | 156:95d6b41a828b | 143 | #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold 4 */ |
<> | 156:95d6b41a828b | 144 | #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold 5 */ |
<> | 156:95d6b41a828b | 145 | #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold 6 */ |
<> | 156:95d6b41a828b | 146 | #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold 7 */ |
<> | 156:95d6b41a828b | 147 | /** |
<> | 156:95d6b41a828b | 148 | * @} |
<> | 156:95d6b41a828b | 149 | */ |
Anna Bridge |
180:96ed750bd169 | 150 | #endif /* PWR_PVD_SUPPORT */ |
<> | 156:95d6b41a828b | 151 | /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins |
Anna Bridge |
180:96ed750bd169 | 152 | * @{ |
Anna Bridge |
180:96ed750bd169 | 153 | */ |
<> | 156:95d6b41a828b | 154 | #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ |
<> | 156:95d6b41a828b | 155 | #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */ |
Anna Bridge |
180:96ed750bd169 | 156 | #if defined(PWR_CSR_EWUP3) |
<> | 156:95d6b41a828b | 157 | #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */ |
<> | 156:95d6b41a828b | 158 | #endif /* PWR_CSR_EWUP3 */ |
Anna Bridge |
180:96ed750bd169 | 159 | #if defined(PWR_CSR_EWUP4) |
<> | 156:95d6b41a828b | 160 | #define LL_PWR_WAKEUP_PIN4 (PWR_CSR_EWUP4) /*!< WKUP pin 4 : LLG TBD */ |
<> | 156:95d6b41a828b | 161 | #endif /* PWR_CSR_EWUP4 */ |
Anna Bridge |
180:96ed750bd169 | 162 | #if defined(PWR_CSR_EWUP5) |
<> | 156:95d6b41a828b | 163 | #define LL_PWR_WAKEUP_PIN5 (PWR_CSR_EWUP5) /*!< WKUP pin 5 : LLG TBD */ |
<> | 156:95d6b41a828b | 164 | #endif /* PWR_CSR_EWUP5 */ |
Anna Bridge |
180:96ed750bd169 | 165 | #if defined(PWR_CSR_EWUP6) |
<> | 156:95d6b41a828b | 166 | #define LL_PWR_WAKEUP_PIN6 (PWR_CSR_EWUP6) /*!< WKUP pin 6 : LLG TBD */ |
<> | 156:95d6b41a828b | 167 | #endif /* PWR_CSR_EWUP6 */ |
Anna Bridge |
180:96ed750bd169 | 168 | #if defined(PWR_CSR_EWUP7) |
<> | 156:95d6b41a828b | 169 | #define LL_PWR_WAKEUP_PIN7 (PWR_CSR_EWUP7) /*!< WKUP pin 7 : LLG TBD */ |
<> | 156:95d6b41a828b | 170 | #endif /* PWR_CSR_EWUP7 */ |
Anna Bridge |
180:96ed750bd169 | 171 | #if defined(PWR_CSR_EWUP8) |
<> | 156:95d6b41a828b | 172 | #define LL_PWR_WAKEUP_PIN8 (PWR_CSR_EWUP8) /*!< WKUP pin 8 : LLG TBD */ |
<> | 156:95d6b41a828b | 173 | #endif /* PWR_CSR_EWUP8 */ |
<> | 156:95d6b41a828b | 174 | /** |
<> | 156:95d6b41a828b | 175 | * @} |
<> | 156:95d6b41a828b | 176 | */ |
<> | 156:95d6b41a828b | 177 | |
<> | 156:95d6b41a828b | 178 | /** |
<> | 156:95d6b41a828b | 179 | * @} |
<> | 156:95d6b41a828b | 180 | */ |
<> | 156:95d6b41a828b | 181 | |
<> | 156:95d6b41a828b | 182 | |
<> | 156:95d6b41a828b | 183 | /* Exported macro ------------------------------------------------------------*/ |
<> | 156:95d6b41a828b | 184 | /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros |
<> | 156:95d6b41a828b | 185 | * @{ |
<> | 156:95d6b41a828b | 186 | */ |
<> | 156:95d6b41a828b | 187 | |
<> | 156:95d6b41a828b | 188 | /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros |
<> | 156:95d6b41a828b | 189 | * @{ |
<> | 156:95d6b41a828b | 190 | */ |
<> | 156:95d6b41a828b | 191 | |
<> | 156:95d6b41a828b | 192 | /** |
<> | 156:95d6b41a828b | 193 | * @brief Write a value in PWR register |
<> | 156:95d6b41a828b | 194 | * @param __REG__ Register to be written |
<> | 156:95d6b41a828b | 195 | * @param __VALUE__ Value to be written in the register |
<> | 156:95d6b41a828b | 196 | * @retval None |
<> | 156:95d6b41a828b | 197 | */ |
<> | 156:95d6b41a828b | 198 | #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) |
<> | 156:95d6b41a828b | 199 | |
<> | 156:95d6b41a828b | 200 | /** |
<> | 156:95d6b41a828b | 201 | * @brief Read a value in PWR register |
<> | 156:95d6b41a828b | 202 | * @param __REG__ Register to be read |
<> | 156:95d6b41a828b | 203 | * @retval Register value |
<> | 156:95d6b41a828b | 204 | */ |
<> | 156:95d6b41a828b | 205 | #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) |
<> | 156:95d6b41a828b | 206 | /** |
<> | 156:95d6b41a828b | 207 | * @} |
<> | 156:95d6b41a828b | 208 | */ |
<> | 156:95d6b41a828b | 209 | |
<> | 156:95d6b41a828b | 210 | /** |
<> | 156:95d6b41a828b | 211 | * @} |
<> | 156:95d6b41a828b | 212 | */ |
<> | 156:95d6b41a828b | 213 | |
<> | 156:95d6b41a828b | 214 | /* Exported functions --------------------------------------------------------*/ |
<> | 156:95d6b41a828b | 215 | /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions |
<> | 156:95d6b41a828b | 216 | * @{ |
<> | 156:95d6b41a828b | 217 | */ |
<> | 156:95d6b41a828b | 218 | |
<> | 156:95d6b41a828b | 219 | /** @defgroup PWR_LL_EF_Configuration Configuration |
<> | 156:95d6b41a828b | 220 | * @{ |
<> | 156:95d6b41a828b | 221 | */ |
<> | 156:95d6b41a828b | 222 | |
<> | 156:95d6b41a828b | 223 | /** |
<> | 156:95d6b41a828b | 224 | * @brief Enable access to the backup domain |
<> | 156:95d6b41a828b | 225 | * @rmtoll CR DBP LL_PWR_EnableBkUpAccess |
<> | 156:95d6b41a828b | 226 | * @retval None |
<> | 156:95d6b41a828b | 227 | */ |
<> | 156:95d6b41a828b | 228 | __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) |
<> | 156:95d6b41a828b | 229 | { |
<> | 156:95d6b41a828b | 230 | SET_BIT(PWR->CR, PWR_CR_DBP); |
<> | 156:95d6b41a828b | 231 | } |
<> | 156:95d6b41a828b | 232 | |
<> | 156:95d6b41a828b | 233 | /** |
<> | 156:95d6b41a828b | 234 | * @brief Disable access to the backup domain |
<> | 156:95d6b41a828b | 235 | * @rmtoll CR DBP LL_PWR_DisableBkUpAccess |
<> | 156:95d6b41a828b | 236 | * @retval None |
<> | 156:95d6b41a828b | 237 | */ |
<> | 156:95d6b41a828b | 238 | __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) |
<> | 156:95d6b41a828b | 239 | { |
<> | 156:95d6b41a828b | 240 | CLEAR_BIT(PWR->CR, PWR_CR_DBP); |
<> | 156:95d6b41a828b | 241 | } |
<> | 156:95d6b41a828b | 242 | |
<> | 156:95d6b41a828b | 243 | /** |
<> | 156:95d6b41a828b | 244 | * @brief Check if the backup domain is enabled |
<> | 156:95d6b41a828b | 245 | * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess |
<> | 156:95d6b41a828b | 246 | * @retval State of bit (1 or 0). |
<> | 156:95d6b41a828b | 247 | */ |
<> | 156:95d6b41a828b | 248 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) |
<> | 156:95d6b41a828b | 249 | { |
<> | 156:95d6b41a828b | 250 | return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); |
<> | 156:95d6b41a828b | 251 | } |
<> | 156:95d6b41a828b | 252 | |
<> | 156:95d6b41a828b | 253 | #if defined(PWR_CR_LPDS) |
<> | 156:95d6b41a828b | 254 | /** |
Anna Bridge |
180:96ed750bd169 | 255 | * @brief Set voltage Regulator mode during deep sleep mode |
<> | 156:95d6b41a828b | 256 | * @rmtoll CR LPDS LL_PWR_SetRegulModeDS |
<> | 156:95d6b41a828b | 257 | * @param RegulMode This parameter can be one of the following values: |
<> | 156:95d6b41a828b | 258 | * @arg @ref LL_PWR_REGU_DSMODE_MAIN |
<> | 156:95d6b41a828b | 259 | * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER |
<> | 156:95d6b41a828b | 260 | * @retval None |
<> | 156:95d6b41a828b | 261 | */ |
<> | 156:95d6b41a828b | 262 | __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) |
<> | 156:95d6b41a828b | 263 | { |
<> | 156:95d6b41a828b | 264 | MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); |
<> | 156:95d6b41a828b | 265 | } |
<> | 156:95d6b41a828b | 266 | |
<> | 156:95d6b41a828b | 267 | /** |
Anna Bridge |
180:96ed750bd169 | 268 | * @brief Get voltage Regulator mode during deep sleep mode |
<> | 156:95d6b41a828b | 269 | * @rmtoll CR LPDS LL_PWR_GetRegulModeDS |
<> | 156:95d6b41a828b | 270 | * @retval Returned value can be one of the following values: |
<> | 156:95d6b41a828b | 271 | * @arg @ref LL_PWR_REGU_DSMODE_MAIN |
<> | 156:95d6b41a828b | 272 | * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER |
<> | 156:95d6b41a828b | 273 | */ |
<> | 156:95d6b41a828b | 274 | __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) |
<> | 156:95d6b41a828b | 275 | { |
<> | 156:95d6b41a828b | 276 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); |
<> | 156:95d6b41a828b | 277 | } |
<> | 156:95d6b41a828b | 278 | #endif /* PWR_CR_LPDS */ |
<> | 156:95d6b41a828b | 279 | |
<> | 156:95d6b41a828b | 280 | /** |
Anna Bridge |
180:96ed750bd169 | 281 | * @brief Set Power Down mode when CPU enters deepsleep |
<> | 156:95d6b41a828b | 282 | * @rmtoll CR PDDS LL_PWR_SetPowerMode\n |
Anna Bridge |
180:96ed750bd169 | 283 | * @rmtoll CR LPDS LL_PWR_SetPowerMode |
<> | 156:95d6b41a828b | 284 | * @param PDMode This parameter can be one of the following values: |
<> | 156:95d6b41a828b | 285 | * @arg @ref LL_PWR_MODE_STOP_MAINREGU |
<> | 156:95d6b41a828b | 286 | * @arg @ref LL_PWR_MODE_STOP_LPREGU |
<> | 156:95d6b41a828b | 287 | * @arg @ref LL_PWR_MODE_STANDBY |
<> | 156:95d6b41a828b | 288 | * @retval None |
<> | 156:95d6b41a828b | 289 | */ |
<> | 156:95d6b41a828b | 290 | __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) |
<> | 156:95d6b41a828b | 291 | { |
<> | 156:95d6b41a828b | 292 | MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); |
<> | 156:95d6b41a828b | 293 | } |
<> | 156:95d6b41a828b | 294 | |
<> | 156:95d6b41a828b | 295 | /** |
Anna Bridge |
180:96ed750bd169 | 296 | * @brief Get Power Down mode when CPU enters deepsleep |
Anna Bridge |
180:96ed750bd169 | 297 | * @rmtoll CR PDDS LL_PWR_GetPowerMode\n |
Anna Bridge |
180:96ed750bd169 | 298 | * @rmtoll CR LPDS LL_PWR_GetPowerMode |
<> | 156:95d6b41a828b | 299 | * @retval Returned value can be one of the following values: |
<> | 156:95d6b41a828b | 300 | * @arg @ref LL_PWR_MODE_STOP_MAINREGU |
<> | 156:95d6b41a828b | 301 | * @arg @ref LL_PWR_MODE_STOP_LPREGU |
<> | 156:95d6b41a828b | 302 | * @arg @ref LL_PWR_MODE_STANDBY |
<> | 156:95d6b41a828b | 303 | */ |
<> | 156:95d6b41a828b | 304 | __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) |
<> | 156:95d6b41a828b | 305 | { |
<> | 156:95d6b41a828b | 306 | return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); |
<> | 156:95d6b41a828b | 307 | } |
<> | 156:95d6b41a828b | 308 | |
Anna Bridge |
180:96ed750bd169 | 309 | #if defined(PWR_PVD_SUPPORT) |
<> | 156:95d6b41a828b | 310 | /** |
<> | 156:95d6b41a828b | 311 | * @brief Configure the voltage threshold detected by the Power Voltage Detector |
<> | 156:95d6b41a828b | 312 | * @rmtoll CR PLS LL_PWR_SetPVDLevel |
<> | 156:95d6b41a828b | 313 | * @param PVDLevel This parameter can be one of the following values: |
<> | 156:95d6b41a828b | 314 | * @arg @ref LL_PWR_PVDLEVEL_0 |
<> | 156:95d6b41a828b | 315 | * @arg @ref LL_PWR_PVDLEVEL_1 |
<> | 156:95d6b41a828b | 316 | * @arg @ref LL_PWR_PVDLEVEL_2 |
<> | 156:95d6b41a828b | 317 | * @arg @ref LL_PWR_PVDLEVEL_3 |
<> | 156:95d6b41a828b | 318 | * @arg @ref LL_PWR_PVDLEVEL_4 |
<> | 156:95d6b41a828b | 319 | * @arg @ref LL_PWR_PVDLEVEL_5 |
<> | 156:95d6b41a828b | 320 | * @arg @ref LL_PWR_PVDLEVEL_6 |
<> | 156:95d6b41a828b | 321 | * @arg @ref LL_PWR_PVDLEVEL_7 |
<> | 156:95d6b41a828b | 322 | * @retval None |
<> | 156:95d6b41a828b | 323 | */ |
<> | 156:95d6b41a828b | 324 | __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) |
<> | 156:95d6b41a828b | 325 | { |
<> | 156:95d6b41a828b | 326 | MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); |
<> | 156:95d6b41a828b | 327 | } |
<> | 156:95d6b41a828b | 328 | |
<> | 156:95d6b41a828b | 329 | /** |
<> | 156:95d6b41a828b | 330 | * @brief Get the voltage threshold detection |
<> | 156:95d6b41a828b | 331 | * @rmtoll CR PLS LL_PWR_GetPVDLevel |
<> | 156:95d6b41a828b | 332 | * @retval Returned value can be one of the following values: |
<> | 156:95d6b41a828b | 333 | * @arg @ref LL_PWR_PVDLEVEL_0 |
<> | 156:95d6b41a828b | 334 | * @arg @ref LL_PWR_PVDLEVEL_1 |
<> | 156:95d6b41a828b | 335 | * @arg @ref LL_PWR_PVDLEVEL_2 |
<> | 156:95d6b41a828b | 336 | * @arg @ref LL_PWR_PVDLEVEL_3 |
<> | 156:95d6b41a828b | 337 | * @arg @ref LL_PWR_PVDLEVEL_4 |
<> | 156:95d6b41a828b | 338 | * @arg @ref LL_PWR_PVDLEVEL_5 |
<> | 156:95d6b41a828b | 339 | * @arg @ref LL_PWR_PVDLEVEL_6 |
<> | 156:95d6b41a828b | 340 | * @arg @ref LL_PWR_PVDLEVEL_7 |
<> | 156:95d6b41a828b | 341 | */ |
<> | 156:95d6b41a828b | 342 | __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) |
<> | 156:95d6b41a828b | 343 | { |
<> | 156:95d6b41a828b | 344 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); |
<> | 156:95d6b41a828b | 345 | } |
<> | 156:95d6b41a828b | 346 | |
<> | 156:95d6b41a828b | 347 | /** |
<> | 156:95d6b41a828b | 348 | * @brief Enable Power Voltage Detector |
<> | 156:95d6b41a828b | 349 | * @rmtoll CR PVDE LL_PWR_EnablePVD |
<> | 156:95d6b41a828b | 350 | * @retval None |
<> | 156:95d6b41a828b | 351 | */ |
<> | 156:95d6b41a828b | 352 | __STATIC_INLINE void LL_PWR_EnablePVD(void) |
<> | 156:95d6b41a828b | 353 | { |
<> | 156:95d6b41a828b | 354 | SET_BIT(PWR->CR, PWR_CR_PVDE); |
<> | 156:95d6b41a828b | 355 | } |
<> | 156:95d6b41a828b | 356 | |
<> | 156:95d6b41a828b | 357 | /** |
<> | 156:95d6b41a828b | 358 | * @brief Disable Power Voltage Detector |
<> | 156:95d6b41a828b | 359 | * @rmtoll CR PVDE LL_PWR_DisablePVD |
<> | 156:95d6b41a828b | 360 | * @retval None |
<> | 156:95d6b41a828b | 361 | */ |
<> | 156:95d6b41a828b | 362 | __STATIC_INLINE void LL_PWR_DisablePVD(void) |
<> | 156:95d6b41a828b | 363 | { |
<> | 156:95d6b41a828b | 364 | CLEAR_BIT(PWR->CR, PWR_CR_PVDE); |
<> | 156:95d6b41a828b | 365 | } |
<> | 156:95d6b41a828b | 366 | |
<> | 156:95d6b41a828b | 367 | /** |
<> | 156:95d6b41a828b | 368 | * @brief Check if Power Voltage Detector is enabled |
<> | 156:95d6b41a828b | 369 | * @rmtoll CR PVDE LL_PWR_IsEnabledPVD |
<> | 156:95d6b41a828b | 370 | * @retval State of bit (1 or 0). |
<> | 156:95d6b41a828b | 371 | */ |
<> | 156:95d6b41a828b | 372 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) |
<> | 156:95d6b41a828b | 373 | { |
<> | 156:95d6b41a828b | 374 | return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); |
<> | 156:95d6b41a828b | 375 | } |
Anna Bridge |
180:96ed750bd169 | 376 | #endif /* PWR_PVD_SUPPORT */ |
<> | 156:95d6b41a828b | 377 | |
<> | 156:95d6b41a828b | 378 | /** |
<> | 156:95d6b41a828b | 379 | * @brief Enable the WakeUp PINx functionality |
<> | 156:95d6b41a828b | 380 | * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 381 | * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 382 | * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 383 | * @rmtoll CSR EWUP4 LL_PWR_EnableWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 384 | * @rmtoll CSR EWUP5 LL_PWR_EnableWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 385 | * @rmtoll CSR EWUP6 LL_PWR_EnableWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 386 | * @rmtoll CSR EWUP7 LL_PWR_EnableWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 387 | * @rmtoll CSR EWUP8 LL_PWR_EnableWakeUpPin |
<> | 156:95d6b41a828b | 388 | * @param WakeUpPin This parameter can be one of the following values: |
<> | 156:95d6b41a828b | 389 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
<> | 156:95d6b41a828b | 390 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
<> | 156:95d6b41a828b | 391 | * @arg @ref LL_PWR_WAKEUP_PIN3 (*) |
<> | 156:95d6b41a828b | 392 | * @arg @ref LL_PWR_WAKEUP_PIN4 (*) |
<> | 156:95d6b41a828b | 393 | * @arg @ref LL_PWR_WAKEUP_PIN5 (*) |
<> | 156:95d6b41a828b | 394 | * @arg @ref LL_PWR_WAKEUP_PIN6 (*) |
<> | 156:95d6b41a828b | 395 | * @arg @ref LL_PWR_WAKEUP_PIN7 (*) |
<> | 156:95d6b41a828b | 396 | * @arg @ref LL_PWR_WAKEUP_PIN8 (*) |
<> | 156:95d6b41a828b | 397 | * |
<> | 156:95d6b41a828b | 398 | * (*) not available on all devices |
<> | 156:95d6b41a828b | 399 | * @retval None |
<> | 156:95d6b41a828b | 400 | */ |
<> | 156:95d6b41a828b | 401 | __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) |
<> | 156:95d6b41a828b | 402 | { |
<> | 156:95d6b41a828b | 403 | SET_BIT(PWR->CSR, WakeUpPin); |
<> | 156:95d6b41a828b | 404 | } |
<> | 156:95d6b41a828b | 405 | |
<> | 156:95d6b41a828b | 406 | /** |
<> | 156:95d6b41a828b | 407 | * @brief Disable the WakeUp PINx functionality |
<> | 156:95d6b41a828b | 408 | * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 409 | * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 410 | * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 411 | * @rmtoll CSR EWUP4 LL_PWR_DisableWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 412 | * @rmtoll CSR EWUP5 LL_PWR_DisableWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 413 | * @rmtoll CSR EWUP6 LL_PWR_DisableWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 414 | * @rmtoll CSR EWUP7 LL_PWR_DisableWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 415 | * @rmtoll CSR EWUP8 LL_PWR_DisableWakeUpPin |
<> | 156:95d6b41a828b | 416 | * @param WakeUpPin This parameter can be one of the following values: |
<> | 156:95d6b41a828b | 417 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
<> | 156:95d6b41a828b | 418 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
<> | 156:95d6b41a828b | 419 | * @arg @ref LL_PWR_WAKEUP_PIN3 (*) |
<> | 156:95d6b41a828b | 420 | * @arg @ref LL_PWR_WAKEUP_PIN4 (*) |
<> | 156:95d6b41a828b | 421 | * @arg @ref LL_PWR_WAKEUP_PIN5 (*) |
<> | 156:95d6b41a828b | 422 | * @arg @ref LL_PWR_WAKEUP_PIN6 (*) |
<> | 156:95d6b41a828b | 423 | * @arg @ref LL_PWR_WAKEUP_PIN7 (*) |
<> | 156:95d6b41a828b | 424 | * @arg @ref LL_PWR_WAKEUP_PIN8 (*) |
<> | 156:95d6b41a828b | 425 | * |
<> | 156:95d6b41a828b | 426 | * (*) not available on all devices |
<> | 156:95d6b41a828b | 427 | * @retval None |
<> | 156:95d6b41a828b | 428 | */ |
<> | 156:95d6b41a828b | 429 | __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) |
<> | 156:95d6b41a828b | 430 | { |
<> | 156:95d6b41a828b | 431 | CLEAR_BIT(PWR->CSR, WakeUpPin); |
<> | 156:95d6b41a828b | 432 | } |
<> | 156:95d6b41a828b | 433 | |
<> | 156:95d6b41a828b | 434 | /** |
<> | 156:95d6b41a828b | 435 | * @brief Check if the WakeUp PINx functionality is enabled |
<> | 156:95d6b41a828b | 436 | * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 437 | * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 438 | * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 439 | * @rmtoll CSR EWUP4 LL_PWR_IsEnabledWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 440 | * @rmtoll CSR EWUP5 LL_PWR_IsEnabledWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 441 | * @rmtoll CSR EWUP6 LL_PWR_IsEnabledWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 442 | * @rmtoll CSR EWUP7 LL_PWR_IsEnabledWakeUpPin\n |
Anna Bridge |
180:96ed750bd169 | 443 | * @rmtoll CSR EWUP8 LL_PWR_IsEnabledWakeUpPin |
<> | 156:95d6b41a828b | 444 | * @param WakeUpPin This parameter can be one of the following values: |
<> | 156:95d6b41a828b | 445 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
<> | 156:95d6b41a828b | 446 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
<> | 156:95d6b41a828b | 447 | * @arg @ref LL_PWR_WAKEUP_PIN3 (*) |
<> | 156:95d6b41a828b | 448 | * @arg @ref LL_PWR_WAKEUP_PIN4 (*) |
<> | 156:95d6b41a828b | 449 | * @arg @ref LL_PWR_WAKEUP_PIN5 (*) |
<> | 156:95d6b41a828b | 450 | * @arg @ref LL_PWR_WAKEUP_PIN6 (*) |
<> | 156:95d6b41a828b | 451 | * @arg @ref LL_PWR_WAKEUP_PIN7 (*) |
<> | 156:95d6b41a828b | 452 | * @arg @ref LL_PWR_WAKEUP_PIN8 (*) |
<> | 156:95d6b41a828b | 453 | * |
<> | 156:95d6b41a828b | 454 | * (*) not available on all devices |
<> | 156:95d6b41a828b | 455 | * @retval State of bit (1 or 0). |
<> | 156:95d6b41a828b | 456 | */ |
<> | 156:95d6b41a828b | 457 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) |
<> | 156:95d6b41a828b | 458 | { |
<> | 156:95d6b41a828b | 459 | return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); |
<> | 156:95d6b41a828b | 460 | } |
<> | 156:95d6b41a828b | 461 | |
Anna Bridge |
180:96ed750bd169 | 462 | |
<> | 156:95d6b41a828b | 463 | /** |
<> | 156:95d6b41a828b | 464 | * @} |
<> | 156:95d6b41a828b | 465 | */ |
<> | 156:95d6b41a828b | 466 | |
<> | 156:95d6b41a828b | 467 | /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management |
<> | 156:95d6b41a828b | 468 | * @{ |
<> | 156:95d6b41a828b | 469 | */ |
<> | 156:95d6b41a828b | 470 | |
<> | 156:95d6b41a828b | 471 | /** |
<> | 156:95d6b41a828b | 472 | * @brief Get Wake-up Flag |
<> | 156:95d6b41a828b | 473 | * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU |
<> | 156:95d6b41a828b | 474 | * @retval State of bit (1 or 0). |
<> | 156:95d6b41a828b | 475 | */ |
<> | 156:95d6b41a828b | 476 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) |
<> | 156:95d6b41a828b | 477 | { |
<> | 156:95d6b41a828b | 478 | return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); |
<> | 156:95d6b41a828b | 479 | } |
<> | 156:95d6b41a828b | 480 | |
<> | 156:95d6b41a828b | 481 | /** |
<> | 156:95d6b41a828b | 482 | * @brief Get Standby Flag |
<> | 156:95d6b41a828b | 483 | * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB |
<> | 156:95d6b41a828b | 484 | * @retval State of bit (1 or 0). |
<> | 156:95d6b41a828b | 485 | */ |
<> | 156:95d6b41a828b | 486 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) |
<> | 156:95d6b41a828b | 487 | { |
<> | 156:95d6b41a828b | 488 | return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); |
<> | 156:95d6b41a828b | 489 | } |
<> | 156:95d6b41a828b | 490 | |
Anna Bridge |
180:96ed750bd169 | 491 | #if defined(PWR_PVD_SUPPORT) |
<> | 156:95d6b41a828b | 492 | /** |
<> | 156:95d6b41a828b | 493 | * @brief Indicate whether VDD voltage is below the selected PVD threshold |
<> | 156:95d6b41a828b | 494 | * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO |
<> | 156:95d6b41a828b | 495 | * @retval State of bit (1 or 0). |
<> | 156:95d6b41a828b | 496 | */ |
<> | 156:95d6b41a828b | 497 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) |
<> | 156:95d6b41a828b | 498 | { |
<> | 156:95d6b41a828b | 499 | return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); |
<> | 156:95d6b41a828b | 500 | } |
Anna Bridge |
180:96ed750bd169 | 501 | #endif /* PWR_PVD_SUPPORT */ |
<> | 156:95d6b41a828b | 502 | |
Anna Bridge |
180:96ed750bd169 | 503 | #if defined(PWR_CSR_VREFINTRDYF) |
<> | 156:95d6b41a828b | 504 | /** |
<> | 156:95d6b41a828b | 505 | * @brief Get Internal Reference VrefInt Flag |
<> | 156:95d6b41a828b | 506 | * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY |
<> | 156:95d6b41a828b | 507 | * @retval State of bit (1 or 0). |
<> | 156:95d6b41a828b | 508 | */ |
<> | 156:95d6b41a828b | 509 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void) |
<> | 156:95d6b41a828b | 510 | { |
<> | 156:95d6b41a828b | 511 | return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF)); |
<> | 156:95d6b41a828b | 512 | } |
Anna Bridge |
180:96ed750bd169 | 513 | #endif /* PWR_CSR_VREFINTRDYF */ |
<> | 156:95d6b41a828b | 514 | /** |
<> | 156:95d6b41a828b | 515 | * @brief Clear Standby Flag |
<> | 156:95d6b41a828b | 516 | * @rmtoll CR CSBF LL_PWR_ClearFlag_SB |
<> | 156:95d6b41a828b | 517 | * @retval None |
<> | 156:95d6b41a828b | 518 | */ |
<> | 156:95d6b41a828b | 519 | __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) |
<> | 156:95d6b41a828b | 520 | { |
<> | 156:95d6b41a828b | 521 | SET_BIT(PWR->CR, PWR_CR_CSBF); |
<> | 156:95d6b41a828b | 522 | } |
<> | 156:95d6b41a828b | 523 | |
<> | 156:95d6b41a828b | 524 | /** |
<> | 156:95d6b41a828b | 525 | * @brief Clear Wake-up Flags |
<> | 156:95d6b41a828b | 526 | * @rmtoll CR CWUF LL_PWR_ClearFlag_WU |
<> | 156:95d6b41a828b | 527 | * @retval None |
<> | 156:95d6b41a828b | 528 | */ |
<> | 156:95d6b41a828b | 529 | __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) |
<> | 156:95d6b41a828b | 530 | { |
<> | 156:95d6b41a828b | 531 | SET_BIT(PWR->CR, PWR_CR_CWUF); |
<> | 156:95d6b41a828b | 532 | } |
<> | 156:95d6b41a828b | 533 | |
Anna Bridge |
180:96ed750bd169 | 534 | /** |
Anna Bridge |
180:96ed750bd169 | 535 | * @} |
Anna Bridge |
180:96ed750bd169 | 536 | */ |
<> | 156:95d6b41a828b | 537 | |
<> | 156:95d6b41a828b | 538 | #if defined(USE_FULL_LL_DRIVER) |
<> | 156:95d6b41a828b | 539 | /** @defgroup PWR_LL_EF_Init De-initialization function |
<> | 156:95d6b41a828b | 540 | * @{ |
<> | 156:95d6b41a828b | 541 | */ |
<> | 156:95d6b41a828b | 542 | ErrorStatus LL_PWR_DeInit(void); |
<> | 156:95d6b41a828b | 543 | /** |
<> | 156:95d6b41a828b | 544 | * @} |
<> | 156:95d6b41a828b | 545 | */ |
<> | 156:95d6b41a828b | 546 | #endif /* USE_FULL_LL_DRIVER */ |
<> | 156:95d6b41a828b | 547 | |
<> | 156:95d6b41a828b | 548 | /** |
<> | 156:95d6b41a828b | 549 | * @} |
<> | 156:95d6b41a828b | 550 | */ |
<> | 156:95d6b41a828b | 551 | |
<> | 156:95d6b41a828b | 552 | /** |
<> | 156:95d6b41a828b | 553 | * @} |
<> | 156:95d6b41a828b | 554 | */ |
<> | 156:95d6b41a828b | 555 | |
<> | 156:95d6b41a828b | 556 | #endif /* defined(PWR) */ |
<> | 156:95d6b41a828b | 557 | |
<> | 156:95d6b41a828b | 558 | /** |
<> | 156:95d6b41a828b | 559 | * @} |
<> | 156:95d6b41a828b | 560 | */ |
<> | 156:95d6b41a828b | 561 | |
<> | 156:95d6b41a828b | 562 | #ifdef __cplusplus |
<> | 156:95d6b41a828b | 563 | } |
<> | 156:95d6b41a828b | 564 | #endif |
<> | 156:95d6b41a828b | 565 | |
<> | 156:95d6b41a828b | 566 | #endif /* __STM32F0xx_LL_PWR_H */ |
<> | 156:95d6b41a828b | 567 | |
<> | 156:95d6b41a828b | 568 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |