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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_dac.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 180:96ed750bd169

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	156:95d6b41a828b	1	/**
<>	156:95d6b41a828b	2	******************************************************************************
<>	156:95d6b41a828b	3	* @file stm32f0xx_ll_dac.h
<>	156:95d6b41a828b	4	* @author MCD Application Team
<>	156:95d6b41a828b	5	* @brief Header file of DAC LL module.
<>	156:95d6b41a828b	6	******************************************************************************
<>	156:95d6b41a828b	7	* @attention
<>	156:95d6b41a828b	8	*
<>	156:95d6b41a828b	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	156:95d6b41a828b	10	*
<>	156:95d6b41a828b	11	* Redistribution and use in source and binary forms, with or without modification,
<>	156:95d6b41a828b	12	* are permitted provided that the following conditions are met:
<>	156:95d6b41a828b	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	156:95d6b41a828b	14	* this list of conditions and the following disclaimer.
<>	156:95d6b41a828b	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	156:95d6b41a828b	16	* this list of conditions and the following disclaimer in the documentation
<>	156:95d6b41a828b	17	* and/or other materials provided with the distribution.
<>	156:95d6b41a828b	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	156:95d6b41a828b	19	* may be used to endorse or promote products derived from this software
<>	156:95d6b41a828b	20	* without specific prior written permission.
<>	156:95d6b41a828b	21	*
<>	156:95d6b41a828b	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	156:95d6b41a828b	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	156:95d6b41a828b	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	156:95d6b41a828b	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	156:95d6b41a828b	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	156:95d6b41a828b	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	156:95d6b41a828b	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	156:95d6b41a828b	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	156:95d6b41a828b	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	156:95d6b41a828b	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	156:95d6b41a828b	32	*
<>	156:95d6b41a828b	33	******************************************************************************
<>	156:95d6b41a828b	34	*/
<>	156:95d6b41a828b	35
<>	156:95d6b41a828b	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	156:95d6b41a828b	37	#ifndef __STM32F0xx_LL_DAC_H
<>	156:95d6b41a828b	38	#define __STM32F0xx_LL_DAC_H
<>	156:95d6b41a828b	39
<>	156:95d6b41a828b	40	#ifdef __cplusplus
<>	156:95d6b41a828b	41	extern "C" {
<>	156:95d6b41a828b	42	#endif
<>	156:95d6b41a828b	43
<>	156:95d6b41a828b	44	/* Includes ------------------------------------------------------------------*/
<>	156:95d6b41a828b	45	#include "stm32f0xx.h"
<>	156:95d6b41a828b	46
<>	156:95d6b41a828b	47	/** @addtogroup STM32F0xx_LL_Driver
<>	156:95d6b41a828b	48	* @{
<>	156:95d6b41a828b	49	*/
<>	156:95d6b41a828b	50
<>	156:95d6b41a828b	51	#if defined (DAC1)
<>	156:95d6b41a828b	52
<>	156:95d6b41a828b	53	/** @defgroup DAC_LL DAC
<>	156:95d6b41a828b	54	* @{
<>	156:95d6b41a828b	55	*/
<>	156:95d6b41a828b	56
<>	156:95d6b41a828b	57	/* Private types -------------------------------------------------------------*/
<>	156:95d6b41a828b	58	/* Private variables ---------------------------------------------------------*/
<>	156:95d6b41a828b	59
<>	156:95d6b41a828b	60	/* Private constants ---------------------------------------------------------*/
<>	156:95d6b41a828b	61	/** @defgroup DAC_LL_Private_Constants DAC Private Constants
<>	156:95d6b41a828b	62	* @{
<>	156:95d6b41a828b	63	*/
<>	156:95d6b41a828b	64
<>	156:95d6b41a828b	65	/* Internal masks for DAC channels definition */
<>	156:95d6b41a828b	66	/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
<>	156:95d6b41a828b	67	/* - channel bits position into register CR */
<>	156:95d6b41a828b	68	/* - channel bits position into register SWTRIG */
<>	156:95d6b41a828b	69	/* - channel register offset of data holding register DHRx */
<>	156:95d6b41a828b	70	/* - channel register offset of data output register DORx */
Anna Bridge	180:96ed750bd169	71	#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
Anna Bridge	180:96ed750bd169	72	#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
<>	156:95d6b41a828b	73	#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET \| DAC_CR_CH2_BITOFFSET)
<>	156:95d6b41a828b	74
<>	156:95d6b41a828b	75	#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
<>	156:95d6b41a828b	76	#if defined(DAC_CHANNEL2_SUPPORT)
<>	156:95d6b41a828b	77	#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
<>	156:95d6b41a828b	78	#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 \| DAC_SWTR_CH2)
<>	156:95d6b41a828b	79	#else
<>	156:95d6b41a828b	80	#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
<>	156:95d6b41a828b	81	#endif /* DAC_CHANNEL2_SUPPORT */
<>	156:95d6b41a828b	82
Anna Bridge	180:96ed750bd169	83	#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
Anna Bridge	180:96ed750bd169	84	#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
Anna Bridge	180:96ed750bd169	85	#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
<>	156:95d6b41a828b	86	#if defined(DAC_CHANNEL2_SUPPORT)
Anna Bridge	180:96ed750bd169	87	#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
Anna Bridge	180:96ed750bd169	88	#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
Anna Bridge	180:96ed750bd169	89	#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
<>	156:95d6b41a828b	90	#endif /* DAC_CHANNEL2_SUPPORT */
Anna Bridge	180:96ed750bd169	91	#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
Anna Bridge	180:96ed750bd169	92	#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
Anna Bridge	180:96ed750bd169	93	#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
<>	156:95d6b41a828b	94	#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK \| DAC_REG_DHR12LX_REGOFFSET_MASK \| DAC_REG_DHR8RX_REGOFFSET_MASK)
<>	156:95d6b41a828b	95
Anna Bridge	180:96ed750bd169	96	#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
<>	156:95d6b41a828b	97	#if defined(DAC_CHANNEL2_SUPPORT)
Anna Bridge	180:96ed750bd169	98	#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
<>	156:95d6b41a828b	99	#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET \| DAC_REG_DOR2_REGOFFSET)
<>	156:95d6b41a828b	100	#else
<>	156:95d6b41a828b	101	#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
<>	156:95d6b41a828b	102	#endif /* DAC_CHANNEL2_SUPPORT */
<>	156:95d6b41a828b	103
Anna Bridge	180:96ed750bd169	104	#define DAC_REG_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of registers offset (DHR12Rx, DHR12Lx, DHR8Rx, DORx, ...) when shifted to position 0 */
<>	156:95d6b41a828b	105
Anna Bridge	180:96ed750bd169	106	#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
Anna Bridge	180:96ed750bd169	107	#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
Anna Bridge	180:96ed750bd169	108	#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
Anna Bridge	180:96ed750bd169	109	#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */
<>	156:95d6b41a828b	110
<>	156:95d6b41a828b	111	/* DAC registers bits positions */
<>	156:95d6b41a828b	112	#if defined(DAC_CHANNEL2_SUPPORT)
Anna Bridge	180:96ed750bd169	113	#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
Anna Bridge	180:96ed750bd169	114	#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
Anna Bridge	180:96ed750bd169	115	#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
<>	156:95d6b41a828b	116	#endif /* DAC_CHANNEL2_SUPPORT */
<>	156:95d6b41a828b	117
<>	156:95d6b41a828b	118	/* Miscellaneous data */
Anna Bridge	180:96ed750bd169	119	#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
<>	156:95d6b41a828b	120
<>	156:95d6b41a828b	121	/**
<>	156:95d6b41a828b	122	* @}
<>	156:95d6b41a828b	123	*/
<>	156:95d6b41a828b	124
<>	156:95d6b41a828b	125
<>	156:95d6b41a828b	126	/* Private macros ------------------------------------------------------------*/
<>	156:95d6b41a828b	127	/** @defgroup DAC_LL_Private_Macros DAC Private Macros
<>	156:95d6b41a828b	128	* @{
<>	156:95d6b41a828b	129	*/
<>	156:95d6b41a828b	130
<>	156:95d6b41a828b	131	/**
<>	156:95d6b41a828b	132	* @brief Driver macro reserved for internal use: set a pointer to
<>	156:95d6b41a828b	133	* a register from a register basis from which an offset
<>	156:95d6b41a828b	134	* is applied.
<>	156:95d6b41a828b	135	* @param __REG__ Register basis from which the offset is applied.
<>	156:95d6b41a828b	136	* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
<>	156:95d6b41a828b	137	* @retval Pointer to register address
<>	156:95d6b41a828b	138	*/
<>	156:95d6b41a828b	139	#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
<>	156:95d6b41a828b	140	((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
<>	156:95d6b41a828b	141
<>	156:95d6b41a828b	142	/**
<>	156:95d6b41a828b	143	* @}
<>	156:95d6b41a828b	144	*/
<>	156:95d6b41a828b	145
<>	156:95d6b41a828b	146
<>	156:95d6b41a828b	147	/* Exported types ------------------------------------------------------------*/
<>	156:95d6b41a828b	148	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	149	/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
<>	156:95d6b41a828b	150	* @{
<>	156:95d6b41a828b	151	*/
<>	156:95d6b41a828b	152
<>	156:95d6b41a828b	153	/**
<>	156:95d6b41a828b	154	* @brief Structure definition of some features of DAC instance.
<>	156:95d6b41a828b	155	*/
<>	156:95d6b41a828b	156	typedef struct
<>	156:95d6b41a828b	157	{
<>	156:95d6b41a828b	158	uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
<>	156:95d6b41a828b	159	This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
<>	156:95d6b41a828b	160
<>	156:95d6b41a828b	161	This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
<>	156:95d6b41a828b	162
<>	156:95d6b41a828b	163	#if defined(DAC_CR_WAVE1)
<>	156:95d6b41a828b	164	uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
<>	156:95d6b41a828b	165	This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
<>	156:95d6b41a828b	166
<>	156:95d6b41a828b	167	This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
<>	156:95d6b41a828b	168
<>	156:95d6b41a828b	169	uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
<>	156:95d6b41a828b	170	If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
<>	156:95d6b41a828b	171	If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
<>	156:95d6b41a828b	172	@note If waveform automatic generation mode is disabled, this parameter is discarded.
<>	156:95d6b41a828b	173
<>	156:95d6b41a828b	174	This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
<>	156:95d6b41a828b	175	#endif
<>	156:95d6b41a828b	176
<>	156:95d6b41a828b	177	uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
<>	156:95d6b41a828b	178	This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
<>	156:95d6b41a828b	179
<>	156:95d6b41a828b	180	This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
<>	156:95d6b41a828b	181
<>	156:95d6b41a828b	182	} LL_DAC_InitTypeDef;
<>	156:95d6b41a828b	183
<>	156:95d6b41a828b	184	/**
<>	156:95d6b41a828b	185	* @}
<>	156:95d6b41a828b	186	*/
<>	156:95d6b41a828b	187	#endif /* USE_FULL_LL_DRIVER */
<>	156:95d6b41a828b	188
<>	156:95d6b41a828b	189	/* Exported constants --------------------------------------------------------*/
<>	156:95d6b41a828b	190	/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
<>	156:95d6b41a828b	191	* @{
<>	156:95d6b41a828b	192	*/
<>	156:95d6b41a828b	193
<>	156:95d6b41a828b	194	/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
<>	156:95d6b41a828b	195	* @brief Flags defines which can be used with LL_DAC_ReadReg function
<>	156:95d6b41a828b	196	* @{
<>	156:95d6b41a828b	197	*/
<>	156:95d6b41a828b	198	/* DAC channel 1 flags */
<>	156:95d6b41a828b	199	#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /!< DAC channel 1 flag DMA underrun /
<>	156:95d6b41a828b	200
<>	156:95d6b41a828b	201	#if defined(DAC_CHANNEL2_SUPPORT)
<>	156:95d6b41a828b	202	/* DAC channel 2 flags */
<>	156:95d6b41a828b	203	#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /!< DAC channel 2 flag DMA underrun /
<>	156:95d6b41a828b	204	#endif /* DAC_CHANNEL2_SUPPORT */
<>	156:95d6b41a828b	205	/**
<>	156:95d6b41a828b	206	* @}
<>	156:95d6b41a828b	207	*/
<>	156:95d6b41a828b	208
<>	156:95d6b41a828b	209	/** @defgroup DAC_LL_EC_IT DAC interruptions
<>	156:95d6b41a828b	210	* @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
<>	156:95d6b41a828b	211	* @{
<>	156:95d6b41a828b	212	*/
<>	156:95d6b41a828b	213	#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /!< DAC channel 1 interruption DMA underrun /
<>	156:95d6b41a828b	214	#if defined(DAC_CHANNEL2_SUPPORT)
<>	156:95d6b41a828b	215	#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /!< DAC channel 2 interruption DMA underrun /
<>	156:95d6b41a828b	216	#endif /* DAC_CHANNEL2_SUPPORT */
<>	156:95d6b41a828b	217	/**
<>	156:95d6b41a828b	218	* @}
<>	156:95d6b41a828b	219	*/
<>	156:95d6b41a828b	220
<>	156:95d6b41a828b	221	/** @defgroup DAC_LL_EC_CHANNEL DAC channels
<>	156:95d6b41a828b	222	* @{
<>	156:95d6b41a828b	223	*/
<>	156:95d6b41a828b	224	#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET \| DAC_REG_DHR12R1_REGOFFSET \| DAC_REG_DHR12L1_REGOFFSET \| DAC_REG_DHR8R1_REGOFFSET \| DAC_CR_CH1_BITOFFSET \| DAC_SWTR_CH1) /!< DAC channel 1 /
<>	156:95d6b41a828b	225	#if defined(DAC_CHANNEL2_SUPPORT)
<>	156:95d6b41a828b	226	#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET \| DAC_REG_DHR12R2_REGOFFSET \| DAC_REG_DHR12L2_REGOFFSET \| DAC_REG_DHR8R2_REGOFFSET \| DAC_CR_CH2_BITOFFSET \| DAC_SWTR_CH2) /!< DAC channel 2 /
<>	156:95d6b41a828b	227	#endif /* DAC_CHANNEL2_SUPPORT */
<>	156:95d6b41a828b	228	/**
<>	156:95d6b41a828b	229	* @}
<>	156:95d6b41a828b	230	*/
<>	156:95d6b41a828b	231
<>	156:95d6b41a828b	232	/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
<>	156:95d6b41a828b	233	* @{
<>	156:95d6b41a828b	234	*/
<>	156:95d6b41a828b	235	#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger internal (SW start) /
<>	156:95d6b41a828b	236	#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /!< DAC channel conversion trigger from external IP: TIM2 TRGO. /
<>	156:95d6b41a828b	237	#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM3 TRGO. /
<>	156:95d6b41a828b	238	#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM4 TRGO. /
Anna Bridge	180:96ed750bd169	239	#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /!< DAC channel conversion trigger from external IP: TIM6 TRGO. /
<>	156:95d6b41a828b	240	#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /!< DAC channel conversion trigger from external IP: TIM7 TRGO. /
<>	156:95d6b41a828b	241	#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM15 TRGO. /
<>	156:95d6b41a828b	242	#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1 ) /!< DAC channel conversion trigger from external IP: external interrupt line 9. /
<>	156:95d6b41a828b	243	/**
<>	156:95d6b41a828b	244	* @}
<>	156:95d6b41a828b	245	*/
<>	156:95d6b41a828b	246
<>	156:95d6b41a828b	247	/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
<>	156:95d6b41a828b	248	* @{
<>	156:95d6b41a828b	249	*/
Anna Bridge	180:96ed750bd169	250	#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /!< DAC channel wave auto generation mode disabled. /
<>	156:95d6b41a828b	251	#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /!< DAC channel wave auto generation mode enabled, set generated noise waveform. /
<>	156:95d6b41a828b	252	#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /!< DAC channel wave auto generation mode enabled, set generated triangle waveform. /
<>	156:95d6b41a828b	253	/**
<>	156:95d6b41a828b	254	* @}
<>	156:95d6b41a828b	255	*/
<>	156:95d6b41a828b	256
<>	156:95d6b41a828b	257	/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
<>	156:95d6b41a828b	258	* @{
<>	156:95d6b41a828b	259	*/
Anna Bridge	180:96ed750bd169	260	#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel /
<>	156:95d6b41a828b	261	#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel /
<>	156:95d6b41a828b	262	#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel /
<>	156:95d6b41a828b	263	#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel /
<>	156:95d6b41a828b	264	#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel /
<>	156:95d6b41a828b	265	#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel /
<>	156:95d6b41a828b	266	#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel /
<>	156:95d6b41a828b	267	#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel /
<>	156:95d6b41a828b	268	#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel /
<>	156:95d6b41a828b	269	#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel /
<>	156:95d6b41a828b	270	#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel /
<>	156:95d6b41a828b	271	#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel /
<>	156:95d6b41a828b	272	/**
<>	156:95d6b41a828b	273	* @}
<>	156:95d6b41a828b	274	*/
<>	156:95d6b41a828b	275
<>	156:95d6b41a828b	276	/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
<>	156:95d6b41a828b	277	* @{
<>	156:95d6b41a828b	278	*/
Anna Bridge	180:96ed750bd169	279	#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel /
<>	156:95d6b41a828b	280	#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel /
<>	156:95d6b41a828b	281	#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel /
<>	156:95d6b41a828b	282	#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel /
<>	156:95d6b41a828b	283	#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel /
<>	156:95d6b41a828b	284	#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel /
<>	156:95d6b41a828b	285	#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel /
<>	156:95d6b41a828b	286	#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel /
<>	156:95d6b41a828b	287	#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel /
<>	156:95d6b41a828b	288	#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel /
<>	156:95d6b41a828b	289	#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel /
<>	156:95d6b41a828b	290	#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel /
<>	156:95d6b41a828b	291	/**
<>	156:95d6b41a828b	292	* @}
<>	156:95d6b41a828b	293	*/
<>	156:95d6b41a828b	294
<>	156:95d6b41a828b	295	/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
<>	156:95d6b41a828b	296	* @{
<>	156:95d6b41a828b	297	*/
Anna Bridge	180:96ed750bd169	298	#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption /
<>	156:95d6b41a828b	299	#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption /
<>	156:95d6b41a828b	300	/**
<>	156:95d6b41a828b	301	* @}
<>	156:95d6b41a828b	302	*/
<>	156:95d6b41a828b	303
<>	156:95d6b41a828b	304
<>	156:95d6b41a828b	305	/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
<>	156:95d6b41a828b	306	* @{
<>	156:95d6b41a828b	307	*/
Anna Bridge	180:96ed750bd169	308	#define LL_DAC_RESOLUTION_12B 0x00000000U /!< DAC channel resolution 12 bits /
Anna Bridge	180:96ed750bd169	309	#define LL_DAC_RESOLUTION_8B 0x00000002U /!< DAC channel resolution 8 bits /
<>	156:95d6b41a828b	310	/**
<>	156:95d6b41a828b	311	* @}
<>	156:95d6b41a828b	312	*/
<>	156:95d6b41a828b	313
<>	156:95d6b41a828b	314	/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
<>	156:95d6b41a828b	315	* @{
<>	156:95d6b41a828b	316	*/
<>	156:95d6b41a828b	317	/* List of DAC registers intended to be used (most commonly) with */
<>	156:95d6b41a828b	318	/* DMA transfer. */
<>	156:95d6b41a828b	319	/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
<>	156:95d6b41a828b	320	#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /!< DAC channel data holding register 12 bits right aligned /
<>	156:95d6b41a828b	321	#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /!< DAC channel data holding register 12 bits left aligned /
<>	156:95d6b41a828b	322	#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /!< DAC channel data holding register 8 bits right aligned /
<>	156:95d6b41a828b	323	/**
<>	156:95d6b41a828b	324	* @}
<>	156:95d6b41a828b	325	*/
<>	156:95d6b41a828b	326
<>	156:95d6b41a828b	327	/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
<>	156:95d6b41a828b	328	* @note Only DAC IP HW delays are defined in DAC LL driver driver,
<>	156:95d6b41a828b	329	* not timeout values.
<>	156:95d6b41a828b	330	* For details on delays values, refer to descriptions in source code
<>	156:95d6b41a828b	331	* above each literal definition.
<>	156:95d6b41a828b	332	* @{
<>	156:95d6b41a828b	333	*/
<>	156:95d6b41a828b	334
<>	156:95d6b41a828b	335	/* Delay for DAC channel voltage settling time from DAC channel startup */
<>	156:95d6b41a828b	336	/* (transition from disable to enable). */
<>	156:95d6b41a828b	337	/* Note: DAC channel startup time depends on board application environment: */
<>	156:95d6b41a828b	338	/* impedance connected to DAC channel output. */
<>	156:95d6b41a828b	339	/* The delay below is specified under conditions: */
<>	156:95d6b41a828b	340	/* - voltage maximum transition (lowest to highest value) */
<>	156:95d6b41a828b	341	/* - until voltage reaches final value +-1LSB */
<>	156:95d6b41a828b	342	/* - DAC channel output buffer enabled */
<>	156:95d6b41a828b	343	/* - load impedance of 5kOhm (min), 50pF (max) */
<>	156:95d6b41a828b	344	/* Literal set to maximum value (refer to device datasheet, */
<>	156:95d6b41a828b	345	/* parameter "tWAKEUP"). */
<>	156:95d6b41a828b	346	/* Unit: us */
Anna Bridge	180:96ed750bd169	347	#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) /
<>	156:95d6b41a828b	348
<>	156:95d6b41a828b	349	/* Delay for DAC channel voltage settling time. */
<>	156:95d6b41a828b	350	/* Note: DAC channel startup time depends on board application environment: */
<>	156:95d6b41a828b	351	/* impedance connected to DAC channel output. */
<>	156:95d6b41a828b	352	/* The delay below is specified under conditions: */
<>	156:95d6b41a828b	353	/* - voltage maximum transition (lowest to highest value) */
<>	156:95d6b41a828b	354	/* - until voltage reaches final value +-1LSB */
<>	156:95d6b41a828b	355	/* - DAC channel output buffer enabled */
<>	156:95d6b41a828b	356	/* - load impedance of 5kOhm min, 50pF max */
<>	156:95d6b41a828b	357	/* Literal set to maximum value (refer to device datasheet, */
<>	156:95d6b41a828b	358	/* parameter "tSETTLING"). */
<>	156:95d6b41a828b	359	/* Unit: us */
Anna Bridge	180:96ed750bd169	360	#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /!< Delay for DAC channel voltage settling time /
<>	156:95d6b41a828b	361	/**
<>	156:95d6b41a828b	362	* @}
<>	156:95d6b41a828b	363	*/
<>	156:95d6b41a828b	364
<>	156:95d6b41a828b	365	/**
<>	156:95d6b41a828b	366	* @}
<>	156:95d6b41a828b	367	*/
<>	156:95d6b41a828b	368
<>	156:95d6b41a828b	369	/* Exported macro ------------------------------------------------------------*/
<>	156:95d6b41a828b	370	/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
<>	156:95d6b41a828b	371	* @{
<>	156:95d6b41a828b	372	*/
<>	156:95d6b41a828b	373
<>	156:95d6b41a828b	374	/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
<>	156:95d6b41a828b	375	* @{
<>	156:95d6b41a828b	376	*/
<>	156:95d6b41a828b	377
<>	156:95d6b41a828b	378	/**
<>	156:95d6b41a828b	379	* @brief Write a value in DAC register
<>	156:95d6b41a828b	380	* @param __INSTANCE__ DAC Instance
<>	156:95d6b41a828b	381	* @param __REG__ Register to be written
<>	156:95d6b41a828b	382	* @param __VALUE__ Value to be written in the register
<>	156:95d6b41a828b	383	* @retval None
<>	156:95d6b41a828b	384	*/
<>	156:95d6b41a828b	385	#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	156:95d6b41a828b	386
<>	156:95d6b41a828b	387	/**
<>	156:95d6b41a828b	388	* @brief Read a value in DAC register
<>	156:95d6b41a828b	389	* @param __INSTANCE__ DAC Instance
<>	156:95d6b41a828b	390	* @param __REG__ Register to be read
<>	156:95d6b41a828b	391	* @retval Register value
<>	156:95d6b41a828b	392	*/
<>	156:95d6b41a828b	393	#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	156:95d6b41a828b	394
<>	156:95d6b41a828b	395	/**
<>	156:95d6b41a828b	396	* @}
<>	156:95d6b41a828b	397	*/
<>	156:95d6b41a828b	398
<>	156:95d6b41a828b	399	/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
<>	156:95d6b41a828b	400	* @{
<>	156:95d6b41a828b	401	*/
<>	156:95d6b41a828b	402
<>	156:95d6b41a828b	403	/**
<>	156:95d6b41a828b	404	* @brief Helper macro to get DAC channel number in decimal format
<>	156:95d6b41a828b	405	* from literals LL_DAC_CHANNEL_x.
<>	156:95d6b41a828b	406	* Example:
<>	156:95d6b41a828b	407	* __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
<>	156:95d6b41a828b	408	* will return decimal number "1".
<>	156:95d6b41a828b	409	* @note The input can be a value from functions where a channel
<>	156:95d6b41a828b	410	* number is returned.
<>	156:95d6b41a828b	411	* @param __CHANNEL__ This parameter can be one of the following values:
<>	156:95d6b41a828b	412	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	413	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	414	*
<>	156:95d6b41a828b	415	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	416	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	417	* @retval 1...2 (value "2" depending on DAC channel 2 availability)
<>	156:95d6b41a828b	418	*/
<>	156:95d6b41a828b	419	#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
<>	156:95d6b41a828b	420	((__CHANNEL__) & DAC_SWTR_CHX_MASK)
<>	156:95d6b41a828b	421
<>	156:95d6b41a828b	422	/**
<>	156:95d6b41a828b	423	* @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
<>	156:95d6b41a828b	424	* from number in decimal format.
<>	156:95d6b41a828b	425	* Example:
<>	156:95d6b41a828b	426	* __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
<>	156:95d6b41a828b	427	* will return a data equivalent to "LL_DAC_CHANNEL_1".
<>	156:95d6b41a828b	428	* @note If the input parameter does not correspond to a DAC channel,
<>	156:95d6b41a828b	429	* this macro returns value '0'.
<>	156:95d6b41a828b	430	* @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
<>	156:95d6b41a828b	431	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	432	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	433	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	434	*
<>	156:95d6b41a828b	435	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	436	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	437	*/
<>	156:95d6b41a828b	438	#if defined(DAC_CHANNEL2_SUPPORT)
<>	156:95d6b41a828b	439	#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
<>	156:95d6b41a828b	440	(((__DECIMAL_NB__) == 1U) \
<>	156:95d6b41a828b	441	? ( \
<>	156:95d6b41a828b	442	LL_DAC_CHANNEL_1 \
<>	156:95d6b41a828b	443	) \
<>	156:95d6b41a828b	444	: \
<>	156:95d6b41a828b	445	(((__DECIMAL_NB__) == 2U) \
<>	156:95d6b41a828b	446	? ( \
<>	156:95d6b41a828b	447	LL_DAC_CHANNEL_2 \
<>	156:95d6b41a828b	448	) \
<>	156:95d6b41a828b	449	: \
<>	156:95d6b41a828b	450	( \
<>	156:95d6b41a828b	451	0 \
<>	156:95d6b41a828b	452	) \
<>	156:95d6b41a828b	453	) \
<>	156:95d6b41a828b	454	)
<>	156:95d6b41a828b	455	#else
<>	156:95d6b41a828b	456	#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
<>	156:95d6b41a828b	457	(((__DECIMAL_NB__) == 1U) \
<>	156:95d6b41a828b	458	? ( \
<>	156:95d6b41a828b	459	LL_DAC_CHANNEL_1 \
<>	156:95d6b41a828b	460	) \
<>	156:95d6b41a828b	461	: \
<>	156:95d6b41a828b	462	( \
<>	156:95d6b41a828b	463	0 \
<>	156:95d6b41a828b	464	) \
<>	156:95d6b41a828b	465	)
<>	156:95d6b41a828b	466	#endif /* DAC_CHANNEL2_SUPPORT */
<>	156:95d6b41a828b	467
<>	156:95d6b41a828b	468	/**
<>	156:95d6b41a828b	469	* @brief Helper macro to define the DAC conversion data full-scale digital
<>	156:95d6b41a828b	470	* value corresponding to the selected DAC resolution.
<>	156:95d6b41a828b	471	* @note DAC conversion data full-scale corresponds to voltage range
<>	156:95d6b41a828b	472	* determined by analog voltage references Vref+ and Vref-
<>	156:95d6b41a828b	473	* (refer to reference manual).
<>	156:95d6b41a828b	474	* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
<>	156:95d6b41a828b	475	* @arg @ref LL_DAC_RESOLUTION_12B
<>	156:95d6b41a828b	476	* @arg @ref LL_DAC_RESOLUTION_8B
<>	156:95d6b41a828b	477	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
<>	156:95d6b41a828b	478	*/
<>	156:95d6b41a828b	479	#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
Anna Bridge	180:96ed750bd169	480	((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
<>	156:95d6b41a828b	481
<>	156:95d6b41a828b	482	/**
<>	156:95d6b41a828b	483	* @brief Helper macro to calculate the DAC conversion data (unit: digital
<>	156:95d6b41a828b	484	* value) corresponding to a voltage (unit: mVolt).
<>	156:95d6b41a828b	485	* @note This helper macro is intended to provide input data in voltage
<>	156:95d6b41a828b	486	* rather than digital value,
<>	156:95d6b41a828b	487	* to be used with LL DAC functions such as
<>	156:95d6b41a828b	488	* @ref LL_DAC_ConvertData12RightAligned().
<>	156:95d6b41a828b	489	* @note Analog reference voltage (Vref+) must be either known from
<>	156:95d6b41a828b	490	* user board environment or can be calculated using ADC measurement
<>	156:95d6b41a828b	491	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<>	156:95d6b41a828b	492	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
<>	156:95d6b41a828b	493	* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
<>	156:95d6b41a828b	494	* (unit: mVolt).
<>	156:95d6b41a828b	495	* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
<>	156:95d6b41a828b	496	* @arg @ref LL_DAC_RESOLUTION_12B
<>	156:95d6b41a828b	497	* @arg @ref LL_DAC_RESOLUTION_8B
<>	156:95d6b41a828b	498	* @retval DAC conversion data (unit: digital value)
<>	156:95d6b41a828b	499	*/
<>	156:95d6b41a828b	500	#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
<>	156:95d6b41a828b	501	__DAC_VOLTAGE__,\
<>	156:95d6b41a828b	502	__DAC_RESOLUTION__) \
<>	156:95d6b41a828b	503	((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
<>	156:95d6b41a828b	504	/ (__VREFANALOG_VOLTAGE__) \
<>	156:95d6b41a828b	505	)
<>	156:95d6b41a828b	506
<>	156:95d6b41a828b	507	/**
<>	156:95d6b41a828b	508	* @}
<>	156:95d6b41a828b	509	*/
<>	156:95d6b41a828b	510
<>	156:95d6b41a828b	511	/**
<>	156:95d6b41a828b	512	* @}
<>	156:95d6b41a828b	513	*/
<>	156:95d6b41a828b	514
<>	156:95d6b41a828b	515
<>	156:95d6b41a828b	516	/* Exported functions --------------------------------------------------------*/
<>	156:95d6b41a828b	517	/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
<>	156:95d6b41a828b	518	* @{
<>	156:95d6b41a828b	519	*/
<>	156:95d6b41a828b	520	/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
<>	156:95d6b41a828b	521	* @{
<>	156:95d6b41a828b	522	*/
<>	156:95d6b41a828b	523
<>	156:95d6b41a828b	524	/**
<>	156:95d6b41a828b	525	* @brief Set the conversion trigger source for the selected DAC channel.
<>	156:95d6b41a828b	526	* @note For conversion trigger source to be effective, DAC trigger
<>	156:95d6b41a828b	527	* must be enabled using function @ref LL_DAC_EnableTrigger().
<>	156:95d6b41a828b	528	* @note To set conversion trigger source, DAC channel must be disabled.
<>	156:95d6b41a828b	529	* Otherwise, the setting is discarded.
<>	156:95d6b41a828b	530	* @note Availability of parameters of trigger sources from timer
<>	156:95d6b41a828b	531	* depends on timers availability on the selected device.
<>	156:95d6b41a828b	532	* @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
<>	156:95d6b41a828b	533	* CR TSEL2 LL_DAC_SetTriggerSource
<>	156:95d6b41a828b	534	* @param DACx DAC instance
<>	156:95d6b41a828b	535	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	536	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	537	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	538	*
<>	156:95d6b41a828b	539	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	540	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	541	* @param TriggerSource This parameter can be one of the following values:
<>	156:95d6b41a828b	542	* @arg @ref LL_DAC_TRIG_SOFTWARE
<>	156:95d6b41a828b	543	* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
<>	156:95d6b41a828b	544	* @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
<>	156:95d6b41a828b	545	* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
<>	156:95d6b41a828b	546	* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
<>	156:95d6b41a828b	547	* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
<>	156:95d6b41a828b	548	* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
<>	156:95d6b41a828b	549	* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
<>	156:95d6b41a828b	550	* @retval None
<>	156:95d6b41a828b	551	*/
<>	156:95d6b41a828b	552	__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
<>	156:95d6b41a828b	553	{
<>	156:95d6b41a828b	554	MODIFY_REG(DACx->CR,
<>	156:95d6b41a828b	555	DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	156:95d6b41a828b	556	TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	156:95d6b41a828b	557	}
<>	156:95d6b41a828b	558
<>	156:95d6b41a828b	559	/**
<>	156:95d6b41a828b	560	* @brief Get the conversion trigger source for the selected DAC channel.
<>	156:95d6b41a828b	561	* @note For conversion trigger source to be effective, DAC trigger
<>	156:95d6b41a828b	562	* must be enabled using function @ref LL_DAC_EnableTrigger().
<>	156:95d6b41a828b	563	* @note Availability of parameters of trigger sources from timer
<>	156:95d6b41a828b	564	* depends on timers availability on the selected device.
<>	156:95d6b41a828b	565	* @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
<>	156:95d6b41a828b	566	* CR TSEL2 LL_DAC_GetTriggerSource
<>	156:95d6b41a828b	567	* @param DACx DAC instance
<>	156:95d6b41a828b	568	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	569	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	570	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	571	*
<>	156:95d6b41a828b	572	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	573	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	574	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	575	* @arg @ref LL_DAC_TRIG_SOFTWARE
<>	156:95d6b41a828b	576	* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
<>	156:95d6b41a828b	577	* @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
<>	156:95d6b41a828b	578	* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
<>	156:95d6b41a828b	579	* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
<>	156:95d6b41a828b	580	* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
<>	156:95d6b41a828b	581	* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
<>	156:95d6b41a828b	582	* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
<>	156:95d6b41a828b	583	*/
<>	156:95d6b41a828b	584	__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	156:95d6b41a828b	585	{
<>	156:95d6b41a828b	586	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	156:95d6b41a828b	587	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	156:95d6b41a828b	588	);
<>	156:95d6b41a828b	589	}
<>	156:95d6b41a828b	590
<>	156:95d6b41a828b	591	#if defined(DAC_CR_WAVE1)
<>	156:95d6b41a828b	592	/**
<>	156:95d6b41a828b	593	* @brief Set the waveform automatic generation mode
<>	156:95d6b41a828b	594	* for the selected DAC channel.
<>	156:95d6b41a828b	595	* @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
<>	156:95d6b41a828b	596	* CR WAVE2 LL_DAC_SetWaveAutoGeneration
<>	156:95d6b41a828b	597	* @param DACx DAC instance
<>	156:95d6b41a828b	598	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	599	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	600	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	601	*
<>	156:95d6b41a828b	602	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	603	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	604	* @param WaveAutoGeneration This parameter can be one of the following values:
<>	156:95d6b41a828b	605	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
<>	156:95d6b41a828b	606	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
<>	156:95d6b41a828b	607	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
<>	156:95d6b41a828b	608	* @retval None
<>	156:95d6b41a828b	609	*/
<>	156:95d6b41a828b	610	__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
<>	156:95d6b41a828b	611	{
<>	156:95d6b41a828b	612	MODIFY_REG(DACx->CR,
<>	156:95d6b41a828b	613	DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	156:95d6b41a828b	614	WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	156:95d6b41a828b	615	}
<>	156:95d6b41a828b	616
<>	156:95d6b41a828b	617	/**
<>	156:95d6b41a828b	618	* @brief Get the waveform automatic generation mode
<>	156:95d6b41a828b	619	* for the selected DAC channel.
<>	156:95d6b41a828b	620	* @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
<>	156:95d6b41a828b	621	* CR WAVE2 LL_DAC_GetWaveAutoGeneration
<>	156:95d6b41a828b	622	* @param DACx DAC instance
<>	156:95d6b41a828b	623	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	624	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	625	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	626	*
<>	156:95d6b41a828b	627	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	628	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	629	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	630	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
<>	156:95d6b41a828b	631	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
<>	156:95d6b41a828b	632	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
<>	156:95d6b41a828b	633	*/
<>	156:95d6b41a828b	634	__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	156:95d6b41a828b	635	{
<>	156:95d6b41a828b	636	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	156:95d6b41a828b	637	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	156:95d6b41a828b	638	);
<>	156:95d6b41a828b	639	}
<>	156:95d6b41a828b	640
<>	156:95d6b41a828b	641	/**
<>	156:95d6b41a828b	642	* @brief Set the noise waveform generation for the selected DAC channel:
<>	156:95d6b41a828b	643	* Noise mode and parameters LFSR (linear feedback shift register).
<>	156:95d6b41a828b	644	* @note For wave generation to be effective, DAC channel
<>	156:95d6b41a828b	645	* wave generation mode must be enabled using
<>	156:95d6b41a828b	646	* function @ref LL_DAC_SetWaveAutoGeneration().
<>	156:95d6b41a828b	647	* @note This setting can be set when the selected DAC channel is disabled
<>	156:95d6b41a828b	648	* (otherwise, the setting operation is ignored).
<>	156:95d6b41a828b	649	* @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
<>	156:95d6b41a828b	650	* CR MAMP2 LL_DAC_SetWaveNoiseLFSR
<>	156:95d6b41a828b	651	* @param DACx DAC instance
<>	156:95d6b41a828b	652	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	653	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	654	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	655	*
<>	156:95d6b41a828b	656	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	657	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	658	* @param NoiseLFSRMask This parameter can be one of the following values:
<>	156:95d6b41a828b	659	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
<>	156:95d6b41a828b	660	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
<>	156:95d6b41a828b	661	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
<>	156:95d6b41a828b	662	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
<>	156:95d6b41a828b	663	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
<>	156:95d6b41a828b	664	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
<>	156:95d6b41a828b	665	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
<>	156:95d6b41a828b	666	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
<>	156:95d6b41a828b	667	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
<>	156:95d6b41a828b	668	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
<>	156:95d6b41a828b	669	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
<>	156:95d6b41a828b	670	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
<>	156:95d6b41a828b	671	* @retval None
<>	156:95d6b41a828b	672	*/
<>	156:95d6b41a828b	673	__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
<>	156:95d6b41a828b	674	{
<>	156:95d6b41a828b	675	MODIFY_REG(DACx->CR,
<>	156:95d6b41a828b	676	DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	156:95d6b41a828b	677	NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	156:95d6b41a828b	678	}
<>	156:95d6b41a828b	679
<>	156:95d6b41a828b	680	/**
<>	156:95d6b41a828b	681	* @brief Set the noise waveform generation for the selected DAC channel:
<>	156:95d6b41a828b	682	* Noise mode and parameters LFSR (linear feedback shift register).
<>	156:95d6b41a828b	683	* @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
<>	156:95d6b41a828b	684	* CR MAMP2 LL_DAC_GetWaveNoiseLFSR
<>	156:95d6b41a828b	685	* @param DACx DAC instance
<>	156:95d6b41a828b	686	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	687	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	688	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	689	*
<>	156:95d6b41a828b	690	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	691	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	692	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	693	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
<>	156:95d6b41a828b	694	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
<>	156:95d6b41a828b	695	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
<>	156:95d6b41a828b	696	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
<>	156:95d6b41a828b	697	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
<>	156:95d6b41a828b	698	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
<>	156:95d6b41a828b	699	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
<>	156:95d6b41a828b	700	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
<>	156:95d6b41a828b	701	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
<>	156:95d6b41a828b	702	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
<>	156:95d6b41a828b	703	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
<>	156:95d6b41a828b	704	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
<>	156:95d6b41a828b	705	*/
<>	156:95d6b41a828b	706	__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	156:95d6b41a828b	707	{
<>	156:95d6b41a828b	708	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	156:95d6b41a828b	709	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	156:95d6b41a828b	710	);
<>	156:95d6b41a828b	711	}
<>	156:95d6b41a828b	712
<>	156:95d6b41a828b	713	/**
<>	156:95d6b41a828b	714	* @brief Set the triangle waveform generation for the selected DAC channel:
<>	156:95d6b41a828b	715	* triangle mode and amplitude.
<>	156:95d6b41a828b	716	* @note For wave generation to be effective, DAC channel
<>	156:95d6b41a828b	717	* wave generation mode must be enabled using
<>	156:95d6b41a828b	718	* function @ref LL_DAC_SetWaveAutoGeneration().
<>	156:95d6b41a828b	719	* @note This setting can be set when the selected DAC channel is disabled
<>	156:95d6b41a828b	720	* (otherwise, the setting operation is ignored).
<>	156:95d6b41a828b	721	* @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
<>	156:95d6b41a828b	722	* CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
<>	156:95d6b41a828b	723	* @param DACx DAC instance
<>	156:95d6b41a828b	724	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	725	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	726	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	727	*
<>	156:95d6b41a828b	728	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	729	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	730	* @param TriangleAmplitude This parameter can be one of the following values:
<>	156:95d6b41a828b	731	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
<>	156:95d6b41a828b	732	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
<>	156:95d6b41a828b	733	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
<>	156:95d6b41a828b	734	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
<>	156:95d6b41a828b	735	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
<>	156:95d6b41a828b	736	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
<>	156:95d6b41a828b	737	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
<>	156:95d6b41a828b	738	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
<>	156:95d6b41a828b	739	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
<>	156:95d6b41a828b	740	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
<>	156:95d6b41a828b	741	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
<>	156:95d6b41a828b	742	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
<>	156:95d6b41a828b	743	* @retval None
<>	156:95d6b41a828b	744	*/
<>	156:95d6b41a828b	745	__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
<>	156:95d6b41a828b	746	{
<>	156:95d6b41a828b	747	MODIFY_REG(DACx->CR,
<>	156:95d6b41a828b	748	DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	156:95d6b41a828b	749	TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	156:95d6b41a828b	750	}
<>	156:95d6b41a828b	751
<>	156:95d6b41a828b	752	/**
<>	156:95d6b41a828b	753	* @brief Set the triangle waveform generation for the selected DAC channel:
<>	156:95d6b41a828b	754	* triangle mode and amplitude.
<>	156:95d6b41a828b	755	* @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
<>	156:95d6b41a828b	756	* CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
<>	156:95d6b41a828b	757	* @param DACx DAC instance
<>	156:95d6b41a828b	758	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	759	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	760	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	761	*
<>	156:95d6b41a828b	762	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	763	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	764	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	765	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
<>	156:95d6b41a828b	766	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
<>	156:95d6b41a828b	767	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
<>	156:95d6b41a828b	768	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
<>	156:95d6b41a828b	769	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
<>	156:95d6b41a828b	770	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
<>	156:95d6b41a828b	771	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
<>	156:95d6b41a828b	772	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
<>	156:95d6b41a828b	773	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
<>	156:95d6b41a828b	774	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
<>	156:95d6b41a828b	775	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
<>	156:95d6b41a828b	776	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
<>	156:95d6b41a828b	777	*/
<>	156:95d6b41a828b	778	__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	156:95d6b41a828b	779	{
<>	156:95d6b41a828b	780	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	156:95d6b41a828b	781	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	156:95d6b41a828b	782	);
<>	156:95d6b41a828b	783	}
<>	156:95d6b41a828b	784	#endif
<>	156:95d6b41a828b	785
<>	156:95d6b41a828b	786	/**
<>	156:95d6b41a828b	787	* @brief Set the output buffer for the selected DAC channel.
<>	156:95d6b41a828b	788	* @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
<>	156:95d6b41a828b	789	* CR BOFF2 LL_DAC_SetOutputBuffer
<>	156:95d6b41a828b	790	* @param DACx DAC instance
<>	156:95d6b41a828b	791	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	792	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	793	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	794	*
<>	156:95d6b41a828b	795	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	796	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	797	* @param OutputBuffer This parameter can be one of the following values:
<>	156:95d6b41a828b	798	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
<>	156:95d6b41a828b	799	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
<>	156:95d6b41a828b	800	* @retval None
<>	156:95d6b41a828b	801	*/
<>	156:95d6b41a828b	802	__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
<>	156:95d6b41a828b	803	{
<>	156:95d6b41a828b	804	MODIFY_REG(DACx->CR,
<>	156:95d6b41a828b	805	DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
<>	156:95d6b41a828b	806	OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	156:95d6b41a828b	807	}
<>	156:95d6b41a828b	808
<>	156:95d6b41a828b	809	/**
<>	156:95d6b41a828b	810	* @brief Get the output buffer state for the selected DAC channel.
<>	156:95d6b41a828b	811	* @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
<>	156:95d6b41a828b	812	* CR BOFF2 LL_DAC_GetOutputBuffer
<>	156:95d6b41a828b	813	* @param DACx DAC instance
<>	156:95d6b41a828b	814	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	815	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	816	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	817	*
<>	156:95d6b41a828b	818	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	819	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	820	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	821	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
<>	156:95d6b41a828b	822	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
<>	156:95d6b41a828b	823	*/
<>	156:95d6b41a828b	824	__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	156:95d6b41a828b	825	{
<>	156:95d6b41a828b	826	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	156:95d6b41a828b	827	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
<>	156:95d6b41a828b	828	);
<>	156:95d6b41a828b	829	}
<>	156:95d6b41a828b	830
<>	156:95d6b41a828b	831	/**
<>	156:95d6b41a828b	832	* @}
<>	156:95d6b41a828b	833	*/
<>	156:95d6b41a828b	834
<>	156:95d6b41a828b	835	/** @defgroup DAC_LL_EF_DMA_Management DMA Management
<>	156:95d6b41a828b	836	* @{
<>	156:95d6b41a828b	837	*/
<>	156:95d6b41a828b	838
<>	156:95d6b41a828b	839	/**
<>	156:95d6b41a828b	840	* @brief Enable DAC DMA transfer request of the selected channel.
<>	156:95d6b41a828b	841	* @note To configure DMA source address (peripheral address),
<>	156:95d6b41a828b	842	* use function @ref LL_DAC_DMA_GetRegAddr().
<>	156:95d6b41a828b	843	* @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
<>	156:95d6b41a828b	844	* CR DMAEN2 LL_DAC_EnableDMAReq
<>	156:95d6b41a828b	845	* @param DACx DAC instance
<>	156:95d6b41a828b	846	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	847	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	848	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	849	*
<>	156:95d6b41a828b	850	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	851	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	852	* @retval None
<>	156:95d6b41a828b	853	*/
<>	156:95d6b41a828b	854	__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	156:95d6b41a828b	855	{
<>	156:95d6b41a828b	856	SET_BIT(DACx->CR,
<>	156:95d6b41a828b	857	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	156:95d6b41a828b	858	}
<>	156:95d6b41a828b	859
<>	156:95d6b41a828b	860	/**
<>	156:95d6b41a828b	861	* @brief Disable DAC DMA transfer request of the selected channel.
<>	156:95d6b41a828b	862	* @note To configure DMA source address (peripheral address),
<>	156:95d6b41a828b	863	* use function @ref LL_DAC_DMA_GetRegAddr().
<>	156:95d6b41a828b	864	* @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
<>	156:95d6b41a828b	865	* CR DMAEN2 LL_DAC_DisableDMAReq
<>	156:95d6b41a828b	866	* @param DACx DAC instance
<>	156:95d6b41a828b	867	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	868	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	869	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	870	*
<>	156:95d6b41a828b	871	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	872	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	873	* @retval None
<>	156:95d6b41a828b	874	*/
<>	156:95d6b41a828b	875	__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	156:95d6b41a828b	876	{
<>	156:95d6b41a828b	877	CLEAR_BIT(DACx->CR,
<>	156:95d6b41a828b	878	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	156:95d6b41a828b	879	}
<>	156:95d6b41a828b	880
<>	156:95d6b41a828b	881	/**
<>	156:95d6b41a828b	882	* @brief Get DAC DMA transfer request state of the selected channel.
<>	156:95d6b41a828b	883	* (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
<>	156:95d6b41a828b	884	* @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
<>	156:95d6b41a828b	885	* CR DMAEN2 LL_DAC_IsDMAReqEnabled
<>	156:95d6b41a828b	886	* @param DACx DAC instance
<>	156:95d6b41a828b	887	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	888	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	889	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	890	*
<>	156:95d6b41a828b	891	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	892	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	893	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	894	*/
<>	156:95d6b41a828b	895	__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	156:95d6b41a828b	896	{
<>	156:95d6b41a828b	897	return (READ_BIT(DACx->CR,
<>	156:95d6b41a828b	898	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	156:95d6b41a828b	899	== (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
<>	156:95d6b41a828b	900	}
<>	156:95d6b41a828b	901
<>	156:95d6b41a828b	902	/**
<>	156:95d6b41a828b	903	* @brief Function to help to configure DMA transfer to DAC: retrieve the
<>	156:95d6b41a828b	904	* DAC register address from DAC instance and a list of DAC registers
<>	156:95d6b41a828b	905	* intended to be used (most commonly) with DMA transfer.
<>	156:95d6b41a828b	906	* @note These DAC registers are data holding registers:
<>	156:95d6b41a828b	907	* when DAC conversion is requested, DAC generates a DMA transfer
<>	156:95d6b41a828b	908	* request to have data available in DAC data holding registers.
<>	156:95d6b41a828b	909	* @note This macro is intended to be used with LL DMA driver, refer to
<>	156:95d6b41a828b	910	* function "LL_DMA_ConfigAddresses()".
<>	156:95d6b41a828b	911	* Example:
<>	156:95d6b41a828b	912	* LL_DMA_ConfigAddresses(DMA1,
<>	156:95d6b41a828b	913	* LL_DMA_CHANNEL_1,
<>	156:95d6b41a828b	914	* (uint32_t)&< array or variable >,
<>	156:95d6b41a828b	915	* LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
<>	156:95d6b41a828b	916	* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
<>	156:95d6b41a828b	917	* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
<>	156:95d6b41a828b	918	* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
<>	156:95d6b41a828b	919	* DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
<>	156:95d6b41a828b	920	* DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
<>	156:95d6b41a828b	921	* DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
<>	156:95d6b41a828b	922	* DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
<>	156:95d6b41a828b	923	* @param DACx DAC instance
<>	156:95d6b41a828b	924	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	925	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	926	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	927	*
<>	156:95d6b41a828b	928	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	929	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	930	* @param Register This parameter can be one of the following values:
<>	156:95d6b41a828b	931	* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
<>	156:95d6b41a828b	932	* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
<>	156:95d6b41a828b	933	* @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
<>	156:95d6b41a828b	934	* @retval DAC register address
<>	156:95d6b41a828b	935	*/
<>	156:95d6b41a828b	936	__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
<>	156:95d6b41a828b	937	{
<>	156:95d6b41a828b	938	/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
<>	156:95d6b41a828b	939	/* DAC channel selected. */
<>	156:95d6b41a828b	940	return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> Register) & DAC_REG_REGOFFSET_MASK_POSBIT0))));
<>	156:95d6b41a828b	941	}
<>	156:95d6b41a828b	942	/**
<>	156:95d6b41a828b	943	* @}
<>	156:95d6b41a828b	944	*/
<>	156:95d6b41a828b	945
<>	156:95d6b41a828b	946	/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
<>	156:95d6b41a828b	947	* @{
<>	156:95d6b41a828b	948	*/
<>	156:95d6b41a828b	949
<>	156:95d6b41a828b	950	/**
<>	156:95d6b41a828b	951	* @brief Enable DAC selected channel.
<>	156:95d6b41a828b	952	* @rmtoll CR EN1 LL_DAC_Enable\n
<>	156:95d6b41a828b	953	* CR EN2 LL_DAC_Enable
<>	156:95d6b41a828b	954	* @note After enable from off state, DAC channel requires a delay
<>	156:95d6b41a828b	955	* for output voltage to reach accuracy +/- 1 LSB.
<>	156:95d6b41a828b	956	* Refer to device datasheet, parameter "tWAKEUP".
<>	156:95d6b41a828b	957	* @param DACx DAC instance
<>	156:95d6b41a828b	958	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	959	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	960	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	961	*
<>	156:95d6b41a828b	962	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	963	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	964	* @retval None
<>	156:95d6b41a828b	965	*/
<>	156:95d6b41a828b	966	__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	156:95d6b41a828b	967	{
<>	156:95d6b41a828b	968	SET_BIT(DACx->CR,
<>	156:95d6b41a828b	969	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	156:95d6b41a828b	970	}
<>	156:95d6b41a828b	971
<>	156:95d6b41a828b	972	/**
<>	156:95d6b41a828b	973	* @brief Disable DAC selected channel.
<>	156:95d6b41a828b	974	* @rmtoll CR EN1 LL_DAC_Disable\n
<>	156:95d6b41a828b	975	* CR EN2 LL_DAC_Disable
<>	156:95d6b41a828b	976	* @param DACx DAC instance
<>	156:95d6b41a828b	977	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	978	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	979	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	980	*
<>	156:95d6b41a828b	981	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	982	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	983	* @retval None
<>	156:95d6b41a828b	984	*/
<>	156:95d6b41a828b	985	__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	156:95d6b41a828b	986	{
<>	156:95d6b41a828b	987	CLEAR_BIT(DACx->CR,
<>	156:95d6b41a828b	988	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	156:95d6b41a828b	989	}
<>	156:95d6b41a828b	990
<>	156:95d6b41a828b	991	/**
<>	156:95d6b41a828b	992	* @brief Get DAC enable state of the selected channel.
<>	156:95d6b41a828b	993	* (0: DAC channel is disabled, 1: DAC channel is enabled)
<>	156:95d6b41a828b	994	* @rmtoll CR EN1 LL_DAC_IsEnabled\n
<>	156:95d6b41a828b	995	* CR EN2 LL_DAC_IsEnabled
<>	156:95d6b41a828b	996	* @param DACx DAC instance
<>	156:95d6b41a828b	997	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	998	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	999	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	1000	*
<>	156:95d6b41a828b	1001	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	1002	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	1003	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1004	*/
<>	156:95d6b41a828b	1005	__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	156:95d6b41a828b	1006	{
<>	156:95d6b41a828b	1007	return (READ_BIT(DACx->CR,
<>	156:95d6b41a828b	1008	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	156:95d6b41a828b	1009	== (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
<>	156:95d6b41a828b	1010	}
<>	156:95d6b41a828b	1011
<>	156:95d6b41a828b	1012	/**
<>	156:95d6b41a828b	1013	* @brief Enable DAC trigger of the selected channel.
<>	156:95d6b41a828b	1014	* @note - If DAC trigger is disabled, DAC conversion is performed
<>	156:95d6b41a828b	1015	* automatically once the data holding register is updated,
<>	156:95d6b41a828b	1016	* using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
<>	156:95d6b41a828b	1017	* @ref LL_DAC_ConvertData12RightAligned(), ...
<>	156:95d6b41a828b	1018	* - If DAC trigger is enabled, DAC conversion is performed
<>	156:95d6b41a828b	1019	* only when a hardware of software trigger event is occurring.
<>	156:95d6b41a828b	1020	* Select trigger source using
<>	156:95d6b41a828b	1021	* function @ref LL_DAC_SetTriggerSource().
<>	156:95d6b41a828b	1022	* @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
<>	156:95d6b41a828b	1023	* CR TEN2 LL_DAC_EnableTrigger
<>	156:95d6b41a828b	1024	* @param DACx DAC instance
<>	156:95d6b41a828b	1025	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1026	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	1027	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	1028	*
<>	156:95d6b41a828b	1029	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	1030	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	1031	* @retval None
<>	156:95d6b41a828b	1032	*/
<>	156:95d6b41a828b	1033	__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	156:95d6b41a828b	1034	{
<>	156:95d6b41a828b	1035	SET_BIT(DACx->CR,
<>	156:95d6b41a828b	1036	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	156:95d6b41a828b	1037	}
<>	156:95d6b41a828b	1038
<>	156:95d6b41a828b	1039	/**
<>	156:95d6b41a828b	1040	* @brief Disable DAC trigger of the selected channel.
<>	156:95d6b41a828b	1041	* @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
<>	156:95d6b41a828b	1042	* CR TEN2 LL_DAC_DisableTrigger
<>	156:95d6b41a828b	1043	* @param DACx DAC instance
<>	156:95d6b41a828b	1044	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1045	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	1046	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	1047	*
<>	156:95d6b41a828b	1048	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	1049	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	1050	* @retval None
<>	156:95d6b41a828b	1051	*/
<>	156:95d6b41a828b	1052	__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	156:95d6b41a828b	1053	{
<>	156:95d6b41a828b	1054	CLEAR_BIT(DACx->CR,
<>	156:95d6b41a828b	1055	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
<>	156:95d6b41a828b	1056	}
<>	156:95d6b41a828b	1057
<>	156:95d6b41a828b	1058	/**
<>	156:95d6b41a828b	1059	* @brief Get DAC trigger state of the selected channel.
<>	156:95d6b41a828b	1060	* (0: DAC trigger is disabled, 1: DAC trigger is enabled)
<>	156:95d6b41a828b	1061	* @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
<>	156:95d6b41a828b	1062	* CR TEN2 LL_DAC_IsTriggerEnabled
<>	156:95d6b41a828b	1063	* @param DACx DAC instance
<>	156:95d6b41a828b	1064	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1065	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	1066	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	1067	*
<>	156:95d6b41a828b	1068	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	1069	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	1070	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1071	*/
<>	156:95d6b41a828b	1072	__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	156:95d6b41a828b	1073	{
<>	156:95d6b41a828b	1074	return (READ_BIT(DACx->CR,
<>	156:95d6b41a828b	1075	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
<>	156:95d6b41a828b	1076	== (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
<>	156:95d6b41a828b	1077	}
<>	156:95d6b41a828b	1078
<>	156:95d6b41a828b	1079	/**
<>	156:95d6b41a828b	1080	* @brief Trig DAC conversion by software for the selected DAC channel.
<>	156:95d6b41a828b	1081	* @note Preliminarily, DAC trigger must be set to software trigger
<>	156:95d6b41a828b	1082	* using function @ref LL_DAC_SetTriggerSource()
<>	156:95d6b41a828b	1083	* with parameter "LL_DAC_TRIGGER_SOFTWARE".
<>	156:95d6b41a828b	1084	* and DAC trigger must be enabled using
<>	156:95d6b41a828b	1085	* function @ref LL_DAC_EnableTrigger().
<>	156:95d6b41a828b	1086	* @note For devices featuring DAC with 2 channels: this function
<>	156:95d6b41a828b	1087	* can perform a SW start of both DAC channels simultaneously.
<>	156:95d6b41a828b	1088	* Two channels can be selected as parameter.
<>	156:95d6b41a828b	1089	* Example: (LL_DAC_CHANNEL_1 \| LL_DAC_CHANNEL_2)
<>	156:95d6b41a828b	1090	* @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
<>	156:95d6b41a828b	1091	* SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
<>	156:95d6b41a828b	1092	* @param DACx DAC instance
<>	156:95d6b41a828b	1093	* @param DAC_Channel This parameter can a combination of the following values:
<>	156:95d6b41a828b	1094	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	1095	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	1096	*
<>	156:95d6b41a828b	1097	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	1098	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	1099	* @retval None
<>	156:95d6b41a828b	1100	*/
<>	156:95d6b41a828b	1101	__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	156:95d6b41a828b	1102	{
<>	156:95d6b41a828b	1103	SET_BIT(DACx->SWTRIGR,
<>	156:95d6b41a828b	1104	(DAC_Channel & DAC_SWTR_CHX_MASK));
<>	156:95d6b41a828b	1105	}
<>	156:95d6b41a828b	1106
<>	156:95d6b41a828b	1107	/**
<>	156:95d6b41a828b	1108	* @brief Set the data to be loaded in the data holding register
<>	156:95d6b41a828b	1109	* in format 12 bits left alignment (LSB aligned on bit 0),
<>	156:95d6b41a828b	1110	* for the selected DAC channel.
<>	156:95d6b41a828b	1111	* @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
<>	156:95d6b41a828b	1112	* DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
<>	156:95d6b41a828b	1113	* @param DACx DAC instance
<>	156:95d6b41a828b	1114	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1115	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	1116	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	1117	*
<>	156:95d6b41a828b	1118	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	1119	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	1120	* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
<>	156:95d6b41a828b	1121	* @retval None
<>	156:95d6b41a828b	1122	*/
<>	156:95d6b41a828b	1123	__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
<>	156:95d6b41a828b	1124	{
<>	156:95d6b41a828b	1125	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
<>	156:95d6b41a828b	1126
<>	156:95d6b41a828b	1127	MODIFY_REG(*preg,
<>	156:95d6b41a828b	1128	DAC_DHR12R1_DACC1DHR,
<>	156:95d6b41a828b	1129	Data);
<>	156:95d6b41a828b	1130	}
<>	156:95d6b41a828b	1131
<>	156:95d6b41a828b	1132	/**
<>	156:95d6b41a828b	1133	* @brief Set the data to be loaded in the data holding register
<>	156:95d6b41a828b	1134	* in format 12 bits left alignment (MSB aligned on bit 15),
<>	156:95d6b41a828b	1135	* for the selected DAC channel.
<>	156:95d6b41a828b	1136	* @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
<>	156:95d6b41a828b	1137	* DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
<>	156:95d6b41a828b	1138	* @param DACx DAC instance
<>	156:95d6b41a828b	1139	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1140	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	1141	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	1142	*
<>	156:95d6b41a828b	1143	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	1144	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	1145	* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
<>	156:95d6b41a828b	1146	* @retval None
<>	156:95d6b41a828b	1147	*/
<>	156:95d6b41a828b	1148	__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
<>	156:95d6b41a828b	1149	{
<>	156:95d6b41a828b	1150	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
<>	156:95d6b41a828b	1151
<>	156:95d6b41a828b	1152	MODIFY_REG(*preg,
<>	156:95d6b41a828b	1153	DAC_DHR12L1_DACC1DHR,
<>	156:95d6b41a828b	1154	Data);
<>	156:95d6b41a828b	1155	}
<>	156:95d6b41a828b	1156
<>	156:95d6b41a828b	1157	/**
<>	156:95d6b41a828b	1158	* @brief Set the data to be loaded in the data holding register
<>	156:95d6b41a828b	1159	* in format 8 bits left alignment (LSB aligned on bit 0),
<>	156:95d6b41a828b	1160	* for the selected DAC channel.
<>	156:95d6b41a828b	1161	* @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
<>	156:95d6b41a828b	1162	* DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
<>	156:95d6b41a828b	1163	* @param DACx DAC instance
<>	156:95d6b41a828b	1164	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1165	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	1166	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	1167	*
<>	156:95d6b41a828b	1168	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	1169	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	1170	* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
<>	156:95d6b41a828b	1171	* @retval None
<>	156:95d6b41a828b	1172	*/
<>	156:95d6b41a828b	1173	__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
<>	156:95d6b41a828b	1174	{
<>	156:95d6b41a828b	1175	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
<>	156:95d6b41a828b	1176
<>	156:95d6b41a828b	1177	MODIFY_REG(*preg,
<>	156:95d6b41a828b	1178	DAC_DHR8R1_DACC1DHR,
<>	156:95d6b41a828b	1179	Data);
<>	156:95d6b41a828b	1180	}
<>	156:95d6b41a828b	1181
<>	156:95d6b41a828b	1182	#if defined(DAC_CHANNEL2_SUPPORT)
<>	156:95d6b41a828b	1183	/**
<>	156:95d6b41a828b	1184	* @brief Set the data to be loaded in the data holding register
<>	156:95d6b41a828b	1185	* in format 12 bits left alignment (LSB aligned on bit 0),
<>	156:95d6b41a828b	1186	* for both DAC channels.
<>	156:95d6b41a828b	1187	* @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
<>	156:95d6b41a828b	1188	* DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
<>	156:95d6b41a828b	1189	* @param DACx DAC instance
<>	156:95d6b41a828b	1190	* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
<>	156:95d6b41a828b	1191	* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
<>	156:95d6b41a828b	1192	* @retval None
<>	156:95d6b41a828b	1193	*/
<>	156:95d6b41a828b	1194	__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
<>	156:95d6b41a828b	1195	{
<>	156:95d6b41a828b	1196	MODIFY_REG(DACx->DHR12RD,
<>	156:95d6b41a828b	1197	(DAC_DHR12RD_DACC2DHR \| DAC_DHR12RD_DACC1DHR),
<>	156:95d6b41a828b	1198	((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) \| DataChannel1));
<>	156:95d6b41a828b	1199	}
<>	156:95d6b41a828b	1200
<>	156:95d6b41a828b	1201	/**
<>	156:95d6b41a828b	1202	* @brief Set the data to be loaded in the data holding register
<>	156:95d6b41a828b	1203	* in format 12 bits left alignment (MSB aligned on bit 15),
<>	156:95d6b41a828b	1204	* for both DAC channels.
<>	156:95d6b41a828b	1205	* @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
<>	156:95d6b41a828b	1206	* DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
<>	156:95d6b41a828b	1207	* @param DACx DAC instance
<>	156:95d6b41a828b	1208	* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
<>	156:95d6b41a828b	1209	* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
<>	156:95d6b41a828b	1210	* @retval None
<>	156:95d6b41a828b	1211	*/
<>	156:95d6b41a828b	1212	__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
<>	156:95d6b41a828b	1213	{
<>	156:95d6b41a828b	1214	/* Note: Data of DAC channel 2 shift value subtracted of 4 because */
<>	156:95d6b41a828b	1215	/* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
<>	156:95d6b41a828b	1216	/* the 4 LSB must be taken into account for the shift value. */
<>	156:95d6b41a828b	1217	MODIFY_REG(DACx->DHR12LD,
<>	156:95d6b41a828b	1218	(DAC_DHR12LD_DACC2DHR \| DAC_DHR12LD_DACC1DHR),
<>	156:95d6b41a828b	1219	((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) \| DataChannel1));
<>	156:95d6b41a828b	1220	}
<>	156:95d6b41a828b	1221
<>	156:95d6b41a828b	1222	/**
<>	156:95d6b41a828b	1223	* @brief Set the data to be loaded in the data holding register
<>	156:95d6b41a828b	1224	* in format 8 bits left alignment (LSB aligned on bit 0),
<>	156:95d6b41a828b	1225	* for both DAC channels.
<>	156:95d6b41a828b	1226	* @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
<>	156:95d6b41a828b	1227	* DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
<>	156:95d6b41a828b	1228	* @param DACx DAC instance
<>	156:95d6b41a828b	1229	* @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
<>	156:95d6b41a828b	1230	* @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
<>	156:95d6b41a828b	1231	* @retval None
<>	156:95d6b41a828b	1232	*/
<>	156:95d6b41a828b	1233	__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
<>	156:95d6b41a828b	1234	{
<>	156:95d6b41a828b	1235	MODIFY_REG(DACx->DHR8RD,
<>	156:95d6b41a828b	1236	(DAC_DHR8RD_DACC2DHR \| DAC_DHR8RD_DACC1DHR),
<>	156:95d6b41a828b	1237	((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) \| DataChannel1));
<>	156:95d6b41a828b	1238	}
<>	156:95d6b41a828b	1239
<>	156:95d6b41a828b	1240	#endif /* DAC_CHANNEL2_SUPPORT */
<>	156:95d6b41a828b	1241	/**
<>	156:95d6b41a828b	1242	* @brief Retrieve output data currently generated for the selected DAC channel.
<>	156:95d6b41a828b	1243	* @note Whatever alignment and resolution settings
<>	156:95d6b41a828b	1244	* (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
<>	156:95d6b41a828b	1245	* @ref LL_DAC_ConvertData12RightAligned(), ...),
<>	156:95d6b41a828b	1246	* output data format is 12 bits right aligned (LSB aligned on bit 0).
<>	156:95d6b41a828b	1247	* @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
<>	156:95d6b41a828b	1248	* DOR2 DACC2DOR LL_DAC_RetrieveOutputData
<>	156:95d6b41a828b	1249	* @param DACx DAC instance
<>	156:95d6b41a828b	1250	* @param DAC_Channel This parameter can be one of the following values:
<>	156:95d6b41a828b	1251	* @arg @ref LL_DAC_CHANNEL_1
<>	156:95d6b41a828b	1252	* @arg @ref LL_DAC_CHANNEL_2 (1)
<>	156:95d6b41a828b	1253	*
<>	156:95d6b41a828b	1254	* (1) On this STM32 serie, parameter not available on all devices.
<>	156:95d6b41a828b	1255	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	1256	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	156:95d6b41a828b	1257	*/
<>	156:95d6b41a828b	1258	__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
<>	156:95d6b41a828b	1259	{
<>	156:95d6b41a828b	1260	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
<>	156:95d6b41a828b	1261
<>	156:95d6b41a828b	1262	return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
<>	156:95d6b41a828b	1263	}
<>	156:95d6b41a828b	1264
<>	156:95d6b41a828b	1265	/**
<>	156:95d6b41a828b	1266	* @}
<>	156:95d6b41a828b	1267	*/
<>	156:95d6b41a828b	1268
<>	156:95d6b41a828b	1269	/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
<>	156:95d6b41a828b	1270	* @{
<>	156:95d6b41a828b	1271	*/
<>	156:95d6b41a828b	1272	/**
<>	156:95d6b41a828b	1273	* @brief Get DAC underrun flag for DAC channel 1
<>	156:95d6b41a828b	1274	* @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
<>	156:95d6b41a828b	1275	* @param DACx DAC instance
<>	156:95d6b41a828b	1276	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1277	*/
<>	156:95d6b41a828b	1278	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
<>	156:95d6b41a828b	1279	{
<>	156:95d6b41a828b	1280	return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
<>	156:95d6b41a828b	1281	}
<>	156:95d6b41a828b	1282
<>	156:95d6b41a828b	1283	#if defined(DAC_CHANNEL2_SUPPORT)
<>	156:95d6b41a828b	1284	/**
<>	156:95d6b41a828b	1285	* @brief Get DAC underrun flag for DAC channel 2
<>	156:95d6b41a828b	1286	* @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
<>	156:95d6b41a828b	1287	* @param DACx DAC instance
<>	156:95d6b41a828b	1288	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1289	*/
<>	156:95d6b41a828b	1290	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
<>	156:95d6b41a828b	1291	{
<>	156:95d6b41a828b	1292	return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
<>	156:95d6b41a828b	1293	}
<>	156:95d6b41a828b	1294	#endif /* DAC_CHANNEL2_SUPPORT */
<>	156:95d6b41a828b	1295
<>	156:95d6b41a828b	1296	/**
<>	156:95d6b41a828b	1297	* @brief Clear DAC underrun flag for DAC channel 1
<>	156:95d6b41a828b	1298	* @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
<>	156:95d6b41a828b	1299	* @param DACx DAC instance
<>	156:95d6b41a828b	1300	* @retval None
<>	156:95d6b41a828b	1301	*/
<>	156:95d6b41a828b	1302	__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
<>	156:95d6b41a828b	1303	{
<>	156:95d6b41a828b	1304	WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
<>	156:95d6b41a828b	1305	}
<>	156:95d6b41a828b	1306
<>	156:95d6b41a828b	1307	#if defined(DAC_CHANNEL2_SUPPORT)
<>	156:95d6b41a828b	1308	/**
<>	156:95d6b41a828b	1309	* @brief Clear DAC underrun flag for DAC channel 2
<>	156:95d6b41a828b	1310	* @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
<>	156:95d6b41a828b	1311	* @param DACx DAC instance
<>	156:95d6b41a828b	1312	* @retval None
<>	156:95d6b41a828b	1313	*/
<>	156:95d6b41a828b	1314	__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
<>	156:95d6b41a828b	1315	{
<>	156:95d6b41a828b	1316	WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
<>	156:95d6b41a828b	1317	}
<>	156:95d6b41a828b	1318	#endif /* DAC_CHANNEL2_SUPPORT */
<>	156:95d6b41a828b	1319
<>	156:95d6b41a828b	1320	/**
<>	156:95d6b41a828b	1321	* @}
<>	156:95d6b41a828b	1322	*/
<>	156:95d6b41a828b	1323
<>	156:95d6b41a828b	1324	/** @defgroup DAC_LL_EF_IT_Management IT management
<>	156:95d6b41a828b	1325	* @{
<>	156:95d6b41a828b	1326	*/
<>	156:95d6b41a828b	1327
<>	156:95d6b41a828b	1328	/**
<>	156:95d6b41a828b	1329	* @brief Enable DMA underrun interrupt for DAC channel 1
<>	156:95d6b41a828b	1330	* @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
<>	156:95d6b41a828b	1331	* @param DACx DAC instance
<>	156:95d6b41a828b	1332	* @retval None
<>	156:95d6b41a828b	1333	*/
<>	156:95d6b41a828b	1334	__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
<>	156:95d6b41a828b	1335	{
<>	156:95d6b41a828b	1336	SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
<>	156:95d6b41a828b	1337	}
<>	156:95d6b41a828b	1338
<>	156:95d6b41a828b	1339	#if defined(DAC_CHANNEL2_SUPPORT)
<>	156:95d6b41a828b	1340	/**
<>	156:95d6b41a828b	1341	* @brief Enable DMA underrun interrupt for DAC channel 2
<>	156:95d6b41a828b	1342	* @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
<>	156:95d6b41a828b	1343	* @param DACx DAC instance
<>	156:95d6b41a828b	1344	* @retval None
<>	156:95d6b41a828b	1345	*/
<>	156:95d6b41a828b	1346	__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
<>	156:95d6b41a828b	1347	{
<>	156:95d6b41a828b	1348	SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
<>	156:95d6b41a828b	1349	}
<>	156:95d6b41a828b	1350	#endif /* DAC_CHANNEL2_SUPPORT */
<>	156:95d6b41a828b	1351
<>	156:95d6b41a828b	1352	/**
<>	156:95d6b41a828b	1353	* @brief Disable DMA underrun interrupt for DAC channel 1
<>	156:95d6b41a828b	1354	* @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
<>	156:95d6b41a828b	1355	* @param DACx DAC instance
<>	156:95d6b41a828b	1356	* @retval None
<>	156:95d6b41a828b	1357	*/
<>	156:95d6b41a828b	1358	__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
<>	156:95d6b41a828b	1359	{
<>	156:95d6b41a828b	1360	CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
<>	156:95d6b41a828b	1361	}
<>	156:95d6b41a828b	1362
<>	156:95d6b41a828b	1363	#if defined(DAC_CHANNEL2_SUPPORT)
<>	156:95d6b41a828b	1364	/**
<>	156:95d6b41a828b	1365	* @brief Disable DMA underrun interrupt for DAC channel 2
<>	156:95d6b41a828b	1366	* @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
<>	156:95d6b41a828b	1367	* @param DACx DAC instance
<>	156:95d6b41a828b	1368	* @retval None
<>	156:95d6b41a828b	1369	*/
<>	156:95d6b41a828b	1370	__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
<>	156:95d6b41a828b	1371	{
<>	156:95d6b41a828b	1372	CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
<>	156:95d6b41a828b	1373	}
<>	156:95d6b41a828b	1374	#endif /* DAC_CHANNEL2_SUPPORT */
<>	156:95d6b41a828b	1375
<>	156:95d6b41a828b	1376	/**
<>	156:95d6b41a828b	1377	* @brief Get DMA underrun interrupt for DAC channel 1
<>	156:95d6b41a828b	1378	* @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
<>	156:95d6b41a828b	1379	* @param DACx DAC instance
<>	156:95d6b41a828b	1380	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1381	*/
<>	156:95d6b41a828b	1382	__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
<>	156:95d6b41a828b	1383	{
<>	156:95d6b41a828b	1384	return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
<>	156:95d6b41a828b	1385	}
<>	156:95d6b41a828b	1386
<>	156:95d6b41a828b	1387	#if defined(DAC_CHANNEL2_SUPPORT)
<>	156:95d6b41a828b	1388	/**
<>	156:95d6b41a828b	1389	* @brief Get DMA underrun interrupt for DAC channel 2
<>	156:95d6b41a828b	1390	* @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
<>	156:95d6b41a828b	1391	* @param DACx DAC instance
<>	156:95d6b41a828b	1392	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1393	*/
<>	156:95d6b41a828b	1394	__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
<>	156:95d6b41a828b	1395	{
<>	156:95d6b41a828b	1396	return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
<>	156:95d6b41a828b	1397	}
<>	156:95d6b41a828b	1398	#endif /* DAC_CHANNEL2_SUPPORT */
<>	156:95d6b41a828b	1399
<>	156:95d6b41a828b	1400	/**
<>	156:95d6b41a828b	1401	* @}
<>	156:95d6b41a828b	1402	*/
<>	156:95d6b41a828b	1403
<>	156:95d6b41a828b	1404	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	1405	/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
<>	156:95d6b41a828b	1406	* @{
<>	156:95d6b41a828b	1407	*/
<>	156:95d6b41a828b	1408
<>	156:95d6b41a828b	1409	ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
<>	156:95d6b41a828b	1410	ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
<>	156:95d6b41a828b	1411	void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
<>	156:95d6b41a828b	1412
<>	156:95d6b41a828b	1413	/**
<>	156:95d6b41a828b	1414	* @}
<>	156:95d6b41a828b	1415	*/
<>	156:95d6b41a828b	1416	#endif /* USE_FULL_LL_DRIVER */
<>	156:95d6b41a828b	1417
<>	156:95d6b41a828b	1418	/**
<>	156:95d6b41a828b	1419	* @}
<>	156:95d6b41a828b	1420	*/
<>	156:95d6b41a828b	1421
<>	156:95d6b41a828b	1422	/**
<>	156:95d6b41a828b	1423	* @}
<>	156:95d6b41a828b	1424	*/
<>	156:95d6b41a828b	1425
<>	156:95d6b41a828b	1426	#endif /* DAC1 */
<>	156:95d6b41a828b	1427
<>	156:95d6b41a828b	1428	/**
<>	156:95d6b41a828b	1429	* @}
<>	156:95d6b41a828b	1430	*/
<>	156:95d6b41a828b	1431
<>	156:95d6b41a828b	1432	#ifdef __cplusplus
<>	156:95d6b41a828b	1433	}
<>	156:95d6b41a828b	1434	#endif
<>	156:95d6b41a828b	1435
<>	156:95d6b41a828b	1436	#endif /* __STM32F0xx_LL_DAC_H */
<>	156:95d6b41a828b	1437
<>	156:95d6b41a828b	1438	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/