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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_bus.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 156:95d6b41a828b 1 /**
<> 156:95d6b41a828b 2 ******************************************************************************
<> 156:95d6b41a828b 3 * @file stm32f0xx_ll_bus.h
<> 156:95d6b41a828b 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @brief Header file of BUS LL module.
<> 156:95d6b41a828b 6
<> 156:95d6b41a828b 7 @verbatim
<> 156:95d6b41a828b 8 ##### RCC Limitations #####
<> 156:95d6b41a828b 9 ==============================================================================
<> 156:95d6b41a828b 10 [..]
<> 156:95d6b41a828b 11 A delay between an RCC peripheral clock enable and the effective peripheral
<> 156:95d6b41a828b 12 enabling should be taken into account in order to manage the peripheral read/write
<> 156:95d6b41a828b 13 from/to registers.
<> 156:95d6b41a828b 14 (+) This delay depends on the peripheral mapping.
<> 156:95d6b41a828b 15 (++) AHB & APB peripherals, 1 dummy read is necessary
<> 156:95d6b41a828b 16
<> 156:95d6b41a828b 17 [..]
<> 156:95d6b41a828b 18 Workarounds:
<> 156:95d6b41a828b 19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
<> 156:95d6b41a828b 20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
<> 156:95d6b41a828b 21
<> 156:95d6b41a828b 22 @endverbatim
<> 156:95d6b41a828b 23 ******************************************************************************
<> 156:95d6b41a828b 24 * @attention
<> 156:95d6b41a828b 25 *
<> 156:95d6b41a828b 26 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 156:95d6b41a828b 27 *
<> 156:95d6b41a828b 28 * Redistribution and use in source and binary forms, with or without modification,
<> 156:95d6b41a828b 29 * are permitted provided that the following conditions are met:
<> 156:95d6b41a828b 30 * 1. Redistributions of source code must retain the above copyright notice,
<> 156:95d6b41a828b 31 * this list of conditions and the following disclaimer.
<> 156:95d6b41a828b 32 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 156:95d6b41a828b 33 * this list of conditions and the following disclaimer in the documentation
<> 156:95d6b41a828b 34 * and/or other materials provided with the distribution.
<> 156:95d6b41a828b 35 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 156:95d6b41a828b 36 * may be used to endorse or promote products derived from this software
<> 156:95d6b41a828b 37 * without specific prior written permission.
<> 156:95d6b41a828b 38 *
<> 156:95d6b41a828b 39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 156:95d6b41a828b 40 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 156:95d6b41a828b 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 156:95d6b41a828b 42 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 156:95d6b41a828b 43 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 156:95d6b41a828b 44 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 156:95d6b41a828b 45 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 156:95d6b41a828b 46 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 156:95d6b41a828b 47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 156:95d6b41a828b 48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 156:95d6b41a828b 49 *
<> 156:95d6b41a828b 50 ******************************************************************************
<> 156:95d6b41a828b 51 */
<> 156:95d6b41a828b 52
<> 156:95d6b41a828b 53 /* Define to prevent recursive inclusion -------------------------------------*/
<> 156:95d6b41a828b 54 #ifndef __STM32F0xx_LL_BUS_H
<> 156:95d6b41a828b 55 #define __STM32F0xx_LL_BUS_H
<> 156:95d6b41a828b 56
<> 156:95d6b41a828b 57 #ifdef __cplusplus
<> 156:95d6b41a828b 58 extern "C" {
<> 156:95d6b41a828b 59 #endif
<> 156:95d6b41a828b 60
<> 156:95d6b41a828b 61 /* Includes ------------------------------------------------------------------*/
<> 156:95d6b41a828b 62 #include "stm32f0xx.h"
<> 156:95d6b41a828b 63
<> 156:95d6b41a828b 64 /** @addtogroup STM32F0xx_LL_Driver
<> 156:95d6b41a828b 65 * @{
<> 156:95d6b41a828b 66 */
<> 156:95d6b41a828b 67
<> 156:95d6b41a828b 68 #if defined(RCC)
<> 156:95d6b41a828b 69
<> 156:95d6b41a828b 70 /** @defgroup BUS_LL BUS
<> 156:95d6b41a828b 71 * @{
<> 156:95d6b41a828b 72 */
<> 156:95d6b41a828b 73
<> 156:95d6b41a828b 74 /* Private types -------------------------------------------------------------*/
<> 156:95d6b41a828b 75 /* Private variables ---------------------------------------------------------*/
<> 156:95d6b41a828b 76
<> 156:95d6b41a828b 77 /* Private constants ---------------------------------------------------------*/
<> 156:95d6b41a828b 78
<> 156:95d6b41a828b 79 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 80
<> 156:95d6b41a828b 81 /* Exported types ------------------------------------------------------------*/
<> 156:95d6b41a828b 82 /* Exported constants --------------------------------------------------------*/
<> 156:95d6b41a828b 83 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
<> 156:95d6b41a828b 84 * @{
<> 156:95d6b41a828b 85 */
<> 156:95d6b41a828b 86
<> 156:95d6b41a828b 87 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
<> 156:95d6b41a828b 88 * @{
<> 156:95d6b41a828b 89 */
<> 156:95d6b41a828b 90 #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
<> 156:95d6b41a828b 91 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
<> 156:95d6b41a828b 92 #if defined(DMA2)
<> 156:95d6b41a828b 93 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
<> 156:95d6b41a828b 94 #endif /*DMA2*/
<> 156:95d6b41a828b 95 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
<> 156:95d6b41a828b 96 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
<> 156:95d6b41a828b 97 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
<> 156:95d6b41a828b 98 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
<> 156:95d6b41a828b 99 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
<> 156:95d6b41a828b 100 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
<> 156:95d6b41a828b 101 #if defined(GPIOD)
<> 156:95d6b41a828b 102 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
<> 156:95d6b41a828b 103 #endif /*GPIOD*/
<> 156:95d6b41a828b 104 #if defined(GPIOE)
<> 156:95d6b41a828b 105 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
<> 156:95d6b41a828b 106 #endif /*GPIOE*/
<> 156:95d6b41a828b 107 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
<> 156:95d6b41a828b 108 #if defined(TSC)
<> 156:95d6b41a828b 109 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
<> 156:95d6b41a828b 110 #endif /*TSC*/
<> 156:95d6b41a828b 111 /**
<> 156:95d6b41a828b 112 * @}
<> 156:95d6b41a828b 113 */
<> 156:95d6b41a828b 114
<> 156:95d6b41a828b 115 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
<> 156:95d6b41a828b 116 * @{
<> 156:95d6b41a828b 117 */
<> 156:95d6b41a828b 118 #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
<> 156:95d6b41a828b 119 #if defined(TIM2)
<> 156:95d6b41a828b 120 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
<> 156:95d6b41a828b 121 #endif /*TIM2*/
<> 156:95d6b41a828b 122 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
<> 156:95d6b41a828b 123 #if defined(TIM6)
<> 156:95d6b41a828b 124 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
<> 156:95d6b41a828b 125 #endif /*TIM6*/
<> 156:95d6b41a828b 126 #if defined(TIM7)
<> 156:95d6b41a828b 127 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
<> 156:95d6b41a828b 128 #endif /*TIM7*/
<> 156:95d6b41a828b 129 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
<> 156:95d6b41a828b 130 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
<> 156:95d6b41a828b 131 #if defined(SPI2)
<> 156:95d6b41a828b 132 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
<> 156:95d6b41a828b 133 #endif /*SPI2*/
<> 156:95d6b41a828b 134 #if defined(USART2)
<> 156:95d6b41a828b 135 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
<> 156:95d6b41a828b 136 #endif /* USART2 */
<> 156:95d6b41a828b 137 #if defined(USART3)
<> 156:95d6b41a828b 138 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
<> 156:95d6b41a828b 139 #endif /* USART3 */
<> 156:95d6b41a828b 140 #if defined(USART4)
<> 156:95d6b41a828b 141 #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN
<> 156:95d6b41a828b 142 #endif /* USART4 */
<> 156:95d6b41a828b 143 #if defined(USART5)
<> 156:95d6b41a828b 144 #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN
<> 156:95d6b41a828b 145 #endif /* USART5 */
<> 156:95d6b41a828b 146 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
<> 156:95d6b41a828b 147 #if defined(I2C2)
<> 156:95d6b41a828b 148 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
<> 156:95d6b41a828b 149 #endif /*I2C2*/
<> 156:95d6b41a828b 150 #if defined(USB)
<> 156:95d6b41a828b 151 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
<> 156:95d6b41a828b 152 #endif /* USB */
<> 156:95d6b41a828b 153 #if defined(CAN)
<> 156:95d6b41a828b 154 #define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN
<> 156:95d6b41a828b 155 #endif /*CAN*/
<> 156:95d6b41a828b 156 #if defined(CRS)
<> 156:95d6b41a828b 157 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN
<> 156:95d6b41a828b 158 #endif /*CRS*/
<> 156:95d6b41a828b 159 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
<> 156:95d6b41a828b 160 #if defined(DAC)
<> 156:95d6b41a828b 161 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
<> 156:95d6b41a828b 162 #endif /*DAC*/
<> 156:95d6b41a828b 163 #if defined(CEC)
<> 156:95d6b41a828b 164 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
<> 156:95d6b41a828b 165 #endif /*CEC*/
<> 156:95d6b41a828b 166 /**
<> 156:95d6b41a828b 167 * @}
<> 156:95d6b41a828b 168 */
<> 156:95d6b41a828b 169
<> 156:95d6b41a828b 170 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
<> 156:95d6b41a828b 171 * @{
<> 156:95d6b41a828b 172 */
<> 156:95d6b41a828b 173 #define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU
<> 156:95d6b41a828b 174 #define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
<> 156:95d6b41a828b 175 #define LL_APB1_GRP2_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
<> 156:95d6b41a828b 176 #if defined(USART8)
<> 156:95d6b41a828b 177 #define LL_APB1_GRP2_PERIPH_USART8 RCC_APB2ENR_USART8EN
<> 156:95d6b41a828b 178 #endif /*USART8*/
<> 156:95d6b41a828b 179 #if defined(USART7)
<> 156:95d6b41a828b 180 #define LL_APB1_GRP2_PERIPH_USART7 RCC_APB2ENR_USART7EN
<> 156:95d6b41a828b 181 #endif /*USART7*/
<> 156:95d6b41a828b 182 #if defined(USART6)
<> 156:95d6b41a828b 183 #define LL_APB1_GRP2_PERIPH_USART6 RCC_APB2ENR_USART6EN
<> 156:95d6b41a828b 184 #endif /*USART6*/
<> 156:95d6b41a828b 185 #define LL_APB1_GRP2_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
<> 156:95d6b41a828b 186 #define LL_APB1_GRP2_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
<> 156:95d6b41a828b 187 #define LL_APB1_GRP2_PERIPH_USART1 RCC_APB2ENR_USART1EN
<> 156:95d6b41a828b 188 #if defined(TIM15)
<> 156:95d6b41a828b 189 #define LL_APB1_GRP2_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
<> 156:95d6b41a828b 190 #endif /*TIM15*/
<> 156:95d6b41a828b 191 #define LL_APB1_GRP2_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
<> 156:95d6b41a828b 192 #define LL_APB1_GRP2_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
<> 156:95d6b41a828b 193 #define LL_APB1_GRP2_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN
<> 156:95d6b41a828b 194 /**
<> 156:95d6b41a828b 195 * @}
<> 156:95d6b41a828b 196 */
<> 156:95d6b41a828b 197
<> 156:95d6b41a828b 198 /**
<> 156:95d6b41a828b 199 * @}
<> 156:95d6b41a828b 200 */
<> 156:95d6b41a828b 201
<> 156:95d6b41a828b 202 /* Exported macro ------------------------------------------------------------*/
<> 156:95d6b41a828b 203 /* Exported functions --------------------------------------------------------*/
<> 156:95d6b41a828b 204 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
<> 156:95d6b41a828b 205 * @{
<> 156:95d6b41a828b 206 */
<> 156:95d6b41a828b 207
<> 156:95d6b41a828b 208 /** @defgroup BUS_LL_EF_AHB1 AHB1
<> 156:95d6b41a828b 209 * @{
<> 156:95d6b41a828b 210 */
<> 156:95d6b41a828b 211
<> 156:95d6b41a828b 212 /**
<> 156:95d6b41a828b 213 * @brief Enable AHB1 peripherals clock.
<> 156:95d6b41a828b 214 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 215 * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 216 * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 217 * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 218 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 219 * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 220 * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 221 * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 222 * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 223 * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 224 * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 225 * AHBENR TSCEN LL_AHB1_GRP1_EnableClock
<> 156:95d6b41a828b 226 * @param Periphs This parameter can be a combination of the following values:
<> 156:95d6b41a828b 227 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 156:95d6b41a828b 228 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 156:95d6b41a828b 229 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
<> 156:95d6b41a828b 230 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 156:95d6b41a828b 231 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 156:95d6b41a828b 232 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 156:95d6b41a828b 233 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 156:95d6b41a828b 234 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 156:95d6b41a828b 235 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
<> 156:95d6b41a828b 236 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 156:95d6b41a828b 237 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
<> 156:95d6b41a828b 238 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
<> 156:95d6b41a828b 239 *
<> 156:95d6b41a828b 240 * (*) value not defined in all devices.
<> 156:95d6b41a828b 241 * @retval None
<> 156:95d6b41a828b 242 */
<> 156:95d6b41a828b 243 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
<> 156:95d6b41a828b 244 {
<> 156:95d6b41a828b 245 __IO uint32_t tmpreg;
<> 156:95d6b41a828b 246 SET_BIT(RCC->AHBENR, Periphs);
<> 156:95d6b41a828b 247 /* Delay after an RCC peripheral clock enabling */
<> 156:95d6b41a828b 248 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
<> 156:95d6b41a828b 249 (void)tmpreg;
<> 156:95d6b41a828b 250 }
<> 156:95d6b41a828b 251
<> 156:95d6b41a828b 252 /**
<> 156:95d6b41a828b 253 * @brief Check if AHB1 peripheral clock is enabled or not
<> 156:95d6b41a828b 254 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 255 * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 256 * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 257 * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 258 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 259 * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 260 * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 261 * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 262 * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 263 * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 264 * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 265 * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock
<> 156:95d6b41a828b 266 * @param Periphs This parameter can be a combination of the following values:
<> 156:95d6b41a828b 267 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 156:95d6b41a828b 268 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 156:95d6b41a828b 269 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
<> 156:95d6b41a828b 270 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 156:95d6b41a828b 271 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 156:95d6b41a828b 272 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 156:95d6b41a828b 273 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 156:95d6b41a828b 274 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 156:95d6b41a828b 275 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
<> 156:95d6b41a828b 276 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 156:95d6b41a828b 277 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
<> 156:95d6b41a828b 278 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
<> 156:95d6b41a828b 279 *
<> 156:95d6b41a828b 280 * (*) value not defined in all devices.
<> 156:95d6b41a828b 281 * @retval State of Periphs (1 or 0).
<> 156:95d6b41a828b 282 */
<> 156:95d6b41a828b 283 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
<> 156:95d6b41a828b 284 {
<> 156:95d6b41a828b 285 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
<> 156:95d6b41a828b 286 }
<> 156:95d6b41a828b 287
<> 156:95d6b41a828b 288 /**
<> 156:95d6b41a828b 289 * @brief Disable AHB1 peripherals clock.
<> 156:95d6b41a828b 290 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 291 * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 292 * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 293 * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 294 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 295 * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 296 * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 297 * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 298 * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 299 * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 300 * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 301 * AHBENR TSCEN LL_AHB1_GRP1_DisableClock
<> 156:95d6b41a828b 302 * @param Periphs This parameter can be a combination of the following values:
<> 156:95d6b41a828b 303 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 156:95d6b41a828b 304 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 156:95d6b41a828b 305 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
<> 156:95d6b41a828b 306 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 156:95d6b41a828b 307 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 156:95d6b41a828b 308 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 156:95d6b41a828b 309 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 156:95d6b41a828b 310 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 156:95d6b41a828b 311 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
<> 156:95d6b41a828b 312 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 156:95d6b41a828b 313 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
<> 156:95d6b41a828b 314 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
<> 156:95d6b41a828b 315 *
<> 156:95d6b41a828b 316 * (*) value not defined in all devices.
<> 156:95d6b41a828b 317 * @retval None
<> 156:95d6b41a828b 318 */
<> 156:95d6b41a828b 319 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
<> 156:95d6b41a828b 320 {
<> 156:95d6b41a828b 321 CLEAR_BIT(RCC->AHBENR, Periphs);
<> 156:95d6b41a828b 322 }
<> 156:95d6b41a828b 323
<> 156:95d6b41a828b 324 /**
<> 156:95d6b41a828b 325 * @brief Force AHB1 peripherals reset.
<> 156:95d6b41a828b 326 * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 327 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 328 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 329 * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 330 * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 331 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 332 * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset
<> 156:95d6b41a828b 333 * @param Periphs This parameter can be a combination of the following values:
<> 156:95d6b41a828b 334 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
<> 156:95d6b41a828b 335 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 156:95d6b41a828b 336 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 156:95d6b41a828b 337 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 156:95d6b41a828b 338 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
<> 156:95d6b41a828b 339 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 156:95d6b41a828b 340 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
<> 156:95d6b41a828b 341 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
<> 156:95d6b41a828b 342 *
<> 156:95d6b41a828b 343 * (*) value not defined in all devices.
<> 156:95d6b41a828b 344 * @retval None
<> 156:95d6b41a828b 345 */
<> 156:95d6b41a828b 346 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
<> 156:95d6b41a828b 347 {
<> 156:95d6b41a828b 348 SET_BIT(RCC->AHBRSTR, Periphs);
<> 156:95d6b41a828b 349 }
<> 156:95d6b41a828b 350
<> 156:95d6b41a828b 351 /**
<> 156:95d6b41a828b 352 * @brief Release AHB1 peripherals reset.
<> 156:95d6b41a828b 353 * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 354 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 355 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 356 * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 357 * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 358 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 359 * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset
<> 156:95d6b41a828b 360 * @param Periphs This parameter can be a combination of the following values:
<> 156:95d6b41a828b 361 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
<> 156:95d6b41a828b 362 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 156:95d6b41a828b 363 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 156:95d6b41a828b 364 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 156:95d6b41a828b 365 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
<> 156:95d6b41a828b 366 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 156:95d6b41a828b 367 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
<> 156:95d6b41a828b 368 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
<> 156:95d6b41a828b 369 *
<> 156:95d6b41a828b 370 * (*) value not defined in all devices.
<> 156:95d6b41a828b 371 * @retval None
<> 156:95d6b41a828b 372 */
<> 156:95d6b41a828b 373 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
<> 156:95d6b41a828b 374 {
<> 156:95d6b41a828b 375 CLEAR_BIT(RCC->AHBRSTR, Periphs);
<> 156:95d6b41a828b 376 }
<> 156:95d6b41a828b 377
<> 156:95d6b41a828b 378 /**
<> 156:95d6b41a828b 379 * @}
<> 156:95d6b41a828b 380 */
<> 156:95d6b41a828b 381
<> 156:95d6b41a828b 382 /** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1
<> 156:95d6b41a828b 383 * @{
<> 156:95d6b41a828b 384 */
<> 156:95d6b41a828b 385
<> 156:95d6b41a828b 386 /**
<> 156:95d6b41a828b 387 * @brief Enable APB1 peripherals clock (available in register 1).
<> 156:95d6b41a828b 388 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 389 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 390 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 391 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 392 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 393 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 394 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 395 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 396 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 397 * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 398 * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 399 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 400 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 401 * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 402 * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 403 * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 404 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 405 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
<> 156:95d6b41a828b 406 * APB1ENR CECEN LL_APB1_GRP1_EnableClock
<> 156:95d6b41a828b 407 * @param Periphs This parameter can be a combination of the following values:
<> 156:95d6b41a828b 408 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
<> 156:95d6b41a828b 409 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 156:95d6b41a828b 410 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
<> 156:95d6b41a828b 411 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
<> 156:95d6b41a828b 412 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
<> 156:95d6b41a828b 413 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 156:95d6b41a828b 414 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
<> 156:95d6b41a828b 415 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
<> 156:95d6b41a828b 416 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
<> 156:95d6b41a828b 417 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
<> 156:95d6b41a828b 418 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
<> 156:95d6b41a828b 419 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 156:95d6b41a828b 420 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
<> 156:95d6b41a828b 421 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
<> 156:95d6b41a828b 422 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
<> 156:95d6b41a828b 423 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
<> 156:95d6b41a828b 424 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 156:95d6b41a828b 425 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
<> 156:95d6b41a828b 426 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
<> 156:95d6b41a828b 427 *
<> 156:95d6b41a828b 428 * (*) value not defined in all devices.
<> 156:95d6b41a828b 429 * @retval None
<> 156:95d6b41a828b 430 */
<> 156:95d6b41a828b 431 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
<> 156:95d6b41a828b 432 {
<> 156:95d6b41a828b 433 __IO uint32_t tmpreg;
<> 156:95d6b41a828b 434 SET_BIT(RCC->APB1ENR, Periphs);
<> 156:95d6b41a828b 435 /* Delay after an RCC peripheral clock enabling */
<> 156:95d6b41a828b 436 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
<> 156:95d6b41a828b 437 (void)tmpreg;
<> 156:95d6b41a828b 438 }
<> 156:95d6b41a828b 439
<> 156:95d6b41a828b 440 /**
<> 156:95d6b41a828b 441 * @brief Check if APB1 peripheral clock is enabled or not (available in register 1).
<> 156:95d6b41a828b 442 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 443 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 444 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 445 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 446 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 447 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 448 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 449 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 450 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 451 * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 452 * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 453 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 454 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 455 * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 456 * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 457 * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 458 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 459 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
<> 156:95d6b41a828b 460 * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock
<> 156:95d6b41a828b 461 * @param Periphs This parameter can be a combination of the following values:
<> 156:95d6b41a828b 462 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
<> 156:95d6b41a828b 463 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 156:95d6b41a828b 464 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
<> 156:95d6b41a828b 465 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
<> 156:95d6b41a828b 466 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
<> 156:95d6b41a828b 467 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 156:95d6b41a828b 468 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
<> 156:95d6b41a828b 469 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
<> 156:95d6b41a828b 470 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
<> 156:95d6b41a828b 471 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
<> 156:95d6b41a828b 472 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
<> 156:95d6b41a828b 473 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 156:95d6b41a828b 474 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
<> 156:95d6b41a828b 475 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
<> 156:95d6b41a828b 476 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
<> 156:95d6b41a828b 477 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
<> 156:95d6b41a828b 478 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 156:95d6b41a828b 479 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
<> 156:95d6b41a828b 480 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
<> 156:95d6b41a828b 481 *
<> 156:95d6b41a828b 482 * (*) value not defined in all devices.
<> 156:95d6b41a828b 483 * @retval State of Periphs (1 or 0).
<> 156:95d6b41a828b 484 */
<> 156:95d6b41a828b 485 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
<> 156:95d6b41a828b 486 {
<> 156:95d6b41a828b 487 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
<> 156:95d6b41a828b 488 }
<> 156:95d6b41a828b 489
<> 156:95d6b41a828b 490 /**
<> 156:95d6b41a828b 491 * @brief Disable APB1 peripherals clock (available in register 1).
<> 156:95d6b41a828b 492 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 493 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 494 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 495 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 496 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 497 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 498 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 499 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 500 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 501 * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 502 * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 503 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 504 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 505 * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 506 * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 507 * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 508 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 509 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
<> 156:95d6b41a828b 510 * APB1ENR CECEN LL_APB1_GRP1_DisableClock
<> 156:95d6b41a828b 511 * @param Periphs This parameter can be a combination of the following values:
<> 156:95d6b41a828b 512 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
<> 156:95d6b41a828b 513 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 156:95d6b41a828b 514 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
<> 156:95d6b41a828b 515 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
<> 156:95d6b41a828b 516 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
<> 156:95d6b41a828b 517 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 156:95d6b41a828b 518 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
<> 156:95d6b41a828b 519 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
<> 156:95d6b41a828b 520 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
<> 156:95d6b41a828b 521 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
<> 156:95d6b41a828b 522 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
<> 156:95d6b41a828b 523 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 156:95d6b41a828b 524 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
<> 156:95d6b41a828b 525 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
<> 156:95d6b41a828b 526 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
<> 156:95d6b41a828b 527 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
<> 156:95d6b41a828b 528 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 156:95d6b41a828b 529 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
<> 156:95d6b41a828b 530 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
<> 156:95d6b41a828b 531 *
<> 156:95d6b41a828b 532 * (*) value not defined in all devices.
<> 156:95d6b41a828b 533 * @retval None
<> 156:95d6b41a828b 534 */
<> 156:95d6b41a828b 535 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
<> 156:95d6b41a828b 536 {
<> 156:95d6b41a828b 537 CLEAR_BIT(RCC->APB1ENR, Periphs);
<> 156:95d6b41a828b 538 }
<> 156:95d6b41a828b 539
<> 156:95d6b41a828b 540 /**
<> 156:95d6b41a828b 541 * @brief Force APB1 peripherals reset (available in register 1).
<> 156:95d6b41a828b 542 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 543 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 544 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 545 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 546 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 547 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 548 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 549 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 550 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 551 * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 552 * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 553 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 554 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 555 * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 556 * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 557 * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 558 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 559 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
<> 156:95d6b41a828b 560 * APB1RSTR CECRST LL_APB1_GRP1_ForceReset
<> 156:95d6b41a828b 561 * @param Periphs This parameter can be a combination of the following values:
<> 156:95d6b41a828b 562 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
<> 156:95d6b41a828b 563 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
<> 156:95d6b41a828b 564 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 156:95d6b41a828b 565 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
<> 156:95d6b41a828b 566 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
<> 156:95d6b41a828b 567 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
<> 156:95d6b41a828b 568 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 156:95d6b41a828b 569 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
<> 156:95d6b41a828b 570 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
<> 156:95d6b41a828b 571 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
<> 156:95d6b41a828b 572 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
<> 156:95d6b41a828b 573 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
<> 156:95d6b41a828b 574 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 156:95d6b41a828b 575 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
<> 156:95d6b41a828b 576 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
<> 156:95d6b41a828b 577 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
<> 156:95d6b41a828b 578 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
<> 156:95d6b41a828b 579 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 156:95d6b41a828b 580 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
<> 156:95d6b41a828b 581 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
<> 156:95d6b41a828b 582 *
<> 156:95d6b41a828b 583 * (*) value not defined in all devices.
<> 156:95d6b41a828b 584 * @retval None
<> 156:95d6b41a828b 585 */
<> 156:95d6b41a828b 586 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
<> 156:95d6b41a828b 587 {
<> 156:95d6b41a828b 588 SET_BIT(RCC->APB1RSTR, Periphs);
<> 156:95d6b41a828b 589 }
<> 156:95d6b41a828b 590
<> 156:95d6b41a828b 591 /**
<> 156:95d6b41a828b 592 * @brief Release APB1 peripherals reset (available in register 1).
<> 156:95d6b41a828b 593 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 594 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 595 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 596 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 597 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 598 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 599 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 600 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 601 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 602 * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 603 * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 604 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 605 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 606 * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 607 * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 608 * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 609 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 610 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
<> 156:95d6b41a828b 611 * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset
<> 156:95d6b41a828b 612 * @param Periphs This parameter can be a combination of the following values:
<> 156:95d6b41a828b 613 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
<> 156:95d6b41a828b 614 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
<> 156:95d6b41a828b 615 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 156:95d6b41a828b 616 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
<> 156:95d6b41a828b 617 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
<> 156:95d6b41a828b 618 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
<> 156:95d6b41a828b 619 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 156:95d6b41a828b 620 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
<> 156:95d6b41a828b 621 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
<> 156:95d6b41a828b 622 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
<> 156:95d6b41a828b 623 * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
<> 156:95d6b41a828b 624 * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
<> 156:95d6b41a828b 625 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 156:95d6b41a828b 626 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
<> 156:95d6b41a828b 627 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
<> 156:95d6b41a828b 628 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
<> 156:95d6b41a828b 629 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
<> 156:95d6b41a828b 630 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 156:95d6b41a828b 631 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
<> 156:95d6b41a828b 632 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
<> 156:95d6b41a828b 633 *
<> 156:95d6b41a828b 634 * (*) value not defined in all devices.
<> 156:95d6b41a828b 635 * @retval None
<> 156:95d6b41a828b 636 */
<> 156:95d6b41a828b 637 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
<> 156:95d6b41a828b 638 {
<> 156:95d6b41a828b 639 CLEAR_BIT(RCC->APB1RSTR, Periphs);
<> 156:95d6b41a828b 640 }
<> 156:95d6b41a828b 641
<> 156:95d6b41a828b 642 /**
<> 156:95d6b41a828b 643 * @}
<> 156:95d6b41a828b 644 */
<> 156:95d6b41a828b 645
<> 156:95d6b41a828b 646 /** @defgroup BUS_LL_EF_APB1_GRP2 APB1 GRP2
<> 156:95d6b41a828b 647 * @{
<> 156:95d6b41a828b 648 */
<> 156:95d6b41a828b 649
<> 156:95d6b41a828b 650 /**
<> 156:95d6b41a828b 651 * @brief Enable APB1 peripherals clock (available in register 2).
<> 156:95d6b41a828b 652 * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_EnableClock\n
<> 156:95d6b41a828b 653 * APB2ENR ADC1EN LL_APB1_GRP2_EnableClock\n
<> 156:95d6b41a828b 654 * APB2ENR USART8EN LL_APB1_GRP2_EnableClock\n
<> 156:95d6b41a828b 655 * APB2ENR USART7EN LL_APB1_GRP2_EnableClock\n
<> 156:95d6b41a828b 656 * APB2ENR USART6EN LL_APB1_GRP2_EnableClock\n
<> 156:95d6b41a828b 657 * APB2ENR TIM1EN LL_APB1_GRP2_EnableClock\n
<> 156:95d6b41a828b 658 * APB2ENR SPI1EN LL_APB1_GRP2_EnableClock\n
<> 156:95d6b41a828b 659 * APB2ENR USART1EN LL_APB1_GRP2_EnableClock\n
<> 156:95d6b41a828b 660 * APB2ENR TIM15EN LL_APB1_GRP2_EnableClock\n
<> 156:95d6b41a828b 661 * APB2ENR TIM16EN LL_APB1_GRP2_EnableClock\n
<> 156:95d6b41a828b 662 * APB2ENR TIM17EN LL_APB1_GRP2_EnableClock\n
<> 156:95d6b41a828b 663 * APB2ENR DBGMCUEN LL_APB1_GRP2_EnableClock
<> 156:95d6b41a828b 664 * @param Periphs This parameter can be a combination of the following values:
<> 156:95d6b41a828b 665 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
<> 156:95d6b41a828b 666 * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
<> 156:95d6b41a828b 667 * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
<> 156:95d6b41a828b 668 * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
<> 156:95d6b41a828b 669 * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
<> 156:95d6b41a828b 670 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
<> 156:95d6b41a828b 671 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
<> 156:95d6b41a828b 672 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
<> 156:95d6b41a828b 673 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
<> 156:95d6b41a828b 674 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
<> 156:95d6b41a828b 675 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
<> 156:95d6b41a828b 676 * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
<> 156:95d6b41a828b 677 *
<> 156:95d6b41a828b 678 * (*) value not defined in all devices.
<> 156:95d6b41a828b 679 * @retval None
<> 156:95d6b41a828b 680 */
<> 156:95d6b41a828b 681 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
<> 156:95d6b41a828b 682 {
<> 156:95d6b41a828b 683 __IO uint32_t tmpreg;
<> 156:95d6b41a828b 684 SET_BIT(RCC->APB2ENR, Periphs);
<> 156:95d6b41a828b 685 /* Delay after an RCC peripheral clock enabling */
<> 156:95d6b41a828b 686 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
<> 156:95d6b41a828b 687 (void)tmpreg;
<> 156:95d6b41a828b 688 }
<> 156:95d6b41a828b 689
<> 156:95d6b41a828b 690 /**
<> 156:95d6b41a828b 691 * @brief Check if APB1 peripheral clock is enabled or not (available in register 2).
<> 156:95d6b41a828b 692 * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_IsEnabledClock\n
<> 156:95d6b41a828b 693 * APB2ENR ADC1EN LL_APB1_GRP2_IsEnabledClock\n
<> 156:95d6b41a828b 694 * APB2ENR USART8EN LL_APB1_GRP2_IsEnabledClock\n
<> 156:95d6b41a828b 695 * APB2ENR USART7EN LL_APB1_GRP2_IsEnabledClock\n
<> 156:95d6b41a828b 696 * APB2ENR USART6EN LL_APB1_GRP2_IsEnabledClock\n
<> 156:95d6b41a828b 697 * APB2ENR TIM1EN LL_APB1_GRP2_IsEnabledClock\n
<> 156:95d6b41a828b 698 * APB2ENR SPI1EN LL_APB1_GRP2_IsEnabledClock\n
<> 156:95d6b41a828b 699 * APB2ENR USART1EN LL_APB1_GRP2_IsEnabledClock\n
<> 156:95d6b41a828b 700 * APB2ENR TIM15EN LL_APB1_GRP2_IsEnabledClock\n
<> 156:95d6b41a828b 701 * APB2ENR TIM16EN LL_APB1_GRP2_IsEnabledClock\n
<> 156:95d6b41a828b 702 * APB2ENR TIM17EN LL_APB1_GRP2_IsEnabledClock\n
<> 156:95d6b41a828b 703 * APB2ENR DBGMCUEN LL_APB1_GRP2_IsEnabledClock
<> 156:95d6b41a828b 704 * @param Periphs This parameter can be a combination of the following values:
<> 156:95d6b41a828b 705 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
<> 156:95d6b41a828b 706 * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
<> 156:95d6b41a828b 707 * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
<> 156:95d6b41a828b 708 * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
<> 156:95d6b41a828b 709 * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
<> 156:95d6b41a828b 710 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
<> 156:95d6b41a828b 711 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
<> 156:95d6b41a828b 712 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
<> 156:95d6b41a828b 713 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
<> 156:95d6b41a828b 714 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
<> 156:95d6b41a828b 715 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
<> 156:95d6b41a828b 716 * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
<> 156:95d6b41a828b 717 *
<> 156:95d6b41a828b 718 * (*) value not defined in all devices.
<> 156:95d6b41a828b 719 * @retval State of Periphs (1 or 0).
<> 156:95d6b41a828b 720 */
<> 156:95d6b41a828b 721 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
<> 156:95d6b41a828b 722 {
<> 156:95d6b41a828b 723 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
<> 156:95d6b41a828b 724 }
<> 156:95d6b41a828b 725
<> 156:95d6b41a828b 726 /**
<> 156:95d6b41a828b 727 * @brief Disable APB1 peripherals clock (available in register 2).
<> 156:95d6b41a828b 728 * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_DisableClock\n
<> 156:95d6b41a828b 729 * APB2ENR ADC1EN LL_APB1_GRP2_DisableClock\n
<> 156:95d6b41a828b 730 * APB2ENR USART8EN LL_APB1_GRP2_DisableClock\n
<> 156:95d6b41a828b 731 * APB2ENR USART7EN LL_APB1_GRP2_DisableClock\n
<> 156:95d6b41a828b 732 * APB2ENR USART6EN LL_APB1_GRP2_DisableClock\n
<> 156:95d6b41a828b 733 * APB2ENR TIM1EN LL_APB1_GRP2_DisableClock\n
<> 156:95d6b41a828b 734 * APB2ENR SPI1EN LL_APB1_GRP2_DisableClock\n
<> 156:95d6b41a828b 735 * APB2ENR USART1EN LL_APB1_GRP2_DisableClock\n
<> 156:95d6b41a828b 736 * APB2ENR TIM15EN LL_APB1_GRP2_DisableClock\n
<> 156:95d6b41a828b 737 * APB2ENR TIM16EN LL_APB1_GRP2_DisableClock\n
<> 156:95d6b41a828b 738 * APB2ENR TIM17EN LL_APB1_GRP2_DisableClock\n
<> 156:95d6b41a828b 739 * APB2ENR DBGMCUEN LL_APB1_GRP2_DisableClock
<> 156:95d6b41a828b 740 * @param Periphs This parameter can be a combination of the following values:
<> 156:95d6b41a828b 741 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
<> 156:95d6b41a828b 742 * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
<> 156:95d6b41a828b 743 * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
<> 156:95d6b41a828b 744 * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
<> 156:95d6b41a828b 745 * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
<> 156:95d6b41a828b 746 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
<> 156:95d6b41a828b 747 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
<> 156:95d6b41a828b 748 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
<> 156:95d6b41a828b 749 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
<> 156:95d6b41a828b 750 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
<> 156:95d6b41a828b 751 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
<> 156:95d6b41a828b 752 * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
<> 156:95d6b41a828b 753 *
<> 156:95d6b41a828b 754 * (*) value not defined in all devices.
<> 156:95d6b41a828b 755 * @retval None
<> 156:95d6b41a828b 756 */
<> 156:95d6b41a828b 757 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
<> 156:95d6b41a828b 758 {
<> 156:95d6b41a828b 759 CLEAR_BIT(RCC->APB2ENR, Periphs);
<> 156:95d6b41a828b 760 }
<> 156:95d6b41a828b 761
<> 156:95d6b41a828b 762 /**
<> 156:95d6b41a828b 763 * @brief Force APB1 peripherals reset (available in register 2).
<> 156:95d6b41a828b 764 * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ForceReset\n
<> 156:95d6b41a828b 765 * APB2RSTR ADC1RST LL_APB1_GRP2_ForceReset\n
<> 156:95d6b41a828b 766 * APB2RSTR USART8RST LL_APB1_GRP2_ForceReset\n
<> 156:95d6b41a828b 767 * APB2RSTR USART7RST LL_APB1_GRP2_ForceReset\n
<> 156:95d6b41a828b 768 * APB2RSTR USART6RST LL_APB1_GRP2_ForceReset\n
<> 156:95d6b41a828b 769 * APB2RSTR TIM1RST LL_APB1_GRP2_ForceReset\n
<> 156:95d6b41a828b 770 * APB2RSTR SPI1RST LL_APB1_GRP2_ForceReset\n
<> 156:95d6b41a828b 771 * APB2RSTR USART1RST LL_APB1_GRP2_ForceReset\n
<> 156:95d6b41a828b 772 * APB2RSTR TIM15RST LL_APB1_GRP2_ForceReset\n
<> 156:95d6b41a828b 773 * APB2RSTR TIM16RST LL_APB1_GRP2_ForceReset\n
<> 156:95d6b41a828b 774 * APB2RSTR TIM17RST LL_APB1_GRP2_ForceReset\n
<> 156:95d6b41a828b 775 * APB2RSTR DBGMCURST LL_APB1_GRP2_ForceReset
<> 156:95d6b41a828b 776 * @param Periphs This parameter can be a combination of the following values:
<> 156:95d6b41a828b 777 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
<> 156:95d6b41a828b 778 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
<> 156:95d6b41a828b 779 * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
<> 156:95d6b41a828b 780 * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
<> 156:95d6b41a828b 781 * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
<> 156:95d6b41a828b 782 * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
<> 156:95d6b41a828b 783 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
<> 156:95d6b41a828b 784 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
<> 156:95d6b41a828b 785 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
<> 156:95d6b41a828b 786 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
<> 156:95d6b41a828b 787 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
<> 156:95d6b41a828b 788 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
<> 156:95d6b41a828b 789 * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
<> 156:95d6b41a828b 790 *
<> 156:95d6b41a828b 791 * (*) value not defined in all devices.
<> 156:95d6b41a828b 792 * @retval None
<> 156:95d6b41a828b 793 */
<> 156:95d6b41a828b 794 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
<> 156:95d6b41a828b 795 {
<> 156:95d6b41a828b 796 SET_BIT(RCC->APB2RSTR, Periphs);
<> 156:95d6b41a828b 797 }
<> 156:95d6b41a828b 798
<> 156:95d6b41a828b 799 /**
<> 156:95d6b41a828b 800 * @brief Release APB1 peripherals reset (available in register 2).
<> 156:95d6b41a828b 801 * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ReleaseReset\n
<> 156:95d6b41a828b 802 * APB2RSTR ADC1RST LL_APB1_GRP2_ReleaseReset\n
<> 156:95d6b41a828b 803 * APB2RSTR USART8RST LL_APB1_GRP2_ReleaseReset\n
<> 156:95d6b41a828b 804 * APB2RSTR USART7RST LL_APB1_GRP2_ReleaseReset\n
<> 156:95d6b41a828b 805 * APB2RSTR USART6RST LL_APB1_GRP2_ReleaseReset\n
<> 156:95d6b41a828b 806 * APB2RSTR TIM1RST LL_APB1_GRP2_ReleaseReset\n
<> 156:95d6b41a828b 807 * APB2RSTR SPI1RST LL_APB1_GRP2_ReleaseReset\n
<> 156:95d6b41a828b 808 * APB2RSTR USART1RST LL_APB1_GRP2_ReleaseReset\n
<> 156:95d6b41a828b 809 * APB2RSTR TIM15RST LL_APB1_GRP2_ReleaseReset\n
<> 156:95d6b41a828b 810 * APB2RSTR TIM16RST LL_APB1_GRP2_ReleaseReset\n
<> 156:95d6b41a828b 811 * APB2RSTR TIM17RST LL_APB1_GRP2_ReleaseReset\n
<> 156:95d6b41a828b 812 * APB2RSTR DBGMCURST LL_APB1_GRP2_ReleaseReset
<> 156:95d6b41a828b 813 * @param Periphs This parameter can be a combination of the following values:
<> 156:95d6b41a828b 814 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
<> 156:95d6b41a828b 815 * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
<> 156:95d6b41a828b 816 * @arg @ref LL_APB1_GRP2_PERIPH_ADC1
<> 156:95d6b41a828b 817 * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
<> 156:95d6b41a828b 818 * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
<> 156:95d6b41a828b 819 * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
<> 156:95d6b41a828b 820 * @arg @ref LL_APB1_GRP2_PERIPH_TIM1
<> 156:95d6b41a828b 821 * @arg @ref LL_APB1_GRP2_PERIPH_SPI1
<> 156:95d6b41a828b 822 * @arg @ref LL_APB1_GRP2_PERIPH_USART1
<> 156:95d6b41a828b 823 * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
<> 156:95d6b41a828b 824 * @arg @ref LL_APB1_GRP2_PERIPH_TIM16
<> 156:95d6b41a828b 825 * @arg @ref LL_APB1_GRP2_PERIPH_TIM17
<> 156:95d6b41a828b 826 * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
<> 156:95d6b41a828b 827 *
<> 156:95d6b41a828b 828 * (*) value not defined in all devices.
<> 156:95d6b41a828b 829 * @retval None
<> 156:95d6b41a828b 830 */
<> 156:95d6b41a828b 831 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
<> 156:95d6b41a828b 832 {
<> 156:95d6b41a828b 833 CLEAR_BIT(RCC->APB2RSTR, Periphs);
<> 156:95d6b41a828b 834 }
<> 156:95d6b41a828b 835
<> 156:95d6b41a828b 836 /**
<> 156:95d6b41a828b 837 * @}
<> 156:95d6b41a828b 838 */
<> 156:95d6b41a828b 839
<> 156:95d6b41a828b 840
<> 156:95d6b41a828b 841 /**
<> 156:95d6b41a828b 842 * @}
<> 156:95d6b41a828b 843 */
<> 156:95d6b41a828b 844
<> 156:95d6b41a828b 845 /**
<> 156:95d6b41a828b 846 * @}
<> 156:95d6b41a828b 847 */
<> 156:95d6b41a828b 848
<> 156:95d6b41a828b 849 #endif /* defined(RCC) */
<> 156:95d6b41a828b 850
<> 156:95d6b41a828b 851 /**
<> 156:95d6b41a828b 852 * @}
<> 156:95d6b41a828b 853 */
<> 156:95d6b41a828b 854
<> 156:95d6b41a828b 855 #ifdef __cplusplus
<> 156:95d6b41a828b 856 }
<> 156:95d6b41a828b 857 #endif
<> 156:95d6b41a828b 858
<> 156:95d6b41a828b 859 #endif /* __STM32F0xx_LL_BUS_H */
<> 156:95d6b41a828b 860
<> 156:95d6b41a828b 861 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/