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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_usart.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_usart.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief USART HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter
<> 144:ef7eb2e8f9f7 8 * Peripheral (USART).
<> 144:ef7eb2e8f9f7 9 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 10 * + IO operation functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 @verbatim
<> 144:ef7eb2e8f9f7 15 ===============================================================================
<> 144:ef7eb2e8f9f7 16 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 17 ===============================================================================
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 The USART HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
<> 144:ef7eb2e8f9f7 22 (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
<> 144:ef7eb2e8f9f7 23 (++) Enable the USARTx interface clock.
<> 144:ef7eb2e8f9f7 24 (++) USART pins configuration:
<> 144:ef7eb2e8f9f7 25 (+++) Enable the clock for the USART GPIOs.
<> 144:ef7eb2e8f9f7 26 (+++) Configure these USART pins as alternate function pull-up.
<> 144:ef7eb2e8f9f7 27 (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
<> 144:ef7eb2e8f9f7 28 HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
<> 144:ef7eb2e8f9f7 29 (+++) Configure the USARTx interrupt priority.
<> 144:ef7eb2e8f9f7 30 (+++) Enable the NVIC USART IRQ handle.
<> 144:ef7eb2e8f9f7 31 (++) USART interrupts handling:
<> 144:ef7eb2e8f9f7 32 -@@- The specific USART interrupts (Transmission complete interrupt,
<> 144:ef7eb2e8f9f7 33 RXNE interrupt and Error Interrupts) will be managed using the macros
<> 144:ef7eb2e8f9f7 34 __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
<> 144:ef7eb2e8f9f7 35 (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
<> 144:ef7eb2e8f9f7 36 HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
<> 144:ef7eb2e8f9f7 37 (+++) Declare a DMA handle structure for the Tx/Rx channel.
<> 144:ef7eb2e8f9f7 38 (+++) Enable the DMAx interface clock.
<> 144:ef7eb2e8f9f7 39 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<> 144:ef7eb2e8f9f7 40 (+++) Configure the DMA Tx/Rx channel.
<> 144:ef7eb2e8f9f7 41 (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
<> 144:ef7eb2e8f9f7 42 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
<> 144:ef7eb2e8f9f7 45 flow control and Mode (Receiver/Transmitter) in the husart handle Init structure.
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 (#) Initialize the USART registers by calling the HAL_USART_Init() API:
<> 144:ef7eb2e8f9f7 48 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<> 144:ef7eb2e8f9f7 49 by calling the customized HAL_USART_MspInit(&husart) API.
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 (#) Three operation modes are available within this driver :
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 54 =================================
<> 144:ef7eb2e8f9f7 55 [..]
<> 144:ef7eb2e8f9f7 56 (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
<> 144:ef7eb2e8f9f7 57 (+) Receive an amount of data in blocking mode using HAL_USART_Receive()
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 60 ===================================
<> 144:ef7eb2e8f9f7 61 [..]
<> 144:ef7eb2e8f9f7 62 (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
<> 144:ef7eb2e8f9f7 63 (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 64 add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
<> 144:ef7eb2e8f9f7 65 (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 66 add his own code by customization of function pointer HAL_USART_TxCpltCallback
<> 144:ef7eb2e8f9f7 67 (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
<> 144:ef7eb2e8f9f7 68 (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 69 add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
<> 144:ef7eb2e8f9f7 70 (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 71 add his own code by customization of function pointer HAL_USART_RxCpltCallback
<> 144:ef7eb2e8f9f7 72 (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 73 add his own code by customization of function pointer HAL_USART_ErrorCallback
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 76 ==============================
<> 144:ef7eb2e8f9f7 77 [..]
<> 144:ef7eb2e8f9f7 78 (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
<> 144:ef7eb2e8f9f7 79 (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 80 add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
<> 144:ef7eb2e8f9f7 81 (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 82 add his own code by customization of function pointer HAL_USART_TxCpltCallback
<> 144:ef7eb2e8f9f7 83 (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
<> 144:ef7eb2e8f9f7 84 (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 85 add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
<> 144:ef7eb2e8f9f7 86 (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 87 add his own code by customization of function pointer HAL_USART_RxCpltCallback
<> 144:ef7eb2e8f9f7 88 (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 89 add his own code by customization of function pointer HAL_USART_ErrorCallback
<> 144:ef7eb2e8f9f7 90 (+) Pause the DMA Transfer using HAL_USART_DMAPause()
<> 144:ef7eb2e8f9f7 91 (+) Resume the DMA Transfer using HAL_USART_DMAResume()
<> 144:ef7eb2e8f9f7 92 (+) Stop the DMA Transfer using HAL_USART_DMAStop()
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 *** USART HAL driver macros list ***
<> 144:ef7eb2e8f9f7 95 =============================================
<> 144:ef7eb2e8f9f7 96 [..]
<> 144:ef7eb2e8f9f7 97 Below the list of most used macros in USART HAL driver.
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 (+) __HAL_USART_ENABLE: Enable the USART peripheral
<> 144:ef7eb2e8f9f7 100 (+) __HAL_USART_DISABLE: Disable the USART peripheral
<> 144:ef7eb2e8f9f7 101 (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
<> 144:ef7eb2e8f9f7 102 (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
<> 144:ef7eb2e8f9f7 103 (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
<> 144:ef7eb2e8f9f7 104 (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 [..]
<> 144:ef7eb2e8f9f7 107 (@) You can refer to the USART HAL driver header file for more useful macros
<> 156:95d6b41a828b 108 [..]
<> 156:95d6b41a828b 109 (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
<> 156:95d6b41a828b 110 HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
<> 156:95d6b41a828b 111 HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 @endverbatim
<> 144:ef7eb2e8f9f7 114 ******************************************************************************
<> 144:ef7eb2e8f9f7 115 * @attention
<> 144:ef7eb2e8f9f7 116 *
<> 144:ef7eb2e8f9f7 117 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 118 *
<> 144:ef7eb2e8f9f7 119 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 120 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 121 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 122 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 123 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 124 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 125 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 126 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 127 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 128 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 129 *
<> 144:ef7eb2e8f9f7 130 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 131 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 132 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 133 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 134 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 135 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 136 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 137 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 138 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 139 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 140 *
<> 144:ef7eb2e8f9f7 141 ******************************************************************************
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 145 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 148 * @{
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /** @defgroup USART USART
<> 144:ef7eb2e8f9f7 152 * @brief HAL USART Synchronous module driver
<> 144:ef7eb2e8f9f7 153 * @{
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 #ifdef HAL_USART_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 159 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 160 /** @defgroup USART_Private_Constants USART Private Constants
<> 144:ef7eb2e8f9f7 161 * @{
<> 144:ef7eb2e8f9f7 162 */
<> 156:95d6b41a828b 163 #define USART_DUMMY_DATA ((uint16_t) 0xFFFFU) /*!< USART transmitted dummy data */
<> 156:95d6b41a828b 164 #define USART_TEACK_REACK_TIMEOUT ( 1000U) /*!< USART TX or RX enable acknowledge time-out value */
<> 144:ef7eb2e8f9f7 165 #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
<> 144:ef7eb2e8f9f7 166 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by USART_SetConfig API */
<> 144:ef7eb2e8f9f7 167 #define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
<> 144:ef7eb2e8f9f7 168 USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */
<> 144:ef7eb2e8f9f7 169 /**
<> 144:ef7eb2e8f9f7 170 * @}
<> 144:ef7eb2e8f9f7 171 */
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 174 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 175 /* Private function prototypes -----------------------------------------------*/
<> 156:95d6b41a828b 176 /** @addtogroup USART_Private_Functions
<> 144:ef7eb2e8f9f7 177 * @{
<> 144:ef7eb2e8f9f7 178 */
<> 156:95d6b41a828b 179 static void USART_EndTransfer(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 180 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 181 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 182 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 183 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 184 static void USART_DMAError(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 185 static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 186 static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 187 static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 188 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 189 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 190 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 191 static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 192 static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 193 static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 194 static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 195 /**
<> 144:ef7eb2e8f9f7 196 * @}
<> 144:ef7eb2e8f9f7 197 */
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /** @defgroup USART_Exported_Functions USART Exported Functions
<> 144:ef7eb2e8f9f7 202 * @{
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 206 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 207 *
<> 144:ef7eb2e8f9f7 208 @verbatim
<> 144:ef7eb2e8f9f7 209 ===============================================================================
<> 144:ef7eb2e8f9f7 210 ##### Initialization and Configuration functions #####
<> 144:ef7eb2e8f9f7 211 ===============================================================================
<> 144:ef7eb2e8f9f7 212 [..]
<> 144:ef7eb2e8f9f7 213 This subsection provides a set of functions allowing to initialize the USART
<> 144:ef7eb2e8f9f7 214 in asynchronous and in synchronous modes.
<> 144:ef7eb2e8f9f7 215 (+) For the asynchronous mode only these parameters can be configured:
<> 144:ef7eb2e8f9f7 216 (++) Baud Rate
<> 144:ef7eb2e8f9f7 217 (++) Word Length
<> 144:ef7eb2e8f9f7 218 (++) Stop Bit
<> 144:ef7eb2e8f9f7 219 (++) Parity
<> 144:ef7eb2e8f9f7 220 (++) USART polarity
<> 144:ef7eb2e8f9f7 221 (++) USART phase
<> 144:ef7eb2e8f9f7 222 (++) USART LastBit
<> 144:ef7eb2e8f9f7 223 (++) Receiver/transmitter modes
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 [..]
<> 144:ef7eb2e8f9f7 226 The HAL_USART_Init() function follows the USART synchronous configuration
<> 144:ef7eb2e8f9f7 227 procedure (details for the procedure are available in reference manual).
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 @endverbatim
<> 144:ef7eb2e8f9f7 230 * @{
<> 144:ef7eb2e8f9f7 231 */
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /*
<> 144:ef7eb2e8f9f7 234 Additional Table: If the parity is enabled, then the MSB bit of the data written
<> 144:ef7eb2e8f9f7 235 in the data register is transmitted but is changed by the parity bit.
<> 144:ef7eb2e8f9f7 236 According to device capability (support or not of 7-bit word length),
<> 144:ef7eb2e8f9f7 237 frame length is either defined by the M bit (8-bits or 9-bits)
<> 144:ef7eb2e8f9f7 238 or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
<> 144:ef7eb2e8f9f7 239 Possible USART frame formats are as listed in the following table:
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 Table 1. USART frame format.
<> 144:ef7eb2e8f9f7 242 +-----------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 243 | M bit | PCE bit | USART frame |
<> 144:ef7eb2e8f9f7 244 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 245 | 0 | 0 | | SB | 8-bit data | STB | |
<> 144:ef7eb2e8f9f7 246 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 247 | 0 | 1 | | SB | 7-bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 248 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 249 | 1 | 0 | | SB | 9-bit data | STB | |
<> 144:ef7eb2e8f9f7 250 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 251 | 1 | 1 | | SB | 8-bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 252 +-----------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 253 | M1 bit | M0 bit | PCE bit | USART frame |
<> 144:ef7eb2e8f9f7 254 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 255 | 0 | 0 | 0 | | SB | 8 bit data | STB | |
<> 144:ef7eb2e8f9f7 256 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 257 | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 258 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 259 | 0 | 1 | 0 | | SB | 9 bit data | STB | |
<> 144:ef7eb2e8f9f7 260 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 261 | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 262 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 263 | 1 | 0 | 0 | | SB | 7 bit data | STB | |
<> 144:ef7eb2e8f9f7 264 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 265 | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 266 +-----------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /**
<> 156:95d6b41a828b 271 * @brief Initialize the USART mode according to the specified
<> 144:ef7eb2e8f9f7 272 * parameters in the USART_InitTypeDef and initialize the associated handle.
<> 156:95d6b41a828b 273 * @param husart USART handle.
<> 144:ef7eb2e8f9f7 274 * @retval HAL status
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 /* Check the USART handle allocation */
<> 144:ef7eb2e8f9f7 279 if(husart == NULL)
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /* Check the parameters */
<> 144:ef7eb2e8f9f7 285 assert_param(IS_USART_INSTANCE(husart->Instance));
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 if(husart->State == HAL_USART_STATE_RESET)
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 290 husart->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /* Init the low level hardware : GPIO, CLOCK */
<> 144:ef7eb2e8f9f7 293 HAL_USART_MspInit(husart);
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 husart->State = HAL_USART_STATE_BUSY;
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 299 __HAL_USART_DISABLE(husart);
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /* Set the Usart Communication parameters */
<> 144:ef7eb2e8f9f7 302 if (USART_SetConfig(husart) == HAL_ERROR)
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 305 }
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /* In Synchronous mode, the following bits must be kept cleared:
<> 144:ef7eb2e8f9f7 308 - LINEN bit (if LIN is supported) in the USART_CR2 register
<> 144:ef7eb2e8f9f7 309 - SCEN (if Smartcard is supported), HDSEL and IREN (if IrDA is supported) bits in the USART_CR3 register. */
<> 144:ef7eb2e8f9f7 310 #if defined (USART_CR2_LINEN)
<> 144:ef7eb2e8f9f7 311 husart->Instance->CR2 &= ~USART_CR2_LINEN;
<> 144:ef7eb2e8f9f7 312 #endif
<> 144:ef7eb2e8f9f7 313 #if defined (USART_CR3_SCEN)
<> 144:ef7eb2e8f9f7 314 #if defined (USART_CR3_IREN)
<> 144:ef7eb2e8f9f7 315 husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
<> 144:ef7eb2e8f9f7 316 #else
<> 144:ef7eb2e8f9f7 317 husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL);
<> 144:ef7eb2e8f9f7 318 #endif
<> 144:ef7eb2e8f9f7 319 #else
<> 144:ef7eb2e8f9f7 320 #if defined (USART_CR3_IREN)
<> 144:ef7eb2e8f9f7 321 husart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN);
<> 144:ef7eb2e8f9f7 322 #else
<> 144:ef7eb2e8f9f7 323 husart->Instance->CR3 &= ~(USART_CR3_HDSEL);
<> 144:ef7eb2e8f9f7 324 #endif
<> 144:ef7eb2e8f9f7 325 #endif
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 328 __HAL_USART_ENABLE(husart);
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /* TEACK and/or REACK to check before moving husart->State to Ready */
<> 144:ef7eb2e8f9f7 331 return (USART_CheckIdleState(husart));
<> 144:ef7eb2e8f9f7 332 }
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /**
<> 156:95d6b41a828b 335 * @brief DeInitialize the USART peripheral.
<> 156:95d6b41a828b 336 * @param husart USART handle.
<> 144:ef7eb2e8f9f7 337 * @retval HAL status
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 340 {
<> 156:95d6b41a828b 341 /* Check the USART handle allocation */
<> 144:ef7eb2e8f9f7 342 if(husart == NULL)
<> 144:ef7eb2e8f9f7 343 {
<> 144:ef7eb2e8f9f7 344 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 345 }
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /* Check the parameters */
<> 144:ef7eb2e8f9f7 348 assert_param(IS_USART_INSTANCE(husart->Instance));
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 husart->State = HAL_USART_STATE_BUSY;
<> 144:ef7eb2e8f9f7 351
<> 156:95d6b41a828b 352 husart->Instance->CR1 = 0x0U;
<> 156:95d6b41a828b 353 husart->Instance->CR2 = 0x0U;
<> 156:95d6b41a828b 354 husart->Instance->CR3 = 0x0U;
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 357 HAL_USART_MspDeInit(husart);
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 husart->ErrorCode = HAL_USART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 360 husart->State = HAL_USART_STATE_RESET;
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /* Process Unlock */
<> 144:ef7eb2e8f9f7 363 __HAL_UNLOCK(husart);
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 return HAL_OK;
<> 144:ef7eb2e8f9f7 366 }
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /**
<> 144:ef7eb2e8f9f7 369 * @brief Initialize the USART MSP.
Anna Bridge 180:96ed750bd169 370 * @param husart USART handle.
<> 144:ef7eb2e8f9f7 371 * @retval None
<> 144:ef7eb2e8f9f7 372 */
<> 156:95d6b41a828b 373 __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 374 {
<> 144:ef7eb2e8f9f7 375 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 376 UNUSED(husart);
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 379 the HAL_USART_MspInit can be implemented in the user file
<> 144:ef7eb2e8f9f7 380 */
<> 144:ef7eb2e8f9f7 381 }
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /**
<> 144:ef7eb2e8f9f7 384 * @brief DeInitialize the USART MSP.
Anna Bridge 180:96ed750bd169 385 * @param husart USART handle.
<> 144:ef7eb2e8f9f7 386 * @retval None
<> 144:ef7eb2e8f9f7 387 */
<> 156:95d6b41a828b 388 __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 389 {
<> 144:ef7eb2e8f9f7 390 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 391 UNUSED(husart);
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 394 the HAL_USART_MspDeInit can be implemented in the user file
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396 }
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 /**
<> 144:ef7eb2e8f9f7 399 * @}
<> 144:ef7eb2e8f9f7 400 */
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /** @defgroup USART_Exported_Functions_Group2 IO operation functions
<> 156:95d6b41a828b 403 * @brief USART Transmit and Receive functions
<> 144:ef7eb2e8f9f7 404 *
<> 144:ef7eb2e8f9f7 405 @verbatim
<> 144:ef7eb2e8f9f7 406 ===============================================================================
<> 144:ef7eb2e8f9f7 407 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 408 ===============================================================================
<> 144:ef7eb2e8f9f7 409 [..] This subsection provides a set of functions allowing to manage the USART synchronous
<> 144:ef7eb2e8f9f7 410 data transfers.
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 [..] The USART supports master mode only: it cannot receive or send data related to an input
<> 144:ef7eb2e8f9f7 413 clock (SCLK is always an output).
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 416 (++) Blocking mode: The communication is performed in polling mode.
<> 144:ef7eb2e8f9f7 417 The HAL status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 418 after finishing transfer.
<> 144:ef7eb2e8f9f7 419 (++) No-Blocking mode: The communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 420 or DMA, These APIs return the HAL status.
<> 144:ef7eb2e8f9f7 421 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 422 dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 423 using DMA mode.
<> 144:ef7eb2e8f9f7 424 The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
<> 144:ef7eb2e8f9f7 425 will be executed respectively at the end of the transmit or Receive process
<> 144:ef7eb2e8f9f7 426 The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 (#) Blocking mode APIs are :
<> 144:ef7eb2e8f9f7 429 (++) HAL_USART_Transmit()in simplex mode
<> 144:ef7eb2e8f9f7 430 (++) HAL_USART_Receive() in full duplex receive only
<> 144:ef7eb2e8f9f7 431 (++) HAL_USART_TransmitReceive() in full duplex mode
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 (#) No-Blocking mode APIs with Interrupt are :
<> 144:ef7eb2e8f9f7 434 (++) HAL_USART_Transmit_IT()in simplex mode
<> 144:ef7eb2e8f9f7 435 (++) HAL_USART_Receive_IT() in full duplex receive only
<> 144:ef7eb2e8f9f7 436 (++) HAL_USART_TransmitReceive_IT()in full duplex mode
<> 144:ef7eb2e8f9f7 437 (++) HAL_USART_IRQHandler()
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 (#) No-Blocking mode APIs with DMA are :
<> 144:ef7eb2e8f9f7 440 (++) HAL_USART_Transmit_DMA()in simplex mode
<> 144:ef7eb2e8f9f7 441 (++) HAL_USART_Receive_DMA() in full duplex receive only
<> 144:ef7eb2e8f9f7 442 (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
<> 144:ef7eb2e8f9f7 443 (++) HAL_USART_DMAPause()
<> 144:ef7eb2e8f9f7 444 (++) HAL_USART_DMAResume()
<> 144:ef7eb2e8f9f7 445 (++) HAL_USART_DMAStop()
<> 144:ef7eb2e8f9f7 446
<> 156:95d6b41a828b 447 (#) A set of Transfer Complete Callbacks are provided in Non-Blocking mode:
<> 144:ef7eb2e8f9f7 448 (++) HAL_USART_TxCpltCallback()
<> 144:ef7eb2e8f9f7 449 (++) HAL_USART_RxCpltCallback()
<> 144:ef7eb2e8f9f7 450 (++) HAL_USART_TxHalfCpltCallback()
<> 144:ef7eb2e8f9f7 451 (++) HAL_USART_RxHalfCpltCallback()
<> 144:ef7eb2e8f9f7 452 (++) HAL_USART_ErrorCallback()
<> 144:ef7eb2e8f9f7 453 (++) HAL_USART_TxRxCpltCallback()
<> 144:ef7eb2e8f9f7 454
<> 156:95d6b41a828b 455 (#) Non-Blocking mode transfers could be aborted using Abort API's :
<> 156:95d6b41a828b 456 (++) HAL_USART_Abort()
<> 156:95d6b41a828b 457 (++) HAL_USART_Abort_IT()
<> 156:95d6b41a828b 458
<> 156:95d6b41a828b 459 (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
<> 156:95d6b41a828b 460 (++) HAL_USART_AbortCpltCallback()
<> 156:95d6b41a828b 461
<> 156:95d6b41a828b 462 (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
<> 156:95d6b41a828b 463 Errors are handled as follows :
<> 156:95d6b41a828b 464 (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
<> 156:95d6b41a828b 465 to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
<> 156:95d6b41a828b 466 Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
<> 156:95d6b41a828b 467 and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
<> 156:95d6b41a828b 468 If user wants to abort it, Abort services should be called by user.
<> 156:95d6b41a828b 469 (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
<> 156:95d6b41a828b 470 This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
<> 156:95d6b41a828b 471 Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
<> 156:95d6b41a828b 472
<> 144:ef7eb2e8f9f7 473 @endverbatim
<> 144:ef7eb2e8f9f7 474 * @{
<> 144:ef7eb2e8f9f7 475 */
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /**
<> 144:ef7eb2e8f9f7 478 * @brief Simplex send an amount of data in blocking mode.
<> 156:95d6b41a828b 479 * @param husart USART handle.
<> 156:95d6b41a828b 480 * @param pTxData Pointer to data buffer.
<> 156:95d6b41a828b 481 * @param Size Amount of data to be sent.
<> 156:95d6b41a828b 482 * @param Timeout Timeout duration.
<> 144:ef7eb2e8f9f7 483 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 484 * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 485 * (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 486 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
<> 144:ef7eb2e8f9f7 487 * @retval HAL status
<> 144:ef7eb2e8f9f7 488 */
<> 144:ef7eb2e8f9f7 489 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 490 {
<> 156:95d6b41a828b 491 uint16_t* tmp=0U;
<> 156:95d6b41a828b 492 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 if(husart->State == HAL_USART_STATE_READY)
<> 144:ef7eb2e8f9f7 495 {
<> 156:95d6b41a828b 496 if((pTxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 497 {
<> 144:ef7eb2e8f9f7 498 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 499 }
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /* In case of 9bits/No Parity transfer, pTxData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 502 should be aligned on a u16 frontier, as data to be filled into TDR will be
<> 144:ef7eb2e8f9f7 503 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 504 if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 505 {
<> 156:95d6b41a828b 506 if((((uint32_t)pTxData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 507 {
<> 144:ef7eb2e8f9f7 508 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 509 }
<> 144:ef7eb2e8f9f7 510 }
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /* Process Locked */
<> 144:ef7eb2e8f9f7 513 __HAL_LOCK(husart);
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 husart->ErrorCode = HAL_USART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 516 husart->State = HAL_USART_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 517
<> 156:95d6b41a828b 518 /* Init tickstart for timeout managment*/
<> 156:95d6b41a828b 519 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 520
<> 144:ef7eb2e8f9f7 521 husart->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 522 husart->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /* Check the remaining data to be sent */
<> 144:ef7eb2e8f9f7 525 while(husart->TxXferCount > 0)
<> 144:ef7eb2e8f9f7 526 {
<> 144:ef7eb2e8f9f7 527 husart->TxXferCount--;
<> 156:95d6b41a828b 528 if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 529 {
<> 144:ef7eb2e8f9f7 530 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 531 }
<> 144:ef7eb2e8f9f7 532 if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 533 {
<> 144:ef7eb2e8f9f7 534 tmp = (uint16_t*) pTxData;
<> 156:95d6b41a828b 535 husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
<> 156:95d6b41a828b 536 pTxData += 2U;
<> 144:ef7eb2e8f9f7 537 }
<> 144:ef7eb2e8f9f7 538 else
<> 144:ef7eb2e8f9f7 539 {
<> 156:95d6b41a828b 540 husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU);
<> 144:ef7eb2e8f9f7 541 }
<> 144:ef7eb2e8f9f7 542 }
<> 144:ef7eb2e8f9f7 543
<> 156:95d6b41a828b 544 if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 545 {
<> 144:ef7eb2e8f9f7 546 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 547 }
<> 144:ef7eb2e8f9f7 548
<> 156:95d6b41a828b 549 /* At end of Tx process, restore husart->State to Ready */
<> 144:ef7eb2e8f9f7 550 husart->State = HAL_USART_STATE_READY;
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 553 __HAL_UNLOCK(husart);
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 return HAL_OK;
<> 144:ef7eb2e8f9f7 556 }
<> 144:ef7eb2e8f9f7 557 else
<> 144:ef7eb2e8f9f7 558 {
<> 144:ef7eb2e8f9f7 559 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 560 }
<> 144:ef7eb2e8f9f7 561 }
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /**
<> 144:ef7eb2e8f9f7 564 * @brief Receive an amount of data in blocking mode.
<> 156:95d6b41a828b 565 * @note To receive synchronous data, dummy data are simultaneously transmitted.
<> 156:95d6b41a828b 566 * @param husart USART handle.
<> 156:95d6b41a828b 567 * @param pRxData Pointer to data buffer.
<> 156:95d6b41a828b 568 * @param Size Amount of data to be received.
<> 156:95d6b41a828b 569 * @param Timeout Timeout duration.
<> 144:ef7eb2e8f9f7 570 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 571 * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 572 * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 573 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
<> 144:ef7eb2e8f9f7 574 * @retval HAL status
<> 144:ef7eb2e8f9f7 575 */
<> 144:ef7eb2e8f9f7 576 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 577 {
<> 156:95d6b41a828b 578 uint16_t* tmp=0U;
<> 144:ef7eb2e8f9f7 579 uint16_t uhMask;
<> 156:95d6b41a828b 580 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 if(husart->State == HAL_USART_STATE_READY)
<> 144:ef7eb2e8f9f7 583 {
<> 156:95d6b41a828b 584 if((pRxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 585 {
<> 144:ef7eb2e8f9f7 586 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 587 }
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /* In case of 9bits/No Parity transfer, pRxData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 590 should be aligned on a u16 frontier, as data to be received from RDR will be
<> 144:ef7eb2e8f9f7 591 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 592 if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 593 {
<> 156:95d6b41a828b 594 if((((uint32_t)pRxData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 595 {
<> 144:ef7eb2e8f9f7 596 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 597 }
<> 144:ef7eb2e8f9f7 598 }
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /* Process Locked */
<> 144:ef7eb2e8f9f7 601 __HAL_LOCK(husart);
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 husart->ErrorCode = HAL_USART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 604 husart->State = HAL_USART_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 605
<> 156:95d6b41a828b 606 /* Init tickstart for timeout managment*/
<> 156:95d6b41a828b 607 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 608
<> 144:ef7eb2e8f9f7 609 husart->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 610 husart->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /* Computation of USART mask to apply to RDR register */
<> 144:ef7eb2e8f9f7 613 USART_MASK_COMPUTATION(husart);
<> 144:ef7eb2e8f9f7 614 uhMask = husart->Mask;
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /* as long as data have to be received */
<> 156:95d6b41a828b 617 while(husart->RxXferCount > 0U)
<> 144:ef7eb2e8f9f7 618 {
<> 144:ef7eb2e8f9f7 619 husart->RxXferCount--;
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /* Wait until TC flag is set to send dummy byte in order to generate the
<> 144:ef7eb2e8f9f7 622 * clock for the slave to send data.
<> 144:ef7eb2e8f9f7 623 * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
<> 144:ef7eb2e8f9f7 624 * can be written for all the cases. */
<> 156:95d6b41a828b 625 if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 626 {
<> 144:ef7eb2e8f9f7 627 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 628 }
<> 156:95d6b41a828b 629 husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FFU);
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 /* Wait for RXNE Flag */
<> 156:95d6b41a828b 632 if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 633 {
<> 144:ef7eb2e8f9f7 634 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 635 }
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 638 {
<> 144:ef7eb2e8f9f7 639 tmp = (uint16_t*) pRxData ;
<> 144:ef7eb2e8f9f7 640 *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
<> 144:ef7eb2e8f9f7 641 pRxData +=2;
<> 144:ef7eb2e8f9f7 642 }
<> 144:ef7eb2e8f9f7 643 else
<> 144:ef7eb2e8f9f7 644 {
<> 144:ef7eb2e8f9f7 645 *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647 }
<> 144:ef7eb2e8f9f7 648
<> 156:95d6b41a828b 649 /* At end of Rx process, restore husart->State to Ready */
<> 144:ef7eb2e8f9f7 650 husart->State = HAL_USART_STATE_READY;
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 653 __HAL_UNLOCK(husart);
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 return HAL_OK;
<> 144:ef7eb2e8f9f7 656 }
<> 144:ef7eb2e8f9f7 657 else
<> 144:ef7eb2e8f9f7 658 {
<> 144:ef7eb2e8f9f7 659 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 660 }
<> 144:ef7eb2e8f9f7 661 }
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /**
<> 156:95d6b41a828b 664 * @brief Full-Duplex Send and Receive an amount of data in blocking mode.
<> 156:95d6b41a828b 665 * @param husart USART handle.
<> 156:95d6b41a828b 666 * @param pTxData pointer to TX data buffer.
<> 156:95d6b41a828b 667 * @param pRxData pointer to RX data buffer.
<> 156:95d6b41a828b 668 * @param Size amount of data to be sent (same amount to be received).
<> 156:95d6b41a828b 669 * @param Timeout Timeout duration.
<> 144:ef7eb2e8f9f7 670 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 671 * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 672 * (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 673 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
<> 144:ef7eb2e8f9f7 674 * @retval HAL status
<> 144:ef7eb2e8f9f7 675 */
<> 144:ef7eb2e8f9f7 676 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 677 {
<> 156:95d6b41a828b 678 uint16_t* tmp=0U;
<> 144:ef7eb2e8f9f7 679 uint16_t uhMask;
<> 156:95d6b41a828b 680 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 if(husart->State == HAL_USART_STATE_READY)
<> 144:ef7eb2e8f9f7 683 {
<> 156:95d6b41a828b 684 if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 685 {
<> 144:ef7eb2e8f9f7 686 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 687 }
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input paramter
<> 144:ef7eb2e8f9f7 690 should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be
<> 144:ef7eb2e8f9f7 691 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 692 if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 693 {
<> 156:95d6b41a828b 694 if(((((uint32_t)pTxData)&1U) != 0U) || ((((uint32_t)pRxData)&1U) != 0U))
<> 144:ef7eb2e8f9f7 695 {
<> 144:ef7eb2e8f9f7 696 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 697 }
<> 144:ef7eb2e8f9f7 698 }
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /* Process Locked */
<> 144:ef7eb2e8f9f7 701 __HAL_LOCK(husart);
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 husart->ErrorCode = HAL_USART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 704 husart->State = HAL_USART_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 705
<> 156:95d6b41a828b 706 /* Init tickstart for timeout managment*/
<> 156:95d6b41a828b 707 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 708
<> 144:ef7eb2e8f9f7 709 husart->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 710 husart->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 711 husart->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 712 husart->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 /* Computation of USART mask to apply to RDR register */
<> 144:ef7eb2e8f9f7 715 USART_MASK_COMPUTATION(husart);
<> 144:ef7eb2e8f9f7 716 uhMask = husart->Mask;
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 /* Check the remain data to be sent */
<> 156:95d6b41a828b 719 while(husart->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 720 {
<> 144:ef7eb2e8f9f7 721 husart->TxXferCount--;
<> 144:ef7eb2e8f9f7 722 husart->RxXferCount--;
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /* Wait until TC flag is set to send data */
<> 156:95d6b41a828b 725 if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 726 {
<> 144:ef7eb2e8f9f7 727 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 728 }
<> 144:ef7eb2e8f9f7 729 if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 tmp = (uint16_t*) pTxData;
<> 144:ef7eb2e8f9f7 732 husart->Instance->TDR = (*tmp & uhMask);
<> 156:95d6b41a828b 733 pTxData += 2U;
<> 144:ef7eb2e8f9f7 734 }
<> 144:ef7eb2e8f9f7 735 else
<> 144:ef7eb2e8f9f7 736 {
<> 144:ef7eb2e8f9f7 737 husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
<> 144:ef7eb2e8f9f7 738 }
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 /* Wait for RXNE Flag */
<> 156:95d6b41a828b 741 if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 742 {
<> 144:ef7eb2e8f9f7 743 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 744 }
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 747 {
<> 144:ef7eb2e8f9f7 748 tmp = (uint16_t*) pRxData ;
<> 144:ef7eb2e8f9f7 749 *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
<> 156:95d6b41a828b 750 pRxData +=2U;
<> 144:ef7eb2e8f9f7 751 }
<> 144:ef7eb2e8f9f7 752 else
<> 144:ef7eb2e8f9f7 753 {
<> 144:ef7eb2e8f9f7 754 *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
<> 144:ef7eb2e8f9f7 755 }
<> 144:ef7eb2e8f9f7 756 }
<> 144:ef7eb2e8f9f7 757
<> 156:95d6b41a828b 758 /* At end of TxRx process, restore husart->State to Ready */
<> 144:ef7eb2e8f9f7 759 husart->State = HAL_USART_STATE_READY;
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 762 __HAL_UNLOCK(husart);
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 return HAL_OK;
<> 144:ef7eb2e8f9f7 765 }
<> 144:ef7eb2e8f9f7 766 else
<> 144:ef7eb2e8f9f7 767 {
<> 144:ef7eb2e8f9f7 768 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 769 }
<> 144:ef7eb2e8f9f7 770 }
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 /**
<> 144:ef7eb2e8f9f7 773 * @brief Send an amount of data in interrupt mode.
<> 156:95d6b41a828b 774 * @param husart USART handle.
<> 156:95d6b41a828b 775 * @param pTxData pointer to data buffer.
<> 156:95d6b41a828b 776 * @param Size amount of data to be sent.
<> 144:ef7eb2e8f9f7 777 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 778 * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 779 * (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 780 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
<> 144:ef7eb2e8f9f7 781 * @retval HAL status
<> 144:ef7eb2e8f9f7 782 */
<> 144:ef7eb2e8f9f7 783 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
<> 144:ef7eb2e8f9f7 784 {
<> 144:ef7eb2e8f9f7 785 if(husart->State == HAL_USART_STATE_READY)
<> 144:ef7eb2e8f9f7 786 {
<> 156:95d6b41a828b 787 if((pTxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 788 {
<> 144:ef7eb2e8f9f7 789 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 790 }
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 /* In case of 9bits/No Parity transfer, pTxData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 793 should be aligned on a u16 frontier, as data to be filled into TDR will be
<> 144:ef7eb2e8f9f7 794 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 795 if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 796 {
<> 156:95d6b41a828b 797 if((((uint32_t)pTxData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 798 {
<> 144:ef7eb2e8f9f7 799 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 800 }
<> 144:ef7eb2e8f9f7 801 }
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 /* Process Locked */
<> 144:ef7eb2e8f9f7 804 __HAL_LOCK(husart);
<> 144:ef7eb2e8f9f7 805
<> 144:ef7eb2e8f9f7 806 husart->pTxBuffPtr = pTxData;
<> 144:ef7eb2e8f9f7 807 husart->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 808 husart->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 husart->ErrorCode = HAL_USART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 811 husart->State = HAL_USART_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /* The USART Error Interrupts: (Frame error, noise error, overrun error)
<> 144:ef7eb2e8f9f7 814 are not managed by the USART Transmit Process to avoid the overrun interrupt
<> 144:ef7eb2e8f9f7 815 when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
<> 144:ef7eb2e8f9f7 816 to benefit for the frame error and noise interrupts the usart mode should be
<> 144:ef7eb2e8f9f7 817 configured only for transmit "USART_MODE_TX" */
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 820 __HAL_UNLOCK(husart);
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /* Enable the USART Transmit Data Register Empty Interrupt */
<> 144:ef7eb2e8f9f7 823 __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 return HAL_OK;
<> 144:ef7eb2e8f9f7 826 }
<> 144:ef7eb2e8f9f7 827 else
<> 144:ef7eb2e8f9f7 828 {
<> 144:ef7eb2e8f9f7 829 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 830 }
<> 144:ef7eb2e8f9f7 831 }
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 /**
<> 156:95d6b41a828b 834 * @brief Receive an amount of data in interrupt mode.
<> 156:95d6b41a828b 835 * @note To receive synchronous data, dummy data are simultaneously transmitted.
<> 156:95d6b41a828b 836 * @param husart USART handle.
<> 156:95d6b41a828b 837 * @param pRxData pointer to data buffer.
<> 156:95d6b41a828b 838 * @param Size amount of data to be received.
<> 144:ef7eb2e8f9f7 839 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 840 * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 841 * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 842 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
<> 144:ef7eb2e8f9f7 843 * @retval HAL status
<> 144:ef7eb2e8f9f7 844 */
<> 144:ef7eb2e8f9f7 845 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
<> 144:ef7eb2e8f9f7 846 {
<> 144:ef7eb2e8f9f7 847 if(husart->State == HAL_USART_STATE_READY)
<> 144:ef7eb2e8f9f7 848 {
<> 156:95d6b41a828b 849 if((pRxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 850 {
<> 144:ef7eb2e8f9f7 851 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 852 }
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 /* In case of 9bits/No Parity transfer, pRxData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 855 should be aligned on a u16 frontier, as data to be received from RDR will be
<> 144:ef7eb2e8f9f7 856 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 857 if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 858 {
<> 156:95d6b41a828b 859 if((((uint32_t)pRxData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 860 {
<> 144:ef7eb2e8f9f7 861 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 862 }
<> 144:ef7eb2e8f9f7 863 }
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /* Process Locked */
<> 144:ef7eb2e8f9f7 866 __HAL_LOCK(husart);
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 husart->pRxBuffPtr = pRxData;
<> 144:ef7eb2e8f9f7 869 husart->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 870 husart->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 USART_MASK_COMPUTATION(husart);
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 husart->ErrorCode = HAL_USART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 875 husart->State = HAL_USART_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 878 __HAL_UNLOCK(husart);
<> 144:ef7eb2e8f9f7 879
<> 156:95d6b41a828b 880 /* Enable the USART Parity Error and Data Register not empty Interrupts */
<> 156:95d6b41a828b 881 SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
<> 156:95d6b41a828b 882
<> 156:95d6b41a828b 883 /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<> 156:95d6b41a828b 884 SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 /* Send dummy byte in order to generate the clock for the Slave to send the next data */
<> 144:ef7eb2e8f9f7 887 if(husart->Init.WordLength == USART_WORDLENGTH_9B)
<> 144:ef7eb2e8f9f7 888 {
<> 156:95d6b41a828b 889 husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FFU);
<> 144:ef7eb2e8f9f7 890 }
<> 144:ef7eb2e8f9f7 891 else
<> 144:ef7eb2e8f9f7 892 {
<> 156:95d6b41a828b 893 husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
<> 144:ef7eb2e8f9f7 894 }
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896 return HAL_OK;
<> 144:ef7eb2e8f9f7 897 }
<> 144:ef7eb2e8f9f7 898 else
<> 144:ef7eb2e8f9f7 899 {
<> 144:ef7eb2e8f9f7 900 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 901 }
<> 144:ef7eb2e8f9f7 902 }
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 /**
<> 156:95d6b41a828b 905 * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
<> 156:95d6b41a828b 906 * @param husart USART handle.
<> 156:95d6b41a828b 907 * @param pTxData pointer to TX data buffer.
<> 156:95d6b41a828b 908 * @param pRxData pointer to RX data buffer.
<> 156:95d6b41a828b 909 * @param Size amount of data to be sent (same amount to be received).
<> 144:ef7eb2e8f9f7 910 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 911 * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 912 * (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 913 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
<> 144:ef7eb2e8f9f7 914 * @retval HAL status
<> 144:ef7eb2e8f9f7 915 */
<> 144:ef7eb2e8f9f7 916 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
<> 144:ef7eb2e8f9f7 917 {
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 if(husart->State == HAL_USART_STATE_READY)
<> 144:ef7eb2e8f9f7 920 {
<> 156:95d6b41a828b 921 if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 922 {
<> 144:ef7eb2e8f9f7 923 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 924 }
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input paramter
<> 144:ef7eb2e8f9f7 927 should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be
<> 144:ef7eb2e8f9f7 928 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 929 if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 930 {
<> 156:95d6b41a828b 931 if(((((uint32_t)pTxData)&1U) != 0U) || ((((uint32_t)pRxData)&1U) != 0U))
<> 144:ef7eb2e8f9f7 932 {
<> 144:ef7eb2e8f9f7 933 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 934 }
<> 144:ef7eb2e8f9f7 935 }
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 /* Process Locked */
<> 144:ef7eb2e8f9f7 938 __HAL_LOCK(husart);
<> 144:ef7eb2e8f9f7 939
<> 144:ef7eb2e8f9f7 940 husart->pRxBuffPtr = pRxData;
<> 144:ef7eb2e8f9f7 941 husart->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 942 husart->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 943 husart->pTxBuffPtr = pTxData;
<> 144:ef7eb2e8f9f7 944 husart->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 945 husart->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 946
<> 144:ef7eb2e8f9f7 947 /* Computation of USART mask to apply to RDR register */
<> 144:ef7eb2e8f9f7 948 USART_MASK_COMPUTATION(husart);
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 husart->ErrorCode = HAL_USART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 951 husart->State = HAL_USART_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 954 __HAL_UNLOCK(husart);
<> 144:ef7eb2e8f9f7 955
<> 156:95d6b41a828b 956 /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<> 156:95d6b41a828b 957 SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 958
<> 156:95d6b41a828b 959 /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
<> 156:95d6b41a828b 960 SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
<> 156:95d6b41a828b 961
<> 144:ef7eb2e8f9f7 962 /* Enable the USART Transmit Data Register Empty Interrupt */
<> 156:95d6b41a828b 963 SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 return HAL_OK;
<> 144:ef7eb2e8f9f7 966 }
<> 144:ef7eb2e8f9f7 967 else
<> 144:ef7eb2e8f9f7 968 {
<> 144:ef7eb2e8f9f7 969 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 970 }
<> 144:ef7eb2e8f9f7 971 }
<> 144:ef7eb2e8f9f7 972
<> 144:ef7eb2e8f9f7 973 /**
<> 156:95d6b41a828b 974 * @brief Send an amount of data in DMA mode.
<> 156:95d6b41a828b 975 * @param husart USART handle.
<> 156:95d6b41a828b 976 * @param pTxData pointer to data buffer.
<> 156:95d6b41a828b 977 * @param Size amount of data to be sent.
<> 144:ef7eb2e8f9f7 978 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 979 * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 980 * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 981 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
<> 144:ef7eb2e8f9f7 982 * @retval HAL status
<> 144:ef7eb2e8f9f7 983 */
<> 144:ef7eb2e8f9f7 984 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
<> 144:ef7eb2e8f9f7 985 {
<> 156:95d6b41a828b 986 uint32_t *tmp=0U;
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 if(husart->State == HAL_USART_STATE_READY)
<> 144:ef7eb2e8f9f7 989 {
<> 156:95d6b41a828b 990 if((pTxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 991 {
<> 144:ef7eb2e8f9f7 992 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 993 }
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 /* In case of 9bits/No Parity transfer, pTxData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 996 should be aligned on a u16 frontier, as data copy into TDR will be
<> 144:ef7eb2e8f9f7 997 handled by DMA from a u16 frontier. */
<> 144:ef7eb2e8f9f7 998 if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 999 {
<> 156:95d6b41a828b 1000 if((((uint32_t)pTxData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 1001 {
<> 144:ef7eb2e8f9f7 1002 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1003 }
<> 144:ef7eb2e8f9f7 1004 }
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006 /* Process Locked */
<> 144:ef7eb2e8f9f7 1007 __HAL_LOCK(husart);
<> 144:ef7eb2e8f9f7 1008
<> 144:ef7eb2e8f9f7 1009 husart->pTxBuffPtr = pTxData;
<> 144:ef7eb2e8f9f7 1010 husart->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1011 husart->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 husart->ErrorCode = HAL_USART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1014 husart->State = HAL_USART_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 /* Set the USART DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1017 husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 /* Set the USART DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1020 husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
<> 144:ef7eb2e8f9f7 1021
<> 144:ef7eb2e8f9f7 1022 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1023 husart->hdmatx->XferErrorCallback = USART_DMAError;
<> 144:ef7eb2e8f9f7 1024
<> 144:ef7eb2e8f9f7 1025 /* Enable the USART transmit DMA channel */
<> 144:ef7eb2e8f9f7 1026 tmp = (uint32_t*)&pTxData;
<> 144:ef7eb2e8f9f7 1027 HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 /* Clear the TC flag in the ICR register */
<> 144:ef7eb2e8f9f7 1030 __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
<> 144:ef7eb2e8f9f7 1031
<> 156:95d6b41a828b 1032 /* Process Unlocked */
<> 156:95d6b41a828b 1033 __HAL_UNLOCK(husart);
<> 156:95d6b41a828b 1034
<> 144:ef7eb2e8f9f7 1035 /* Enable the DMA transfer for transmit request by setting the DMAT bit
<> 144:ef7eb2e8f9f7 1036 in the USART CR3 register */
<> 156:95d6b41a828b 1037 SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1038
<> 144:ef7eb2e8f9f7 1039 return HAL_OK;
<> 144:ef7eb2e8f9f7 1040 }
<> 144:ef7eb2e8f9f7 1041 else
<> 144:ef7eb2e8f9f7 1042 {
<> 144:ef7eb2e8f9f7 1043 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1044 }
<> 144:ef7eb2e8f9f7 1045 }
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 /**
<> 156:95d6b41a828b 1048 * @brief Receive an amount of data in DMA mode.
<> 156:95d6b41a828b 1049 * @param husart USART handle.
<> 156:95d6b41a828b 1050 * @param pRxData pointer to data buffer.
<> 156:95d6b41a828b 1051 * @param Size amount of data to be received.
<> 144:ef7eb2e8f9f7 1052 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 1053 * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 1054 * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 1055 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
<> 156:95d6b41a828b 1056 * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
<> 144:ef7eb2e8f9f7 1057 * @retval HAL status
<> 144:ef7eb2e8f9f7 1058 */
<> 144:ef7eb2e8f9f7 1059 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1060 {
<> 144:ef7eb2e8f9f7 1061 uint32_t *tmp;
<> 144:ef7eb2e8f9f7 1062
<> 156:95d6b41a828b 1063 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 1064 if(husart->State == HAL_USART_STATE_READY)
<> 144:ef7eb2e8f9f7 1065 {
<> 156:95d6b41a828b 1066 if((pRxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1067 {
<> 144:ef7eb2e8f9f7 1068 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1069 }
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071 /* In case of 9bits/No Parity transfer, pRxData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 1072 should be aligned on a u16 frontier, as data copy from RDR will be
<> 144:ef7eb2e8f9f7 1073 handled by DMA from a u16 frontier. */
<> 144:ef7eb2e8f9f7 1074 if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 1075 {
<> 156:95d6b41a828b 1076 if((((uint32_t)pRxData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 1077 {
<> 144:ef7eb2e8f9f7 1078 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1079 }
<> 144:ef7eb2e8f9f7 1080 }
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082 /* Process Locked */
<> 144:ef7eb2e8f9f7 1083 __HAL_LOCK(husart);
<> 144:ef7eb2e8f9f7 1084
<> 144:ef7eb2e8f9f7 1085 husart->pRxBuffPtr = pRxData;
<> 144:ef7eb2e8f9f7 1086 husart->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1087 husart->pTxBuffPtr = pRxData;
<> 144:ef7eb2e8f9f7 1088 husart->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090 husart->ErrorCode = HAL_USART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1091 husart->State = HAL_USART_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /* Set the USART DMA Rx transfer complete callback */
<> 144:ef7eb2e8f9f7 1094 husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 1095
<> 144:ef7eb2e8f9f7 1096 /* Set the USART DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1097 husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
<> 144:ef7eb2e8f9f7 1098
<> 144:ef7eb2e8f9f7 1099 /* Set the USART DMA Rx transfer error callback */
<> 144:ef7eb2e8f9f7 1100 husart->hdmarx->XferErrorCallback = USART_DMAError;
<> 144:ef7eb2e8f9f7 1101
<> 144:ef7eb2e8f9f7 1102 /* Enable the USART receive DMA channel */
<> 144:ef7eb2e8f9f7 1103 tmp = (uint32_t*)&pRxData;
<> 144:ef7eb2e8f9f7 1104 HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
<> 144:ef7eb2e8f9f7 1105
<> 144:ef7eb2e8f9f7 1106 /* Enable the USART transmit DMA channel: the transmit channel is used in order
<> 144:ef7eb2e8f9f7 1107 to generate in the non-blocking mode the clock to the slave device,
<> 144:ef7eb2e8f9f7 1108 this mode isn't a simplex receive mode but a full-duplex receive mode */
<> 156:95d6b41a828b 1109 /* Set the USART DMA Tx Complete and Error callback to Null */
<> 156:95d6b41a828b 1110 husart->hdmatx->XferErrorCallback = NULL;
<> 156:95d6b41a828b 1111 husart->hdmatx->XferHalfCpltCallback = NULL;
<> 156:95d6b41a828b 1112 husart->hdmatx->XferCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1113 HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
<> 144:ef7eb2e8f9f7 1114
<> 156:95d6b41a828b 1115 /* Process Unlocked */
<> 156:95d6b41a828b 1116 __HAL_UNLOCK(husart);
<> 156:95d6b41a828b 1117
<> 156:95d6b41a828b 1118 /* Enable the USART Parity Error Interrupt */
<> 156:95d6b41a828b 1119 SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
<> 156:95d6b41a828b 1120
<> 156:95d6b41a828b 1121 /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<> 156:95d6b41a828b 1122 SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1123
<> 144:ef7eb2e8f9f7 1124 /* Enable the DMA transfer for the receiver request by setting the DMAR bit
<> 144:ef7eb2e8f9f7 1125 in the USART CR3 register */
<> 156:95d6b41a828b 1126 SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1127
<> 144:ef7eb2e8f9f7 1128 /* Enable the DMA transfer for transmit request by setting the DMAT bit
<> 144:ef7eb2e8f9f7 1129 in the USART CR3 register */
<> 156:95d6b41a828b 1130 SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1131
<> 144:ef7eb2e8f9f7 1132 return HAL_OK;
<> 144:ef7eb2e8f9f7 1133 }
<> 144:ef7eb2e8f9f7 1134 else
<> 144:ef7eb2e8f9f7 1135 {
<> 144:ef7eb2e8f9f7 1136 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1137 }
<> 144:ef7eb2e8f9f7 1138 }
<> 144:ef7eb2e8f9f7 1139
<> 144:ef7eb2e8f9f7 1140 /**
<> 156:95d6b41a828b 1141 * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
<> 156:95d6b41a828b 1142 * @param husart USART handle.
<> 156:95d6b41a828b 1143 * @param pTxData pointer to TX data buffer.
<> 156:95d6b41a828b 1144 * @param pRxData pointer to RX data buffer.
<> 156:95d6b41a828b 1145 * @param Size amount of data to be received/sent.
<> 144:ef7eb2e8f9f7 1146 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 1147 * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 1148 * (as sent/received data will be handled by DMA from halfword frontier). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 1149 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
<> 144:ef7eb2e8f9f7 1150 * @retval HAL status
<> 144:ef7eb2e8f9f7 1151 */
<> 144:ef7eb2e8f9f7 1152 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1153 {
<> 144:ef7eb2e8f9f7 1154 uint32_t *tmp;
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 if(husart->State == HAL_USART_STATE_READY)
<> 144:ef7eb2e8f9f7 1157 {
<> 156:95d6b41a828b 1158 if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1159 {
<> 144:ef7eb2e8f9f7 1160 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1161 }
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input paramter
<> 144:ef7eb2e8f9f7 1164 should be aligned on a u16 frontier, as data copy to/from TDR/RDR will be
<> 144:ef7eb2e8f9f7 1165 handled by DMA from a u16 frontier. */
<> 144:ef7eb2e8f9f7 1166 if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 1167 {
<> 156:95d6b41a828b 1168 if(((((uint32_t)pTxData)&1U) != 0U) || ((((uint32_t)pRxData)&1U) != 0U))
<> 144:ef7eb2e8f9f7 1169 {
<> 144:ef7eb2e8f9f7 1170 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1171 }
<> 144:ef7eb2e8f9f7 1172 }
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 /* Process Locked */
<> 144:ef7eb2e8f9f7 1175 __HAL_LOCK(husart);
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177 husart->pRxBuffPtr = pRxData;
<> 144:ef7eb2e8f9f7 1178 husart->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1179 husart->pTxBuffPtr = pTxData;
<> 144:ef7eb2e8f9f7 1180 husart->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 husart->ErrorCode = HAL_USART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1183 husart->State = HAL_USART_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 1184
<> 144:ef7eb2e8f9f7 1185 /* Set the USART DMA Rx transfer complete callback */
<> 144:ef7eb2e8f9f7 1186 husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 1187
<> 144:ef7eb2e8f9f7 1188 /* Set the USART DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1189 husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
<> 144:ef7eb2e8f9f7 1190
<> 144:ef7eb2e8f9f7 1191 /* Set the USART DMA Tx transfer complete callback */
<> 144:ef7eb2e8f9f7 1192 husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
<> 144:ef7eb2e8f9f7 1193
<> 144:ef7eb2e8f9f7 1194 /* Set the USART DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1195 husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
<> 144:ef7eb2e8f9f7 1196
<> 144:ef7eb2e8f9f7 1197 /* Set the USART DMA Tx transfer error callback */
<> 144:ef7eb2e8f9f7 1198 husart->hdmatx->XferErrorCallback = USART_DMAError;
<> 144:ef7eb2e8f9f7 1199
<> 144:ef7eb2e8f9f7 1200 /* Set the USART DMA Rx transfer error callback */
<> 144:ef7eb2e8f9f7 1201 husart->hdmarx->XferErrorCallback = USART_DMAError;
<> 144:ef7eb2e8f9f7 1202
<> 144:ef7eb2e8f9f7 1203 /* Enable the USART receive DMA channel */
<> 144:ef7eb2e8f9f7 1204 tmp = (uint32_t*)&pRxData;
<> 144:ef7eb2e8f9f7 1205 HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
<> 144:ef7eb2e8f9f7 1206
<> 144:ef7eb2e8f9f7 1207 /* Enable the USART transmit DMA channel */
<> 144:ef7eb2e8f9f7 1208 tmp = (uint32_t*)&pTxData;
<> 144:ef7eb2e8f9f7 1209 HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
<> 144:ef7eb2e8f9f7 1210
<> 156:95d6b41a828b 1211 /* Process Unlocked */
<> 156:95d6b41a828b 1212 __HAL_UNLOCK(husart);
<> 156:95d6b41a828b 1213
<> 156:95d6b41a828b 1214 /* Enable the USART Parity Error Interrupt */
<> 156:95d6b41a828b 1215 SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
<> 156:95d6b41a828b 1216
<> 156:95d6b41a828b 1217 /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<> 156:95d6b41a828b 1218 SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1219
<> 144:ef7eb2e8f9f7 1220 /* Clear the TC flag in the ICR register */
<> 144:ef7eb2e8f9f7 1221 __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
<> 144:ef7eb2e8f9f7 1222
<> 144:ef7eb2e8f9f7 1223 /* Enable the DMA transfer for the receiver request by setting the DMAR bit
<> 144:ef7eb2e8f9f7 1224 in the USART CR3 register */
<> 156:95d6b41a828b 1225 SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1226
<> 144:ef7eb2e8f9f7 1227 /* Enable the DMA transfer for transmit request by setting the DMAT bit
<> 144:ef7eb2e8f9f7 1228 in the USART CR3 register */
<> 156:95d6b41a828b 1229 SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1230
<> 144:ef7eb2e8f9f7 1231 return HAL_OK;
<> 144:ef7eb2e8f9f7 1232 }
<> 144:ef7eb2e8f9f7 1233 else
<> 144:ef7eb2e8f9f7 1234 {
<> 144:ef7eb2e8f9f7 1235 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1236 }
<> 144:ef7eb2e8f9f7 1237 }
<> 144:ef7eb2e8f9f7 1238
<> 144:ef7eb2e8f9f7 1239 /**
<> 156:95d6b41a828b 1240 * @brief Pause the DMA Transfer.
<> 156:95d6b41a828b 1241 * @param husart USART handle.
<> 144:ef7eb2e8f9f7 1242 * @retval HAL status
<> 144:ef7eb2e8f9f7 1243 */
<> 144:ef7eb2e8f9f7 1244 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 1245 {
<> 144:ef7eb2e8f9f7 1246 /* Process Locked */
<> 144:ef7eb2e8f9f7 1247 __HAL_LOCK(husart);
<> 144:ef7eb2e8f9f7 1248
<> 156:95d6b41a828b 1249 if( (husart->State == HAL_USART_STATE_BUSY_TX) &&
<> 156:95d6b41a828b 1250 (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))
<> 144:ef7eb2e8f9f7 1251 {
<> 144:ef7eb2e8f9f7 1252 /* Disable the USART DMA Tx request */
<> 156:95d6b41a828b 1253 CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1254 }
<> 156:95d6b41a828b 1255 else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
<> 156:95d6b41a828b 1256 (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
<> 144:ef7eb2e8f9f7 1257 {
<> 156:95d6b41a828b 1258 if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
<> 156:95d6b41a828b 1259 {
<> 156:95d6b41a828b 1260 /* Disable the USART DMA Tx request */
<> 156:95d6b41a828b 1261 CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1262 }
<> 156:95d6b41a828b 1263 if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1264 {
<> 156:95d6b41a828b 1265 /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1266 CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
<> 156:95d6b41a828b 1267 CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1268
<> 156:95d6b41a828b 1269 /* Disable the USART DMA Rx request */
<> 156:95d6b41a828b 1270 CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1271 }
<> 144:ef7eb2e8f9f7 1272 }
<> 144:ef7eb2e8f9f7 1273
<> 144:ef7eb2e8f9f7 1274 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1275 __HAL_UNLOCK(husart);
<> 144:ef7eb2e8f9f7 1276
<> 144:ef7eb2e8f9f7 1277 return HAL_OK;
<> 144:ef7eb2e8f9f7 1278 }
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 /**
<> 156:95d6b41a828b 1281 * @brief Resume the DMA Transfer.
<> 156:95d6b41a828b 1282 * @param husart USART handle.
<> 144:ef7eb2e8f9f7 1283 * @retval HAL status
<> 144:ef7eb2e8f9f7 1284 */
<> 144:ef7eb2e8f9f7 1285 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 1286 {
<> 144:ef7eb2e8f9f7 1287 /* Process Locked */
<> 144:ef7eb2e8f9f7 1288 __HAL_LOCK(husart);
<> 144:ef7eb2e8f9f7 1289
<> 144:ef7eb2e8f9f7 1290 if(husart->State == HAL_USART_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1291 {
<> 144:ef7eb2e8f9f7 1292 /* Enable the USART DMA Tx request */
<> 156:95d6b41a828b 1293 SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1294 }
<> 156:95d6b41a828b 1295 else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
<> 156:95d6b41a828b 1296 (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
<> 144:ef7eb2e8f9f7 1297 {
<> 156:95d6b41a828b 1298 /* Clear the Overrun flag before resuming the Rx transfer*/
<> 144:ef7eb2e8f9f7 1299 __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
<> 144:ef7eb2e8f9f7 1300
<> 156:95d6b41a828b 1301 /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1302 SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
<> 156:95d6b41a828b 1303 SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305 /* Enable the USART DMA Rx request before the DMA Tx request */
<> 156:95d6b41a828b 1306 SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1307
<> 144:ef7eb2e8f9f7 1308 /* Enable the USART DMA Tx request */
<> 156:95d6b41a828b 1309 SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1310 }
<> 144:ef7eb2e8f9f7 1311
<> 144:ef7eb2e8f9f7 1312 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1313 __HAL_UNLOCK(husart);
<> 144:ef7eb2e8f9f7 1314
<> 144:ef7eb2e8f9f7 1315 return HAL_OK;
<> 144:ef7eb2e8f9f7 1316 }
<> 144:ef7eb2e8f9f7 1317
<> 144:ef7eb2e8f9f7 1318 /**
<> 156:95d6b41a828b 1319 * @brief Stop the DMA Transfer.
<> 156:95d6b41a828b 1320 * @param husart USART handle.
<> 144:ef7eb2e8f9f7 1321 * @retval HAL status
<> 144:ef7eb2e8f9f7 1322 */
<> 144:ef7eb2e8f9f7 1323 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 1324 {
<> 144:ef7eb2e8f9f7 1325 /* The Lock is not implemented on this API to allow the user application
<> 144:ef7eb2e8f9f7 1326 to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
<> 144:ef7eb2e8f9f7 1327 HAL_USART_TxHalfCpltCallback() / HAL_USART_RxHalfCpltCallback ():
<> 144:ef7eb2e8f9f7 1328 indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is
<> 144:ef7eb2e8f9f7 1329 generated if the DMA transfer interruption occurs at the middle or at the end of the stream
<> 144:ef7eb2e8f9f7 1330 and the corresponding call back is executed.
<> 144:ef7eb2e8f9f7 1331 */
<> 144:ef7eb2e8f9f7 1332
<> 144:ef7eb2e8f9f7 1333 /* Disable the USART Tx/Rx DMA requests */
<> 156:95d6b41a828b 1334 CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1335 CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1336
<> 144:ef7eb2e8f9f7 1337 /* Abort the USART DMA tx channel */
<> 144:ef7eb2e8f9f7 1338 if(husart->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 1339 {
<> 144:ef7eb2e8f9f7 1340 HAL_DMA_Abort(husart->hdmatx);
<> 144:ef7eb2e8f9f7 1341 }
<> 144:ef7eb2e8f9f7 1342 /* Abort the USART DMA rx channel */
<> 144:ef7eb2e8f9f7 1343 if(husart->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 1344 {
<> 144:ef7eb2e8f9f7 1345 HAL_DMA_Abort(husart->hdmarx);
<> 144:ef7eb2e8f9f7 1346 }
<> 144:ef7eb2e8f9f7 1347
<> 156:95d6b41a828b 1348 USART_EndTransfer(husart);
<> 144:ef7eb2e8f9f7 1349 husart->State = HAL_USART_STATE_READY;
<> 144:ef7eb2e8f9f7 1350
<> 144:ef7eb2e8f9f7 1351 return HAL_OK;
<> 144:ef7eb2e8f9f7 1352 }
<> 144:ef7eb2e8f9f7 1353
<> 144:ef7eb2e8f9f7 1354 /**
<> 156:95d6b41a828b 1355 * @brief Abort ongoing transfers (blocking mode).
<> 156:95d6b41a828b 1356 * @param husart USART handle.
<> 156:95d6b41a828b 1357 * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1358 * This procedure performs following operations :
<> 156:95d6b41a828b 1359 * - Disable USART Interrupts (Tx and Rx)
<> 156:95d6b41a828b 1360 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1361 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1362 * - Set handle State to READY
<> 156:95d6b41a828b 1363 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
<> 156:95d6b41a828b 1364 * @retval HAL status
<> 156:95d6b41a828b 1365 */
<> 156:95d6b41a828b 1366 HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
<> 156:95d6b41a828b 1367 {
<> 156:95d6b41a828b 1368 /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1369 CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
<> 156:95d6b41a828b 1370 CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1371
<> 156:95d6b41a828b 1372 /* Disable the USART DMA Tx request if enabled */
<> 156:95d6b41a828b 1373 if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
<> 156:95d6b41a828b 1374 {
<> 156:95d6b41a828b 1375 CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1376
<> 156:95d6b41a828b 1377 /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
<> 156:95d6b41a828b 1378 if(husart->hdmatx != NULL)
<> 156:95d6b41a828b 1379 {
<> 156:95d6b41a828b 1380 /* Set the USART DMA Abort callback to Null.
<> 156:95d6b41a828b 1381 No call back execution at end of DMA abort procedure */
<> 156:95d6b41a828b 1382 husart->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1383
<> 156:95d6b41a828b 1384 HAL_DMA_Abort(husart->hdmatx);
<> 156:95d6b41a828b 1385 }
<> 156:95d6b41a828b 1386 }
<> 156:95d6b41a828b 1387
<> 156:95d6b41a828b 1388 /* Disable the USART DMA Rx request if enabled */
<> 156:95d6b41a828b 1389 if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1390 {
<> 156:95d6b41a828b 1391 CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1392
<> 156:95d6b41a828b 1393 /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
<> 156:95d6b41a828b 1394 if(husart->hdmarx != NULL)
<> 156:95d6b41a828b 1395 {
<> 156:95d6b41a828b 1396 /* Set the USART DMA Abort callback to Null.
<> 156:95d6b41a828b 1397 No call back execution at end of DMA abort procedure */
<> 156:95d6b41a828b 1398 husart->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1399
<> 156:95d6b41a828b 1400 HAL_DMA_Abort(husart->hdmarx);
<> 156:95d6b41a828b 1401 }
<> 156:95d6b41a828b 1402 }
<> 156:95d6b41a828b 1403
<> 156:95d6b41a828b 1404 /* Reset Tx and Rx transfer counters */
<> 156:95d6b41a828b 1405 husart->TxXferCount = 0U;
<> 156:95d6b41a828b 1406 husart->RxXferCount = 0U;
<> 156:95d6b41a828b 1407
<> 156:95d6b41a828b 1408 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 1409 __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
<> 156:95d6b41a828b 1410
<> 156:95d6b41a828b 1411 /* Restore husart->State to Ready */
<> 156:95d6b41a828b 1412 husart->State = HAL_USART_STATE_READY;
<> 156:95d6b41a828b 1413
<> 156:95d6b41a828b 1414 /* Reset Handle ErrorCode to No Error */
<> 156:95d6b41a828b 1415 husart->ErrorCode = HAL_USART_ERROR_NONE;
<> 156:95d6b41a828b 1416
<> 156:95d6b41a828b 1417 return HAL_OK;
<> 156:95d6b41a828b 1418 }
<> 156:95d6b41a828b 1419
<> 156:95d6b41a828b 1420 /**
<> 156:95d6b41a828b 1421 * @brief Abort ongoing transfers (Interrupt mode).
<> 156:95d6b41a828b 1422 * @param husart USART handle.
<> 156:95d6b41a828b 1423 * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1424 * This procedure performs following operations :
<> 156:95d6b41a828b 1425 * - Disable USART Interrupts (Tx and Rx)
<> 156:95d6b41a828b 1426 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1427 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1428 * - Set handle State to READY
<> 156:95d6b41a828b 1429 * - At abort completion, call user abort complete callback
<> 156:95d6b41a828b 1430 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
<> 156:95d6b41a828b 1431 * considered as completed only when user abort complete callback is executed (not when exiting function).
<> 156:95d6b41a828b 1432 * @retval HAL status
<> 156:95d6b41a828b 1433 */
<> 156:95d6b41a828b 1434 HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
<> 156:95d6b41a828b 1435 {
<> 156:95d6b41a828b 1436 uint32_t abortcplt = 1U;
<> 156:95d6b41a828b 1437
<> 156:95d6b41a828b 1438 /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1439 CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
<> 156:95d6b41a828b 1440 CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1441
<> 156:95d6b41a828b 1442 /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
<> 156:95d6b41a828b 1443 before any call to DMA Abort functions */
<> 156:95d6b41a828b 1444 /* DMA Tx Handle is valid */
<> 156:95d6b41a828b 1445 if(husart->hdmatx != NULL)
<> 156:95d6b41a828b 1446 {
<> 156:95d6b41a828b 1447 /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
<> 156:95d6b41a828b 1448 Otherwise, set it to NULL */
<> 156:95d6b41a828b 1449 if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
<> 156:95d6b41a828b 1450 {
<> 156:95d6b41a828b 1451 husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
<> 156:95d6b41a828b 1452 }
<> 156:95d6b41a828b 1453 else
<> 156:95d6b41a828b 1454 {
<> 156:95d6b41a828b 1455 husart->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1456 }
<> 156:95d6b41a828b 1457 }
<> 156:95d6b41a828b 1458 /* DMA Rx Handle is valid */
<> 156:95d6b41a828b 1459 if(husart->hdmarx != NULL)
<> 156:95d6b41a828b 1460 {
<> 156:95d6b41a828b 1461 /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
<> 156:95d6b41a828b 1462 Otherwise, set it to NULL */
<> 156:95d6b41a828b 1463 if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1464 {
<> 156:95d6b41a828b 1465 husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
<> 156:95d6b41a828b 1466 }
<> 156:95d6b41a828b 1467 else
<> 156:95d6b41a828b 1468 {
<> 156:95d6b41a828b 1469 husart->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1470 }
<> 156:95d6b41a828b 1471 }
<> 156:95d6b41a828b 1472
<> 156:95d6b41a828b 1473 /* Disable the USART DMA Tx request if enabled */
<> 156:95d6b41a828b 1474 if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
<> 156:95d6b41a828b 1475 {
<> 156:95d6b41a828b 1476 /* Disable DMA Tx at USART level */
<> 156:95d6b41a828b 1477 CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1478
<> 156:95d6b41a828b 1479 /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
<> 156:95d6b41a828b 1480 if(husart->hdmatx != NULL)
<> 156:95d6b41a828b 1481 {
<> 156:95d6b41a828b 1482 /* USART Tx DMA Abort callback has already been initialised :
<> 156:95d6b41a828b 1483 will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1484
<> 156:95d6b41a828b 1485 /* Abort DMA TX */
<> 156:95d6b41a828b 1486 if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
<> 156:95d6b41a828b 1487 {
<> 156:95d6b41a828b 1488 husart->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1489 }
<> 156:95d6b41a828b 1490 else
<> 156:95d6b41a828b 1491 {
<> 156:95d6b41a828b 1492 abortcplt = 0U;
<> 156:95d6b41a828b 1493 }
<> 156:95d6b41a828b 1494 }
<> 156:95d6b41a828b 1495 }
<> 156:95d6b41a828b 1496
<> 156:95d6b41a828b 1497 /* Disable the USART DMA Rx request if enabled */
<> 156:95d6b41a828b 1498 if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1499 {
<> 156:95d6b41a828b 1500 CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1501
<> 156:95d6b41a828b 1502 /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
<> 156:95d6b41a828b 1503 if(husart->hdmarx != NULL)
<> 156:95d6b41a828b 1504 {
<> 156:95d6b41a828b 1505 /* USART Rx DMA Abort callback has already been initialised :
<> 156:95d6b41a828b 1506 will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1507
<> 156:95d6b41a828b 1508 /* Abort DMA RX */
<> 156:95d6b41a828b 1509 if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
<> 156:95d6b41a828b 1510 {
<> 156:95d6b41a828b 1511 husart->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1512 abortcplt = 1U;
<> 156:95d6b41a828b 1513 }
<> 156:95d6b41a828b 1514 else
<> 156:95d6b41a828b 1515 {
<> 156:95d6b41a828b 1516 abortcplt = 0U;
<> 156:95d6b41a828b 1517 }
<> 156:95d6b41a828b 1518 }
<> 156:95d6b41a828b 1519 }
<> 156:95d6b41a828b 1520
<> 156:95d6b41a828b 1521 /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
<> 156:95d6b41a828b 1522 if (abortcplt == 1U)
<> 156:95d6b41a828b 1523 {
<> 156:95d6b41a828b 1524 /* Reset Tx and Rx transfer counters */
<> 156:95d6b41a828b 1525 husart->TxXferCount = 0U;
<> 156:95d6b41a828b 1526 husart->RxXferCount = 0U;
<> 156:95d6b41a828b 1527
<> 156:95d6b41a828b 1528 /* Reset errorCode */
<> 156:95d6b41a828b 1529 husart->ErrorCode = HAL_USART_ERROR_NONE;
<> 156:95d6b41a828b 1530
<> 156:95d6b41a828b 1531 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 1532 __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
<> 156:95d6b41a828b 1533
<> 156:95d6b41a828b 1534 /* Restore husart->State to Ready */
<> 156:95d6b41a828b 1535 husart->State = HAL_USART_STATE_READY;
<> 156:95d6b41a828b 1536
<> 156:95d6b41a828b 1537 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 156:95d6b41a828b 1538 HAL_USART_AbortCpltCallback(husart);
<> 156:95d6b41a828b 1539 }
<> 156:95d6b41a828b 1540
<> 156:95d6b41a828b 1541 return HAL_OK;
<> 156:95d6b41a828b 1542 }
<> 156:95d6b41a828b 1543
<> 156:95d6b41a828b 1544 /**
<> 144:ef7eb2e8f9f7 1545 * @brief Handle USART interrupt request.
<> 156:95d6b41a828b 1546 * @param husart USART handle.
<> 144:ef7eb2e8f9f7 1547 * @retval None
<> 144:ef7eb2e8f9f7 1548 */
<> 144:ef7eb2e8f9f7 1549 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 1550 {
<> 156:95d6b41a828b 1551 uint32_t isrflags = READ_REG(husart->Instance->ISR);
<> 156:95d6b41a828b 1552 uint32_t cr1its = READ_REG(husart->Instance->CR1);
<> 156:95d6b41a828b 1553 uint32_t cr3its;
<> 156:95d6b41a828b 1554 uint32_t errorflags;
<> 144:ef7eb2e8f9f7 1555
<> 156:95d6b41a828b 1556 /* If no error occurs */
<> 156:95d6b41a828b 1557 errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
<> 156:95d6b41a828b 1558 if (errorflags == RESET)
<> 144:ef7eb2e8f9f7 1559 {
<> 156:95d6b41a828b 1560 /* USART in mode Receiver ---------------------------------------------------*/
<> 156:95d6b41a828b 1561 if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<> 144:ef7eb2e8f9f7 1562 {
<> 156:95d6b41a828b 1563 if(husart->State == HAL_USART_STATE_BUSY_RX)
<> 156:95d6b41a828b 1564 {
<> 156:95d6b41a828b 1565 USART_Receive_IT(husart);
<> 156:95d6b41a828b 1566 }
<> 156:95d6b41a828b 1567 else
<> 156:95d6b41a828b 1568 {
<> 156:95d6b41a828b 1569 USART_TransmitReceive_IT(husart);
<> 156:95d6b41a828b 1570 }
<> 156:95d6b41a828b 1571 return;
<> 144:ef7eb2e8f9f7 1572 }
<> 144:ef7eb2e8f9f7 1573 }
<> 144:ef7eb2e8f9f7 1574
<> 156:95d6b41a828b 1575 /* If some errors occur */
<> 156:95d6b41a828b 1576 cr3its = READ_REG(husart->Instance->CR3);
<> 156:95d6b41a828b 1577 if( (errorflags != RESET)
<> 156:95d6b41a828b 1578 && ( ((cr3its & USART_CR3_EIE) != RESET)
<> 156:95d6b41a828b 1579 || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
<> 156:95d6b41a828b 1580 {
<> 156:95d6b41a828b 1581 /* USART parity error interrupt occurred -------------------------------------*/
<> 156:95d6b41a828b 1582 if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
<> 156:95d6b41a828b 1583 {
<> 156:95d6b41a828b 1584 __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
<> 156:95d6b41a828b 1585
<> 156:95d6b41a828b 1586 husart->ErrorCode |= HAL_USART_ERROR_PE;
<> 156:95d6b41a828b 1587 }
<> 156:95d6b41a828b 1588
<> 156:95d6b41a828b 1589 /* USART frame error interrupt occurred --------------------------------------*/
<> 156:95d6b41a828b 1590 if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<> 156:95d6b41a828b 1591 {
<> 156:95d6b41a828b 1592 __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
<> 156:95d6b41a828b 1593
<> 156:95d6b41a828b 1594 husart->ErrorCode |= HAL_USART_ERROR_FE;
<> 156:95d6b41a828b 1595 }
<> 156:95d6b41a828b 1596
<> 156:95d6b41a828b 1597 /* USART noise error interrupt occurred --------------------------------------*/
<> 156:95d6b41a828b 1598 if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<> 156:95d6b41a828b 1599 {
<> 156:95d6b41a828b 1600 __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
<> 156:95d6b41a828b 1601
<> 156:95d6b41a828b 1602 husart->ErrorCode |= HAL_USART_ERROR_NE;
<> 156:95d6b41a828b 1603 }
<> 156:95d6b41a828b 1604
<> 156:95d6b41a828b 1605 /* USART Over-Run interrupt occurred -----------------------------------------*/
<> 156:95d6b41a828b 1606 if(((isrflags & USART_ISR_ORE) != RESET) &&
<> 156:95d6b41a828b 1607 (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
<> 156:95d6b41a828b 1608 {
<> 156:95d6b41a828b 1609 __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
<> 156:95d6b41a828b 1610
<> 156:95d6b41a828b 1611 husart->ErrorCode |= HAL_USART_ERROR_ORE;
<> 156:95d6b41a828b 1612 }
<> 156:95d6b41a828b 1613
<> 156:95d6b41a828b 1614 /* Call USART Error Call back function if need be --------------------------*/
<> 156:95d6b41a828b 1615 if(husart->ErrorCode != HAL_USART_ERROR_NONE)
<> 156:95d6b41a828b 1616 {
<> 156:95d6b41a828b 1617 /* USART in mode Receiver ---------------------------------------------------*/
<> 156:95d6b41a828b 1618 if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<> 156:95d6b41a828b 1619 {
<> 156:95d6b41a828b 1620 if(husart->State == HAL_USART_STATE_BUSY_RX)
<> 156:95d6b41a828b 1621 {
<> 156:95d6b41a828b 1622 USART_Receive_IT(husart);
<> 156:95d6b41a828b 1623 }
<> 156:95d6b41a828b 1624 else
<> 156:95d6b41a828b 1625 {
<> 156:95d6b41a828b 1626 USART_TransmitReceive_IT(husart);
<> 156:95d6b41a828b 1627 }
<> 156:95d6b41a828b 1628 }
<> 156:95d6b41a828b 1629
<> 156:95d6b41a828b 1630 /* If Overrun error occurs, or if any error occurs in DMA mode reception,
<> 156:95d6b41a828b 1631 consider error as blocking */
<> 156:95d6b41a828b 1632 if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) ||
<> 156:95d6b41a828b 1633 (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
<> 156:95d6b41a828b 1634 {
<> 156:95d6b41a828b 1635 /* Blocking error : transfer is aborted
<> 156:95d6b41a828b 1636 Set the USART state ready to be able to start again the process,
<> 156:95d6b41a828b 1637 Disable Interrupts, and disable DMA requests, if ongoing */
<> 156:95d6b41a828b 1638 USART_EndTransfer(husart);
<> 156:95d6b41a828b 1639
<> 156:95d6b41a828b 1640 /* Disable the USART DMA Rx request if enabled */
<> 156:95d6b41a828b 1641 if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1642 {
<> 156:95d6b41a828b 1643 CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
<> 156:95d6b41a828b 1644
<> 156:95d6b41a828b 1645 /* Abort the USART DMA Tx channel */
<> 156:95d6b41a828b 1646 if(husart->hdmatx != NULL)
<> 156:95d6b41a828b 1647 {
<> 156:95d6b41a828b 1648 /* Set the USART Tx DMA Abort callback to NULL : no callback
<> 156:95d6b41a828b 1649 executed at end of DMA abort procedure */
<> 156:95d6b41a828b 1650 husart->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1651
<> 156:95d6b41a828b 1652 /* Abort DMA TX */
<> 156:95d6b41a828b 1653 HAL_DMA_Abort_IT(husart->hdmatx);
<> 156:95d6b41a828b 1654 }
<> 156:95d6b41a828b 1655
<> 156:95d6b41a828b 1656 /* Abort the USART DMA Rx channel */
<> 156:95d6b41a828b 1657 if(husart->hdmarx != NULL)
<> 156:95d6b41a828b 1658 {
<> 156:95d6b41a828b 1659 /* Set the USART Rx DMA Abort callback :
<> 156:95d6b41a828b 1660 will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1661 husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
<> 156:95d6b41a828b 1662
<> 156:95d6b41a828b 1663 /* Abort DMA RX */
<> 156:95d6b41a828b 1664 if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
<> 156:95d6b41a828b 1665 {
<> 156:95d6b41a828b 1666 /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
<> 156:95d6b41a828b 1667 husart->hdmarx->XferAbortCallback(husart->hdmarx);
<> 156:95d6b41a828b 1668 }
<> 156:95d6b41a828b 1669 }
<> 156:95d6b41a828b 1670 else
<> 156:95d6b41a828b 1671 {
<> 156:95d6b41a828b 1672 /* Call user error callback */
<> 156:95d6b41a828b 1673 HAL_USART_ErrorCallback(husart);
<> 156:95d6b41a828b 1674 }
<> 156:95d6b41a828b 1675 }
<> 156:95d6b41a828b 1676 else
<> 156:95d6b41a828b 1677 {
<> 156:95d6b41a828b 1678 /* Call user error callback */
<> 156:95d6b41a828b 1679 HAL_USART_ErrorCallback(husart);
<> 156:95d6b41a828b 1680 }
<> 156:95d6b41a828b 1681 }
<> 156:95d6b41a828b 1682 else
<> 156:95d6b41a828b 1683 {
<> 156:95d6b41a828b 1684 /* Non Blocking error : transfer could go on.
<> 156:95d6b41a828b 1685 Error is notified to user through user error callback */
<> 156:95d6b41a828b 1686 HAL_USART_ErrorCallback(husart);
<> 156:95d6b41a828b 1687 husart->ErrorCode = HAL_USART_ERROR_NONE;
<> 156:95d6b41a828b 1688 }
<> 156:95d6b41a828b 1689 }
<> 156:95d6b41a828b 1690 return;
<> 156:95d6b41a828b 1691
<> 156:95d6b41a828b 1692 } /* End if some error occurs */
<> 156:95d6b41a828b 1693
<> 156:95d6b41a828b 1694
<> 156:95d6b41a828b 1695 /* USART in mode Transmitter ------------------------------------------------*/
<> 156:95d6b41a828b 1696 if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
<> 144:ef7eb2e8f9f7 1697 {
<> 144:ef7eb2e8f9f7 1698 if(husart->State == HAL_USART_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1699 {
<> 144:ef7eb2e8f9f7 1700 USART_Transmit_IT(husart);
<> 144:ef7eb2e8f9f7 1701 }
<> 144:ef7eb2e8f9f7 1702 else
<> 144:ef7eb2e8f9f7 1703 {
<> 144:ef7eb2e8f9f7 1704 USART_TransmitReceive_IT(husart);
<> 144:ef7eb2e8f9f7 1705 }
<> 156:95d6b41a828b 1706 return;
<> 144:ef7eb2e8f9f7 1707 }
<> 144:ef7eb2e8f9f7 1708
<> 144:ef7eb2e8f9f7 1709 /* USART in mode Transmitter (transmission end) -----------------------------*/
<> 156:95d6b41a828b 1710 if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
<> 144:ef7eb2e8f9f7 1711 {
<> 144:ef7eb2e8f9f7 1712 USART_EndTransmit_IT(husart);
<> 156:95d6b41a828b 1713 return;
<> 144:ef7eb2e8f9f7 1714 }
<> 144:ef7eb2e8f9f7 1715
<> 144:ef7eb2e8f9f7 1716 }
<> 144:ef7eb2e8f9f7 1717
<> 144:ef7eb2e8f9f7 1718 /**
<> 144:ef7eb2e8f9f7 1719 * @brief Tx Transfer completed callback.
Anna Bridge 180:96ed750bd169 1720 * @param husart USART handle.
<> 144:ef7eb2e8f9f7 1721 * @retval None
<> 144:ef7eb2e8f9f7 1722 */
<> 144:ef7eb2e8f9f7 1723 __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 1724 {
<> 144:ef7eb2e8f9f7 1725 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1726 UNUSED(husart);
<> 144:ef7eb2e8f9f7 1727
<> 144:ef7eb2e8f9f7 1728 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1729 the HAL_USART_TxCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1730 */
<> 144:ef7eb2e8f9f7 1731 }
<> 144:ef7eb2e8f9f7 1732
<> 144:ef7eb2e8f9f7 1733 /**
<> 144:ef7eb2e8f9f7 1734 * @brief Tx Half Transfer completed callback.
Anna Bridge 180:96ed750bd169 1735 * @param husart USART handle.
<> 144:ef7eb2e8f9f7 1736 * @retval None
<> 144:ef7eb2e8f9f7 1737 */
<> 156:95d6b41a828b 1738 __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 1739 {
<> 144:ef7eb2e8f9f7 1740 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1741 UNUSED(husart);
<> 144:ef7eb2e8f9f7 1742
<> 144:ef7eb2e8f9f7 1743 /* NOTE: This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1744 the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1745 */
<> 144:ef7eb2e8f9f7 1746 }
<> 144:ef7eb2e8f9f7 1747
<> 144:ef7eb2e8f9f7 1748 /**
<> 144:ef7eb2e8f9f7 1749 * @brief Rx Transfer completed callback.
Anna Bridge 180:96ed750bd169 1750 * @param husart USART handle.
<> 144:ef7eb2e8f9f7 1751 * @retval None
<> 144:ef7eb2e8f9f7 1752 */
<> 144:ef7eb2e8f9f7 1753 __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 1754 {
<> 144:ef7eb2e8f9f7 1755 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1756 UNUSED(husart);
<> 144:ef7eb2e8f9f7 1757
<> 144:ef7eb2e8f9f7 1758 /* NOTE: This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1759 the HAL_USART_RxCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1760 */
<> 144:ef7eb2e8f9f7 1761 }
<> 144:ef7eb2e8f9f7 1762
<> 144:ef7eb2e8f9f7 1763 /**
<> 144:ef7eb2e8f9f7 1764 * @brief Rx Half Transfer completed callback.
Anna Bridge 180:96ed750bd169 1765 * @param husart USART handle.
<> 144:ef7eb2e8f9f7 1766 * @retval None
<> 144:ef7eb2e8f9f7 1767 */
<> 144:ef7eb2e8f9f7 1768 __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 1769 {
<> 144:ef7eb2e8f9f7 1770 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1771 UNUSED(husart);
<> 144:ef7eb2e8f9f7 1772
<> 144:ef7eb2e8f9f7 1773 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1774 the HAL_USART_RxHalfCpltCallback can be implemented in the user file
<> 144:ef7eb2e8f9f7 1775 */
<> 144:ef7eb2e8f9f7 1776 }
<> 144:ef7eb2e8f9f7 1777
<> 144:ef7eb2e8f9f7 1778 /**
<> 144:ef7eb2e8f9f7 1779 * @brief Tx/Rx Transfers completed callback for the non-blocking process.
Anna Bridge 180:96ed750bd169 1780 * @param husart USART handle.
<> 144:ef7eb2e8f9f7 1781 * @retval None
<> 144:ef7eb2e8f9f7 1782 */
<> 144:ef7eb2e8f9f7 1783 __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 1784 {
<> 144:ef7eb2e8f9f7 1785 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1786 UNUSED(husart);
<> 144:ef7eb2e8f9f7 1787
<> 144:ef7eb2e8f9f7 1788 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1789 the HAL_USART_TxRxCpltCallback can be implemented in the user file
<> 144:ef7eb2e8f9f7 1790 */
<> 144:ef7eb2e8f9f7 1791 }
<> 144:ef7eb2e8f9f7 1792
<> 144:ef7eb2e8f9f7 1793 /**
<> 144:ef7eb2e8f9f7 1794 * @brief USART error callback.
Anna Bridge 180:96ed750bd169 1795 * @param husart USART handle.
<> 144:ef7eb2e8f9f7 1796 * @retval None
<> 144:ef7eb2e8f9f7 1797 */
<> 144:ef7eb2e8f9f7 1798 __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 1799 {
<> 144:ef7eb2e8f9f7 1800 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1801 UNUSED(husart);
<> 144:ef7eb2e8f9f7 1802
<> 144:ef7eb2e8f9f7 1803 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1804 the HAL_USART_ErrorCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1805 */
<> 144:ef7eb2e8f9f7 1806 }
<> 144:ef7eb2e8f9f7 1807
<> 144:ef7eb2e8f9f7 1808 /**
<> 156:95d6b41a828b 1809 * @brief USART Abort Complete callback.
<> 156:95d6b41a828b 1810 * @param husart USART handle.
<> 156:95d6b41a828b 1811 * @retval None
<> 156:95d6b41a828b 1812 */
<> 156:95d6b41a828b 1813 __weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
<> 156:95d6b41a828b 1814 {
<> 156:95d6b41a828b 1815 /* Prevent unused argument(s) compilation warning */
<> 156:95d6b41a828b 1816 UNUSED(husart);
<> 156:95d6b41a828b 1817
<> 156:95d6b41a828b 1818 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1819 the HAL_USART_AbortCpltCallback can be implemented in the user file.
<> 156:95d6b41a828b 1820 */
<> 156:95d6b41a828b 1821 }
<> 156:95d6b41a828b 1822
<> 156:95d6b41a828b 1823 /**
<> 144:ef7eb2e8f9f7 1824 * @}
<> 144:ef7eb2e8f9f7 1825 */
<> 144:ef7eb2e8f9f7 1826
<> 144:ef7eb2e8f9f7 1827 /** @defgroup USART_Exported_Functions_Group3 Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 1828 * @brief USART Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 1829 *
<> 144:ef7eb2e8f9f7 1830 @verbatim
<> 144:ef7eb2e8f9f7 1831 ==============================================================================
<> 144:ef7eb2e8f9f7 1832 ##### Peripheral State and Error functions #####
<> 144:ef7eb2e8f9f7 1833 ==============================================================================
<> 144:ef7eb2e8f9f7 1834 [..]
<> 144:ef7eb2e8f9f7 1835 This subsection provides functions allowing to :
<> 144:ef7eb2e8f9f7 1836 (+) Return the USART handle state
<> 144:ef7eb2e8f9f7 1837 (+) Return the USART handle error code
<> 144:ef7eb2e8f9f7 1838
<> 144:ef7eb2e8f9f7 1839 @endverbatim
<> 144:ef7eb2e8f9f7 1840 * @{
<> 144:ef7eb2e8f9f7 1841 */
<> 144:ef7eb2e8f9f7 1842
<> 144:ef7eb2e8f9f7 1843
<> 144:ef7eb2e8f9f7 1844 /**
<> 144:ef7eb2e8f9f7 1845 * @brief Return the USART handle state.
Anna Bridge 180:96ed750bd169 1846 * @param husart pointer to a USART_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1847 * the configuration information for the specified USART.
<> 144:ef7eb2e8f9f7 1848 * @retval USART handle state
<> 144:ef7eb2e8f9f7 1849 */
<> 144:ef7eb2e8f9f7 1850 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 1851 {
<> 144:ef7eb2e8f9f7 1852 return husart->State;
<> 144:ef7eb2e8f9f7 1853 }
<> 144:ef7eb2e8f9f7 1854
<> 144:ef7eb2e8f9f7 1855 /**
<> 144:ef7eb2e8f9f7 1856 * @brief Return the USART error code.
Anna Bridge 180:96ed750bd169 1857 * @param husart pointer to a USART_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1858 * the configuration information for the specified USART.
<> 144:ef7eb2e8f9f7 1859 * @retval USART handle Error Code
<> 144:ef7eb2e8f9f7 1860 */
<> 144:ef7eb2e8f9f7 1861 uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 1862 {
<> 144:ef7eb2e8f9f7 1863 return husart->ErrorCode;
<> 144:ef7eb2e8f9f7 1864 }
<> 144:ef7eb2e8f9f7 1865
<> 144:ef7eb2e8f9f7 1866 /**
<> 144:ef7eb2e8f9f7 1867 * @}
<> 144:ef7eb2e8f9f7 1868 */
<> 144:ef7eb2e8f9f7 1869
<> 144:ef7eb2e8f9f7 1870 /**
<> 144:ef7eb2e8f9f7 1871 * @}
<> 144:ef7eb2e8f9f7 1872 */
<> 144:ef7eb2e8f9f7 1873
<> 144:ef7eb2e8f9f7 1874 /** @defgroup USART_Private_Functions USART Private Functions
<> 144:ef7eb2e8f9f7 1875 * @brief USART Private functions
<> 144:ef7eb2e8f9f7 1876 *
<> 144:ef7eb2e8f9f7 1877 @verbatim
<> 144:ef7eb2e8f9f7 1878 [..]
<> 144:ef7eb2e8f9f7 1879 This subsection provides a set of functions allowing to control the USART.
<> 144:ef7eb2e8f9f7 1880 (+) USART_SetConfig() API is used to set the USART communication parameters.
<> 144:ef7eb2e8f9f7 1881 (+) USART_CheckIdleState() APi ensures that TEACK and/or REACK bits are set after initialization
<> 144:ef7eb2e8f9f7 1882
<> 144:ef7eb2e8f9f7 1883 @endverbatim
<> 144:ef7eb2e8f9f7 1884 * @{
<> 144:ef7eb2e8f9f7 1885 */
<> 156:95d6b41a828b 1886 /**
<> 156:95d6b41a828b 1887 * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion).
<> 156:95d6b41a828b 1888 * @param husart USART handle.
<> 156:95d6b41a828b 1889 * @retval None
<> 156:95d6b41a828b 1890 */
<> 156:95d6b41a828b 1891 static void USART_EndTransfer(USART_HandleTypeDef *husart)
<> 156:95d6b41a828b 1892 {
<> 156:95d6b41a828b 1893 /* Disable TXEIE and TCIE interrupts */
<> 156:95d6b41a828b 1894 /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1895 CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | USART_CR1_PEIE));
<> 156:95d6b41a828b 1896 CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1897
<> 156:95d6b41a828b 1898 /* At end of process, restore husart->State to Ready */
<> 156:95d6b41a828b 1899 husart->State = HAL_USART_STATE_READY;
<> 156:95d6b41a828b 1900 }
<> 156:95d6b41a828b 1901
<> 156:95d6b41a828b 1902 /**
<> 156:95d6b41a828b 1903 * @brief DMA USART transmit process complete callback.
<> 156:95d6b41a828b 1904 * @param hdma DMA handle.
<> 156:95d6b41a828b 1905 * @retval None
<> 156:95d6b41a828b 1906 */
<> 156:95d6b41a828b 1907 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 1908 {
<> 156:95d6b41a828b 1909 USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
<> 156:95d6b41a828b 1910
<> 156:95d6b41a828b 1911 /* DMA Normal mode */
<> 156:95d6b41a828b 1912 if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
<> 156:95d6b41a828b 1913 {
<> 156:95d6b41a828b 1914 husart->TxXferCount = 0U;
<> 156:95d6b41a828b 1915
<> 156:95d6b41a828b 1916 if(husart->State == HAL_USART_STATE_BUSY_TX)
<> 156:95d6b41a828b 1917 {
<> 156:95d6b41a828b 1918 /* Disable the DMA transfer for transmit request by resetting the DMAT bit
<> 156:95d6b41a828b 1919 in the USART CR3 register */
<> 156:95d6b41a828b 1920 CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1921
<> 156:95d6b41a828b 1922 /* Enable the USART Transmit Complete Interrupt */
<> 156:95d6b41a828b 1923 __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
<> 156:95d6b41a828b 1924 }
<> 156:95d6b41a828b 1925 }
<> 156:95d6b41a828b 1926 /* DMA Circular mode */
<> 156:95d6b41a828b 1927 else
<> 156:95d6b41a828b 1928 {
<> 156:95d6b41a828b 1929 if(husart->State == HAL_USART_STATE_BUSY_TX)
<> 156:95d6b41a828b 1930 {
<> 156:95d6b41a828b 1931 HAL_USART_TxCpltCallback(husart);
<> 156:95d6b41a828b 1932 }
<> 156:95d6b41a828b 1933 }
<> 156:95d6b41a828b 1934 }
<> 156:95d6b41a828b 1935
<> 156:95d6b41a828b 1936 /**
<> 156:95d6b41a828b 1937 * @brief DMA USART transmit process half complete callback.
<> 156:95d6b41a828b 1938 * @param hdma DMA handle.
<> 156:95d6b41a828b 1939 * @retval None
<> 156:95d6b41a828b 1940 */
<> 156:95d6b41a828b 1941 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 1942 {
<> 156:95d6b41a828b 1943 USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
<> 156:95d6b41a828b 1944
<> 156:95d6b41a828b 1945 HAL_USART_TxHalfCpltCallback(husart);
<> 156:95d6b41a828b 1946 }
<> 156:95d6b41a828b 1947
<> 156:95d6b41a828b 1948 /**
<> 156:95d6b41a828b 1949 * @brief DMA USART receive process complete callback.
<> 156:95d6b41a828b 1950 * @param hdma DMA handle.
<> 156:95d6b41a828b 1951 * @retval None
<> 156:95d6b41a828b 1952 */
<> 156:95d6b41a828b 1953 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 1954 {
<> 156:95d6b41a828b 1955 USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
<> 156:95d6b41a828b 1956
<> 156:95d6b41a828b 1957 /* DMA Normal mode */
<> 156:95d6b41a828b 1958 if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
<> 156:95d6b41a828b 1959 {
<> 156:95d6b41a828b 1960 husart->RxXferCount = 0U;
<> 156:95d6b41a828b 1961
<> 156:95d6b41a828b 1962 /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1963 CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
<> 156:95d6b41a828b 1964 CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1965
<> 156:95d6b41a828b 1966 /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
<> 156:95d6b41a828b 1967 in USART CR3 register */
<> 156:95d6b41a828b 1968 CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1969 /* similarly, disable the DMA TX transfer that was started to provide the
<> 156:95d6b41a828b 1970 clock to the slave device */
<> 156:95d6b41a828b 1971 CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1972
<> 156:95d6b41a828b 1973 if(husart->State == HAL_USART_STATE_BUSY_RX)
<> 156:95d6b41a828b 1974 {
<> 156:95d6b41a828b 1975 HAL_USART_RxCpltCallback(husart);
<> 156:95d6b41a828b 1976 }
<> 156:95d6b41a828b 1977 /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
<> 156:95d6b41a828b 1978 else
<> 156:95d6b41a828b 1979 {
<> 156:95d6b41a828b 1980 HAL_USART_TxRxCpltCallback(husart);
<> 156:95d6b41a828b 1981 }
<> 156:95d6b41a828b 1982 husart->State= HAL_USART_STATE_READY;
<> 156:95d6b41a828b 1983 }
<> 156:95d6b41a828b 1984 /* DMA circular mode */
<> 156:95d6b41a828b 1985 else
<> 156:95d6b41a828b 1986 {
<> 156:95d6b41a828b 1987 if(husart->State == HAL_USART_STATE_BUSY_RX)
<> 156:95d6b41a828b 1988 {
<> 156:95d6b41a828b 1989 HAL_USART_RxCpltCallback(husart);
<> 156:95d6b41a828b 1990 }
<> 156:95d6b41a828b 1991 /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
<> 156:95d6b41a828b 1992 else
<> 156:95d6b41a828b 1993 {
<> 156:95d6b41a828b 1994 HAL_USART_TxRxCpltCallback(husart);
<> 156:95d6b41a828b 1995 }
<> 156:95d6b41a828b 1996 }
<> 156:95d6b41a828b 1997
<> 156:95d6b41a828b 1998 }
<> 156:95d6b41a828b 1999
<> 156:95d6b41a828b 2000 /**
<> 156:95d6b41a828b 2001 * @brief DMA USART receive process half complete callback.
<> 156:95d6b41a828b 2002 * @param hdma DMA handle.
<> 156:95d6b41a828b 2003 * @retval None
<> 156:95d6b41a828b 2004 */
<> 156:95d6b41a828b 2005 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2006 {
<> 156:95d6b41a828b 2007 USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
<> 156:95d6b41a828b 2008
<> 156:95d6b41a828b 2009 HAL_USART_RxHalfCpltCallback(husart);
<> 156:95d6b41a828b 2010 }
<> 156:95d6b41a828b 2011
<> 156:95d6b41a828b 2012 /**
<> 156:95d6b41a828b 2013 * @brief DMA USART communication error callback.
Anna Bridge 180:96ed750bd169 2014 * @param hdma DMA handle.
<> 156:95d6b41a828b 2015 * @retval None
<> 156:95d6b41a828b 2016 */
<> 156:95d6b41a828b 2017 static void USART_DMAError(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2018 {
<> 156:95d6b41a828b 2019 USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
<> 156:95d6b41a828b 2020
<> 156:95d6b41a828b 2021 husart->RxXferCount = 0U;
<> 156:95d6b41a828b 2022 husart->TxXferCount = 0U;
<> 156:95d6b41a828b 2023 USART_EndTransfer(husart);
<> 156:95d6b41a828b 2024
<> 156:95d6b41a828b 2025 husart->ErrorCode |= HAL_USART_ERROR_DMA;
<> 156:95d6b41a828b 2026 husart->State= HAL_USART_STATE_READY;
<> 156:95d6b41a828b 2027
<> 156:95d6b41a828b 2028 HAL_USART_ErrorCallback(husart);
<> 156:95d6b41a828b 2029 }
<> 156:95d6b41a828b 2030
<> 156:95d6b41a828b 2031 /**
<> 156:95d6b41a828b 2032 * @brief DMA USART communication abort callback, when initiated by HAL services on Error
<> 156:95d6b41a828b 2033 * (To be called at end of DMA Abort procedure following error occurrence).
<> 156:95d6b41a828b 2034 * @param hdma DMA handle.
<> 156:95d6b41a828b 2035 * @retval None
<> 156:95d6b41a828b 2036 */
<> 156:95d6b41a828b 2037 static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2038 {
<> 156:95d6b41a828b 2039 USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
<> 156:95d6b41a828b 2040 husart->RxXferCount = 0U;
<> 156:95d6b41a828b 2041 husart->TxXferCount = 0U;
<> 156:95d6b41a828b 2042
<> 156:95d6b41a828b 2043 HAL_USART_ErrorCallback(husart);
<> 156:95d6b41a828b 2044 }
<> 156:95d6b41a828b 2045
<> 156:95d6b41a828b 2046 /**
<> 156:95d6b41a828b 2047 * @brief DMA USART Tx communication abort callback, when initiated by user
<> 156:95d6b41a828b 2048 * (To be called at end of DMA Tx Abort procedure following user abort request).
<> 156:95d6b41a828b 2049 * @note When this callback is executed, User Abort complete call back is called only if no
<> 156:95d6b41a828b 2050 * Abort still ongoing for Rx DMA Handle.
<> 156:95d6b41a828b 2051 * @param hdma DMA handle.
<> 156:95d6b41a828b 2052 * @retval None
<> 156:95d6b41a828b 2053 */
<> 156:95d6b41a828b 2054 static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2055 {
<> 156:95d6b41a828b 2056 USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
<> 156:95d6b41a828b 2057
<> 156:95d6b41a828b 2058 husart->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2059
<> 156:95d6b41a828b 2060 /* Check if an Abort process is still ongoing */
<> 156:95d6b41a828b 2061 if(husart->hdmarx != NULL)
<> 156:95d6b41a828b 2062 {
<> 156:95d6b41a828b 2063 if(husart->hdmarx->XferAbortCallback != NULL)
<> 156:95d6b41a828b 2064 {
<> 156:95d6b41a828b 2065 return;
<> 156:95d6b41a828b 2066 }
<> 156:95d6b41a828b 2067 }
<> 156:95d6b41a828b 2068
<> 156:95d6b41a828b 2069 /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
<> 156:95d6b41a828b 2070 husart->TxXferCount = 0U;
<> 156:95d6b41a828b 2071 husart->RxXferCount = 0U;
<> 156:95d6b41a828b 2072
<> 156:95d6b41a828b 2073 /* Reset errorCode */
<> 156:95d6b41a828b 2074 husart->ErrorCode = HAL_USART_ERROR_NONE;
<> 156:95d6b41a828b 2075
<> 156:95d6b41a828b 2076 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 2077 __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
<> 156:95d6b41a828b 2078
<> 156:95d6b41a828b 2079 /* Restore husart->State to Ready */
<> 156:95d6b41a828b 2080 husart->State = HAL_USART_STATE_READY;
<> 156:95d6b41a828b 2081
<> 156:95d6b41a828b 2082 /* Call user Abort complete callback */
<> 156:95d6b41a828b 2083 HAL_USART_AbortCpltCallback(husart);
<> 156:95d6b41a828b 2084 }
<> 156:95d6b41a828b 2085
<> 156:95d6b41a828b 2086
<> 156:95d6b41a828b 2087 /**
<> 156:95d6b41a828b 2088 * @brief DMA USART Rx communication abort callback, when initiated by user
<> 156:95d6b41a828b 2089 * (To be called at end of DMA Rx Abort procedure following user abort request).
<> 156:95d6b41a828b 2090 * @note When this callback is executed, User Abort complete call back is called only if no
<> 156:95d6b41a828b 2091 * Abort still ongoing for Tx DMA Handle.
<> 156:95d6b41a828b 2092 * @param hdma DMA handle.
<> 156:95d6b41a828b 2093 * @retval None
<> 156:95d6b41a828b 2094 */
<> 156:95d6b41a828b 2095 static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2096 {
<> 156:95d6b41a828b 2097 USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
<> 156:95d6b41a828b 2098
<> 156:95d6b41a828b 2099 husart->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2100
<> 156:95d6b41a828b 2101 /* Check if an Abort process is still ongoing */
<> 156:95d6b41a828b 2102 if(husart->hdmatx != NULL)
<> 156:95d6b41a828b 2103 {
<> 156:95d6b41a828b 2104 if(husart->hdmatx->XferAbortCallback != NULL)
<> 156:95d6b41a828b 2105 {
<> 156:95d6b41a828b 2106 return;
<> 156:95d6b41a828b 2107 }
<> 156:95d6b41a828b 2108 }
<> 156:95d6b41a828b 2109
<> 156:95d6b41a828b 2110 /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
<> 156:95d6b41a828b 2111 husart->TxXferCount = 0U;
<> 156:95d6b41a828b 2112 husart->RxXferCount = 0U;
<> 156:95d6b41a828b 2113
<> 156:95d6b41a828b 2114 /* Reset errorCode */
<> 156:95d6b41a828b 2115 husart->ErrorCode = HAL_USART_ERROR_NONE;
<> 156:95d6b41a828b 2116
<> 156:95d6b41a828b 2117 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 2118 __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
<> 156:95d6b41a828b 2119
<> 156:95d6b41a828b 2120 /* Restore husart->State to Ready */
<> 156:95d6b41a828b 2121 husart->State = HAL_USART_STATE_READY;
<> 156:95d6b41a828b 2122
<> 156:95d6b41a828b 2123 /* Call user Abort complete callback */
<> 156:95d6b41a828b 2124 HAL_USART_AbortCpltCallback(husart);
<> 156:95d6b41a828b 2125 }
<> 156:95d6b41a828b 2126
<> 156:95d6b41a828b 2127
<> 156:95d6b41a828b 2128 /**
<> 156:95d6b41a828b 2129 * @brief Handle USART Communication Timeout.
<> 156:95d6b41a828b 2130 * @param husart USART handle.
<> 156:95d6b41a828b 2131 * @param Flag Specifies the USART flag to check.
<> 156:95d6b41a828b 2132 * @param Status the Flag status (SET or RESET).
<> 156:95d6b41a828b 2133 * @param Tickstart Tick start value
<> 156:95d6b41a828b 2134 * @param Timeout timeout duration.
<> 156:95d6b41a828b 2135 * @retval HAL status
<> 156:95d6b41a828b 2136 */
<> 156:95d6b41a828b 2137 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
<> 156:95d6b41a828b 2138 {
<> 156:95d6b41a828b 2139 /* Wait until flag is set */
<> 156:95d6b41a828b 2140 while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
<> 156:95d6b41a828b 2141 {
<> 156:95d6b41a828b 2142 /* Check for the Timeout */
<> 156:95d6b41a828b 2143 if(Timeout != HAL_MAX_DELAY)
<> 156:95d6b41a828b 2144 {
<> 156:95d6b41a828b 2145 if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
<> 156:95d6b41a828b 2146 {
<> 156:95d6b41a828b 2147 /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
<> 156:95d6b41a828b 2148 CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
<> 156:95d6b41a828b 2149 CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 2150
<> 156:95d6b41a828b 2151 husart->State= HAL_USART_STATE_READY;
<> 156:95d6b41a828b 2152
<> 156:95d6b41a828b 2153 /* Process Unlocked */
<> 156:95d6b41a828b 2154 __HAL_UNLOCK(husart);
<> 156:95d6b41a828b 2155
<> 156:95d6b41a828b 2156 return HAL_TIMEOUT;
<> 156:95d6b41a828b 2157 }
<> 156:95d6b41a828b 2158 }
<> 156:95d6b41a828b 2159 }
<> 156:95d6b41a828b 2160 return HAL_OK;
<> 156:95d6b41a828b 2161 }
<> 156:95d6b41a828b 2162
<> 144:ef7eb2e8f9f7 2163
<> 144:ef7eb2e8f9f7 2164 /**
<> 144:ef7eb2e8f9f7 2165 * @brief Configure the USART peripheral.
Anna Bridge 180:96ed750bd169 2166 * @param husart USART handle.
<> 144:ef7eb2e8f9f7 2167 * @retval HAL status
<> 144:ef7eb2e8f9f7 2168 */
<> 144:ef7eb2e8f9f7 2169 static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 2170 {
<> 156:95d6b41a828b 2171 uint32_t tmpreg = 0x0U;
<> 144:ef7eb2e8f9f7 2172 USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;
<> 144:ef7eb2e8f9f7 2173 HAL_StatusTypeDef ret = HAL_OK;
<> 156:95d6b41a828b 2174 uint16_t brrtemp = 0x0000U;
<> 156:95d6b41a828b 2175 uint16_t usartdiv = 0x0000U;
<> 144:ef7eb2e8f9f7 2176
<> 144:ef7eb2e8f9f7 2177 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2178 assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
<> 144:ef7eb2e8f9f7 2179 assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
<> 144:ef7eb2e8f9f7 2180 assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
<> 144:ef7eb2e8f9f7 2181 assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2182 assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
<> 144:ef7eb2e8f9f7 2183 assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
<> 144:ef7eb2e8f9f7 2184 assert_param(IS_USART_PARITY(husart->Init.Parity));
<> 144:ef7eb2e8f9f7 2185 assert_param(IS_USART_MODE(husart->Init.Mode));
<> 144:ef7eb2e8f9f7 2186
<> 144:ef7eb2e8f9f7 2187
<> 144:ef7eb2e8f9f7 2188 /*-------------------------- USART CR1 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 2189 /* Clear M, PCE, PS, TE and RE bits and configure
<> 144:ef7eb2e8f9f7 2190 * the USART Word Length, Parity and Mode:
<> 144:ef7eb2e8f9f7 2191 * set the M bits according to husart->Init.WordLength value
<> 144:ef7eb2e8f9f7 2192 * set PCE and PS bits according to husart->Init.Parity value
<> 144:ef7eb2e8f9f7 2193 * set TE and RE bits according to husart->Init.Mode value
<> 144:ef7eb2e8f9f7 2194 * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
<> 144:ef7eb2e8f9f7 2195 tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
<> 144:ef7eb2e8f9f7 2196 MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
<> 144:ef7eb2e8f9f7 2197
<> 144:ef7eb2e8f9f7 2198 /*---------------------------- USART CR2 Configuration ---------------------*/
<> 144:ef7eb2e8f9f7 2199 /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
<> 144:ef7eb2e8f9f7 2200 * set CPOL bit according to husart->Init.CLKPolarity value
<> 144:ef7eb2e8f9f7 2201 * set CPHA bit according to husart->Init.CLKPhase value
<> 144:ef7eb2e8f9f7 2202 * set LBCL bit according to husart->Init.CLKLastBit value
<> 144:ef7eb2e8f9f7 2203 * set STOP[13:12] bits according to husart->Init.StopBits value */
<> 144:ef7eb2e8f9f7 2204 tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
<> 144:ef7eb2e8f9f7 2205 tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
<> 144:ef7eb2e8f9f7 2206 tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);
<> 144:ef7eb2e8f9f7 2207 MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
<> 144:ef7eb2e8f9f7 2208
<> 144:ef7eb2e8f9f7 2209 /*-------------------------- USART CR3 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 2210 /* no CR3 register configuration */
<> 144:ef7eb2e8f9f7 2211
<> 144:ef7eb2e8f9f7 2212 /*-------------------------- USART BRR Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 2213 /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */
<> 144:ef7eb2e8f9f7 2214 USART_GETCLOCKSOURCE(husart, clocksource);
<> 144:ef7eb2e8f9f7 2215 switch (clocksource)
<> 144:ef7eb2e8f9f7 2216 {
<> 144:ef7eb2e8f9f7 2217 case USART_CLOCKSOURCE_PCLK1:
<> 144:ef7eb2e8f9f7 2218 usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
<> 144:ef7eb2e8f9f7 2219 break;
<> 144:ef7eb2e8f9f7 2220 case USART_CLOCKSOURCE_HSI:
<> 144:ef7eb2e8f9f7 2221 usartdiv = (uint16_t)(((2*HSI_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
<> 144:ef7eb2e8f9f7 2222 break;
<> 144:ef7eb2e8f9f7 2223 case USART_CLOCKSOURCE_SYSCLK:
<> 144:ef7eb2e8f9f7 2224 usartdiv = (uint16_t)(((2*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
<> 144:ef7eb2e8f9f7 2225 break;
<> 144:ef7eb2e8f9f7 2226 case USART_CLOCKSOURCE_LSE:
<> 144:ef7eb2e8f9f7 2227 usartdiv = (uint16_t)(((2*LSE_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
<> 144:ef7eb2e8f9f7 2228 break;
<> 144:ef7eb2e8f9f7 2229 case USART_CLOCKSOURCE_UNDEFINED:
<> 144:ef7eb2e8f9f7 2230 default:
<> 144:ef7eb2e8f9f7 2231 ret = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2232 break;
<> 144:ef7eb2e8f9f7 2233 }
<> 144:ef7eb2e8f9f7 2234
<> 156:95d6b41a828b 2235 brrtemp = usartdiv & 0xFFF0U;
<> 156:95d6b41a828b 2236 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
<> 144:ef7eb2e8f9f7 2237 husart->Instance->BRR = brrtemp;
<> 144:ef7eb2e8f9f7 2238
<> 144:ef7eb2e8f9f7 2239 return ret;
<> 144:ef7eb2e8f9f7 2240 }
<> 144:ef7eb2e8f9f7 2241
<> 144:ef7eb2e8f9f7 2242 /**
<> 144:ef7eb2e8f9f7 2243 * @brief Check the USART Idle State.
Anna Bridge 180:96ed750bd169 2244 * @param husart USART handle.
<> 144:ef7eb2e8f9f7 2245 * @retval HAL status
<> 144:ef7eb2e8f9f7 2246 */
<> 144:ef7eb2e8f9f7 2247 static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 2248 {
<> 156:95d6b41a828b 2249 #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
<> 156:95d6b41a828b 2250 uint32_t tickstart = 0U;
<> 156:95d6b41a828b 2251 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
<> 156:95d6b41a828b 2252
<> 144:ef7eb2e8f9f7 2253 /* Initialize the USART ErrorCode */
<> 144:ef7eb2e8f9f7 2254 husart->ErrorCode = HAL_USART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 2255
<> 156:95d6b41a828b 2256 #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
<> 156:95d6b41a828b 2257 /* Init tickstart for timeout managment*/
<> 156:95d6b41a828b 2258 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 2259
<> 144:ef7eb2e8f9f7 2260 /* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices).
<> 144:ef7eb2e8f9f7 2261 Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature.
<> 144:ef7eb2e8f9f7 2262 */
<> 144:ef7eb2e8f9f7 2263 if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(husart->Instance))
<> 144:ef7eb2e8f9f7 2264 {
<> 144:ef7eb2e8f9f7 2265 /* Check if the Transmitter is enabled */
<> 144:ef7eb2e8f9f7 2266 if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
<> 144:ef7eb2e8f9f7 2267 {
<> 144:ef7eb2e8f9f7 2268 /* Wait until TEACK flag is set */
<> 156:95d6b41a828b 2269 if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
<> 144:ef7eb2e8f9f7 2270 {
<> 144:ef7eb2e8f9f7 2271 /* Timeout occurred */
<> 144:ef7eb2e8f9f7 2272 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2273 }
<> 144:ef7eb2e8f9f7 2274 }
<> 144:ef7eb2e8f9f7 2275
<> 144:ef7eb2e8f9f7 2276 /* Check if the Receiver is enabled */
<> 144:ef7eb2e8f9f7 2277 if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
<> 144:ef7eb2e8f9f7 2278 {
<> 144:ef7eb2e8f9f7 2279 /* Wait until REACK flag is set */
<> 156:95d6b41a828b 2280 if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
<> 144:ef7eb2e8f9f7 2281 {
<> 144:ef7eb2e8f9f7 2282 /* Timeout occurred */
<> 144:ef7eb2e8f9f7 2283 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2284 }
<> 144:ef7eb2e8f9f7 2285 }
<> 144:ef7eb2e8f9f7 2286 }
<> 144:ef7eb2e8f9f7 2287 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 2288
<> 144:ef7eb2e8f9f7 2289 /* Initialize the USART state*/
<> 144:ef7eb2e8f9f7 2290 husart->State= HAL_USART_STATE_READY;
<> 144:ef7eb2e8f9f7 2291
<> 144:ef7eb2e8f9f7 2292 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2293 __HAL_UNLOCK(husart);
<> 144:ef7eb2e8f9f7 2294
<> 144:ef7eb2e8f9f7 2295 return HAL_OK;
<> 144:ef7eb2e8f9f7 2296 }
<> 144:ef7eb2e8f9f7 2297
<> 144:ef7eb2e8f9f7 2298
<> 144:ef7eb2e8f9f7 2299 /**
<> 144:ef7eb2e8f9f7 2300 * @brief Simplex send an amount of data in non-blocking mode.
<> 144:ef7eb2e8f9f7 2301 * @note Function called under interruption only, once
<> 144:ef7eb2e8f9f7 2302 * interruptions have been enabled by HAL_USART_Transmit_IT().
<> 144:ef7eb2e8f9f7 2303 * @note The USART errors are not managed to avoid the overrun error.
<> 156:95d6b41a828b 2304 * @param husart USART handle.
<> 144:ef7eb2e8f9f7 2305 * @retval HAL status
<> 144:ef7eb2e8f9f7 2306 */
<> 144:ef7eb2e8f9f7 2307 static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 2308 {
<> 156:95d6b41a828b 2309 uint16_t* tmp=0U;
<> 144:ef7eb2e8f9f7 2310
<> 156:95d6b41a828b 2311 /* Check that a Tx process is ongoing */
<> 144:ef7eb2e8f9f7 2312 if(husart->State == HAL_USART_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 2313 {
<> 144:ef7eb2e8f9f7 2314
<> 156:95d6b41a828b 2315 if(husart->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 2316 {
<> 144:ef7eb2e8f9f7 2317 /* Disable the USART Transmit data register empty interrupt */
<> 144:ef7eb2e8f9f7 2318 __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
<> 144:ef7eb2e8f9f7 2319
<> 144:ef7eb2e8f9f7 2320 /* Enable the USART Transmit Complete Interrupt */
<> 144:ef7eb2e8f9f7 2321 __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
<> 144:ef7eb2e8f9f7 2322
<> 144:ef7eb2e8f9f7 2323 return HAL_OK;
<> 144:ef7eb2e8f9f7 2324 }
<> 144:ef7eb2e8f9f7 2325 else
<> 144:ef7eb2e8f9f7 2326 {
<> 144:ef7eb2e8f9f7 2327 if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 2328 {
<> 144:ef7eb2e8f9f7 2329 tmp = (uint16_t*) husart->pTxBuffPtr;
<> 156:95d6b41a828b 2330 husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
<> 156:95d6b41a828b 2331 husart->pTxBuffPtr += 2U;
<> 144:ef7eb2e8f9f7 2332 }
<> 144:ef7eb2e8f9f7 2333 else
<> 144:ef7eb2e8f9f7 2334 {
<> 156:95d6b41a828b 2335 husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFFU);
<> 144:ef7eb2e8f9f7 2336 }
<> 144:ef7eb2e8f9f7 2337
<> 144:ef7eb2e8f9f7 2338 husart->TxXferCount--;
<> 144:ef7eb2e8f9f7 2339
<> 144:ef7eb2e8f9f7 2340 return HAL_OK;
<> 144:ef7eb2e8f9f7 2341 }
<> 144:ef7eb2e8f9f7 2342 }
<> 144:ef7eb2e8f9f7 2343 else
<> 144:ef7eb2e8f9f7 2344 {
<> 144:ef7eb2e8f9f7 2345 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2346 }
<> 144:ef7eb2e8f9f7 2347 }
<> 144:ef7eb2e8f9f7 2348
<> 144:ef7eb2e8f9f7 2349
<> 144:ef7eb2e8f9f7 2350 /**
<> 144:ef7eb2e8f9f7 2351 * @brief Wraps up transmission in non-blocking mode.
<> 156:95d6b41a828b 2352 * @param husart Pointer to a USART_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2353 * the configuration information for the specified USART module.
<> 144:ef7eb2e8f9f7 2354 * @retval HAL status
<> 144:ef7eb2e8f9f7 2355 */
<> 144:ef7eb2e8f9f7 2356 static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 2357 {
<> 144:ef7eb2e8f9f7 2358 /* Disable the USART Transmit Complete Interrupt */
<> 144:ef7eb2e8f9f7 2359 __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
<> 144:ef7eb2e8f9f7 2360
<> 144:ef7eb2e8f9f7 2361 /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<> 144:ef7eb2e8f9f7 2362 __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
<> 144:ef7eb2e8f9f7 2363
<> 156:95d6b41a828b 2364 /* Tx process is ended, restore husart->State to Ready */
<> 144:ef7eb2e8f9f7 2365 husart->State = HAL_USART_STATE_READY;
<> 144:ef7eb2e8f9f7 2366
<> 144:ef7eb2e8f9f7 2367 HAL_USART_TxCpltCallback(husart);
<> 144:ef7eb2e8f9f7 2368
<> 144:ef7eb2e8f9f7 2369 return HAL_OK;
<> 144:ef7eb2e8f9f7 2370 }
<> 144:ef7eb2e8f9f7 2371
<> 144:ef7eb2e8f9f7 2372
<> 144:ef7eb2e8f9f7 2373 /**
<> 144:ef7eb2e8f9f7 2374 * @brief Simplex receive an amount of data in non-blocking mode.
<> 144:ef7eb2e8f9f7 2375 * @note Function called under interruption only, once
<> 144:ef7eb2e8f9f7 2376 * interruptions have been enabled by HAL_USART_Receive_IT().
<> 156:95d6b41a828b 2377 * @param husart USART handle
<> 144:ef7eb2e8f9f7 2378 * @retval HAL status
<> 144:ef7eb2e8f9f7 2379 */
<> 144:ef7eb2e8f9f7 2380 static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 2381 {
<> 156:95d6b41a828b 2382 uint16_t* tmp=0U;
<> 144:ef7eb2e8f9f7 2383 uint16_t uhMask = husart->Mask;
<> 144:ef7eb2e8f9f7 2384
<> 144:ef7eb2e8f9f7 2385 if(husart->State == HAL_USART_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 2386 {
<> 144:ef7eb2e8f9f7 2387
<> 144:ef7eb2e8f9f7 2388 if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 2389 {
<> 144:ef7eb2e8f9f7 2390 tmp = (uint16_t*) husart->pRxBuffPtr;
<> 144:ef7eb2e8f9f7 2391 *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
<> 156:95d6b41a828b 2392 husart->pRxBuffPtr += 2U;
<> 144:ef7eb2e8f9f7 2393 }
<> 144:ef7eb2e8f9f7 2394 else
<> 144:ef7eb2e8f9f7 2395 {
<> 144:ef7eb2e8f9f7 2396 *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
<> 144:ef7eb2e8f9f7 2397 }
<> 144:ef7eb2e8f9f7 2398
<> 144:ef7eb2e8f9f7 2399 /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
<> 156:95d6b41a828b 2400 husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
<> 144:ef7eb2e8f9f7 2401
<> 156:95d6b41a828b 2402 if(--husart->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 2403 {
<> 156:95d6b41a828b 2404 /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
<> 156:95d6b41a828b 2405 CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
<> 144:ef7eb2e8f9f7 2406
<> 144:ef7eb2e8f9f7 2407 /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<> 156:95d6b41a828b 2408 CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 2409
<> 156:95d6b41a828b 2410 /* Rx process is completed, restore husart->State to Ready */
<> 144:ef7eb2e8f9f7 2411 husart->State = HAL_USART_STATE_READY;
<> 144:ef7eb2e8f9f7 2412
<> 144:ef7eb2e8f9f7 2413 HAL_USART_RxCpltCallback(husart);
<> 144:ef7eb2e8f9f7 2414
<> 144:ef7eb2e8f9f7 2415 return HAL_OK;
<> 144:ef7eb2e8f9f7 2416 }
<> 144:ef7eb2e8f9f7 2417
<> 144:ef7eb2e8f9f7 2418 return HAL_OK;
<> 144:ef7eb2e8f9f7 2419 }
<> 144:ef7eb2e8f9f7 2420 else
<> 144:ef7eb2e8f9f7 2421 {
<> 144:ef7eb2e8f9f7 2422 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2423 }
<> 144:ef7eb2e8f9f7 2424 }
<> 144:ef7eb2e8f9f7 2425
<> 144:ef7eb2e8f9f7 2426 /**
<> 144:ef7eb2e8f9f7 2427 * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
<> 144:ef7eb2e8f9f7 2428 * @note Function called under interruption only, once
<> 144:ef7eb2e8f9f7 2429 * interruptions have been enabled by HAL_USART_TransmitReceive_IT().
Anna Bridge 180:96ed750bd169 2430 * @param husart USART handle.
<> 144:ef7eb2e8f9f7 2431 * @retval HAL status
<> 144:ef7eb2e8f9f7 2432 */
<> 144:ef7eb2e8f9f7 2433 static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
<> 144:ef7eb2e8f9f7 2434 {
<> 156:95d6b41a828b 2435 uint16_t* tmp=0U;
<> 144:ef7eb2e8f9f7 2436 uint16_t uhMask = husart->Mask;
<> 144:ef7eb2e8f9f7 2437
<> 144:ef7eb2e8f9f7 2438 if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 2439 {
<> 144:ef7eb2e8f9f7 2440
<> 156:95d6b41a828b 2441 if(husart->TxXferCount != 0x00U)
<> 144:ef7eb2e8f9f7 2442 {
<> 144:ef7eb2e8f9f7 2443 if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
<> 144:ef7eb2e8f9f7 2444 {
<> 144:ef7eb2e8f9f7 2445 if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 2446 {
<> 144:ef7eb2e8f9f7 2447 tmp = (uint16_t*) husart->pTxBuffPtr;
<> 144:ef7eb2e8f9f7 2448 husart->Instance->TDR = (uint16_t)(*tmp & uhMask);
<> 156:95d6b41a828b 2449 husart->pTxBuffPtr += 2U;
<> 144:ef7eb2e8f9f7 2450 }
<> 144:ef7eb2e8f9f7 2451 else
<> 144:ef7eb2e8f9f7 2452 {
<> 144:ef7eb2e8f9f7 2453 husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);
<> 144:ef7eb2e8f9f7 2454 }
<> 144:ef7eb2e8f9f7 2455 husart->TxXferCount--;
<> 144:ef7eb2e8f9f7 2456
<> 144:ef7eb2e8f9f7 2457 /* Check the latest data transmitted */
<> 156:95d6b41a828b 2458 if(husart->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 2459 {
<> 144:ef7eb2e8f9f7 2460 __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
<> 144:ef7eb2e8f9f7 2461 }
<> 144:ef7eb2e8f9f7 2462 }
<> 144:ef7eb2e8f9f7 2463 }
<> 144:ef7eb2e8f9f7 2464
<> 156:95d6b41a828b 2465 if(husart->RxXferCount != 0x00U)
<> 144:ef7eb2e8f9f7 2466 {
<> 144:ef7eb2e8f9f7 2467 if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
<> 144:ef7eb2e8f9f7 2468 {
<> 144:ef7eb2e8f9f7 2469 if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 2470 {
<> 144:ef7eb2e8f9f7 2471 tmp = (uint16_t*) husart->pRxBuffPtr;
<> 144:ef7eb2e8f9f7 2472 *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
<> 156:95d6b41a828b 2473 husart->pRxBuffPtr += 2U;
<> 144:ef7eb2e8f9f7 2474 }
<> 144:ef7eb2e8f9f7 2475 else
<> 144:ef7eb2e8f9f7 2476 {
<> 144:ef7eb2e8f9f7 2477 *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
<> 144:ef7eb2e8f9f7 2478 }
<> 144:ef7eb2e8f9f7 2479 husart->RxXferCount--;
<> 144:ef7eb2e8f9f7 2480 }
<> 144:ef7eb2e8f9f7 2481 }
<> 144:ef7eb2e8f9f7 2482
<> 144:ef7eb2e8f9f7 2483 /* Check the latest data received */
<> 156:95d6b41a828b 2484 if(husart->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 2485 {
<> 156:95d6b41a828b 2486 /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
<> 156:95d6b41a828b 2487 CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
<> 144:ef7eb2e8f9f7 2488
<> 144:ef7eb2e8f9f7 2489 /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
<> 156:95d6b41a828b 2490 CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 2491
<> 156:95d6b41a828b 2492 /* Rx process is completed, restore husart->State to Ready */
<> 144:ef7eb2e8f9f7 2493 husart->State = HAL_USART_STATE_READY;
<> 144:ef7eb2e8f9f7 2494
<> 144:ef7eb2e8f9f7 2495 HAL_USART_TxRxCpltCallback(husart);
<> 144:ef7eb2e8f9f7 2496
<> 144:ef7eb2e8f9f7 2497 return HAL_OK;
<> 144:ef7eb2e8f9f7 2498 }
<> 144:ef7eb2e8f9f7 2499
<> 144:ef7eb2e8f9f7 2500 return HAL_OK;
<> 144:ef7eb2e8f9f7 2501 }
<> 144:ef7eb2e8f9f7 2502 else
<> 144:ef7eb2e8f9f7 2503 {
<> 144:ef7eb2e8f9f7 2504 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2505 }
<> 144:ef7eb2e8f9f7 2506 }
<> 144:ef7eb2e8f9f7 2507
<> 144:ef7eb2e8f9f7 2508 /**
<> 144:ef7eb2e8f9f7 2509 * @}
<> 144:ef7eb2e8f9f7 2510 */
<> 144:ef7eb2e8f9f7 2511
<> 144:ef7eb2e8f9f7 2512 #endif /* HAL_USART_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2513 /**
<> 144:ef7eb2e8f9f7 2514 * @}
<> 144:ef7eb2e8f9f7 2515 */
<> 144:ef7eb2e8f9f7 2516
<> 144:ef7eb2e8f9f7 2517 /**
<> 144:ef7eb2e8f9f7 2518 * @}
<> 144:ef7eb2e8f9f7 2519 */
<> 144:ef7eb2e8f9f7 2520
<> 144:ef7eb2e8f9f7 2521 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/