mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_uart.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of UART HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 156:95d6b41a828b 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F0xx_HAL_UART_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F0xx_HAL_UART_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup UART
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56 /** @defgroup UART_Exported_Types UART Exported Types
<> 144:ef7eb2e8f9f7 57 * @{
<> 144:ef7eb2e8f9f7 58 */
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /**
<> 144:ef7eb2e8f9f7 61 * @brief UART Init Structure definition
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63 typedef struct
<> 144:ef7eb2e8f9f7 64 {
<> 144:ef7eb2e8f9f7 65 uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
<> 144:ef7eb2e8f9f7 66 The baud rate register is computed using the following formula:
<> 144:ef7eb2e8f9f7 67 - If oversampling is 16 or in LIN mode (LIN mode not available on F030xx devices),
<> 144:ef7eb2e8f9f7 68 Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
<> 144:ef7eb2e8f9f7 69 - If oversampling is 8,
<> 144:ef7eb2e8f9f7 70 Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
<> 144:ef7eb2e8f9f7 71 Baud Rate Register[3] = 0
<> 156:95d6b41a828b 72 Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1U */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
<> 156:95d6b41a828b 75 This parameter can be a value of @ref UARTEx_Word_Length. */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
<> 156:95d6b41a828b 78 This parameter can be a value of @ref UART_Stop_Bits. */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 uint32_t Parity; /*!< Specifies the parity mode.
<> 144:ef7eb2e8f9f7 81 This parameter can be a value of @ref UART_Parity
<> 144:ef7eb2e8f9f7 82 @note When parity is enabled, the computed parity is inserted
<> 144:ef7eb2e8f9f7 83 at the MSB position of the transmitted data (9th bit when
<> 144:ef7eb2e8f9f7 84 the word length is set to 9 data bits; 8th bit when the
<> 144:ef7eb2e8f9f7 85 word length is set to 8 data bits). */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
<> 156:95d6b41a828b 88 This parameter can be a value of @ref UART_Mode. */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
<> 144:ef7eb2e8f9f7 91 or disabled.
<> 156:95d6b41a828b 92 This parameter can be a value of @ref UART_Hardware_Flow_Control. */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
<> 156:95d6b41a828b 95 This parameter can be a value of @ref UART_Over_Sampling. */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
<> 144:ef7eb2e8f9f7 98 Selecting the single sample method increases the receiver tolerance to clock
<> 144:ef7eb2e8f9f7 99 deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
<> 144:ef7eb2e8f9f7 100 }UART_InitTypeDef;
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /**
<> 144:ef7eb2e8f9f7 103 * @brief UART Advanced Features initalization structure definition
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105 typedef struct
<> 144:ef7eb2e8f9f7 106 {
<> 144:ef7eb2e8f9f7 107 uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
<> 144:ef7eb2e8f9f7 108 Advanced Features may be initialized at the same time .
<> 156:95d6b41a828b 109 This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
<> 156:95d6b41a828b 112 This parameter can be a value of @ref UART_Tx_Inv. */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
<> 156:95d6b41a828b 115 This parameter can be a value of @ref UART_Rx_Inv. */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
<> 144:ef7eb2e8f9f7 118 vs negative/inverted logic).
<> 156:95d6b41a828b 119 This parameter can be a value of @ref UART_Data_Inv. */
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
<> 156:95d6b41a828b 122 This parameter can be a value of @ref UART_Rx_Tx_Swap. */
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
<> 156:95d6b41a828b 125 This parameter can be a value of @ref UART_Overrun_Disable. */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
<> 156:95d6b41a828b 128 This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
<> 144:ef7eb2e8f9f7 131 This parameter can be a value of @ref UART_AutoBaudRate_Enable */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
<> 144:ef7eb2e8f9f7 134 detection is carried out.
<> 156:95d6b41a828b 135 This parameter can be a value of @ref UARTEx_AutoBaud_Rate_Mode. */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
<> 156:95d6b41a828b 138 This parameter can be a value of @ref UART_MSB_First. */
<> 144:ef7eb2e8f9f7 139 } UART_AdvFeatureInitTypeDef;
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /**
<> 144:ef7eb2e8f9f7 144 * @brief HAL UART State structures definition
<> 144:ef7eb2e8f9f7 145 * @note HAL UART State value is a combination of 2 different substates: gState and RxState.
<> 144:ef7eb2e8f9f7 146 * - gState contains UART state information related to global Handle management
<> 144:ef7eb2e8f9f7 147 * and also information related to Tx operations.
<> 144:ef7eb2e8f9f7 148 * gState value coding follow below described bitmap :
<> 144:ef7eb2e8f9f7 149 * b7-b6 Error information
<> 144:ef7eb2e8f9f7 150 * 00 : No Error
<> 144:ef7eb2e8f9f7 151 * 01 : (Not Used)
<> 144:ef7eb2e8f9f7 152 * 10 : Timeout
<> 144:ef7eb2e8f9f7 153 * 11 : Error
<> 144:ef7eb2e8f9f7 154 * b5 IP initilisation status
<> 144:ef7eb2e8f9f7 155 * 0 : Reset (IP not initialized)
<> 144:ef7eb2e8f9f7 156 * 1 : Init done (IP not initialized. HAL UART Init function already called)
<> 144:ef7eb2e8f9f7 157 * b4-b3 (not used)
<> 144:ef7eb2e8f9f7 158 * xx : Should be set to 00
<> 144:ef7eb2e8f9f7 159 * b2 Intrinsic process state
<> 144:ef7eb2e8f9f7 160 * 0 : Ready
<> 144:ef7eb2e8f9f7 161 * 1 : Busy (IP busy with some configuration or internal operations)
<> 144:ef7eb2e8f9f7 162 * b1 (not used)
<> 144:ef7eb2e8f9f7 163 * x : Should be set to 0
<> 144:ef7eb2e8f9f7 164 * b0 Tx state
<> 144:ef7eb2e8f9f7 165 * 0 : Ready (no Tx operation ongoing)
<> 144:ef7eb2e8f9f7 166 * 1 : Busy (Tx operation ongoing)
<> 144:ef7eb2e8f9f7 167 * - RxState contains information related to Rx operations.
<> 144:ef7eb2e8f9f7 168 * RxState value coding follow below described bitmap :
<> 144:ef7eb2e8f9f7 169 * b7-b6 (not used)
<> 144:ef7eb2e8f9f7 170 * xx : Should be set to 00
<> 144:ef7eb2e8f9f7 171 * b5 IP initilisation status
<> 144:ef7eb2e8f9f7 172 * 0 : Reset (IP not initialized)
<> 144:ef7eb2e8f9f7 173 * 1 : Init done (IP not initialized)
<> 144:ef7eb2e8f9f7 174 * b4-b2 (not used)
<> 144:ef7eb2e8f9f7 175 * xxx : Should be set to 000
<> 144:ef7eb2e8f9f7 176 * b1 Rx state
<> 144:ef7eb2e8f9f7 177 * 0 : Ready (no Rx operation ongoing)
<> 144:ef7eb2e8f9f7 178 * 1 : Busy (Rx operation ongoing)
<> 144:ef7eb2e8f9f7 179 * b0 (not used)
<> 144:ef7eb2e8f9f7 180 * x : Should be set to 0.
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182 typedef enum
<> 144:ef7eb2e8f9f7 183 {
<> 144:ef7eb2e8f9f7 184 HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
<> 144:ef7eb2e8f9f7 185 Value is allowed for gState and RxState */
<> 144:ef7eb2e8f9f7 186 HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
<> 144:ef7eb2e8f9f7 187 Value is allowed for gState and RxState */
<> 144:ef7eb2e8f9f7 188 HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
<> 144:ef7eb2e8f9f7 189 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 190 HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
<> 144:ef7eb2e8f9f7 191 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 192 HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
<> 144:ef7eb2e8f9f7 193 Value is allowed for RxState only */
<> 144:ef7eb2e8f9f7 194 HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
<> 144:ef7eb2e8f9f7 195 Not to be used for neither gState nor RxState.
<> 144:ef7eb2e8f9f7 196 Value is result of combination (Or) between gState and RxState values */
<> 144:ef7eb2e8f9f7 197 HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
<> 144:ef7eb2e8f9f7 198 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 199 HAL_UART_STATE_ERROR = 0xE0U /*!< Error
<> 144:ef7eb2e8f9f7 200 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 201 }HAL_UART_StateTypeDef;
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /**
<> 144:ef7eb2e8f9f7 204 * @brief UART clock sources definition
<> 144:ef7eb2e8f9f7 205 */
<> 144:ef7eb2e8f9f7 206 typedef enum
<> 144:ef7eb2e8f9f7 207 {
<> 156:95d6b41a828b 208 UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
<> 156:95d6b41a828b 209 UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
<> 156:95d6b41a828b 210 UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
<> 156:95d6b41a828b 211 UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
<> 156:95d6b41a828b 212 UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
<> 144:ef7eb2e8f9f7 213 }UART_ClockSourceTypeDef;
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /**
<> 144:ef7eb2e8f9f7 216 * @brief UART handle Structure definition
<> 144:ef7eb2e8f9f7 217 */
<> 144:ef7eb2e8f9f7 218 typedef struct
<> 144:ef7eb2e8f9f7 219 {
<> 144:ef7eb2e8f9f7 220 USART_TypeDef *Instance; /*!< UART registers base address */
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 UART_InitTypeDef Init; /*!< UART communication parameters */
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 uint16_t TxXferSize; /*!< UART Tx Transfer size */
<> 144:ef7eb2e8f9f7 229
<> 156:95d6b41a828b 230 __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 uint16_t RxXferSize; /*!< UART Rx Transfer size */
<> 144:ef7eb2e8f9f7 235
<> 156:95d6b41a828b 236 __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 uint16_t Mask; /*!< UART Rx RDR register mask */
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
<> 144:ef7eb2e8f9f7 243
<> 156:95d6b41a828b 244 HAL_LockTypeDef Lock; /*!< Locking object */
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
<> 144:ef7eb2e8f9f7 247 and also related to Tx operations.
<> 144:ef7eb2e8f9f7 248 This parameter can be a value of @ref HAL_UART_StateTypeDef */
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
<> 144:ef7eb2e8f9f7 251 This parameter can be a value of @ref HAL_UART_StateTypeDef */
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 __IO uint32_t ErrorCode; /*!< UART Error code */
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 }UART_HandleTypeDef;
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /**
<> 144:ef7eb2e8f9f7 258 * @}
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 262 /** @defgroup UART_Exported_Constants UART Exported Constants
<> 144:ef7eb2e8f9f7 263 * @{
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /** @defgroup UART_Error UART Error
<> 144:ef7eb2e8f9f7 267 * @{
<> 144:ef7eb2e8f9f7 268 */
<> 156:95d6b41a828b 269 #define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */
<> 156:95d6b41a828b 270 #define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */
<> 156:95d6b41a828b 271 #define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */
<> 156:95d6b41a828b 272 #define HAL_UART_ERROR_FE (0x00000004U) /*!< frame error */
<> 156:95d6b41a828b 273 #define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */
<> 156:95d6b41a828b 274 #define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
<> 156:95d6b41a828b 275 #define HAL_UART_ERROR_BUSY (0x00000020U) /*!< Busy Error */
<> 144:ef7eb2e8f9f7 276 /**
<> 144:ef7eb2e8f9f7 277 * @}
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /** @defgroup UART_Stop_Bits UART Number of Stop Bits
<> 144:ef7eb2e8f9f7 281 * @{
<> 144:ef7eb2e8f9f7 282 */
<> 144:ef7eb2e8f9f7 283 #ifdef USART_SMARTCARD_SUPPORT
<> 144:ef7eb2e8f9f7 284 #define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */
<> 156:95d6b41a828b 285 #define UART_STOPBITS_1 (0x00000000U) /*!< UART frame with 1 stop bit */
<> 144:ef7eb2e8f9f7 286 #define UART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< UART frame with 1.5 stop bits */
<> 144:ef7eb2e8f9f7 287 #define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< UART frame with 2 stop bits */
<> 144:ef7eb2e8f9f7 288 #else
<> 156:95d6b41a828b 289 #define UART_STOPBITS_1 (0x00000000U) /*!< UART frame with 1 stop bit */
<> 144:ef7eb2e8f9f7 290 #define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< UART frame with 2 stop bits */
<> 144:ef7eb2e8f9f7 291 #endif
<> 144:ef7eb2e8f9f7 292 /**
<> 144:ef7eb2e8f9f7 293 * @}
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /** @defgroup UART_Parity UART Parity
<> 144:ef7eb2e8f9f7 297 * @{
<> 144:ef7eb2e8f9f7 298 */
<> 156:95d6b41a828b 299 #define UART_PARITY_NONE (0x00000000U) /*!< No parity */
<> 144:ef7eb2e8f9f7 300 #define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
<> 144:ef7eb2e8f9f7 301 #define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
<> 144:ef7eb2e8f9f7 302 /**
<> 144:ef7eb2e8f9f7 303 * @}
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
<> 144:ef7eb2e8f9f7 307 * @{
<> 144:ef7eb2e8f9f7 308 */
<> 156:95d6b41a828b 309 #define UART_HWCONTROL_NONE (0x00000000U) /*!< No hardware control */
<> 144:ef7eb2e8f9f7 310 #define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) /*!< Request To Send */
<> 144:ef7eb2e8f9f7 311 #define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) /*!< Clear To Send */
<> 144:ef7eb2e8f9f7 312 #define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) /*!< Request and Clear To Send */
<> 144:ef7eb2e8f9f7 313 /**
<> 144:ef7eb2e8f9f7 314 * @}
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /** @defgroup UART_Mode UART Transfer Mode
<> 144:ef7eb2e8f9f7 318 * @{
<> 144:ef7eb2e8f9f7 319 */
<> 144:ef7eb2e8f9f7 320 #define UART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
<> 144:ef7eb2e8f9f7 321 #define UART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
<> 144:ef7eb2e8f9f7 322 #define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
<> 144:ef7eb2e8f9f7 323 /**
<> 144:ef7eb2e8f9f7 324 * @}
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /** @defgroup UART_State UART State
<> 144:ef7eb2e8f9f7 328 * @{
<> 144:ef7eb2e8f9f7 329 */
<> 156:95d6b41a828b 330 #define UART_STATE_DISABLE (0x00000000U) /*!< UART disabled */
<> 144:ef7eb2e8f9f7 331 #define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< UART enabled */
<> 144:ef7eb2e8f9f7 332 /**
<> 144:ef7eb2e8f9f7 333 * @}
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /** @defgroup UART_Over_Sampling UART Over Sampling
<> 144:ef7eb2e8f9f7 337 * @{
<> 144:ef7eb2e8f9f7 338 */
<> 156:95d6b41a828b 339 #define UART_OVERSAMPLING_16 (0x00000000U) /*!< Oversampling by 16 */
<> 144:ef7eb2e8f9f7 340 #define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /*!< Oversampling by 8 */
<> 144:ef7eb2e8f9f7 341 /**
<> 144:ef7eb2e8f9f7 342 * @}
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
<> 144:ef7eb2e8f9f7 346 * @{
<> 144:ef7eb2e8f9f7 347 */
<> 156:95d6b41a828b 348 #define UART_ONE_BIT_SAMPLE_DISABLE (0x00000000U) /*!< One-bit sampling disable */
<> 144:ef7eb2e8f9f7 349 #define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enable */
<> 144:ef7eb2e8f9f7 350 /**
<> 144:ef7eb2e8f9f7 351 * @}
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
<> 144:ef7eb2e8f9f7 355 * @{
<> 144:ef7eb2e8f9f7 356 */
<> 156:95d6b41a828b 357 #define UART_RECEIVER_TIMEOUT_DISABLE (0x00000000U) /*!< UART receiver timeout disable */
<> 156:95d6b41a828b 358 #define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< UART receiver timeout enable */
<> 144:ef7eb2e8f9f7 359 /**
<> 144:ef7eb2e8f9f7 360 * @}
<> 144:ef7eb2e8f9f7 361 */
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /** @defgroup UART_DMA_Tx UART DMA Tx
<> 144:ef7eb2e8f9f7 364 * @{
<> 144:ef7eb2e8f9f7 365 */
<> 156:95d6b41a828b 366 #define UART_DMA_TX_DISABLE (0x00000000U) /*!< UART DMA TX disabled */
<> 156:95d6b41a828b 367 #define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< UART DMA TX enabled */
<> 144:ef7eb2e8f9f7 368 /**
<> 144:ef7eb2e8f9f7 369 * @}
<> 144:ef7eb2e8f9f7 370 */
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /** @defgroup UART_DMA_Rx UART DMA Rx
<> 144:ef7eb2e8f9f7 373 * @{
<> 144:ef7eb2e8f9f7 374 */
<> 156:95d6b41a828b 375 #define UART_DMA_RX_DISABLE (0x00000000U) /*!< UART DMA RX disabled */
<> 156:95d6b41a828b 376 #define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< UART DMA RX enabled */
<> 144:ef7eb2e8f9f7 377 /**
<> 144:ef7eb2e8f9f7 378 * @}
<> 144:ef7eb2e8f9f7 379 */
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
<> 144:ef7eb2e8f9f7 382 * @{
<> 144:ef7eb2e8f9f7 383 */
<> 156:95d6b41a828b 384 #define UART_HALF_DUPLEX_DISABLE (0x00000000U) /*!< UART half-duplex disabled */
<> 156:95d6b41a828b 385 #define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) /*!< UART half-duplex enabled */
<> 144:ef7eb2e8f9f7 386 /**
<> 144:ef7eb2e8f9f7 387 * @}
<> 144:ef7eb2e8f9f7 388 */
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /** @defgroup UART_WakeUp_Address_Length UART WakeUp Address Length
<> 144:ef7eb2e8f9f7 391 * @{
<> 144:ef7eb2e8f9f7 392 */
<> 156:95d6b41a828b 393 #define UART_ADDRESS_DETECT_4B (0x00000000U) /*!< 4-bit long wake-up address */
<> 156:95d6b41a828b 394 #define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) /*!< 7-bit long wake-up address */
<> 144:ef7eb2e8f9f7 395 /**
<> 144:ef7eb2e8f9f7 396 * @}
<> 144:ef7eb2e8f9f7 397 */
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /** @defgroup UART_WakeUp_Methods UART WakeUp Methods
<> 144:ef7eb2e8f9f7 400 * @{
<> 144:ef7eb2e8f9f7 401 */
<> 156:95d6b41a828b 402 #define UART_WAKEUPMETHOD_IDLELINE (0x00000000U) /*!< UART wake-up on idle line */
<> 156:95d6b41a828b 403 #define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /*!< UART wake-up on address mark */
<> 144:ef7eb2e8f9f7 404 /**
<> 144:ef7eb2e8f9f7 405 * @}
<> 144:ef7eb2e8f9f7 406 */
<> 144:ef7eb2e8f9f7 407
<> 156:95d6b41a828b 408 /** @defgroup UART_IT UART IT
Anna Bridge 180:96ed750bd169 409 * Elements values convention: 0000ZZZZ0XXYYYYYb
<> 144:ef7eb2e8f9f7 410 * - YYYYY : Interrupt source position in the XX register (5bits)
<> 144:ef7eb2e8f9f7 411 * - XX : Interrupt source register (2bits)
<> 144:ef7eb2e8f9f7 412 * - 01: CR1 register
<> 144:ef7eb2e8f9f7 413 * - 10: CR2 register
<> 144:ef7eb2e8f9f7 414 * - 11: CR3 register
Anna Bridge 180:96ed750bd169 415 * - ZZZZ : Flag position in the ISR register(4bits)
<> 144:ef7eb2e8f9f7 416 * @{
<> 144:ef7eb2e8f9f7 417 */
<> 156:95d6b41a828b 418 #define UART_IT_ERR (0x0060U) /*!< UART error interruption */
<> 156:95d6b41a828b 419 #define UART_IT_ORE (0x0300U) /*!< UART overrun error interruption */
<> 156:95d6b41a828b 420 #define UART_IT_NE (0x0200U) /*!< UART noise error interruption */
<> 156:95d6b41a828b 421 #define UART_IT_FE (0x0100U) /*!< UART frame error interruption */
<> 144:ef7eb2e8f9f7 422 /**
<> 144:ef7eb2e8f9f7 423 * @}
<> 144:ef7eb2e8f9f7 424 */
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type
<> 144:ef7eb2e8f9f7 427 * @{
<> 144:ef7eb2e8f9f7 428 */
<> 156:95d6b41a828b 429 #define UART_ADVFEATURE_NO_INIT (0x00000000U) /*!< No advanced feature initialization */
<> 156:95d6b41a828b 430 #define UART_ADVFEATURE_TXINVERT_INIT (0x00000001U) /*!< TX pin active level inversion */
<> 156:95d6b41a828b 431 #define UART_ADVFEATURE_RXINVERT_INIT (0x00000002U) /*!< RX pin active level inversion */
<> 156:95d6b41a828b 432 #define UART_ADVFEATURE_DATAINVERT_INIT (0x00000004U) /*!< Binary data inversion */
<> 156:95d6b41a828b 433 #define UART_ADVFEATURE_SWAP_INIT (0x00000008U) /*!< TX/RX pins swap */
<> 156:95d6b41a828b 434 #define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT (0x00000010U) /*!< RX overrun disable */
<> 156:95d6b41a828b 435 #define UART_ADVFEATURE_DMADISABLEONERROR_INIT (0x00000020U) /*!< DMA disable on Reception Error */
<> 156:95d6b41a828b 436 #define UART_ADVFEATURE_AUTOBAUDRATE_INIT (0x00000040U) /*!< Auto Baud rate detection initialization */
<> 156:95d6b41a828b 437 #define UART_ADVFEATURE_MSBFIRST_INIT (0x00000080U) /*!< Most significant bit sent/received first */
<> 144:ef7eb2e8f9f7 438 /**
<> 144:ef7eb2e8f9f7 439 * @}
<> 144:ef7eb2e8f9f7 440 */
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
<> 144:ef7eb2e8f9f7 443 * @{
<> 144:ef7eb2e8f9f7 444 */
<> 156:95d6b41a828b 445 #define UART_ADVFEATURE_TXINV_DISABLE (0x00000000U) /*!< TX pin active level inversion disable */
<> 156:95d6b41a828b 446 #define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */
<> 144:ef7eb2e8f9f7 447 /**
<> 144:ef7eb2e8f9f7 448 * @}
<> 144:ef7eb2e8f9f7 449 */
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
<> 144:ef7eb2e8f9f7 452 * @{
<> 144:ef7eb2e8f9f7 453 */
<> 156:95d6b41a828b 454 #define UART_ADVFEATURE_RXINV_DISABLE (0x00000000U) /*!< RX pin active level inversion disable */
<> 156:95d6b41a828b 455 #define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */
<> 144:ef7eb2e8f9f7 456 /**
<> 144:ef7eb2e8f9f7 457 * @}
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
<> 144:ef7eb2e8f9f7 461 * @{
<> 144:ef7eb2e8f9f7 462 */
<> 156:95d6b41a828b 463 #define UART_ADVFEATURE_DATAINV_DISABLE (0x00000000U) /*!< Binary data inversion disable */
<> 156:95d6b41a828b 464 #define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */
<> 144:ef7eb2e8f9f7 465 /**
<> 144:ef7eb2e8f9f7 466 * @}
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
<> 144:ef7eb2e8f9f7 470 * @{
<> 144:ef7eb2e8f9f7 471 */
<> 156:95d6b41a828b 472 #define UART_ADVFEATURE_SWAP_DISABLE (0x00000000U) /*!< TX/RX pins swap disable */
<> 156:95d6b41a828b 473 #define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */
<> 144:ef7eb2e8f9f7 474 /**
<> 144:ef7eb2e8f9f7 475 * @}
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
<> 144:ef7eb2e8f9f7 479 * @{
<> 144:ef7eb2e8f9f7 480 */
<> 156:95d6b41a828b 481 #define UART_ADVFEATURE_OVERRUN_ENABLE (0x00000000U) /*!< RX overrun enable */
<> 156:95d6b41a828b 482 #define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */
<> 144:ef7eb2e8f9f7 483 /**
<> 144:ef7eb2e8f9f7 484 * @}
<> 144:ef7eb2e8f9f7 485 */
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable
<> 144:ef7eb2e8f9f7 488 * @{
<> 144:ef7eb2e8f9f7 489 */
<> 156:95d6b41a828b 490 #define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE (0x00000000U) /*!< RX Auto Baud rate detection enable */
<> 156:95d6b41a828b 491 #define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) /*!< RX Auto Baud rate detection disable */
<> 144:ef7eb2e8f9f7 492 /**
<> 144:ef7eb2e8f9f7 493 * @}
<> 144:ef7eb2e8f9f7 494 */
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
<> 144:ef7eb2e8f9f7 497 * @{
<> 144:ef7eb2e8f9f7 498 */
<> 156:95d6b41a828b 499 #define UART_ADVFEATURE_DMA_ENABLEONRXERROR (0x00000000U) /*!< DMA enable on Reception Error */
<> 156:95d6b41a828b 500 #define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */
<> 144:ef7eb2e8f9f7 501 /**
<> 144:ef7eb2e8f9f7 502 * @}
<> 144:ef7eb2e8f9f7 503 */
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /** @defgroup UART_MSB_First UART Advanced Feature MSB First
<> 144:ef7eb2e8f9f7 506 * @{
<> 144:ef7eb2e8f9f7 507 */
<> 156:95d6b41a828b 508 #define UART_ADVFEATURE_MSBFIRST_DISABLE (0x00000000U) /*!< Most significant bit sent/received first disable */
<> 156:95d6b41a828b 509 #define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */
<> 144:ef7eb2e8f9f7 510 /**
<> 144:ef7eb2e8f9f7 511 * @}
<> 144:ef7eb2e8f9f7 512 */
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
<> 144:ef7eb2e8f9f7 515 * @{
<> 144:ef7eb2e8f9f7 516 */
<> 156:95d6b41a828b 517 #define UART_ADVFEATURE_MUTEMODE_DISABLE (0x00000000U) /*!< UART mute mode disable */
<> 156:95d6b41a828b 518 #define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) /*!< UART mute mode enable */
<> 144:ef7eb2e8f9f7 519 /**
<> 144:ef7eb2e8f9f7 520 * @}
<> 144:ef7eb2e8f9f7 521 */
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
<> 144:ef7eb2e8f9f7 524 * @{
<> 144:ef7eb2e8f9f7 525 */
<> 156:95d6b41a828b 526 #define UART_CR2_ADDRESS_LSB_POS ( 24U) /*!< UART address-matching LSB position in CR2 register */
<> 144:ef7eb2e8f9f7 527 /**
<> 144:ef7eb2e8f9f7 528 * @}
<> 144:ef7eb2e8f9f7 529 */
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
<> 144:ef7eb2e8f9f7 532 * @{
<> 144:ef7eb2e8f9f7 533 */
<> 156:95d6b41a828b 534 #define UART_DE_POLARITY_HIGH (0x00000000U) /*!< Driver enable signal is active high */
<> 156:95d6b41a828b 535 #define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) /*!< Driver enable signal is active low */
<> 144:ef7eb2e8f9f7 536 /**
<> 144:ef7eb2e8f9f7 537 * @}
<> 144:ef7eb2e8f9f7 538 */
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
<> 144:ef7eb2e8f9f7 541 * @{
<> 144:ef7eb2e8f9f7 542 */
<> 156:95d6b41a828b 543 #define UART_CR1_DEAT_ADDRESS_LSB_POS ( 21U) /*!< UART Driver Enable assertion time LSB position in CR1 register */
<> 144:ef7eb2e8f9f7 544 /**
<> 144:ef7eb2e8f9f7 545 * @}
<> 144:ef7eb2e8f9f7 546 */
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
<> 144:ef7eb2e8f9f7 549 * @{
<> 144:ef7eb2e8f9f7 550 */
<> 156:95d6b41a828b 551 #define UART_CR1_DEDT_ADDRESS_LSB_POS ( 16U) /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
<> 144:ef7eb2e8f9f7 552 /**
<> 144:ef7eb2e8f9f7 553 * @}
<> 144:ef7eb2e8f9f7 554 */
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
<> 144:ef7eb2e8f9f7 557 * @{
<> 144:ef7eb2e8f9f7 558 */
<> 156:95d6b41a828b 559 #define UART_IT_MASK (0x001FU) /*!< UART interruptions flags mask */
<> 144:ef7eb2e8f9f7 560 /**
<> 144:ef7eb2e8f9f7 561 * @}
<> 144:ef7eb2e8f9f7 562 */
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 /** @defgroup UART_TimeOut_Value UART polling-based communications time-out value
<> 144:ef7eb2e8f9f7 565 * @{
<> 144:ef7eb2e8f9f7 566 */
<> 156:95d6b41a828b 567 #define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */
<> 144:ef7eb2e8f9f7 568 /**
<> 144:ef7eb2e8f9f7 569 * @}
<> 144:ef7eb2e8f9f7 570 */
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 /**
<> 144:ef7eb2e8f9f7 574 * @}
<> 144:ef7eb2e8f9f7 575 */
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 578 /** @defgroup UART_Exported_Macros UART Exported Macros
<> 144:ef7eb2e8f9f7 579 * @{
<> 144:ef7eb2e8f9f7 580 */
<> 144:ef7eb2e8f9f7 581
<> 156:95d6b41a828b 582 /** @brief Reset UART handle states.
Anna Bridge 180:96ed750bd169 583 * @param __HANDLE__ UART handle.
<> 144:ef7eb2e8f9f7 584 * @retval None
<> 144:ef7eb2e8f9f7 585 */
<> 144:ef7eb2e8f9f7 586 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
<> 144:ef7eb2e8f9f7 587 (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
<> 144:ef7eb2e8f9f7 588 (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
<> 144:ef7eb2e8f9f7 589 } while(0)
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /** @brief Clear the specified UART pending flag.
Anna Bridge 180:96ed750bd169 592 * @param __HANDLE__ specifies the UART Handle.
Anna Bridge 180:96ed750bd169 593 * @param __FLAG__ specifies the flag to check.
<> 144:ef7eb2e8f9f7 594 * This parameter can be any combination of the following values:
<> 156:95d6b41a828b 595 * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
<> 156:95d6b41a828b 596 * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
<> 156:95d6b41a828b 597 * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
<> 156:95d6b41a828b 598 * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
<> 156:95d6b41a828b 599 * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
<> 156:95d6b41a828b 600 * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
<> 156:95d6b41a828b 601 @if STM32F030x6
<> 156:95d6b41a828b 602 @elseif STM32F030x8
<> 156:95d6b41a828b 603 @elseif STM32F030xC
<> 156:95d6b41a828b 604 @elseif STM32F070x6
<> 156:95d6b41a828b 605 @elseif STM32F070xB
<> 156:95d6b41a828b 606 @else
<> 156:95d6b41a828b 607 * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag (not available on all devices)
<> 156:95d6b41a828b 608 @endif
<> 156:95d6b41a828b 609 * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
<> 156:95d6b41a828b 610 * @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag
<> 156:95d6b41a828b 611 @if STM32F030x6
<> 156:95d6b41a828b 612 @elseif STM32F030x8
<> 156:95d6b41a828b 613 @elseif STM32F030xC
<> 156:95d6b41a828b 614 @elseif STM32F070x6
<> 156:95d6b41a828b 615 @elseif STM32F070xB
<> 156:95d6b41a828b 616 @else
<> 156:95d6b41a828b 617 * @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag (not available on all devices)
<> 156:95d6b41a828b 618 @endif
<> 156:95d6b41a828b 619 * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
<> 156:95d6b41a828b 620 @if STM32F030x6
<> 156:95d6b41a828b 621 @elseif STM32F030x8
<> 156:95d6b41a828b 622 @elseif STM32F030xC
<> 156:95d6b41a828b 623 @elseif STM32F070x6
<> 156:95d6b41a828b 624 @elseif STM32F070xB
<> 156:95d6b41a828b 625 @else
<> 156:95d6b41a828b 626 * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag (not available on all devices)
<> 156:95d6b41a828b 627 @endif
<> 144:ef7eb2e8f9f7 628 * @retval None
<> 144:ef7eb2e8f9f7 629 */
<> 144:ef7eb2e8f9f7 630 #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /** @brief Clear the UART PE pending flag.
Anna Bridge 180:96ed750bd169 633 * @param __HANDLE__ specifies the UART Handle.
<> 144:ef7eb2e8f9f7 634 * @retval None
<> 144:ef7eb2e8f9f7 635 */
<> 144:ef7eb2e8f9f7 636 #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 /** @brief Clear the UART FE pending flag.
Anna Bridge 180:96ed750bd169 639 * @param __HANDLE__ specifies the UART Handle.
<> 144:ef7eb2e8f9f7 640 * @retval None
<> 144:ef7eb2e8f9f7 641 */
<> 144:ef7eb2e8f9f7 642 #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 /** @brief Clear the UART NE pending flag.
Anna Bridge 180:96ed750bd169 645 * @param __HANDLE__ specifies the UART Handle.
<> 144:ef7eb2e8f9f7 646 * @retval None
<> 144:ef7eb2e8f9f7 647 */
<> 144:ef7eb2e8f9f7 648 #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /** @brief Clear the UART ORE pending flag.
Anna Bridge 180:96ed750bd169 651 * @param __HANDLE__ specifies the UART Handle.
<> 144:ef7eb2e8f9f7 652 * @retval None
<> 144:ef7eb2e8f9f7 653 */
<> 144:ef7eb2e8f9f7 654 #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /** @brief Clear the UART IDLE pending flag.
Anna Bridge 180:96ed750bd169 657 * @param __HANDLE__ specifies the UART Handle.
<> 144:ef7eb2e8f9f7 658 * @retval None
<> 144:ef7eb2e8f9f7 659 */
<> 144:ef7eb2e8f9f7 660 #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /** @brief Check whether the specified UART flag is set or not.
Anna Bridge 180:96ed750bd169 663 * @param __HANDLE__ specifies the UART Handle.
Anna Bridge 180:96ed750bd169 664 * @param __FLAG__ specifies the flag to check.
<> 144:ef7eb2e8f9f7 665 * This parameter can be one of the following values:
<> 156:95d6b41a828b 666 @if STM32F030x6
<> 156:95d6b41a828b 667 @elseif STM32F030x8
<> 156:95d6b41a828b 668 @elseif STM32F030xC
<> 156:95d6b41a828b 669 @elseif STM32F070x6
<> 156:95d6b41a828b 670 @elseif STM32F070xB
<> 156:95d6b41a828b 671 @else
<> 156:95d6b41a828b 672 * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
<> 156:95d6b41a828b 673 @endif
<> 156:95d6b41a828b 674 * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
<> 156:95d6b41a828b 675 @if STM32F030x6
<> 156:95d6b41a828b 676 @elseif STM32F030x8
<> 156:95d6b41a828b 677 @elseif STM32F030xC
<> 156:95d6b41a828b 678 @elseif STM32F070x6
<> 156:95d6b41a828b 679 @elseif STM32F070xB
<> 156:95d6b41a828b 680 @else
<> 156:95d6b41a828b 681 * @arg @ref UART_FLAG_WUF Wake up from stop mode flag (not available on F030xx devices)
<> 156:95d6b41a828b 682 @endif
<> 156:95d6b41a828b 683 * @arg @ref UART_FLAG_RWU Receiver wake up flag (not available on F030xx devices)
<> 156:95d6b41a828b 684 * @arg @ref UART_FLAG_SBKF Send Break flag
<> 156:95d6b41a828b 685 * @arg @ref UART_FLAG_CMF Character match flag
<> 156:95d6b41a828b 686 * @arg @ref UART_FLAG_BUSY Busy flag
<> 156:95d6b41a828b 687 * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag
<> 156:95d6b41a828b 688 * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag
<> 156:95d6b41a828b 689 @if STM32F030x6
<> 156:95d6b41a828b 690 @elseif STM32F030x8
<> 156:95d6b41a828b 691 @elseif STM32F030xC
<> 156:95d6b41a828b 692 @elseif STM32F070x6
<> 156:95d6b41a828b 693 @elseif STM32F070xB
<> 156:95d6b41a828b 694 @else
<> 156:95d6b41a828b 695 * @arg @ref UART_FLAG_EOBF End of block flag (not available on F030xx devices)
<> 156:95d6b41a828b 696 @endif
<> 156:95d6b41a828b 697 * @arg @ref UART_FLAG_RTOF Receiver timeout flag
<> 156:95d6b41a828b 698 * @arg @ref UART_FLAG_CTS CTS Change flag
<> 156:95d6b41a828b 699 @if STM32F030x6
<> 156:95d6b41a828b 700 @elseif STM32F030x8
<> 156:95d6b41a828b 701 @elseif STM32F030xC
<> 156:95d6b41a828b 702 @elseif STM32F070x6
<> 156:95d6b41a828b 703 @elseif STM32F070xB
<> 156:95d6b41a828b 704 @else
<> 156:95d6b41a828b 705 * @arg @ref UART_FLAG_LBDF LIN Break detection flag (not available on F030xx devices)
<> 156:95d6b41a828b 706 @endif
<> 156:95d6b41a828b 707 * @arg @ref UART_FLAG_TXE Transmit data register empty flag
<> 156:95d6b41a828b 708 * @arg @ref UART_FLAG_TC Transmission Complete flag
<> 156:95d6b41a828b 709 * @arg @ref UART_FLAG_RXNE Receive data register not empty flag
<> 156:95d6b41a828b 710 * @arg @ref UART_FLAG_IDLE Idle Line detection flag
<> 156:95d6b41a828b 711 * @arg @ref UART_FLAG_ORE Overrun Error flag
<> 156:95d6b41a828b 712 * @arg @ref UART_FLAG_NE Noise Error flag
<> 156:95d6b41a828b 713 * @arg @ref UART_FLAG_FE Framing Error flag
<> 156:95d6b41a828b 714 * @arg @ref UART_FLAG_PE Parity Error flag
<> 144:ef7eb2e8f9f7 715 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 716 */
<> 144:ef7eb2e8f9f7 717 #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 /** @brief Enable the specified UART interrupt.
Anna Bridge 180:96ed750bd169 720 * @param __HANDLE__ specifies the UART Handle.
Anna Bridge 180:96ed750bd169 721 * @param __INTERRUPT__ specifies the UART interrupt source to enable.
<> 144:ef7eb2e8f9f7 722 * This parameter can be one of the following values:
<> 156:95d6b41a828b 723 @if STM32F030x6
<> 156:95d6b41a828b 724 @elseif STM32F030x8
<> 156:95d6b41a828b 725 @elseif STM32F030xC
<> 156:95d6b41a828b 726 @elseif STM32F070x6
<> 156:95d6b41a828b 727 @elseif STM32F070xB
<> 156:95d6b41a828b 728 @else
<> 156:95d6b41a828b 729 * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt (not available on F030xx devices)
<> 156:95d6b41a828b 730 @endif
<> 156:95d6b41a828b 731 * @arg @ref UART_IT_CM Character match interrupt
<> 156:95d6b41a828b 732 * @arg @ref UART_IT_CTS CTS change interrupt
<> 156:95d6b41a828b 733 @if STM32F030x6
<> 156:95d6b41a828b 734 @elseif STM32F030x8
<> 156:95d6b41a828b 735 @elseif STM32F030xC
<> 156:95d6b41a828b 736 @elseif STM32F070x6
<> 156:95d6b41a828b 737 @elseif STM32F070xB
<> 156:95d6b41a828b 738 @else
<> 156:95d6b41a828b 739 * @arg @ref UART_IT_LBD LIN Break detection interrupt (not available on F030xx devices)
<> 156:95d6b41a828b 740 @endif
<> 156:95d6b41a828b 741 * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
<> 156:95d6b41a828b 742 * @arg @ref UART_IT_TC Transmission complete interrupt
<> 156:95d6b41a828b 743 * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
<> 156:95d6b41a828b 744 * @arg @ref UART_IT_IDLE Idle line detection interrupt
<> 156:95d6b41a828b 745 * @arg @ref UART_IT_PE Parity Error interrupt
<> 156:95d6b41a828b 746 * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
<> 144:ef7eb2e8f9f7 747 * @retval None
<> 144:ef7eb2e8f9f7 748 */
<> 156:95d6b41a828b 749 #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
<> 156:95d6b41a828b 750 ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
<> 144:ef7eb2e8f9f7 751 ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /** @brief Disable the specified UART interrupt.
Anna Bridge 180:96ed750bd169 755 * @param __HANDLE__ specifies the UART Handle.
Anna Bridge 180:96ed750bd169 756 * @param __INTERRUPT__ specifies the UART interrupt source to disable.
<> 144:ef7eb2e8f9f7 757 * This parameter can be one of the following values:
<> 156:95d6b41a828b 758 @if STM32F030x6
<> 156:95d6b41a828b 759 @elseif STM32F030x8
<> 156:95d6b41a828b 760 @elseif STM32F030xC
<> 156:95d6b41a828b 761 @elseif STM32F070x6
<> 156:95d6b41a828b 762 @elseif STM32F070xB
<> 156:95d6b41a828b 763 @else
<> 156:95d6b41a828b 764 * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt (not available on F030xx devices)
<> 156:95d6b41a828b 765 @endif
<> 156:95d6b41a828b 766 * @arg @ref UART_IT_CM Character match interrupt
<> 156:95d6b41a828b 767 * @arg @ref UART_IT_CTS CTS change interrupt
<> 156:95d6b41a828b 768 @if STM32F030x6
<> 156:95d6b41a828b 769 @elseif STM32F030x8
<> 156:95d6b41a828b 770 @elseif STM32F030xC
<> 156:95d6b41a828b 771 @elseif STM32F070x6
<> 156:95d6b41a828b 772 @elseif STM32F070xB
<> 156:95d6b41a828b 773 @else
<> 156:95d6b41a828b 774 * @arg @ref UART_IT_LBD LIN Break detection interrupt (not available on F030xx devices)
<> 156:95d6b41a828b 775 @endif
<> 156:95d6b41a828b 776 * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
<> 156:95d6b41a828b 777 * @arg @ref UART_IT_TC Transmission complete interrupt
<> 156:95d6b41a828b 778 * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
<> 156:95d6b41a828b 779 * @arg @ref UART_IT_IDLE Idle line detection interrupt
<> 156:95d6b41a828b 780 * @arg @ref UART_IT_PE Parity Error interrupt
<> 156:95d6b41a828b 781 * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
<> 144:ef7eb2e8f9f7 782 * @retval None
<> 144:ef7eb2e8f9f7 783 */
<> 156:95d6b41a828b 784 #define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
<> 156:95d6b41a828b 785 ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
<> 144:ef7eb2e8f9f7 786 ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 /** @brief Check whether the specified UART interrupt has occurred or not.
Anna Bridge 180:96ed750bd169 789 * @param __HANDLE__ specifies the UART Handle.
Anna Bridge 180:96ed750bd169 790 * @param __IT__ specifies the UART interrupt to check.
<> 144:ef7eb2e8f9f7 791 * This parameter can be one of the following values:
<> 156:95d6b41a828b 792 @if STM32F030x6
<> 156:95d6b41a828b 793 @elseif STM32F030x8
<> 156:95d6b41a828b 794 @elseif STM32F030xC
<> 156:95d6b41a828b 795 @elseif STM32F070x6
<> 156:95d6b41a828b 796 @elseif STM32F070xB
<> 156:95d6b41a828b 797 @else
<> 156:95d6b41a828b 798 * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt (not available on F030xx devices)
<> 156:95d6b41a828b 799 @endif
<> 156:95d6b41a828b 800 * @arg @ref UART_IT_CM Character match interrupt
<> 156:95d6b41a828b 801 * @arg @ref UART_IT_CTS CTS change interrupt
<> 156:95d6b41a828b 802 @if STM32F030x6
<> 156:95d6b41a828b 803 @elseif STM32F030x8
<> 156:95d6b41a828b 804 @elseif STM32F030xC
<> 156:95d6b41a828b 805 @elseif STM32F070x6
<> 156:95d6b41a828b 806 @elseif STM32F070xB
<> 156:95d6b41a828b 807 @else
<> 156:95d6b41a828b 808 * @arg @ref UART_IT_LBD LIN Break detection interrupt (not available on F030xx devices)
<> 156:95d6b41a828b 809 @endif
<> 156:95d6b41a828b 810 * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
<> 156:95d6b41a828b 811 * @arg @ref UART_IT_TC Transmission complete interrupt
<> 156:95d6b41a828b 812 * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
<> 156:95d6b41a828b 813 * @arg @ref UART_IT_IDLE Idle line detection interrupt
<> 156:95d6b41a828b 814 * @arg @ref UART_IT_ORE Overrun Error interrupt
<> 156:95d6b41a828b 815 * @arg @ref UART_IT_NE Noise Error interrupt
<> 156:95d6b41a828b 816 * @arg @ref UART_IT_FE Framing Error interrupt
<> 156:95d6b41a828b 817 * @arg @ref UART_IT_PE Parity Error interrupt
<> 144:ef7eb2e8f9f7 818 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 819 */
<> 156:95d6b41a828b 820 #define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /** @brief Check whether the specified UART interrupt source is enabled or not.
Anna Bridge 180:96ed750bd169 823 * @param __HANDLE__ specifies the UART Handle.
Anna Bridge 180:96ed750bd169 824 * @param __IT__ specifies the UART interrupt source to check.
<> 144:ef7eb2e8f9f7 825 * This parameter can be one of the following values:
<> 156:95d6b41a828b 826 @if STM32F030x6
<> 156:95d6b41a828b 827 @elseif STM32F030x8
<> 156:95d6b41a828b 828 @elseif STM32F030xC
<> 156:95d6b41a828b 829 @elseif STM32F070x6
<> 156:95d6b41a828b 830 @elseif STM32F070xB
<> 156:95d6b41a828b 831 @else
<> 156:95d6b41a828b 832 * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt (not available on F030xx devices)
<> 156:95d6b41a828b 833 @endif
<> 156:95d6b41a828b 834 * @arg @ref UART_IT_CM Character match interrupt
<> 156:95d6b41a828b 835 * @arg @ref UART_IT_CTS CTS change interrupt
<> 156:95d6b41a828b 836 @if STM32F030x6
<> 156:95d6b41a828b 837 @elseif STM32F030x8
<> 156:95d6b41a828b 838 @elseif STM32F030xC
<> 156:95d6b41a828b 839 @elseif STM32F070x6
<> 156:95d6b41a828b 840 @elseif STM32F070xB
<> 156:95d6b41a828b 841 @else
<> 156:95d6b41a828b 842 * @arg @ref UART_IT_LBD LIN Break detection interrupt (not available on F030xx devices)
<> 156:95d6b41a828b 843 @endif
<> 156:95d6b41a828b 844 * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
<> 156:95d6b41a828b 845 * @arg @ref UART_IT_TC Transmission complete interrupt
<> 156:95d6b41a828b 846 * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
<> 156:95d6b41a828b 847 * @arg @ref UART_IT_IDLE Idle line detection interrupt
<> 156:95d6b41a828b 848 * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
<> 156:95d6b41a828b 849 * @arg @ref UART_IT_PE Parity Error interrupt
<> 144:ef7eb2e8f9f7 850 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 851 */
<> 156:95d6b41a828b 852 #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
<> 156:95d6b41a828b 853 (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & UART_IT_MASK)))
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
Anna Bridge 180:96ed750bd169 856 * @param __HANDLE__ specifies the UART Handle.
Anna Bridge 180:96ed750bd169 857 * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
<> 144:ef7eb2e8f9f7 858 * to clear the corresponding interrupt
<> 144:ef7eb2e8f9f7 859 * This parameter can be one of the following values:
<> 156:95d6b41a828b 860 * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
<> 156:95d6b41a828b 861 * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
<> 156:95d6b41a828b 862 * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
<> 156:95d6b41a828b 863 * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
<> 156:95d6b41a828b 864 * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
<> 156:95d6b41a828b 865 * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
<> 156:95d6b41a828b 866 @if STM32F030x6
<> 156:95d6b41a828b 867 @elseif STM32F030x8
<> 156:95d6b41a828b 868 @elseif STM32F030xC
<> 156:95d6b41a828b 869 @elseif STM32F070x6
<> 156:95d6b41a828b 870 @elseif STM32F070xB
<> 156:95d6b41a828b 871 @else
<> 156:95d6b41a828b 872 * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag (not available on F030xx devices)
<> 156:95d6b41a828b 873 @endif
<> 156:95d6b41a828b 874 * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
<> 156:95d6b41a828b 875 * @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag
<> 156:95d6b41a828b 876 @if STM32F030x6
<> 156:95d6b41a828b 877 @elseif STM32F030x8
<> 156:95d6b41a828b 878 @elseif STM32F030xC
<> 156:95d6b41a828b 879 @elseif STM32F070x6
<> 156:95d6b41a828b 880 @elseif STM32F070xB
<> 156:95d6b41a828b 881 @else
<> 156:95d6b41a828b 882 * @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag
<> 156:95d6b41a828b 883 @endif
<> 156:95d6b41a828b 884 * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
<> 156:95d6b41a828b 885 @if STM32F030x6
<> 156:95d6b41a828b 886 @elseif STM32F030x8
<> 156:95d6b41a828b 887 @elseif STM32F030xC
<> 156:95d6b41a828b 888 @elseif STM32F070x6
<> 156:95d6b41a828b 889 @elseif STM32F070xB
<> 156:95d6b41a828b 890 @else
<> 156:95d6b41a828b 891 * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag (not available on F030xx devices)
<> 156:95d6b41a828b 892 @endif
<> 144:ef7eb2e8f9f7 893 * @retval None
<> 144:ef7eb2e8f9f7 894 */
<> 144:ef7eb2e8f9f7 895 #define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /** @brief Set a specific UART request flag.
Anna Bridge 180:96ed750bd169 898 * @param __HANDLE__ specifies the UART Handle.
Anna Bridge 180:96ed750bd169 899 * @param __REQ__ specifies the request flag to set
<> 144:ef7eb2e8f9f7 900 * This parameter can be one of the following values:
<> 156:95d6b41a828b 901 * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
<> 156:95d6b41a828b 902 * @arg @ref UART_SENDBREAK_REQUEST Send Break Request
<> 156:95d6b41a828b 903 * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
<> 156:95d6b41a828b 904 * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
<> 156:95d6b41a828b 905 @if STM32F030x6
<> 156:95d6b41a828b 906 @elseif STM32F030x8
<> 156:95d6b41a828b 907 @elseif STM32F030xC
<> 156:95d6b41a828b 908 @elseif STM32F070x6
<> 156:95d6b41a828b 909 @elseif STM32F070xB
<> 156:95d6b41a828b 910 @else
<> 156:95d6b41a828b 911 * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request (not available on F030xx devices)
<> 156:95d6b41a828b 912 @endif
<> 144:ef7eb2e8f9f7 913 * @retval None
<> 144:ef7eb2e8f9f7 914 */
<> 156:95d6b41a828b 915 #define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 /** @brief Enable the UART one bit sample method.
Anna Bridge 180:96ed750bd169 918 * @param __HANDLE__ specifies the UART Handle.
<> 144:ef7eb2e8f9f7 919 * @retval None
<> 144:ef7eb2e8f9f7 920 */
<> 144:ef7eb2e8f9f7 921 #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
<> 144:ef7eb2e8f9f7 922
<> 144:ef7eb2e8f9f7 923 /** @brief Disable the UART one bit sample method.
Anna Bridge 180:96ed750bd169 924 * @param __HANDLE__ specifies the UART Handle.
<> 144:ef7eb2e8f9f7 925 * @retval None
<> 144:ef7eb2e8f9f7 926 */
<> 144:ef7eb2e8f9f7 927 #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /** @brief Enable UART.
Anna Bridge 180:96ed750bd169 930 * @param __HANDLE__ specifies the UART Handle.
<> 144:ef7eb2e8f9f7 931 * @retval None
<> 144:ef7eb2e8f9f7 932 */
<> 144:ef7eb2e8f9f7 933 #define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /** @brief Disable UART.
Anna Bridge 180:96ed750bd169 936 * @param __HANDLE__ specifies the UART Handle.
<> 144:ef7eb2e8f9f7 937 * @retval None
<> 144:ef7eb2e8f9f7 938 */
<> 144:ef7eb2e8f9f7 939 #define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 /** @brief Enable CTS flow control.
<> 144:ef7eb2e8f9f7 942 * @note This macro allows to enable CTS hardware flow control for a given UART instance,
<> 144:ef7eb2e8f9f7 943 * without need to call HAL_UART_Init() function.
<> 144:ef7eb2e8f9f7 944 * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<> 144:ef7eb2e8f9f7 945 * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
<> 144:ef7eb2e8f9f7 946 * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<> 144:ef7eb2e8f9f7 947 * - UART instance should have already been initialised (through call of HAL_UART_Init() )
<> 144:ef7eb2e8f9f7 948 * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
<> 144:ef7eb2e8f9f7 949 * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Anna Bridge 180:96ed750bd169 950 * @param __HANDLE__ specifies the UART Handle.
<> 144:ef7eb2e8f9f7 951 * @retval None
<> 144:ef7eb2e8f9f7 952 */
<> 144:ef7eb2e8f9f7 953 #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 954 do{ \
<> 144:ef7eb2e8f9f7 955 SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
<> 144:ef7eb2e8f9f7 956 (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
<> 144:ef7eb2e8f9f7 957 } while(0)
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /** @brief Disable CTS flow control.
<> 144:ef7eb2e8f9f7 960 * @note This macro allows to disable CTS hardware flow control for a given UART instance,
<> 144:ef7eb2e8f9f7 961 * without need to call HAL_UART_Init() function.
<> 144:ef7eb2e8f9f7 962 * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<> 144:ef7eb2e8f9f7 963 * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
<> 144:ef7eb2e8f9f7 964 * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<> 144:ef7eb2e8f9f7 965 * - UART instance should have already been initialised (through call of HAL_UART_Init() )
<> 144:ef7eb2e8f9f7 966 * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
<> 144:ef7eb2e8f9f7 967 * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Anna Bridge 180:96ed750bd169 968 * @param __HANDLE__ specifies the UART Handle.
<> 144:ef7eb2e8f9f7 969 * @retval None
<> 144:ef7eb2e8f9f7 970 */
<> 144:ef7eb2e8f9f7 971 #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 972 do{ \
<> 144:ef7eb2e8f9f7 973 CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
<> 144:ef7eb2e8f9f7 974 (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
<> 144:ef7eb2e8f9f7 975 } while(0)
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 /** @brief Enable RTS flow control.
<> 144:ef7eb2e8f9f7 978 * @note This macro allows to enable RTS hardware flow control for a given UART instance,
<> 144:ef7eb2e8f9f7 979 * without need to call HAL_UART_Init() function.
<> 144:ef7eb2e8f9f7 980 * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<> 144:ef7eb2e8f9f7 981 * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
<> 144:ef7eb2e8f9f7 982 * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<> 144:ef7eb2e8f9f7 983 * - UART instance should have already been initialised (through call of HAL_UART_Init() )
<> 144:ef7eb2e8f9f7 984 * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
<> 144:ef7eb2e8f9f7 985 * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Anna Bridge 180:96ed750bd169 986 * @param __HANDLE__ specifies the UART Handle.
<> 144:ef7eb2e8f9f7 987 * @retval None
<> 144:ef7eb2e8f9f7 988 */
<> 144:ef7eb2e8f9f7 989 #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 990 do{ \
<> 144:ef7eb2e8f9f7 991 SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
<> 144:ef7eb2e8f9f7 992 (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
<> 144:ef7eb2e8f9f7 993 } while(0)
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 /** @brief Disable RTS flow control.
<> 144:ef7eb2e8f9f7 996 * @note This macro allows to disable RTS hardware flow control for a given UART instance,
<> 144:ef7eb2e8f9f7 997 * without need to call HAL_UART_Init() function.
<> 144:ef7eb2e8f9f7 998 * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<> 144:ef7eb2e8f9f7 999 * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
<> 144:ef7eb2e8f9f7 1000 * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<> 144:ef7eb2e8f9f7 1001 * - UART instance should have already been initialised (through call of HAL_UART_Init() )
<> 144:ef7eb2e8f9f7 1002 * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
<> 144:ef7eb2e8f9f7 1003 * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
Anna Bridge 180:96ed750bd169 1004 * @param __HANDLE__ specifies the UART Handle.
<> 144:ef7eb2e8f9f7 1005 * @retval None
<> 144:ef7eb2e8f9f7 1006 */
<> 144:ef7eb2e8f9f7 1007 #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 1008 do{ \
<> 144:ef7eb2e8f9f7 1009 CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
<> 144:ef7eb2e8f9f7 1010 (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
<> 144:ef7eb2e8f9f7 1011 } while(0)
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /**
<> 144:ef7eb2e8f9f7 1014 * @}
<> 144:ef7eb2e8f9f7 1015 */
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 /* Private macros --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1018 /** @defgroup UART_Private_Macros UART Private Macros
<> 144:ef7eb2e8f9f7 1019 * @{
<> 144:ef7eb2e8f9f7 1020 */
<> 144:ef7eb2e8f9f7 1021
<> 144:ef7eb2e8f9f7 1022 /** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
Anna Bridge 180:96ed750bd169 1023 * @param __PCLK__ UART clock.
Anna Bridge 180:96ed750bd169 1024 * @param __BAUD__ Baud rate set by the user.
<> 144:ef7eb2e8f9f7 1025 * @retval Division result
<> 144:ef7eb2e8f9f7 1026 */
<> 156:95d6b41a828b 1027 #define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 /** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
Anna Bridge 180:96ed750bd169 1030 * @param __PCLK__ UART clock.
Anna Bridge 180:96ed750bd169 1031 * @param __BAUD__ Baud rate set by the user.
<> 144:ef7eb2e8f9f7 1032 * @retval Division result
<> 144:ef7eb2e8f9f7 1033 */
<> 156:95d6b41a828b 1034 #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))
<> 144:ef7eb2e8f9f7 1035
<> 156:95d6b41a828b 1036 /** @brief Check UART Baud rate.
Anna Bridge 180:96ed750bd169 1037 * @param __BAUDRATE__ Baudrate specified by the user.
<> 144:ef7eb2e8f9f7 1038 * The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz)
<> 156:95d6b41a828b 1039 * divided by the smallest oversampling used on the USART (i.e. 8)
<> 144:ef7eb2e8f9f7 1040 * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
<> 144:ef7eb2e8f9f7 1041 */
<> 156:95d6b41a828b 1042 #define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6000001U)
<> 144:ef7eb2e8f9f7 1043
<> 144:ef7eb2e8f9f7 1044 /** @brief Check UART assertion time.
Anna Bridge 180:96ed750bd169 1045 * @param __TIME__ 5-bit value assertion time.
<> 144:ef7eb2e8f9f7 1046 * @retval Test result (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 1047 */
<> 144:ef7eb2e8f9f7 1048 #define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
<> 144:ef7eb2e8f9f7 1049
<> 144:ef7eb2e8f9f7 1050 /** @brief Check UART deassertion time.
Anna Bridge 180:96ed750bd169 1051 * @param __TIME__ 5-bit value deassertion time.
<> 144:ef7eb2e8f9f7 1052 * @retval Test result (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 1053 */
<> 144:ef7eb2e8f9f7 1054 #define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
<> 144:ef7eb2e8f9f7 1055
<> 144:ef7eb2e8f9f7 1056 /**
<> 144:ef7eb2e8f9f7 1057 * @brief Ensure that UART frame number of stop bits is valid.
Anna Bridge 180:96ed750bd169 1058 * @param __STOPBITS__ UART frame number of stop bits.
<> 144:ef7eb2e8f9f7 1059 * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
<> 144:ef7eb2e8f9f7 1060 */
<> 144:ef7eb2e8f9f7 1061 #ifdef USART_SMARTCARD_SUPPORT
<> 144:ef7eb2e8f9f7 1062 #define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
<> 144:ef7eb2e8f9f7 1063 ((__STOPBITS__) == UART_STOPBITS_1) || \
<> 144:ef7eb2e8f9f7 1064 ((__STOPBITS__) == UART_STOPBITS_1_5) || \
<> 144:ef7eb2e8f9f7 1065 ((__STOPBITS__) == UART_STOPBITS_2))
<> 144:ef7eb2e8f9f7 1066 #else
<> 144:ef7eb2e8f9f7 1067 #define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
<> 144:ef7eb2e8f9f7 1068 ((__STOPBITS__) == UART_STOPBITS_2))
<> 144:ef7eb2e8f9f7 1069 #endif
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071 /**
<> 144:ef7eb2e8f9f7 1072 * @brief Ensure that UART frame parity is valid.
Anna Bridge 180:96ed750bd169 1073 * @param __PARITY__ UART frame parity.
<> 144:ef7eb2e8f9f7 1074 * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
<> 144:ef7eb2e8f9f7 1075 */
<> 144:ef7eb2e8f9f7 1076 #define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
<> 144:ef7eb2e8f9f7 1077 ((__PARITY__) == UART_PARITY_EVEN) || \
<> 144:ef7eb2e8f9f7 1078 ((__PARITY__) == UART_PARITY_ODD))
<> 144:ef7eb2e8f9f7 1079
<> 144:ef7eb2e8f9f7 1080 /**
<> 144:ef7eb2e8f9f7 1081 * @brief Ensure that UART hardware flow control is valid.
Anna Bridge 180:96ed750bd169 1082 * @param __CONTROL__ UART hardware flow control.
<> 144:ef7eb2e8f9f7 1083 * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
<> 144:ef7eb2e8f9f7 1084 */
<> 144:ef7eb2e8f9f7 1085 #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
<> 144:ef7eb2e8f9f7 1086 (((__CONTROL__) == UART_HWCONTROL_NONE) || \
<> 144:ef7eb2e8f9f7 1087 ((__CONTROL__) == UART_HWCONTROL_RTS) || \
<> 144:ef7eb2e8f9f7 1088 ((__CONTROL__) == UART_HWCONTROL_CTS) || \
<> 144:ef7eb2e8f9f7 1089 ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
<> 144:ef7eb2e8f9f7 1090
<> 144:ef7eb2e8f9f7 1091 /**
<> 144:ef7eb2e8f9f7 1092 * @brief Ensure that UART communication mode is valid.
Anna Bridge 180:96ed750bd169 1093 * @param __MODE__ UART communication mode.
<> 144:ef7eb2e8f9f7 1094 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
<> 144:ef7eb2e8f9f7 1095 */
<> 156:95d6b41a828b 1096 #define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
<> 144:ef7eb2e8f9f7 1097
<> 144:ef7eb2e8f9f7 1098 /**
<> 144:ef7eb2e8f9f7 1099 * @brief Ensure that UART state is valid.
Anna Bridge 180:96ed750bd169 1100 * @param __STATE__ UART state.
<> 144:ef7eb2e8f9f7 1101 * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
<> 144:ef7eb2e8f9f7 1102 */
<> 144:ef7eb2e8f9f7 1103 #define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
<> 144:ef7eb2e8f9f7 1104 ((__STATE__) == UART_STATE_ENABLE))
<> 144:ef7eb2e8f9f7 1105
<> 144:ef7eb2e8f9f7 1106 /**
<> 144:ef7eb2e8f9f7 1107 * @brief Ensure that UART oversampling is valid.
Anna Bridge 180:96ed750bd169 1108 * @param __SAMPLING__ UART oversampling.
<> 144:ef7eb2e8f9f7 1109 * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
<> 144:ef7eb2e8f9f7 1110 */
<> 144:ef7eb2e8f9f7 1111 #define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
<> 144:ef7eb2e8f9f7 1112 ((__SAMPLING__) == UART_OVERSAMPLING_8))
<> 144:ef7eb2e8f9f7 1113
<> 144:ef7eb2e8f9f7 1114 /**
<> 144:ef7eb2e8f9f7 1115 * @brief Ensure that UART frame sampling is valid.
Anna Bridge 180:96ed750bd169 1116 * @param __ONEBIT__ UART frame sampling.
<> 144:ef7eb2e8f9f7 1117 * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
<> 144:ef7eb2e8f9f7 1118 */
<> 144:ef7eb2e8f9f7 1119 #define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
<> 144:ef7eb2e8f9f7 1120 ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
<> 144:ef7eb2e8f9f7 1121
<> 144:ef7eb2e8f9f7 1122 /**
<> 144:ef7eb2e8f9f7 1123 * @brief Ensure that Address Length detection parameter is valid.
Anna Bridge 180:96ed750bd169 1124 * @param __ADDRESS__ UART Adress length value.
<> 144:ef7eb2e8f9f7 1125 * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
<> 144:ef7eb2e8f9f7 1126 */
<> 144:ef7eb2e8f9f7 1127 #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
<> 144:ef7eb2e8f9f7 1128 ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
<> 144:ef7eb2e8f9f7 1129
<> 144:ef7eb2e8f9f7 1130 /**
<> 144:ef7eb2e8f9f7 1131 * @brief Ensure that UART receiver timeout setting is valid.
Anna Bridge 180:96ed750bd169 1132 * @param __TIMEOUT__ UART receiver timeout setting.
<> 144:ef7eb2e8f9f7 1133 * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
<> 144:ef7eb2e8f9f7 1134 */
<> 144:ef7eb2e8f9f7 1135 #define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
<> 144:ef7eb2e8f9f7 1136 ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
<> 144:ef7eb2e8f9f7 1137
<> 144:ef7eb2e8f9f7 1138 /**
<> 144:ef7eb2e8f9f7 1139 * @brief Ensure that UART DMA TX state is valid.
Anna Bridge 180:96ed750bd169 1140 * @param __DMATX__ UART DMA TX state.
<> 144:ef7eb2e8f9f7 1141 * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
<> 144:ef7eb2e8f9f7 1142 */
<> 144:ef7eb2e8f9f7 1143 #define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \
<> 144:ef7eb2e8f9f7 1144 ((__DMATX__) == UART_DMA_TX_ENABLE))
<> 144:ef7eb2e8f9f7 1145
<> 144:ef7eb2e8f9f7 1146 /**
<> 144:ef7eb2e8f9f7 1147 * @brief Ensure that UART DMA RX state is valid.
Anna Bridge 180:96ed750bd169 1148 * @param __DMARX__ UART DMA RX state.
<> 144:ef7eb2e8f9f7 1149 * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
<> 144:ef7eb2e8f9f7 1150 */
<> 144:ef7eb2e8f9f7 1151 #define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \
<> 144:ef7eb2e8f9f7 1152 ((__DMARX__) == UART_DMA_RX_ENABLE))
<> 144:ef7eb2e8f9f7 1153
<> 144:ef7eb2e8f9f7 1154 /**
<> 144:ef7eb2e8f9f7 1155 * @brief Ensure that UART half-duplex state is valid.
Anna Bridge 180:96ed750bd169 1156 * @param __HDSEL__ UART half-duplex state.
<> 144:ef7eb2e8f9f7 1157 * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
<> 144:ef7eb2e8f9f7 1158 */
<> 144:ef7eb2e8f9f7 1159 #define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
<> 144:ef7eb2e8f9f7 1160 ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
<> 144:ef7eb2e8f9f7 1161
<> 144:ef7eb2e8f9f7 1162 /**
<> 144:ef7eb2e8f9f7 1163 * @brief Ensure that UART wake-up method is valid.
Anna Bridge 180:96ed750bd169 1164 * @param __WAKEUP__ UART wake-up method .
<> 144:ef7eb2e8f9f7 1165 * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
<> 144:ef7eb2e8f9f7 1166 */
<> 144:ef7eb2e8f9f7 1167 #define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
<> 144:ef7eb2e8f9f7 1168 ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
<> 144:ef7eb2e8f9f7 1169
<> 144:ef7eb2e8f9f7 1170 /**
<> 144:ef7eb2e8f9f7 1171 * @brief Ensure that UART advanced features initialization is valid.
Anna Bridge 180:96ed750bd169 1172 * @param __INIT__ UART advanced features initialization.
<> 144:ef7eb2e8f9f7 1173 * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
<> 144:ef7eb2e8f9f7 1174 */
<> 144:ef7eb2e8f9f7 1175 #define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \
<> 144:ef7eb2e8f9f7 1176 UART_ADVFEATURE_TXINVERT_INIT | \
<> 144:ef7eb2e8f9f7 1177 UART_ADVFEATURE_RXINVERT_INIT | \
<> 144:ef7eb2e8f9f7 1178 UART_ADVFEATURE_DATAINVERT_INIT | \
<> 144:ef7eb2e8f9f7 1179 UART_ADVFEATURE_SWAP_INIT | \
<> 144:ef7eb2e8f9f7 1180 UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
<> 144:ef7eb2e8f9f7 1181 UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
<> 144:ef7eb2e8f9f7 1182 UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
<> 144:ef7eb2e8f9f7 1183 UART_ADVFEATURE_MSBFIRST_INIT))
<> 144:ef7eb2e8f9f7 1184
<> 144:ef7eb2e8f9f7 1185 /**
<> 144:ef7eb2e8f9f7 1186 * @brief Ensure that UART frame TX inversion setting is valid.
Anna Bridge 180:96ed750bd169 1187 * @param __TXINV__ UART frame TX inversion setting.
<> 144:ef7eb2e8f9f7 1188 * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
<> 144:ef7eb2e8f9f7 1189 */
<> 144:ef7eb2e8f9f7 1190 #define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
<> 144:ef7eb2e8f9f7 1191 ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 /**
<> 144:ef7eb2e8f9f7 1194 * @brief Ensure that UART frame RX inversion setting is valid.
Anna Bridge 180:96ed750bd169 1195 * @param __RXINV__ UART frame RX inversion setting.
<> 144:ef7eb2e8f9f7 1196 * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
<> 144:ef7eb2e8f9f7 1197 */
<> 144:ef7eb2e8f9f7 1198 #define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
<> 144:ef7eb2e8f9f7 1199 ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
<> 144:ef7eb2e8f9f7 1200
<> 144:ef7eb2e8f9f7 1201 /**
<> 144:ef7eb2e8f9f7 1202 * @brief Ensure that UART frame data inversion setting is valid.
Anna Bridge 180:96ed750bd169 1203 * @param __DATAINV__ UART frame data inversion setting.
<> 144:ef7eb2e8f9f7 1204 * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
<> 144:ef7eb2e8f9f7 1205 */
<> 144:ef7eb2e8f9f7 1206 #define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
<> 144:ef7eb2e8f9f7 1207 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /**
<> 144:ef7eb2e8f9f7 1210 * @brief Ensure that UART frame RX/TX pins swap setting is valid.
Anna Bridge 180:96ed750bd169 1211 * @param __SWAP__ UART frame RX/TX pins swap setting.
<> 144:ef7eb2e8f9f7 1212 * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
<> 144:ef7eb2e8f9f7 1213 */
<> 144:ef7eb2e8f9f7 1214 #define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
<> 144:ef7eb2e8f9f7 1215 ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
<> 144:ef7eb2e8f9f7 1216
<> 144:ef7eb2e8f9f7 1217 /**
<> 144:ef7eb2e8f9f7 1218 * @brief Ensure that UART frame overrun setting is valid.
Anna Bridge 180:96ed750bd169 1219 * @param __OVERRUN__ UART frame overrun setting.
<> 144:ef7eb2e8f9f7 1220 * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
<> 144:ef7eb2e8f9f7 1221 */
<> 144:ef7eb2e8f9f7 1222 #define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
<> 144:ef7eb2e8f9f7 1223 ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
<> 144:ef7eb2e8f9f7 1224
<> 144:ef7eb2e8f9f7 1225 /**
<> 144:ef7eb2e8f9f7 1226 * @brief Ensure that UART auto Baud rate state is valid.
Anna Bridge 180:96ed750bd169 1227 * @param __AUTOBAUDRATE__ UART auto Baud rate state.
<> 144:ef7eb2e8f9f7 1228 * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
<> 144:ef7eb2e8f9f7 1229 */
<> 144:ef7eb2e8f9f7 1230 #define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
<> 144:ef7eb2e8f9f7 1231 ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
<> 144:ef7eb2e8f9f7 1232
<> 144:ef7eb2e8f9f7 1233 /**
<> 144:ef7eb2e8f9f7 1234 * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
Anna Bridge 180:96ed750bd169 1235 * @param __DMA__ UART DMA enabling or disabling on error setting.
<> 144:ef7eb2e8f9f7 1236 * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
<> 144:ef7eb2e8f9f7 1237 */
<> 144:ef7eb2e8f9f7 1238 #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
<> 144:ef7eb2e8f9f7 1239 ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 /**
<> 144:ef7eb2e8f9f7 1242 * @brief Ensure that UART frame MSB first setting is valid.
Anna Bridge 180:96ed750bd169 1243 * @param __MSBFIRST__ UART frame MSB first setting.
<> 144:ef7eb2e8f9f7 1244 * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
<> 144:ef7eb2e8f9f7 1245 */
<> 144:ef7eb2e8f9f7 1246 #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
<> 144:ef7eb2e8f9f7 1247 ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
<> 144:ef7eb2e8f9f7 1248
<> 144:ef7eb2e8f9f7 1249 /**
<> 144:ef7eb2e8f9f7 1250 * @brief Ensure that UART mute mode state is valid.
Anna Bridge 180:96ed750bd169 1251 * @param __MUTE__ UART mute mode state.
<> 144:ef7eb2e8f9f7 1252 * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
<> 144:ef7eb2e8f9f7 1253 */
<> 144:ef7eb2e8f9f7 1254 #define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 1255 ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
<> 144:ef7eb2e8f9f7 1256
<> 144:ef7eb2e8f9f7 1257 /**
<> 144:ef7eb2e8f9f7 1258 * @brief Ensure that UART driver enable polarity is valid.
Anna Bridge 180:96ed750bd169 1259 * @param __POLARITY__ UART driver enable polarity.
<> 144:ef7eb2e8f9f7 1260 * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
<> 144:ef7eb2e8f9f7 1261 */
<> 144:ef7eb2e8f9f7 1262 #define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
<> 144:ef7eb2e8f9f7 1263 ((__POLARITY__) == UART_DE_POLARITY_LOW))
<> 144:ef7eb2e8f9f7 1264
<> 144:ef7eb2e8f9f7 1265 /**
<> 144:ef7eb2e8f9f7 1266 * @}
<> 144:ef7eb2e8f9f7 1267 */
<> 144:ef7eb2e8f9f7 1268
<> 156:95d6b41a828b 1269 /* Include UART HAL Extended module */
<> 144:ef7eb2e8f9f7 1270 #include "stm32f0xx_hal_uart_ex.h"
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1273 /** @addtogroup UART_Exported_Functions UART Exported Functions
<> 144:ef7eb2e8f9f7 1274 * @{
<> 144:ef7eb2e8f9f7 1275 */
<> 144:ef7eb2e8f9f7 1276
<> 144:ef7eb2e8f9f7 1277 /** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 1278 * @{
<> 144:ef7eb2e8f9f7 1279 */
<> 144:ef7eb2e8f9f7 1280
<> 144:ef7eb2e8f9f7 1281 /* Initialization and de-initialization functions ****************************/
<> 144:ef7eb2e8f9f7 1282 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1283 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1284 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
<> 144:ef7eb2e8f9f7 1285 HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1286 void HAL_UART_MspInit(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1287 void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1288
<> 144:ef7eb2e8f9f7 1289 /**
<> 144:ef7eb2e8f9f7 1290 * @}
<> 144:ef7eb2e8f9f7 1291 */
<> 144:ef7eb2e8f9f7 1292
<> 144:ef7eb2e8f9f7 1293 /** @addtogroup UART_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 1294 * @{
<> 144:ef7eb2e8f9f7 1295 */
<> 144:ef7eb2e8f9f7 1296
<> 144:ef7eb2e8f9f7 1297 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 1298 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 1299 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 1300 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 1301 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 1302 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 1303 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 1304 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1305 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1306 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
<> 156:95d6b41a828b 1307 /* Transfer Abort functions */
<> 156:95d6b41a828b 1308 HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
<> 156:95d6b41a828b 1309 HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
<> 156:95d6b41a828b 1310 HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
<> 156:95d6b41a828b 1311 HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
<> 156:95d6b41a828b 1312 HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
<> 156:95d6b41a828b 1313 HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
<> 156:95d6b41a828b 1314
<> 144:ef7eb2e8f9f7 1315 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1316 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1317 void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1318 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1319 void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1320 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
<> 156:95d6b41a828b 1321 void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart);
<> 156:95d6b41a828b 1322 void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart);
<> 156:95d6b41a828b 1323 void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1324
<> 144:ef7eb2e8f9f7 1325 /**
<> 144:ef7eb2e8f9f7 1326 * @}
<> 144:ef7eb2e8f9f7 1327 */
<> 144:ef7eb2e8f9f7 1328
<> 144:ef7eb2e8f9f7 1329 /** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 1330 * @{
<> 144:ef7eb2e8f9f7 1331 */
<> 144:ef7eb2e8f9f7 1332
<> 144:ef7eb2e8f9f7 1333 /* Peripheral Control functions ************************************************/
<> 144:ef7eb2e8f9f7 1334 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1335 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1336 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1337 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1338 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1339
<> 144:ef7eb2e8f9f7 1340 /**
<> 144:ef7eb2e8f9f7 1341 * @}
<> 144:ef7eb2e8f9f7 1342 */
<> 144:ef7eb2e8f9f7 1343
<> 144:ef7eb2e8f9f7 1344 /** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 1345 * @{
<> 144:ef7eb2e8f9f7 1346 */
<> 144:ef7eb2e8f9f7 1347
<> 144:ef7eb2e8f9f7 1348 /* Peripheral State and Errors functions **************************************************/
<> 144:ef7eb2e8f9f7 1349 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1350 uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1351
<> 144:ef7eb2e8f9f7 1352 /**
<> 144:ef7eb2e8f9f7 1353 * @}
<> 144:ef7eb2e8f9f7 1354 */
<> 144:ef7eb2e8f9f7 1355
<> 144:ef7eb2e8f9f7 1356 /**
<> 144:ef7eb2e8f9f7 1357 * @}
<> 144:ef7eb2e8f9f7 1358 */
<> 144:ef7eb2e8f9f7 1359
<> 144:ef7eb2e8f9f7 1360 /* Private functions -----------------------------------------------------------*/
<> 156:95d6b41a828b 1361 /** @addtogroup UART_Private_Functions UART Private Functions
<> 144:ef7eb2e8f9f7 1362 * @{
<> 144:ef7eb2e8f9f7 1363 */
<> 144:ef7eb2e8f9f7 1364 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1365 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1366 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1367 HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1368 HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 1369 HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
<> 156:95d6b41a828b 1370 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
<> 156:95d6b41a828b 1371
<> 144:ef7eb2e8f9f7 1372 /**
<> 144:ef7eb2e8f9f7 1373 * @}
<> 144:ef7eb2e8f9f7 1374 */
<> 144:ef7eb2e8f9f7 1375
<> 144:ef7eb2e8f9f7 1376 /**
<> 144:ef7eb2e8f9f7 1377 * @}
<> 144:ef7eb2e8f9f7 1378 */
<> 144:ef7eb2e8f9f7 1379
<> 144:ef7eb2e8f9f7 1380 /**
<> 144:ef7eb2e8f9f7 1381 * @}
<> 144:ef7eb2e8f9f7 1382 */
<> 144:ef7eb2e8f9f7 1383
<> 144:ef7eb2e8f9f7 1384 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1385 }
<> 144:ef7eb2e8f9f7 1386 #endif
<> 144:ef7eb2e8f9f7 1387
<> 144:ef7eb2e8f9f7 1388 #endif /* __STM32F0xx_HAL_UART_H */
<> 144:ef7eb2e8f9f7 1389
<> 144:ef7eb2e8f9f7 1390 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 1391