mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_uart.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief UART HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
<> 144:ef7eb2e8f9f7 8 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 9 * + IO operation functions
<> 144:ef7eb2e8f9f7 10 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ===============================================================================
<> 144:ef7eb2e8f9f7 15 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 16 ===============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 The UART HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
<> 144:ef7eb2e8f9f7 21 (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
<> 144:ef7eb2e8f9f7 22 (++) Enable the USARTx interface clock.
<> 144:ef7eb2e8f9f7 23 (++) UART pins configuration:
<> 144:ef7eb2e8f9f7 24 (+++) Enable the clock for the UART GPIOs.
<> 144:ef7eb2e8f9f7 25 (+++) Configure these UART pins as alternate function pull-up.
<> 144:ef7eb2e8f9f7 26 (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
<> 144:ef7eb2e8f9f7 27 and HAL_UART_Receive_IT() APIs):
<> 144:ef7eb2e8f9f7 28 (+++) Configure the USARTx interrupt priority.
<> 144:ef7eb2e8f9f7 29 (+++) Enable the NVIC USART IRQ handle.
<> 144:ef7eb2e8f9f7 30 (++) UART interrupts handling:
<> 144:ef7eb2e8f9f7 31 -@@- The specific UART interrupts (Transmission complete interrupt,
<> 144:ef7eb2e8f9f7 32 RXNE interrupt and Error Interrupts) are managed using the macros
<> 144:ef7eb2e8f9f7 33 __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes.
<> 144:ef7eb2e8f9f7 34 (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
<> 144:ef7eb2e8f9f7 35 and HAL_UART_Receive_DMA() APIs):
<> 144:ef7eb2e8f9f7 36 (+++) Declare a DMA handle structure for the Tx/Rx channel.
<> 144:ef7eb2e8f9f7 37 (+++) Enable the DMAx interface clock.
<> 144:ef7eb2e8f9f7 38 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<> 144:ef7eb2e8f9f7 39 (+++) Configure the DMA Tx/Rx channel.
<> 144:ef7eb2e8f9f7 40 (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
<> 144:ef7eb2e8f9f7 41 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
<> 144:ef7eb2e8f9f7 44 flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
<> 144:ef7eb2e8f9f7 47 in the huart handle AdvancedInit structure.
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 (#) For the UART asynchronous mode, initialize the UART registers by calling
<> 144:ef7eb2e8f9f7 50 the HAL_UART_Init() API.
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 (#) For the UART Half duplex mode, initialize the UART registers by calling
<> 144:ef7eb2e8f9f7 53 the HAL_HalfDuplex_Init() API.
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 (#) For the UART Multiprocessor mode, initialize the UART registers
<> 144:ef7eb2e8f9f7 56 by calling the HAL_MultiProcessor_Init() API.
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
<> 144:ef7eb2e8f9f7 59 by calling the HAL_RS485Ex_Init() API.
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 [..]
<> 144:ef7eb2e8f9f7 62 (@) These APIs(HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(),
<> 144:ef7eb2e8f9f7 63 also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
<> 144:ef7eb2e8f9f7 64 calling the customized HAL_UART_MspInit() API.
<> 144:ef7eb2e8f9f7 65
<> 156:95d6b41a828b 66 [..]
<> 156:95d6b41a828b 67 [..] Three operation modes are available within this driver :
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 70 =================================
<> 144:ef7eb2e8f9f7 71 [..]
<> 144:ef7eb2e8f9f7 72 (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
<> 144:ef7eb2e8f9f7 73 (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 76 ===================================
<> 144:ef7eb2e8f9f7 77 [..]
<> 144:ef7eb2e8f9f7 78 (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
<> 144:ef7eb2e8f9f7 79 (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 80 add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
<> 144:ef7eb2e8f9f7 81 (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 82 add his own code by customization of function pointer HAL_UART_TxCpltCallback
<> 144:ef7eb2e8f9f7 83 (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
<> 144:ef7eb2e8f9f7 84 (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 85 add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
<> 144:ef7eb2e8f9f7 86 (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 87 add his own code by customization of function pointer HAL_UART_RxCpltCallback
<> 144:ef7eb2e8f9f7 88 (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 89 add his own code by customization of function pointer HAL_UART_ErrorCallback
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 92 ==============================
<> 144:ef7eb2e8f9f7 93 [..]
<> 144:ef7eb2e8f9f7 94 (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
<> 144:ef7eb2e8f9f7 95 (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 96 add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
<> 144:ef7eb2e8f9f7 97 (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 98 add his own code by customization of function pointer HAL_UART_TxCpltCallback
<> 144:ef7eb2e8f9f7 99 (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
<> 144:ef7eb2e8f9f7 100 (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 101 add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
<> 144:ef7eb2e8f9f7 102 (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 103 add his own code by customization of function pointer HAL_UART_RxCpltCallback
<> 144:ef7eb2e8f9f7 104 (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 105 add his own code by customization of function pointer HAL_UART_ErrorCallback
<> 144:ef7eb2e8f9f7 106 (+) Pause the DMA Transfer using HAL_UART_DMAPause()
<> 144:ef7eb2e8f9f7 107 (+) Resume the DMA Transfer using HAL_UART_DMAResume()
<> 144:ef7eb2e8f9f7 108 (+) Stop the DMA Transfer using HAL_UART_DMAStop()
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 *** UART HAL driver macros list ***
<> 144:ef7eb2e8f9f7 111 =============================================
<> 144:ef7eb2e8f9f7 112 [..]
<> 144:ef7eb2e8f9f7 113 Below the list of most used macros in UART HAL driver.
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 (+) __HAL_UART_ENABLE: Enable the UART peripheral
<> 144:ef7eb2e8f9f7 116 (+) __HAL_UART_DISABLE: Disable the UART peripheral
<> 144:ef7eb2e8f9f7 117 (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
<> 144:ef7eb2e8f9f7 118 (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
<> 144:ef7eb2e8f9f7 119 (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
<> 144:ef7eb2e8f9f7 120 (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 [..]
<> 144:ef7eb2e8f9f7 123 (@) You can refer to the UART HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 @endverbatim
<> 144:ef7eb2e8f9f7 126 ******************************************************************************
<> 144:ef7eb2e8f9f7 127 * @attention
<> 144:ef7eb2e8f9f7 128 *
<> 144:ef7eb2e8f9f7 129 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 130 *
<> 144:ef7eb2e8f9f7 131 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 132 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 133 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 134 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 135 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 136 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 137 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 138 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 139 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 140 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 141 *
<> 144:ef7eb2e8f9f7 142 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 143 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 144 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 145 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 146 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 147 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 148 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 149 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 150 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 151 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 152 *
<> 144:ef7eb2e8f9f7 153 ******************************************************************************
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 157 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 160 * @{
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /** @defgroup UART UART
<> 144:ef7eb2e8f9f7 164 * @brief HAL UART module driver
<> 144:ef7eb2e8f9f7 165 * @{
<> 144:ef7eb2e8f9f7 166 */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 #ifdef HAL_UART_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 171 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 172 /** @defgroup UART_Private_Constants UART Private Constants
<> 144:ef7eb2e8f9f7 173 * @{
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175 #define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
<> 144:ef7eb2e8f9f7 176 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
<> 144:ef7eb2e8f9f7 177 /**
<> 144:ef7eb2e8f9f7 178 * @}
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 182 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 183 /* Private function prototypes -----------------------------------------------*/
<> 156:95d6b41a828b 184 /** @addtogroup UART_Private_Functions
<> 144:ef7eb2e8f9f7 185 * @{
<> 144:ef7eb2e8f9f7 186 */
<> 156:95d6b41a828b 187 static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
<> 156:95d6b41a828b 188 static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 189 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 190 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 191 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 192 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 193 static void UART_DMAError(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 194 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 195 static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 196 static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 197 static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 198 static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 199 HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
<> 156:95d6b41a828b 200 HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
<> 156:95d6b41a828b 201 HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 202 /**
<> 144:ef7eb2e8f9f7 203 * @}
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /** @defgroup UART_Exported_Functions UART Exported Functions
<> 144:ef7eb2e8f9f7 209 * @{
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 213 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 214 *
<> 144:ef7eb2e8f9f7 215 @verbatim
<> 144:ef7eb2e8f9f7 216 ===============================================================================
<> 144:ef7eb2e8f9f7 217 ##### Initialization and Configuration functions #####
<> 144:ef7eb2e8f9f7 218 ===============================================================================
<> 144:ef7eb2e8f9f7 219 [..]
<> 144:ef7eb2e8f9f7 220 This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
<> 144:ef7eb2e8f9f7 221 in asynchronous mode.
<> 144:ef7eb2e8f9f7 222 (+) For the asynchronous mode the parameters below can be configured:
<> 144:ef7eb2e8f9f7 223 (++) Baud Rate
<> 144:ef7eb2e8f9f7 224 (++) Word Length
<> 144:ef7eb2e8f9f7 225 (++) Stop Bit
<> 144:ef7eb2e8f9f7 226 (++) Parity
<> 144:ef7eb2e8f9f7 227 (++) Hardware flow control
<> 144:ef7eb2e8f9f7 228 (++) Receiver/transmitter modes
<> 144:ef7eb2e8f9f7 229 (++) Over Sampling Method
<> 144:ef7eb2e8f9f7 230 (++) One-Bit Sampling Method
<> 144:ef7eb2e8f9f7 231 (+) For the asynchronous mode, the following advanced features can be configured as well:
<> 144:ef7eb2e8f9f7 232 (++) TX and/or RX pin level inversion
<> 144:ef7eb2e8f9f7 233 (++) data logical level inversion
<> 144:ef7eb2e8f9f7 234 (++) RX and TX pins swap
<> 144:ef7eb2e8f9f7 235 (++) RX overrun detection disabling
<> 144:ef7eb2e8f9f7 236 (++) DMA disabling on RX error
<> 144:ef7eb2e8f9f7 237 (++) MSB first on communication line
<> 144:ef7eb2e8f9f7 238 (++) auto Baud rate detection
<> 144:ef7eb2e8f9f7 239 [..]
<> 144:ef7eb2e8f9f7 240 The HAL_UART_Init(), HAL_HalfDuplex_Init() and HAL_MultiProcessor_Init()
<> 144:ef7eb2e8f9f7 241 API follow respectively the UART asynchronous, UART Half duplex and multiprocessor mode
<> 144:ef7eb2e8f9f7 242 configuration procedures (details for the procedures are available in reference manual).
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 @endverbatim
<> 144:ef7eb2e8f9f7 245 * @{
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /*
<> 144:ef7eb2e8f9f7 249 Additional Table: If the parity is enabled, then the MSB bit of the data written
<> 144:ef7eb2e8f9f7 250 in the data register is transmitted but is changed by the parity bit.
<> 144:ef7eb2e8f9f7 251 According to device capability (support or not of 7-bit word length),
<> 144:ef7eb2e8f9f7 252 frame length is either defined by the M bit (8-bits or 9-bits)
<> 144:ef7eb2e8f9f7 253 or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
<> 144:ef7eb2e8f9f7 254 Possible UART frame formats are as listed in the following table:
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 Table 1. UART frame format.
<> 144:ef7eb2e8f9f7 257 +-----------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 258 | M bit | PCE bit | UART frame |
<> 144:ef7eb2e8f9f7 259 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 260 | 0 | 0 | | SB | 8-bit data | STB | |
<> 144:ef7eb2e8f9f7 261 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 262 | 0 | 1 | | SB | 7-bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 263 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 264 | 1 | 0 | | SB | 9-bit data | STB | |
<> 144:ef7eb2e8f9f7 265 |-------------------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 266 | 1 | 1 | | SB | 8-bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 267 +-----------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 268 | M1 bit | M0 bit | PCE bit | UART frame |
<> 144:ef7eb2e8f9f7 269 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 270 | 0 | 0 | 0 | | SB | 8 bit data | STB | |
<> 144:ef7eb2e8f9f7 271 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 272 | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 273 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 274 | 0 | 1 | 0 | | SB | 9 bit data | STB | |
<> 144:ef7eb2e8f9f7 275 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 276 | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 277 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 278 | 1 | 0 | 0 | | SB | 7 bit data | STB | |
<> 144:ef7eb2e8f9f7 279 |---------|---------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 280 | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 281 +-----------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 */
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @brief Initialize the UART mode according to the specified
<> 156:95d6b41a828b 287 * parameters in the UART_InitTypeDef and initialize the associated handle.
Anna Bridge 180:96ed750bd169 288 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 289 * @retval HAL status
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 292 {
<> 144:ef7eb2e8f9f7 293 /* Check the UART handle allocation */
<> 144:ef7eb2e8f9f7 294 if(huart == NULL)
<> 144:ef7eb2e8f9f7 295 {
<> 144:ef7eb2e8f9f7 296 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
<> 144:ef7eb2e8f9f7 300 {
<> 144:ef7eb2e8f9f7 301 /* Check the parameters */
<> 144:ef7eb2e8f9f7 302 assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
<> 144:ef7eb2e8f9f7 303 }
<> 144:ef7eb2e8f9f7 304 else
<> 144:ef7eb2e8f9f7 305 {
<> 144:ef7eb2e8f9f7 306 /* Check the parameters */
<> 144:ef7eb2e8f9f7 307 assert_param(IS_UART_INSTANCE(huart->Instance));
<> 144:ef7eb2e8f9f7 308 }
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 if(huart->gState == HAL_UART_STATE_RESET)
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 313 huart->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /* Init the low level hardware : GPIO, CLOCK */
<> 144:ef7eb2e8f9f7 316 HAL_UART_MspInit(huart);
<> 144:ef7eb2e8f9f7 317 }
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 huart->gState = HAL_UART_STATE_BUSY;
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 322 __HAL_UART_DISABLE(huart);
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /* Set the UART Communication parameters */
<> 144:ef7eb2e8f9f7 325 if (UART_SetConfig(huart) == HAL_ERROR)
<> 144:ef7eb2e8f9f7 326 {
<> 144:ef7eb2e8f9f7 327 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 328 }
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
<> 144:ef7eb2e8f9f7 331 {
<> 144:ef7eb2e8f9f7 332 UART_AdvFeatureConfig(huart);
<> 144:ef7eb2e8f9f7 333 }
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /* In asynchronous mode, the following bits must be kept cleared:
<> 144:ef7eb2e8f9f7 336 - LINEN (if LIN is supported) and CLKEN bits in the USART_CR2 register,
<> 144:ef7eb2e8f9f7 337 - SCEN (if Smartcard is supported), HDSEL and IREN (if IrDA is supported) bits in the USART_CR3 register. */
<> 144:ef7eb2e8f9f7 338 #if defined (USART_CR2_LINEN)
<> 156:95d6b41a828b 339 CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
<> 144:ef7eb2e8f9f7 340 #else
<> 156:95d6b41a828b 341 CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
<> 144:ef7eb2e8f9f7 342 #endif
<> 144:ef7eb2e8f9f7 343 #if defined (USART_CR3_SCEN)
<> 144:ef7eb2e8f9f7 344 #if defined (USART_CR3_IREN)
<> 156:95d6b41a828b 345 CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
<> 144:ef7eb2e8f9f7 346 #else
<> 156:95d6b41a828b 347 CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
<> 144:ef7eb2e8f9f7 348 #endif
<> 144:ef7eb2e8f9f7 349 #else
<> 144:ef7eb2e8f9f7 350 #if defined (USART_CR3_IREN)
<> 156:95d6b41a828b 351 CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
<> 144:ef7eb2e8f9f7 352 #else
<> 156:95d6b41a828b 353 CLEAR_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
<> 144:ef7eb2e8f9f7 354 #endif
<> 144:ef7eb2e8f9f7 355 #endif
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 358 __HAL_UART_ENABLE(huart);
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
<> 144:ef7eb2e8f9f7 361 return (UART_CheckIdleState(huart));
<> 144:ef7eb2e8f9f7 362 }
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /**
<> 144:ef7eb2e8f9f7 365 * @brief Initialize the half-duplex mode according to the specified
<> 156:95d6b41a828b 366 * parameters in the UART_InitTypeDef and creates the associated handle.
Anna Bridge 180:96ed750bd169 367 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 368 * @retval HAL status
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 371 {
<> 144:ef7eb2e8f9f7 372 /* Check the UART handle allocation */
<> 144:ef7eb2e8f9f7 373 if(huart == NULL)
<> 144:ef7eb2e8f9f7 374 {
<> 144:ef7eb2e8f9f7 375 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 376 }
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /* Check UART instance */
<> 144:ef7eb2e8f9f7 379 assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 if(huart->gState == HAL_UART_STATE_RESET)
<> 144:ef7eb2e8f9f7 382 {
<> 144:ef7eb2e8f9f7 383 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 384 huart->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /* Init the low level hardware : GPIO, CLOCK */
<> 144:ef7eb2e8f9f7 387 HAL_UART_MspInit(huart);
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 huart->gState = HAL_UART_STATE_BUSY;
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 393 __HAL_UART_DISABLE(huart);
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /* Set the UART Communication parameters */
<> 144:ef7eb2e8f9f7 396 if (UART_SetConfig(huart) == HAL_ERROR)
<> 144:ef7eb2e8f9f7 397 {
<> 144:ef7eb2e8f9f7 398 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 399 }
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
<> 144:ef7eb2e8f9f7 402 {
<> 144:ef7eb2e8f9f7 403 UART_AdvFeatureConfig(huart);
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /* In half-duplex mode, the following bits must be kept cleared:
<> 144:ef7eb2e8f9f7 407 - LINEN (if LIN is supported) and CLKEN bits in the USART_CR2 register,
<> 144:ef7eb2e8f9f7 408 - SCEN (if Smartcard is supported), and IREN (if IrDA is supported) bits in the USART_CR3 register. */
<> 144:ef7eb2e8f9f7 409 #if defined (USART_CR2_LINEN)
<> 156:95d6b41a828b 410 CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
<> 144:ef7eb2e8f9f7 411 #else
<> 156:95d6b41a828b 412 CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
<> 144:ef7eb2e8f9f7 413 #endif
<> 144:ef7eb2e8f9f7 414 #if defined (USART_CR3_SCEN)
<> 144:ef7eb2e8f9f7 415 #if defined (USART_CR3_IREN)
<> 156:95d6b41a828b 416 CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
<> 144:ef7eb2e8f9f7 417 #else
<> 156:95d6b41a828b 418 CLEAR_BIT(huart->Instance->CR3, USART_CR3_SCEN);
<> 144:ef7eb2e8f9f7 419 #endif
<> 144:ef7eb2e8f9f7 420 #else
<> 144:ef7eb2e8f9f7 421 #if defined (USART_CR3_IREN)
<> 156:95d6b41a828b 422 CLEAR_BIT(huart->Instance->CR3, USART_CR3_IREN);
<> 144:ef7eb2e8f9f7 423 #endif
<> 144:ef7eb2e8f9f7 424 #endif
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
<> 156:95d6b41a828b 427 SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 430 __HAL_UART_ENABLE(huart);
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
<> 144:ef7eb2e8f9f7 433 return (UART_CheckIdleState(huart));
<> 144:ef7eb2e8f9f7 434 }
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /**
<> 144:ef7eb2e8f9f7 438 * @brief Initialize the multiprocessor mode according to the specified
<> 156:95d6b41a828b 439 * parameters in the UART_InitTypeDef and initialize the associated handle.
Anna Bridge 180:96ed750bd169 440 * @param huart UART handle.
Anna Bridge 180:96ed750bd169 441 * @param Address UART node address (4-, 6-, 7- or 8-bit long).
Anna Bridge 180:96ed750bd169 442 * @param WakeUpMethod specifies the UART wakeup method.
<> 144:ef7eb2e8f9f7 443 * This parameter can be one of the following values:
<> 156:95d6b41a828b 444 * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
<> 156:95d6b41a828b 445 * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
<> 144:ef7eb2e8f9f7 446 * @note If the user resorts to idle line detection wake up, the Address parameter
<> 144:ef7eb2e8f9f7 447 * is useless and ignored by the initialization function.
<> 144:ef7eb2e8f9f7 448 * @note If the user resorts to address mark wake up, the address length detection
<> 144:ef7eb2e8f9f7 449 * is configured by default to 4 bits only. For the UART to be able to
<> 144:ef7eb2e8f9f7 450 * manage 6-, 7- or 8-bit long addresses detection, the API
<> 144:ef7eb2e8f9f7 451 * HAL_MultiProcessorEx_AddressLength_Set() must be called after
<> 144:ef7eb2e8f9f7 452 * HAL_MultiProcessor_Init().
<> 144:ef7eb2e8f9f7 453 * @retval HAL status
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
<> 144:ef7eb2e8f9f7 456 {
<> 144:ef7eb2e8f9f7 457 /* Check the UART handle allocation */
<> 144:ef7eb2e8f9f7 458 if(huart == NULL)
<> 144:ef7eb2e8f9f7 459 {
<> 144:ef7eb2e8f9f7 460 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 461 }
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /* Check the wake up method parameter */
<> 144:ef7eb2e8f9f7 464 assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 if(huart->gState == HAL_UART_STATE_RESET)
<> 144:ef7eb2e8f9f7 467 {
<> 144:ef7eb2e8f9f7 468 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 469 huart->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /* Init the low level hardware : GPIO, CLOCK */
<> 144:ef7eb2e8f9f7 472 HAL_UART_MspInit(huart);
<> 144:ef7eb2e8f9f7 473 }
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 huart->gState = HAL_UART_STATE_BUSY;
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 478 __HAL_UART_DISABLE(huart);
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /* Set the UART Communication parameters */
<> 144:ef7eb2e8f9f7 481 if (UART_SetConfig(huart) == HAL_ERROR)
<> 144:ef7eb2e8f9f7 482 {
<> 144:ef7eb2e8f9f7 483 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 484 }
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
<> 144:ef7eb2e8f9f7 487 {
<> 144:ef7eb2e8f9f7 488 UART_AdvFeatureConfig(huart);
<> 144:ef7eb2e8f9f7 489 }
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* In multiprocessor mode, the following bits must be kept cleared:
<> 144:ef7eb2e8f9f7 492 - LINEN (if LIN is supported) and CLKEN bits in the USART_CR2 register,
<> 144:ef7eb2e8f9f7 493 - SCEN (if Smartcard is supported), HDSEL and IREN (if IrDA is supported) bits in the USART_CR3 register. */
<> 144:ef7eb2e8f9f7 494 #if defined (USART_CR2_LINEN)
<> 156:95d6b41a828b 495 CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
<> 144:ef7eb2e8f9f7 496 #else
<> 156:95d6b41a828b 497 CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
<> 144:ef7eb2e8f9f7 498 #endif
<> 144:ef7eb2e8f9f7 499 #if defined (USART_CR3_SCEN)
<> 144:ef7eb2e8f9f7 500 #if defined (USART_CR3_IREN)
<> 156:95d6b41a828b 501 CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
<> 144:ef7eb2e8f9f7 502 #else
<> 156:95d6b41a828b 503 CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
<> 144:ef7eb2e8f9f7 504 #endif
<> 144:ef7eb2e8f9f7 505 #else
<> 144:ef7eb2e8f9f7 506 #if defined (USART_CR3_IREN)
<> 156:95d6b41a828b 507 CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
<> 144:ef7eb2e8f9f7 508 #else
<> 156:95d6b41a828b 509 CLEAR_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
<> 144:ef7eb2e8f9f7 510 #endif
<> 144:ef7eb2e8f9f7 511 #endif
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
<> 144:ef7eb2e8f9f7 514 {
<> 144:ef7eb2e8f9f7 515 /* If address mark wake up method is chosen, set the USART address node */
<> 144:ef7eb2e8f9f7 516 MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
<> 144:ef7eb2e8f9f7 517 }
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /* Set the wake up method by setting the WAKE bit in the CR1 register */
<> 144:ef7eb2e8f9f7 520 MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 523 __HAL_UART_ENABLE(huart);
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
<> 144:ef7eb2e8f9f7 526 return (UART_CheckIdleState(huart));
<> 144:ef7eb2e8f9f7 527 }
<> 144:ef7eb2e8f9f7 528
<> 156:95d6b41a828b 529
<> 144:ef7eb2e8f9f7 530 /**
<> 144:ef7eb2e8f9f7 531 * @brief DeInitialize the UART peripheral.
Anna Bridge 180:96ed750bd169 532 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 533 * @retval HAL status
<> 144:ef7eb2e8f9f7 534 */
<> 144:ef7eb2e8f9f7 535 HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 536 {
<> 144:ef7eb2e8f9f7 537 /* Check the UART handle allocation */
<> 144:ef7eb2e8f9f7 538 if(huart == NULL)
<> 144:ef7eb2e8f9f7 539 {
<> 144:ef7eb2e8f9f7 540 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 541 }
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /* Check the parameters */
<> 144:ef7eb2e8f9f7 544 assert_param(IS_UART_INSTANCE(huart->Instance));
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 huart->gState = HAL_UART_STATE_BUSY;
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 549 __HAL_UART_DISABLE(huart);
<> 144:ef7eb2e8f9f7 550
<> 156:95d6b41a828b 551 huart->Instance->CR1 = 0x0U;
<> 156:95d6b41a828b 552 huart->Instance->CR2 = 0x0U;
<> 156:95d6b41a828b 553 huart->Instance->CR3 = 0x0U;
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 556 HAL_UART_MspDeInit(huart);
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 156:95d6b41a828b 559 huart->gState = HAL_UART_STATE_RESET;
<> 156:95d6b41a828b 560 huart->RxState = HAL_UART_STATE_RESET;
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* Process Unlock */
<> 144:ef7eb2e8f9f7 563 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 return HAL_OK;
<> 144:ef7eb2e8f9f7 566 }
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /**
<> 144:ef7eb2e8f9f7 569 * @brief Initialize the UART MSP.
Anna Bridge 180:96ed750bd169 570 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 571 * @retval None
<> 144:ef7eb2e8f9f7 572 */
<> 156:95d6b41a828b 573 __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 574 {
<> 144:ef7eb2e8f9f7 575 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 576 UNUSED(huart);
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 579 the HAL_UART_MspInit can be implemented in the user file
<> 144:ef7eb2e8f9f7 580 */
<> 144:ef7eb2e8f9f7 581 }
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 /**
<> 144:ef7eb2e8f9f7 584 * @brief DeInitialize the UART MSP.
Anna Bridge 180:96ed750bd169 585 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 586 * @retval None
<> 144:ef7eb2e8f9f7 587 */
<> 156:95d6b41a828b 588 __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 589 {
<> 144:ef7eb2e8f9f7 590 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 591 UNUSED(huart);
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 594 the HAL_UART_MspDeInit can be implemented in the user file
<> 144:ef7eb2e8f9f7 595 */
<> 144:ef7eb2e8f9f7 596 }
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /**
<> 144:ef7eb2e8f9f7 599 * @}
<> 144:ef7eb2e8f9f7 600 */
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /** @defgroup UART_Exported_Functions_Group2 IO operation functions
<> 156:95d6b41a828b 603 * @brief UART Transmit/Receive functions
<> 144:ef7eb2e8f9f7 604 *
<> 144:ef7eb2e8f9f7 605 @verbatim
<> 144:ef7eb2e8f9f7 606 ===============================================================================
<> 144:ef7eb2e8f9f7 607 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 608 ===============================================================================
<> 144:ef7eb2e8f9f7 609 This subsection provides a set of functions allowing to manage the UART asynchronous
<> 144:ef7eb2e8f9f7 610 and Half duplex data transfers.
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 (#) There are two mode of transfer:
<> 156:95d6b41a828b 613 (++) Blocking mode: The communication is performed in polling mode.
<> 156:95d6b41a828b 614 The HAL status of all data processing is returned by the same function
<> 156:95d6b41a828b 615 after finishing transfer.
<> 156:95d6b41a828b 616 (++) Non-Blocking mode: The communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 617 or DMA, These API's return the HAL status.
<> 144:ef7eb2e8f9f7 618 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 619 dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 620 using DMA mode.
<> 144:ef7eb2e8f9f7 621 The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
<> 144:ef7eb2e8f9f7 622 will be executed respectively at the end of the transmit or Receive process
<> 144:ef7eb2e8f9f7 623 The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 (#) Blocking mode API's are :
<> 156:95d6b41a828b 626 (++) HAL_UART_Transmit()
<> 156:95d6b41a828b 627 (++) HAL_UART_Receive()
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 (#) Non-Blocking mode API's with Interrupt are :
<> 156:95d6b41a828b 630 (++) HAL_UART_Transmit_IT()
<> 156:95d6b41a828b 631 (++) HAL_UART_Receive_IT()
<> 156:95d6b41a828b 632 (++) HAL_UART_IRQHandler()
<> 156:95d6b41a828b 633
<> 156:95d6b41a828b 634 (#) Non-Blocking mode API's with DMA are :
<> 156:95d6b41a828b 635 (++) HAL_UART_Transmit_DMA()
<> 156:95d6b41a828b 636 (++) HAL_UART_Receive_DMA()
<> 156:95d6b41a828b 637 (++) HAL_UART_DMAPause()
<> 156:95d6b41a828b 638 (++) HAL_UART_DMAResume()
<> 156:95d6b41a828b 639 (++) HAL_UART_DMAStop()
<> 156:95d6b41a828b 640
<> 156:95d6b41a828b 641 (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
<> 156:95d6b41a828b 642 (++) HAL_UART_TxHalfCpltCallback()
<> 156:95d6b41a828b 643 (++) HAL_UART_TxCpltCallback()
<> 156:95d6b41a828b 644 (++) HAL_UART_RxHalfCpltCallback()
<> 156:95d6b41a828b 645 (++) HAL_UART_RxCpltCallback()
<> 156:95d6b41a828b 646 (++) HAL_UART_ErrorCallback()
<> 156:95d6b41a828b 647
<> 156:95d6b41a828b 648 (#) Non-Blocking mode transfers could be aborted using Abort API's :
<> 156:95d6b41a828b 649 (++) HAL_UART_Abort()
<> 156:95d6b41a828b 650 (++) HAL_UART_AbortTransmit()
<> 156:95d6b41a828b 651 (++) HAL_UART_AbortReceive()
<> 156:95d6b41a828b 652 (++) HAL_UART_Abort_IT()
<> 156:95d6b41a828b 653 (++) HAL_UART_AbortTransmit_IT()
<> 156:95d6b41a828b 654 (++) HAL_UART_AbortReceive_IT()
<> 156:95d6b41a828b 655
<> 156:95d6b41a828b 656 (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
<> 156:95d6b41a828b 657 (++) HAL_UART_AbortCpltCallback()
<> 156:95d6b41a828b 658 (++) HAL_UART_AbortTransmitCpltCallback()
<> 156:95d6b41a828b 659 (++) HAL_UART_AbortReceiveCpltCallback()
<> 156:95d6b41a828b 660
<> 156:95d6b41a828b 661 (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
<> 156:95d6b41a828b 662 Errors are handled as follows :
<> 156:95d6b41a828b 663 (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
<> 156:95d6b41a828b 664 to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
<> 156:95d6b41a828b 665 Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
<> 156:95d6b41a828b 666 and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
<> 156:95d6b41a828b 667 If user wants to abort it, Abort services should be called by user.
<> 156:95d6b41a828b 668 (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
<> 156:95d6b41a828b 669 This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
<> 156:95d6b41a828b 670 Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 -@- In the Half duplex communication, it is forbidden to run the transmit
<> 144:ef7eb2e8f9f7 673 and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 @endverbatim
<> 144:ef7eb2e8f9f7 676 * @{
<> 144:ef7eb2e8f9f7 677 */
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /**
<> 144:ef7eb2e8f9f7 680 * @brief Send an amount of data in blocking mode.
Anna Bridge 180:96ed750bd169 681 * @param huart UART handle.
Anna Bridge 180:96ed750bd169 682 * @param pData Pointer to data buffer.
Anna Bridge 180:96ed750bd169 683 * @param Size Amount of data to be sent.
Anna Bridge 180:96ed750bd169 684 * @param Timeout Timeout duration.
<> 144:ef7eb2e8f9f7 685 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 686 * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 687 * (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 688 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 689 * @retval HAL status
<> 144:ef7eb2e8f9f7 690 */
<> 144:ef7eb2e8f9f7 691 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 692 {
<> 156:95d6b41a828b 693 uint16_t* tmp;
<> 156:95d6b41a828b 694 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 697 if(huart->gState == HAL_UART_STATE_READY)
<> 144:ef7eb2e8f9f7 698 {
<> 156:95d6b41a828b 699 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 700 {
<> 144:ef7eb2e8f9f7 701 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 702 }
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 705 should be aligned on a u16 frontier, as data to be filled into TDR will be
<> 144:ef7eb2e8f9f7 706 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 707 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 708 {
<> 156:95d6b41a828b 709 if((((uint32_t)pData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 710 {
<> 144:ef7eb2e8f9f7 711 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 712 }
<> 144:ef7eb2e8f9f7 713 }
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 /* Process Locked */
<> 144:ef7eb2e8f9f7 716 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 719 huart->gState = HAL_UART_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 720
<> 156:95d6b41a828b 721 /* Init tickstart for timeout managment*/
<> 156:95d6b41a828b 722 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 723
<> 144:ef7eb2e8f9f7 724 huart->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 725 huart->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 726 while(huart->TxXferCount > 0)
<> 144:ef7eb2e8f9f7 727 {
<> 144:ef7eb2e8f9f7 728 huart->TxXferCount--;
<> 156:95d6b41a828b 729 if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 732 }
<> 144:ef7eb2e8f9f7 733 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 734 {
<> 144:ef7eb2e8f9f7 735 tmp = (uint16_t*) pData;
<> 156:95d6b41a828b 736 huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
<> 144:ef7eb2e8f9f7 737 pData += 2;
<> 144:ef7eb2e8f9f7 738 }
<> 144:ef7eb2e8f9f7 739 else
<> 144:ef7eb2e8f9f7 740 {
<> 156:95d6b41a828b 741 huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
<> 144:ef7eb2e8f9f7 742 }
<> 144:ef7eb2e8f9f7 743 }
<> 156:95d6b41a828b 744 if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 745 {
<> 144:ef7eb2e8f9f7 746 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 747 }
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /* At end of Tx process, restore huart->gState to Ready */
<> 144:ef7eb2e8f9f7 750 huart->gState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 753 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 return HAL_OK;
<> 144:ef7eb2e8f9f7 756 }
<> 144:ef7eb2e8f9f7 757 else
<> 144:ef7eb2e8f9f7 758 {
<> 144:ef7eb2e8f9f7 759 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 760 }
<> 144:ef7eb2e8f9f7 761 }
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 /**
<> 144:ef7eb2e8f9f7 764 * @brief Receive an amount of data in blocking mode.
Anna Bridge 180:96ed750bd169 765 * @param huart UART handle.
Anna Bridge 180:96ed750bd169 766 * @param pData pointer to data buffer.
Anna Bridge 180:96ed750bd169 767 * @param Size amount of data to be received.
Anna Bridge 180:96ed750bd169 768 * @param Timeout Timeout duration.
<> 144:ef7eb2e8f9f7 769 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 770 * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 771 * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 772 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 773 * @retval HAL status
<> 144:ef7eb2e8f9f7 774 */
<> 144:ef7eb2e8f9f7 775 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 776 {
<> 144:ef7eb2e8f9f7 777 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 778 uint16_t uhMask;
<> 156:95d6b41a828b 779 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 782 if(huart->RxState == HAL_UART_STATE_READY)
<> 144:ef7eb2e8f9f7 783 {
<> 156:95d6b41a828b 784 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 785 {
<> 144:ef7eb2e8f9f7 786 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 787 }
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 790 should be aligned on a u16 frontier, as data to be received from RDR will be
<> 144:ef7eb2e8f9f7 791 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 792 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 793 {
<> 156:95d6b41a828b 794 if((((uint32_t)pData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 795 {
<> 144:ef7eb2e8f9f7 796 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 797 }
<> 144:ef7eb2e8f9f7 798 }
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 /* Process Locked */
<> 144:ef7eb2e8f9f7 801 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 804 huart->RxState = HAL_UART_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 805
<> 156:95d6b41a828b 806 /* Init tickstart for timeout managment*/
<> 156:95d6b41a828b 807 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 808
<> 144:ef7eb2e8f9f7 809 huart->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 810 huart->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /* Computation of UART mask to apply to RDR register */
<> 144:ef7eb2e8f9f7 813 UART_MASK_COMPUTATION(huart);
<> 144:ef7eb2e8f9f7 814 uhMask = huart->Mask;
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /* as long as data have to be received */
<> 156:95d6b41a828b 817 while(huart->RxXferCount > 0U)
<> 144:ef7eb2e8f9f7 818 {
<> 144:ef7eb2e8f9f7 819 huart->RxXferCount--;
<> 156:95d6b41a828b 820 if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 821 {
<> 144:ef7eb2e8f9f7 822 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 823 }
<> 144:ef7eb2e8f9f7 824 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 825 {
<> 144:ef7eb2e8f9f7 826 tmp = (uint16_t*) pData ;
<> 144:ef7eb2e8f9f7 827 *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
<> 156:95d6b41a828b 828 pData +=2U;
<> 144:ef7eb2e8f9f7 829 }
<> 144:ef7eb2e8f9f7 830 else
<> 144:ef7eb2e8f9f7 831 {
<> 144:ef7eb2e8f9f7 832 *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
<> 144:ef7eb2e8f9f7 833 }
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /* At end of Rx process, restore huart->RxState to Ready */
<> 144:ef7eb2e8f9f7 837 huart->RxState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 840 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 return HAL_OK;
<> 144:ef7eb2e8f9f7 843 }
<> 144:ef7eb2e8f9f7 844 else
<> 144:ef7eb2e8f9f7 845 {
<> 144:ef7eb2e8f9f7 846 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 847 }
<> 144:ef7eb2e8f9f7 848 }
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /**
<> 144:ef7eb2e8f9f7 851 * @brief Send an amount of data in interrupt mode.
Anna Bridge 180:96ed750bd169 852 * @param huart UART handle.
Anna Bridge 180:96ed750bd169 853 * @param pData pointer to data buffer.
Anna Bridge 180:96ed750bd169 854 * @param Size amount of data to be sent.
<> 144:ef7eb2e8f9f7 855 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 856 * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 857 * (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 858 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 859 * @retval HAL status
<> 144:ef7eb2e8f9f7 860 */
<> 144:ef7eb2e8f9f7 861 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 862 {
<> 144:ef7eb2e8f9f7 863 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 864 if(huart->gState == HAL_UART_STATE_READY)
<> 144:ef7eb2e8f9f7 865 {
<> 156:95d6b41a828b 866 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 867 {
<> 144:ef7eb2e8f9f7 868 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 869 }
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 872 should be aligned on a u16 frontier, as data to be filled into TDR will be
<> 144:ef7eb2e8f9f7 873 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 874 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 875 {
<> 156:95d6b41a828b 876 if((((uint32_t)pData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 877 {
<> 144:ef7eb2e8f9f7 878 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 879 }
<> 144:ef7eb2e8f9f7 880 }
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /* Process Locked */
<> 144:ef7eb2e8f9f7 883 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885 huart->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 886 huart->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 887 huart->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 888
<> 144:ef7eb2e8f9f7 889 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 890 huart->gState = HAL_UART_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 893 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 /* Enable the UART Transmit Data Register Empty Interrupt */
<> 156:95d6b41a828b 896 SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 return HAL_OK;
<> 144:ef7eb2e8f9f7 899 }
<> 144:ef7eb2e8f9f7 900 else
<> 144:ef7eb2e8f9f7 901 {
<> 144:ef7eb2e8f9f7 902 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 903 }
<> 144:ef7eb2e8f9f7 904 }
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 /**
<> 144:ef7eb2e8f9f7 907 * @brief Receive an amount of data in interrupt mode.
Anna Bridge 180:96ed750bd169 908 * @param huart UART handle.
Anna Bridge 180:96ed750bd169 909 * @param pData pointer to data buffer.
Anna Bridge 180:96ed750bd169 910 * @param Size amount of data to be received.
<> 144:ef7eb2e8f9f7 911 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 912 * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 913 * (as received data will be handled using u16 pointer cast). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 914 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 915 * @retval HAL status
<> 144:ef7eb2e8f9f7 916 */
<> 144:ef7eb2e8f9f7 917 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 918 {
<> 144:ef7eb2e8f9f7 919 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 920 if(huart->RxState == HAL_UART_STATE_READY)
<> 144:ef7eb2e8f9f7 921 {
<> 156:95d6b41a828b 922 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 923 {
<> 144:ef7eb2e8f9f7 924 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 925 }
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 928 should be aligned on a u16 frontier, as data to be received from RDR will be
<> 144:ef7eb2e8f9f7 929 handled through a u16 cast. */
<> 144:ef7eb2e8f9f7 930 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 931 {
<> 156:95d6b41a828b 932 if((((uint32_t)pData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 933 {
<> 144:ef7eb2e8f9f7 934 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 935 }
<> 144:ef7eb2e8f9f7 936 }
<> 144:ef7eb2e8f9f7 937
<> 144:ef7eb2e8f9f7 938 /* Process Locked */
<> 144:ef7eb2e8f9f7 939 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 huart->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 942 huart->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 943 huart->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 944
<> 144:ef7eb2e8f9f7 945 /* Computation of UART mask to apply to RDR register */
<> 144:ef7eb2e8f9f7 946 UART_MASK_COMPUTATION(huart);
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 949 huart->RxState = HAL_UART_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 950
<> 156:95d6b41a828b 951 /* Process Unlocked */
<> 156:95d6b41a828b 952 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
<> 156:95d6b41a828b 955 SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 956
<> 156:95d6b41a828b 957 /* Enable the UART Parity Error and Data Register not empty Interrupts */
<> 156:95d6b41a828b 958 SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 return HAL_OK;
<> 144:ef7eb2e8f9f7 961 }
<> 144:ef7eb2e8f9f7 962 else
<> 144:ef7eb2e8f9f7 963 {
<> 144:ef7eb2e8f9f7 964 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 965 }
<> 144:ef7eb2e8f9f7 966 }
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 /**
<> 144:ef7eb2e8f9f7 969 * @brief Send an amount of data in DMA mode.
Anna Bridge 180:96ed750bd169 970 * @param huart UART handle.
Anna Bridge 180:96ed750bd169 971 * @param pData pointer to data buffer.
Anna Bridge 180:96ed750bd169 972 * @param Size amount of data to be sent.
<> 144:ef7eb2e8f9f7 973 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 974 * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 975 * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 976 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 977 * @retval HAL status
<> 144:ef7eb2e8f9f7 978 */
<> 144:ef7eb2e8f9f7 979 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 980 {
<> 144:ef7eb2e8f9f7 981 /* Check that a Tx process is not already ongoing */
<> 144:ef7eb2e8f9f7 982 if(huart->gState == HAL_UART_STATE_READY)
<> 144:ef7eb2e8f9f7 983 {
<> 156:95d6b41a828b 984 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 985 {
<> 144:ef7eb2e8f9f7 986 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 987 }
<> 144:ef7eb2e8f9f7 988
<> 144:ef7eb2e8f9f7 989 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 990 should be aligned on a u16 frontier, as data copy into TDR will be
<> 144:ef7eb2e8f9f7 991 handled by DMA from a u16 frontier. */
<> 144:ef7eb2e8f9f7 992 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 993 {
<> 156:95d6b41a828b 994 if((((uint32_t)pData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 995 {
<> 144:ef7eb2e8f9f7 996 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 997 }
<> 144:ef7eb2e8f9f7 998 }
<> 144:ef7eb2e8f9f7 999
<> 144:ef7eb2e8f9f7 1000 /* Process Locked */
<> 144:ef7eb2e8f9f7 1001 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 huart->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1004 huart->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1005 huart->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1008 huart->gState = HAL_UART_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 /* Set the UART DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1011 huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /* Set the UART DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1014 huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1017 huart->hdmatx->XferErrorCallback = UART_DMAError;
<> 144:ef7eb2e8f9f7 1018
<> 156:95d6b41a828b 1019 /* Set the DMA abort callback */
<> 156:95d6b41a828b 1020 huart->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1021
<> 144:ef7eb2e8f9f7 1022 /* Enable the UART transmit DMA channel */
<> 156:95d6b41a828b 1023 HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size);
<> 144:ef7eb2e8f9f7 1024
<> 144:ef7eb2e8f9f7 1025 /* Clear the TC flag in the ICR register */
<> 144:ef7eb2e8f9f7 1026 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
<> 144:ef7eb2e8f9f7 1027
<> 156:95d6b41a828b 1028 /* Process Unlocked */
<> 156:95d6b41a828b 1029 __HAL_UNLOCK(huart);
<> 156:95d6b41a828b 1030
<> 144:ef7eb2e8f9f7 1031 /* Enable the DMA transfer for transmit request by setting the DMAT bit
<> 144:ef7eb2e8f9f7 1032 in the UART CR3 register */
<> 156:95d6b41a828b 1033 SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 return HAL_OK;
<> 144:ef7eb2e8f9f7 1036 }
<> 144:ef7eb2e8f9f7 1037 else
<> 144:ef7eb2e8f9f7 1038 {
<> 144:ef7eb2e8f9f7 1039 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1040 }
<> 144:ef7eb2e8f9f7 1041 }
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 /**
<> 144:ef7eb2e8f9f7 1044 * @brief Receive an amount of data in DMA mode.
Anna Bridge 180:96ed750bd169 1045 * @param huart UART handle.
Anna Bridge 180:96ed750bd169 1046 * @param pData pointer to data buffer.
Anna Bridge 180:96ed750bd169 1047 * @param Size amount of data to be received.
<> 144:ef7eb2e8f9f7 1048 * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
<> 144:ef7eb2e8f9f7 1049 * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
<> 144:ef7eb2e8f9f7 1050 * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
<> 144:ef7eb2e8f9f7 1051 * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
<> 144:ef7eb2e8f9f7 1052 * @retval HAL status
<> 144:ef7eb2e8f9f7 1053 */
<> 144:ef7eb2e8f9f7 1054 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1055 {
<> 144:ef7eb2e8f9f7 1056 /* Check that a Rx process is not already ongoing */
<> 144:ef7eb2e8f9f7 1057 if(huart->RxState == HAL_UART_STATE_READY)
<> 144:ef7eb2e8f9f7 1058 {
<> 156:95d6b41a828b 1059 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1060 {
<> 144:ef7eb2e8f9f7 1061 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1062 }
<> 144:ef7eb2e8f9f7 1063
<> 144:ef7eb2e8f9f7 1064 /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
<> 144:ef7eb2e8f9f7 1065 should be aligned on a u16 frontier, as data copy from RDR will be
<> 144:ef7eb2e8f9f7 1066 handled by DMA from a u16 frontier. */
<> 144:ef7eb2e8f9f7 1067 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 1068 {
<> 156:95d6b41a828b 1069 if((((uint32_t)pData)&1U) != 0U)
<> 144:ef7eb2e8f9f7 1070 {
<> 144:ef7eb2e8f9f7 1071 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1072 }
<> 144:ef7eb2e8f9f7 1073 }
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075 /* Process Locked */
<> 144:ef7eb2e8f9f7 1076 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 1077
<> 144:ef7eb2e8f9f7 1078 huart->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1079 huart->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1080
<> 144:ef7eb2e8f9f7 1081 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1082 huart->RxState = HAL_UART_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1083
<> 144:ef7eb2e8f9f7 1084 /* Set the UART DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1085 huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 1086
<> 144:ef7eb2e8f9f7 1087 /* Set the UART DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1088 huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1091 huart->hdmarx->XferErrorCallback = UART_DMAError;
<> 144:ef7eb2e8f9f7 1092
<> 156:95d6b41a828b 1093 /* Set the DMA abort callback */
<> 156:95d6b41a828b 1094 huart->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1095
<> 144:ef7eb2e8f9f7 1096 /* Enable the DMA channel */
<> 156:95d6b41a828b 1097 HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size);
<> 156:95d6b41a828b 1098
<> 156:95d6b41a828b 1099 /* Process Unlocked */
<> 156:95d6b41a828b 1100 __HAL_UNLOCK(huart);
<> 156:95d6b41a828b 1101
<> 156:95d6b41a828b 1102 /* Enable the UART Parity Error Interrupt */
<> 156:95d6b41a828b 1103 SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
<> 156:95d6b41a828b 1104
<> 156:95d6b41a828b 1105 /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
<> 156:95d6b41a828b 1106 SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 /* Enable the DMA transfer for the receiver request by setting the DMAR bit
<> 144:ef7eb2e8f9f7 1109 in the UART CR3 register */
<> 156:95d6b41a828b 1110 SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1111
<> 144:ef7eb2e8f9f7 1112 return HAL_OK;
<> 144:ef7eb2e8f9f7 1113 }
<> 144:ef7eb2e8f9f7 1114 else
<> 144:ef7eb2e8f9f7 1115 {
<> 144:ef7eb2e8f9f7 1116 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1117 }
<> 144:ef7eb2e8f9f7 1118 }
<> 144:ef7eb2e8f9f7 1119
<> 144:ef7eb2e8f9f7 1120 /**
<> 144:ef7eb2e8f9f7 1121 * @brief Pause the DMA Transfer.
Anna Bridge 180:96ed750bd169 1122 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 1123 * @retval HAL status
<> 144:ef7eb2e8f9f7 1124 */
<> 144:ef7eb2e8f9f7 1125 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1126 {
<> 144:ef7eb2e8f9f7 1127 /* Process Locked */
<> 144:ef7eb2e8f9f7 1128 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 1129
<> 156:95d6b41a828b 1130 if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
<> 156:95d6b41a828b 1131 (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
<> 144:ef7eb2e8f9f7 1132 {
<> 144:ef7eb2e8f9f7 1133 /* Disable the UART DMA Tx request */
<> 156:95d6b41a828b 1134 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1135 }
<> 156:95d6b41a828b 1136 if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
<> 156:95d6b41a828b 1137 (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
<> 144:ef7eb2e8f9f7 1138 {
<> 156:95d6b41a828b 1139 /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1140 CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
<> 156:95d6b41a828b 1141 CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1142
<> 144:ef7eb2e8f9f7 1143 /* Disable the UART DMA Rx request */
<> 156:95d6b41a828b 1144 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1145 }
<> 144:ef7eb2e8f9f7 1146
<> 144:ef7eb2e8f9f7 1147 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1148 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 1149
<> 144:ef7eb2e8f9f7 1150 return HAL_OK;
<> 144:ef7eb2e8f9f7 1151 }
<> 144:ef7eb2e8f9f7 1152
<> 144:ef7eb2e8f9f7 1153 /**
<> 144:ef7eb2e8f9f7 1154 * @brief Resume the DMA Transfer.
Anna Bridge 180:96ed750bd169 1155 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 1156 * @retval HAL status
<> 144:ef7eb2e8f9f7 1157 */
<> 144:ef7eb2e8f9f7 1158 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1159 {
<> 144:ef7eb2e8f9f7 1160 /* Process Locked */
<> 144:ef7eb2e8f9f7 1161 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 if(huart->gState == HAL_UART_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1164 {
<> 144:ef7eb2e8f9f7 1165 /* Enable the UART DMA Tx request */
<> 156:95d6b41a828b 1166 SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1167 }
<> 144:ef7eb2e8f9f7 1168 if(huart->RxState == HAL_UART_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1169 {
<> 156:95d6b41a828b 1170 /* Clear the Overrun flag before resuming the Rx transfer */
<> 144:ef7eb2e8f9f7 1171 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
<> 144:ef7eb2e8f9f7 1172
<> 156:95d6b41a828b 1173 /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1174 SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
<> 156:95d6b41a828b 1175 SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1176
<> 144:ef7eb2e8f9f7 1177 /* Enable the UART DMA Rx request */
<> 156:95d6b41a828b 1178 SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1179 }
<> 144:ef7eb2e8f9f7 1180
<> 144:ef7eb2e8f9f7 1181 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1182 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 1183
<> 144:ef7eb2e8f9f7 1184 return HAL_OK;
<> 144:ef7eb2e8f9f7 1185 }
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 /**
<> 144:ef7eb2e8f9f7 1188 * @brief Stop the DMA Transfer.
Anna Bridge 180:96ed750bd169 1189 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 1190 * @retval HAL status
<> 144:ef7eb2e8f9f7 1191 */
<> 144:ef7eb2e8f9f7 1192 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1193 {
<> 144:ef7eb2e8f9f7 1194 /* The Lock is not implemented on this API to allow the user application
<> 144:ef7eb2e8f9f7 1195 to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
<> 156:95d6b41a828b 1196 HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
<> 156:95d6b41a828b 1197 indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
<> 156:95d6b41a828b 1198 interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
<> 156:95d6b41a828b 1199 the stream and the corresponding call back is executed. */
<> 156:95d6b41a828b 1200
<> 156:95d6b41a828b 1201 /* Stop UART DMA Tx request if ongoing */
<> 156:95d6b41a828b 1202 if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
<> 156:95d6b41a828b 1203 (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
<> 156:95d6b41a828b 1204 {
<> 156:95d6b41a828b 1205 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1206
<> 156:95d6b41a828b 1207 /* Abort the UART DMA Tx channel */
<> 156:95d6b41a828b 1208 if(huart->hdmatx != NULL)
<> 156:95d6b41a828b 1209 {
<> 156:95d6b41a828b 1210 HAL_DMA_Abort(huart->hdmatx);
<> 156:95d6b41a828b 1211 }
<> 156:95d6b41a828b 1212
<> 156:95d6b41a828b 1213 UART_EndTxTransfer(huart);
<> 156:95d6b41a828b 1214 }
<> 156:95d6b41a828b 1215
<> 156:95d6b41a828b 1216 /* Stop UART DMA Rx request if ongoing */
<> 156:95d6b41a828b 1217 if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
<> 156:95d6b41a828b 1218 (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
<> 156:95d6b41a828b 1219 {
<> 156:95d6b41a828b 1220 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1221
<> 156:95d6b41a828b 1222 /* Abort the UART DMA Rx channel */
<> 156:95d6b41a828b 1223 if(huart->hdmarx != NULL)
<> 156:95d6b41a828b 1224 {
<> 156:95d6b41a828b 1225 HAL_DMA_Abort(huart->hdmarx);
<> 156:95d6b41a828b 1226 }
<> 156:95d6b41a828b 1227
<> 156:95d6b41a828b 1228 UART_EndRxTransfer(huart);
<> 156:95d6b41a828b 1229 }
<> 156:95d6b41a828b 1230
<> 156:95d6b41a828b 1231 return HAL_OK;
<> 156:95d6b41a828b 1232 }
<> 156:95d6b41a828b 1233
<> 156:95d6b41a828b 1234 /**
<> 156:95d6b41a828b 1235 * @brief Abort ongoing transfers (blocking mode).
<> 156:95d6b41a828b 1236 * @param huart UART handle.
<> 156:95d6b41a828b 1237 * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1238 * This procedure performs following operations :
<> 156:95d6b41a828b 1239 * - Disable UART Interrupts (Tx and Rx)
<> 156:95d6b41a828b 1240 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1241 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1242 * - Set handle State to READY
<> 156:95d6b41a828b 1243 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
<> 156:95d6b41a828b 1244 * @retval HAL status
<> 156:95d6b41a828b 1245 */
<> 156:95d6b41a828b 1246 HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1247 {
<> 156:95d6b41a828b 1248 /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1249 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
<> 156:95d6b41a828b 1250 CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1251
<> 156:95d6b41a828b 1252 /* Disable the UART DMA Tx request if enabled */
<> 156:95d6b41a828b 1253 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
<> 156:95d6b41a828b 1254 {
<> 156:95d6b41a828b 1255 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1256
<> 156:95d6b41a828b 1257 /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
<> 156:95d6b41a828b 1258 if(huart->hdmatx != NULL)
<> 156:95d6b41a828b 1259 {
<> 156:95d6b41a828b 1260 /* Set the UART DMA Abort callback to Null.
<> 156:95d6b41a828b 1261 No call back execution at end of DMA abort procedure */
<> 156:95d6b41a828b 1262 huart->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1263
<> 156:95d6b41a828b 1264 HAL_DMA_Abort(huart->hdmatx);
<> 156:95d6b41a828b 1265 }
<> 156:95d6b41a828b 1266 }
<> 156:95d6b41a828b 1267
<> 156:95d6b41a828b 1268 /* Disable the UART DMA Rx request if enabled */
<> 156:95d6b41a828b 1269 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
<> 144:ef7eb2e8f9f7 1270 {
<> 156:95d6b41a828b 1271 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1272
<> 156:95d6b41a828b 1273 /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
<> 156:95d6b41a828b 1274 if(huart->hdmarx != NULL)
<> 156:95d6b41a828b 1275 {
<> 156:95d6b41a828b 1276 /* Set the UART DMA Abort callback to Null.
<> 156:95d6b41a828b 1277 No call back execution at end of DMA abort procedure */
<> 156:95d6b41a828b 1278 huart->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1279
<> 156:95d6b41a828b 1280 HAL_DMA_Abort(huart->hdmarx);
<> 156:95d6b41a828b 1281 }
<> 144:ef7eb2e8f9f7 1282 }
<> 156:95d6b41a828b 1283
<> 156:95d6b41a828b 1284 /* Reset Tx and Rx transfer counters */
<> 156:95d6b41a828b 1285 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 1286 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 1287
<> 156:95d6b41a828b 1288 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 1289 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
<> 156:95d6b41a828b 1290
<> 156:95d6b41a828b 1291 /* Restore huart->gState and huart->RxState to Ready */
<> 156:95d6b41a828b 1292 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1293 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1294
<> 156:95d6b41a828b 1295 /* Reset Handle ErrorCode to No Error */
<> 156:95d6b41a828b 1296 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 156:95d6b41a828b 1297
<> 156:95d6b41a828b 1298 return HAL_OK;
<> 156:95d6b41a828b 1299 }
<> 156:95d6b41a828b 1300
<> 156:95d6b41a828b 1301 /**
<> 156:95d6b41a828b 1302 * @brief Abort ongoing Transmit transfer (blocking mode).
<> 156:95d6b41a828b 1303 * @param huart UART handle.
<> 156:95d6b41a828b 1304 * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1305 * This procedure performs following operations :
<> 156:95d6b41a828b 1306 * - Disable UART Interrupts (Tx)
<> 156:95d6b41a828b 1307 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1308 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1309 * - Set handle State to READY
<> 156:95d6b41a828b 1310 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
<> 156:95d6b41a828b 1311 * @retval HAL status
<> 156:95d6b41a828b 1312 */
<> 156:95d6b41a828b 1313 HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1314 {
<> 156:95d6b41a828b 1315 /* Disable TXEIE and TCIE interrupts */
<> 156:95d6b41a828b 1316 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
<> 156:95d6b41a828b 1317
<> 156:95d6b41a828b 1318 /* Disable the UART DMA Tx request if enabled */
<> 156:95d6b41a828b 1319 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
<> 144:ef7eb2e8f9f7 1320 {
<> 156:95d6b41a828b 1321 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1322
<> 156:95d6b41a828b 1323 /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
<> 156:95d6b41a828b 1324 if(huart->hdmatx != NULL)
<> 156:95d6b41a828b 1325 {
<> 156:95d6b41a828b 1326 /* Set the UART DMA Abort callback to Null.
<> 156:95d6b41a828b 1327 No call back execution at end of DMA abort procedure */
<> 156:95d6b41a828b 1328 huart->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1329
<> 156:95d6b41a828b 1330 HAL_DMA_Abort(huart->hdmatx);
<> 156:95d6b41a828b 1331 }
<> 144:ef7eb2e8f9f7 1332 }
<> 144:ef7eb2e8f9f7 1333
<> 156:95d6b41a828b 1334 /* Reset Tx transfer counter */
<> 156:95d6b41a828b 1335 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 1336
<> 156:95d6b41a828b 1337 /* Restore huart->gState to Ready */
<> 144:ef7eb2e8f9f7 1338 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1339
<> 156:95d6b41a828b 1340 return HAL_OK;
<> 156:95d6b41a828b 1341 }
<> 156:95d6b41a828b 1342
<> 156:95d6b41a828b 1343 /**
<> 156:95d6b41a828b 1344 * @brief Abort ongoing Receive transfer (blocking mode).
<> 156:95d6b41a828b 1345 * @param huart UART handle.
<> 156:95d6b41a828b 1346 * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1347 * This procedure performs following operations :
<> 156:95d6b41a828b 1348 * - Disable UART Interrupts (Rx)
<> 156:95d6b41a828b 1349 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1350 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1351 * - Set handle State to READY
<> 156:95d6b41a828b 1352 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
<> 156:95d6b41a828b 1353 * @retval HAL status
<> 156:95d6b41a828b 1354 */
<> 156:95d6b41a828b 1355 HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1356 {
<> 156:95d6b41a828b 1357 /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1358 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
<> 156:95d6b41a828b 1359 CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1360
<> 156:95d6b41a828b 1361 /* Disable the UART DMA Rx request if enabled */
<> 156:95d6b41a828b 1362 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1363 {
<> 156:95d6b41a828b 1364 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1365
<> 156:95d6b41a828b 1366 /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
<> 156:95d6b41a828b 1367 if(huart->hdmarx != NULL)
<> 156:95d6b41a828b 1368 {
<> 156:95d6b41a828b 1369 /* Set the UART DMA Abort callback to Null.
<> 156:95d6b41a828b 1370 No call back execution at end of DMA abort procedure */
<> 156:95d6b41a828b 1371 huart->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1372
<> 156:95d6b41a828b 1373 HAL_DMA_Abort(huart->hdmarx);
<> 156:95d6b41a828b 1374 }
<> 156:95d6b41a828b 1375 }
<> 156:95d6b41a828b 1376
<> 156:95d6b41a828b 1377 /* Reset Rx transfer counter */
<> 156:95d6b41a828b 1378 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 1379
<> 156:95d6b41a828b 1380 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 1381 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
<> 156:95d6b41a828b 1382
<> 156:95d6b41a828b 1383 /* Restore huart->RxState to Ready */
<> 144:ef7eb2e8f9f7 1384 huart->RxState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 1385
<> 144:ef7eb2e8f9f7 1386 return HAL_OK;
<> 144:ef7eb2e8f9f7 1387 }
<> 144:ef7eb2e8f9f7 1388
<> 144:ef7eb2e8f9f7 1389 /**
<> 156:95d6b41a828b 1390 * @brief Abort ongoing transfers (Interrupt mode).
<> 156:95d6b41a828b 1391 * @param huart UART handle.
<> 156:95d6b41a828b 1392 * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1393 * This procedure performs following operations :
<> 156:95d6b41a828b 1394 * - Disable UART Interrupts (Tx and Rx)
<> 156:95d6b41a828b 1395 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1396 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1397 * - Set handle State to READY
<> 156:95d6b41a828b 1398 * - At abort completion, call user abort complete callback
<> 156:95d6b41a828b 1399 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
<> 156:95d6b41a828b 1400 * considered as completed only when user abort complete callback is executed (not when exiting function).
<> 156:95d6b41a828b 1401 * @retval HAL status
<> 156:95d6b41a828b 1402 */
<> 156:95d6b41a828b 1403 HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1404 {
<> 156:95d6b41a828b 1405 uint32_t abortcplt = 1U;
<> 156:95d6b41a828b 1406
<> 156:95d6b41a828b 1407 /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1408 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
<> 156:95d6b41a828b 1409 CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1410
<> 156:95d6b41a828b 1411 /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
<> 156:95d6b41a828b 1412 before any call to DMA Abort functions */
<> 156:95d6b41a828b 1413 /* DMA Tx Handle is valid */
<> 156:95d6b41a828b 1414 if(huart->hdmatx != NULL)
<> 156:95d6b41a828b 1415 {
<> 156:95d6b41a828b 1416 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
<> 156:95d6b41a828b 1417 Otherwise, set it to NULL */
<> 156:95d6b41a828b 1418 if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
<> 156:95d6b41a828b 1419 {
<> 156:95d6b41a828b 1420 huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
<> 156:95d6b41a828b 1421 }
<> 156:95d6b41a828b 1422 else
<> 156:95d6b41a828b 1423 {
<> 156:95d6b41a828b 1424 huart->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1425 }
<> 156:95d6b41a828b 1426 }
<> 156:95d6b41a828b 1427 /* DMA Rx Handle is valid */
<> 156:95d6b41a828b 1428 if(huart->hdmarx != NULL)
<> 156:95d6b41a828b 1429 {
<> 156:95d6b41a828b 1430 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
<> 156:95d6b41a828b 1431 Otherwise, set it to NULL */
<> 156:95d6b41a828b 1432 if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1433 {
<> 156:95d6b41a828b 1434 huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
<> 156:95d6b41a828b 1435 }
<> 156:95d6b41a828b 1436 else
<> 156:95d6b41a828b 1437 {
<> 156:95d6b41a828b 1438 huart->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1439 }
<> 156:95d6b41a828b 1440 }
<> 156:95d6b41a828b 1441
<> 156:95d6b41a828b 1442 /* Disable the UART DMA Tx request if enabled */
<> 156:95d6b41a828b 1443 if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
<> 156:95d6b41a828b 1444 {
<> 156:95d6b41a828b 1445 /* Disable DMA Tx at UART level */
<> 156:95d6b41a828b 1446 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1447
<> 156:95d6b41a828b 1448 /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
<> 156:95d6b41a828b 1449 if(huart->hdmatx != NULL)
<> 156:95d6b41a828b 1450 {
<> 156:95d6b41a828b 1451 /* UART Tx DMA Abort callback has already been initialised :
<> 156:95d6b41a828b 1452 will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1453
<> 156:95d6b41a828b 1454 /* Abort DMA TX */
<> 156:95d6b41a828b 1455 if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
<> 156:95d6b41a828b 1456 {
<> 156:95d6b41a828b 1457 huart->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1458 }
<> 156:95d6b41a828b 1459 else
<> 156:95d6b41a828b 1460 {
<> 156:95d6b41a828b 1461 abortcplt = 0U;
<> 156:95d6b41a828b 1462 }
<> 156:95d6b41a828b 1463 }
<> 156:95d6b41a828b 1464 }
<> 156:95d6b41a828b 1465
<> 156:95d6b41a828b 1466 /* Disable the UART DMA Rx request if enabled */
<> 156:95d6b41a828b 1467 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1468 {
<> 156:95d6b41a828b 1469 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1470
<> 156:95d6b41a828b 1471 /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
<> 156:95d6b41a828b 1472 if(huart->hdmarx != NULL)
<> 156:95d6b41a828b 1473 {
<> 156:95d6b41a828b 1474 /* UART Rx DMA Abort callback has already been initialised :
<> 156:95d6b41a828b 1475 will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1476
<> 156:95d6b41a828b 1477 /* Abort DMA RX */
<> 156:95d6b41a828b 1478 if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
<> 156:95d6b41a828b 1479 {
<> 156:95d6b41a828b 1480 huart->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1481 abortcplt = 1U;
<> 156:95d6b41a828b 1482 }
<> 156:95d6b41a828b 1483 else
<> 156:95d6b41a828b 1484 {
<> 156:95d6b41a828b 1485 abortcplt = 0U;
<> 156:95d6b41a828b 1486 }
<> 156:95d6b41a828b 1487 }
<> 156:95d6b41a828b 1488 }
<> 156:95d6b41a828b 1489
<> 156:95d6b41a828b 1490 /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
<> 156:95d6b41a828b 1491 if (abortcplt == 1U)
<> 156:95d6b41a828b 1492 {
<> 156:95d6b41a828b 1493 /* Reset Tx and Rx transfer counters */
<> 156:95d6b41a828b 1494 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 1495 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 1496
<> 156:95d6b41a828b 1497 /* Reset errorCode */
<> 156:95d6b41a828b 1498 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 156:95d6b41a828b 1499
<> 156:95d6b41a828b 1500 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 1501 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
<> 156:95d6b41a828b 1502
<> 156:95d6b41a828b 1503 /* Restore huart->gState and huart->RxState to Ready */
<> 156:95d6b41a828b 1504 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1505 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1506
<> 156:95d6b41a828b 1507 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 156:95d6b41a828b 1508 HAL_UART_AbortCpltCallback(huart);
<> 156:95d6b41a828b 1509 }
<> 156:95d6b41a828b 1510
<> 156:95d6b41a828b 1511 return HAL_OK;
<> 156:95d6b41a828b 1512 }
<> 156:95d6b41a828b 1513
<> 156:95d6b41a828b 1514 /**
<> 156:95d6b41a828b 1515 * @brief Abort ongoing Transmit transfer (Interrupt mode).
<> 156:95d6b41a828b 1516 * @param huart UART handle.
<> 156:95d6b41a828b 1517 * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1518 * This procedure performs following operations :
<> 156:95d6b41a828b 1519 * - Disable UART Interrupts (Tx)
<> 156:95d6b41a828b 1520 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1521 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1522 * - Set handle State to READY
<> 156:95d6b41a828b 1523 * - At abort completion, call user abort complete callback
<> 156:95d6b41a828b 1524 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
<> 156:95d6b41a828b 1525 * considered as completed only when user abort complete callback is executed (not when exiting function).
<> 156:95d6b41a828b 1526 * @retval HAL status
<> 156:95d6b41a828b 1527 */
<> 156:95d6b41a828b 1528 HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1529 {
<> 156:95d6b41a828b 1530 /* Disable TXEIE and TCIE interrupts */
<> 156:95d6b41a828b 1531 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
<> 156:95d6b41a828b 1532
<> 156:95d6b41a828b 1533 /* Disable the UART DMA Tx request if enabled */
<> 156:95d6b41a828b 1534 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
<> 156:95d6b41a828b 1535 {
<> 156:95d6b41a828b 1536 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<> 156:95d6b41a828b 1537
<> 156:95d6b41a828b 1538 /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
<> 156:95d6b41a828b 1539 if(huart->hdmatx != NULL)
<> 156:95d6b41a828b 1540 {
<> 156:95d6b41a828b 1541 /* Set the UART DMA Abort callback :
<> 156:95d6b41a828b 1542 will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1543 huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
<> 156:95d6b41a828b 1544
<> 156:95d6b41a828b 1545 /* Abort DMA TX */
<> 156:95d6b41a828b 1546 if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
<> 156:95d6b41a828b 1547 {
<> 156:95d6b41a828b 1548 /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
<> 156:95d6b41a828b 1549 huart->hdmatx->XferAbortCallback(huart->hdmatx);
<> 156:95d6b41a828b 1550 }
<> 156:95d6b41a828b 1551 }
<> 156:95d6b41a828b 1552 else
<> 156:95d6b41a828b 1553 {
<> 156:95d6b41a828b 1554 /* Reset Tx transfer counter */
<> 156:95d6b41a828b 1555 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 1556
<> 156:95d6b41a828b 1557 /* Restore huart->gState to Ready */
<> 156:95d6b41a828b 1558 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1559
<> 156:95d6b41a828b 1560 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 156:95d6b41a828b 1561 HAL_UART_AbortTransmitCpltCallback(huart);
<> 156:95d6b41a828b 1562 }
<> 156:95d6b41a828b 1563 }
<> 156:95d6b41a828b 1564 else
<> 156:95d6b41a828b 1565 {
<> 156:95d6b41a828b 1566 /* Reset Tx transfer counter */
<> 156:95d6b41a828b 1567 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 1568
<> 156:95d6b41a828b 1569 /* Restore huart->gState to Ready */
<> 156:95d6b41a828b 1570 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1571
<> 156:95d6b41a828b 1572 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 156:95d6b41a828b 1573 HAL_UART_AbortTransmitCpltCallback(huart);
<> 156:95d6b41a828b 1574 }
<> 156:95d6b41a828b 1575
<> 156:95d6b41a828b 1576 return HAL_OK;
<> 156:95d6b41a828b 1577 }
<> 156:95d6b41a828b 1578
<> 156:95d6b41a828b 1579 /**
<> 156:95d6b41a828b 1580 * @brief Abort ongoing Receive transfer (Interrupt mode).
<> 156:95d6b41a828b 1581 * @param huart UART handle.
<> 156:95d6b41a828b 1582 * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1583 * This procedure performs following operations :
<> 156:95d6b41a828b 1584 * - Disable UART Interrupts (Rx)
<> 156:95d6b41a828b 1585 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1586 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1587 * - Set handle State to READY
<> 156:95d6b41a828b 1588 * - At abort completion, call user abort complete callback
<> 156:95d6b41a828b 1589 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
<> 156:95d6b41a828b 1590 * considered as completed only when user abort complete callback is executed (not when exiting function).
<> 156:95d6b41a828b 1591 * @retval HAL status
<> 156:95d6b41a828b 1592 */
<> 156:95d6b41a828b 1593 HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1594 {
<> 156:95d6b41a828b 1595 /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 1596 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
<> 156:95d6b41a828b 1597 CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 1598
<> 156:95d6b41a828b 1599 /* Disable the UART DMA Rx request if enabled */
<> 156:95d6b41a828b 1600 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1601 {
<> 156:95d6b41a828b 1602 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1603
<> 156:95d6b41a828b 1604 /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
<> 156:95d6b41a828b 1605 if(huart->hdmarx != NULL)
<> 156:95d6b41a828b 1606 {
<> 156:95d6b41a828b 1607 /* Set the UART DMA Abort callback :
<> 156:95d6b41a828b 1608 will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1609 huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
<> 156:95d6b41a828b 1610
<> 156:95d6b41a828b 1611 /* Abort DMA RX */
<> 156:95d6b41a828b 1612 if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
<> 156:95d6b41a828b 1613 {
<> 156:95d6b41a828b 1614 /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
<> 156:95d6b41a828b 1615 huart->hdmarx->XferAbortCallback(huart->hdmarx);
<> 156:95d6b41a828b 1616 }
<> 156:95d6b41a828b 1617 }
<> 156:95d6b41a828b 1618 else
<> 156:95d6b41a828b 1619 {
<> 156:95d6b41a828b 1620 /* Reset Rx transfer counter */
<> 156:95d6b41a828b 1621 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 1622
<> 156:95d6b41a828b 1623 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 1624 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
<> 156:95d6b41a828b 1625
<> 156:95d6b41a828b 1626 /* Restore huart->RxState to Ready */
<> 156:95d6b41a828b 1627 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1628
<> 156:95d6b41a828b 1629 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 156:95d6b41a828b 1630 HAL_UART_AbortReceiveCpltCallback(huart);
<> 156:95d6b41a828b 1631 }
<> 156:95d6b41a828b 1632 }
<> 156:95d6b41a828b 1633 else
<> 156:95d6b41a828b 1634 {
<> 156:95d6b41a828b 1635 /* Reset Rx transfer counter */
<> 156:95d6b41a828b 1636 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 1637
<> 156:95d6b41a828b 1638 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 1639 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
<> 156:95d6b41a828b 1640
<> 156:95d6b41a828b 1641 /* Restore huart->RxState to Ready */
<> 156:95d6b41a828b 1642 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1643
<> 156:95d6b41a828b 1644 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 156:95d6b41a828b 1645 HAL_UART_AbortReceiveCpltCallback(huart);
<> 156:95d6b41a828b 1646 }
<> 156:95d6b41a828b 1647
<> 156:95d6b41a828b 1648 return HAL_OK;
<> 156:95d6b41a828b 1649 }
<> 156:95d6b41a828b 1650
<> 156:95d6b41a828b 1651 /**
<> 156:95d6b41a828b 1652 * @brief Handle UART interrupt request.
Anna Bridge 180:96ed750bd169 1653 * @param huart UART handle.
<> 156:95d6b41a828b 1654 * @retval None
<> 156:95d6b41a828b 1655 */
<> 156:95d6b41a828b 1656 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1657 {
<> 156:95d6b41a828b 1658 uint32_t isrflags = READ_REG(huart->Instance->ISR);
<> 156:95d6b41a828b 1659 uint32_t cr1its = READ_REG(huart->Instance->CR1);
<> 156:95d6b41a828b 1660 uint32_t cr3its;
<> 156:95d6b41a828b 1661 uint32_t errorflags;
<> 156:95d6b41a828b 1662
<> 156:95d6b41a828b 1663 /* If no error occurs */
<> 156:95d6b41a828b 1664 errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
<> 156:95d6b41a828b 1665 if (errorflags == RESET)
<> 156:95d6b41a828b 1666 {
<> 156:95d6b41a828b 1667 /* UART in mode Receiver ---------------------------------------------------*/
<> 156:95d6b41a828b 1668 if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<> 156:95d6b41a828b 1669 {
<> 156:95d6b41a828b 1670 UART_Receive_IT(huart);
<> 156:95d6b41a828b 1671 return;
<> 156:95d6b41a828b 1672 }
<> 156:95d6b41a828b 1673 }
<> 156:95d6b41a828b 1674
<> 156:95d6b41a828b 1675 /* If some errors occur */
<> 156:95d6b41a828b 1676 cr3its = READ_REG(huart->Instance->CR3);
<> 156:95d6b41a828b 1677 if( (errorflags != RESET)
<> 156:95d6b41a828b 1678 && ( ((cr3its & USART_CR3_EIE) != RESET)
<> 156:95d6b41a828b 1679 || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
<> 156:95d6b41a828b 1680 {
<> 156:95d6b41a828b 1681 /* UART parity error interrupt occurred -------------------------------------*/
<> 156:95d6b41a828b 1682 if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
<> 156:95d6b41a828b 1683 {
<> 156:95d6b41a828b 1684 __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
<> 156:95d6b41a828b 1685
<> 156:95d6b41a828b 1686 huart->ErrorCode |= HAL_UART_ERROR_PE;
<> 156:95d6b41a828b 1687 }
<> 156:95d6b41a828b 1688
<> 156:95d6b41a828b 1689 /* UART frame error interrupt occurred --------------------------------------*/
<> 156:95d6b41a828b 1690 if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<> 156:95d6b41a828b 1691 {
<> 156:95d6b41a828b 1692 __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
<> 156:95d6b41a828b 1693
<> 156:95d6b41a828b 1694 huart->ErrorCode |= HAL_UART_ERROR_FE;
<> 156:95d6b41a828b 1695 }
<> 156:95d6b41a828b 1696
<> 156:95d6b41a828b 1697 /* UART noise error interrupt occurred --------------------------------------*/
<> 156:95d6b41a828b 1698 if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<> 156:95d6b41a828b 1699 {
<> 156:95d6b41a828b 1700 __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
<> 156:95d6b41a828b 1701
<> 156:95d6b41a828b 1702 huart->ErrorCode |= HAL_UART_ERROR_NE;
<> 156:95d6b41a828b 1703 }
<> 156:95d6b41a828b 1704
<> 156:95d6b41a828b 1705 /* UART Over-Run interrupt occurred -----------------------------------------*/
<> 156:95d6b41a828b 1706 if(((isrflags & USART_ISR_ORE) != RESET) &&
<> 156:95d6b41a828b 1707 (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
<> 156:95d6b41a828b 1708 {
<> 156:95d6b41a828b 1709 __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
<> 156:95d6b41a828b 1710
<> 156:95d6b41a828b 1711 huart->ErrorCode |= HAL_UART_ERROR_ORE;
<> 156:95d6b41a828b 1712 }
<> 156:95d6b41a828b 1713
<> 156:95d6b41a828b 1714 /* Call UART Error Call back function if need be --------------------------*/
<> 156:95d6b41a828b 1715 if(huart->ErrorCode != HAL_UART_ERROR_NONE)
<> 156:95d6b41a828b 1716 {
<> 156:95d6b41a828b 1717 /* UART in mode Receiver ---------------------------------------------------*/
<> 156:95d6b41a828b 1718 if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<> 156:95d6b41a828b 1719 {
<> 156:95d6b41a828b 1720 UART_Receive_IT(huart);
<> 156:95d6b41a828b 1721 }
<> 156:95d6b41a828b 1722
<> 156:95d6b41a828b 1723 /* If Overrun error occurs, or if any error occurs in DMA mode reception,
<> 156:95d6b41a828b 1724 consider error as blocking */
<> 156:95d6b41a828b 1725 if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||
<> 156:95d6b41a828b 1726 (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
<> 156:95d6b41a828b 1727 {
<> 156:95d6b41a828b 1728 /* Blocking error : transfer is aborted
<> 156:95d6b41a828b 1729 Set the UART state ready to be able to start again the process,
<> 156:95d6b41a828b 1730 Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
<> 156:95d6b41a828b 1731 UART_EndRxTransfer(huart);
<> 156:95d6b41a828b 1732
<> 156:95d6b41a828b 1733 /* Disable the UART DMA Rx request if enabled */
<> 156:95d6b41a828b 1734 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
<> 156:95d6b41a828b 1735 {
<> 156:95d6b41a828b 1736 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 156:95d6b41a828b 1737
<> 156:95d6b41a828b 1738 /* Abort the UART DMA Rx channel */
<> 156:95d6b41a828b 1739 if(huart->hdmarx != NULL)
<> 156:95d6b41a828b 1740 {
<> 156:95d6b41a828b 1741 /* Set the UART DMA Abort callback :
<> 156:95d6b41a828b 1742 will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 1743 huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
<> 156:95d6b41a828b 1744
<> 156:95d6b41a828b 1745 /* Abort DMA RX */
<> 156:95d6b41a828b 1746 if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
<> 156:95d6b41a828b 1747 {
<> 156:95d6b41a828b 1748 /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
<> 156:95d6b41a828b 1749 huart->hdmarx->XferAbortCallback(huart->hdmarx);
<> 156:95d6b41a828b 1750 }
<> 156:95d6b41a828b 1751 }
<> 156:95d6b41a828b 1752 else
<> 156:95d6b41a828b 1753 {
<> 156:95d6b41a828b 1754 /* Call user error callback */
<> 156:95d6b41a828b 1755 HAL_UART_ErrorCallback(huart);
<> 156:95d6b41a828b 1756 }
<> 156:95d6b41a828b 1757 }
<> 156:95d6b41a828b 1758 else
<> 156:95d6b41a828b 1759 {
<> 156:95d6b41a828b 1760 /* Call user error callback */
<> 156:95d6b41a828b 1761 HAL_UART_ErrorCallback(huart);
<> 156:95d6b41a828b 1762 }
<> 156:95d6b41a828b 1763 }
<> 156:95d6b41a828b 1764 else
<> 156:95d6b41a828b 1765 {
<> 156:95d6b41a828b 1766 /* Non Blocking error : transfer could go on.
<> 156:95d6b41a828b 1767 Error is notified to user through user error callback */
<> 156:95d6b41a828b 1768 HAL_UART_ErrorCallback(huart);
<> 156:95d6b41a828b 1769 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 156:95d6b41a828b 1770 }
<> 156:95d6b41a828b 1771 }
<> 156:95d6b41a828b 1772 return;
<> 156:95d6b41a828b 1773
<> 156:95d6b41a828b 1774 } /* End if some error occurs */
<> 156:95d6b41a828b 1775
<> 156:95d6b41a828b 1776 #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
<> 156:95d6b41a828b 1777 /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
<> 156:95d6b41a828b 1778 if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET))
<> 156:95d6b41a828b 1779 {
<> 156:95d6b41a828b 1780 __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF);
<> 156:95d6b41a828b 1781 /* Set the UART state ready to be able to start again the process */
<> 156:95d6b41a828b 1782 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1783 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 1784 HAL_UARTEx_WakeupCallback(huart);
<> 156:95d6b41a828b 1785 return;
<> 156:95d6b41a828b 1786 }
<> 156:95d6b41a828b 1787 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
<> 156:95d6b41a828b 1788
<> 156:95d6b41a828b 1789 /* UART in mode Transmitter ------------------------------------------------*/
<> 156:95d6b41a828b 1790 if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
<> 156:95d6b41a828b 1791 {
<> 156:95d6b41a828b 1792 UART_Transmit_IT(huart);
<> 156:95d6b41a828b 1793 return;
<> 156:95d6b41a828b 1794 }
<> 156:95d6b41a828b 1795
<> 156:95d6b41a828b 1796 /* UART in mode Transmitter (transmission end) -----------------------------*/
<> 156:95d6b41a828b 1797 if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
<> 156:95d6b41a828b 1798 {
<> 156:95d6b41a828b 1799 UART_EndTransmit_IT(huart);
<> 156:95d6b41a828b 1800 return;
<> 156:95d6b41a828b 1801 }
<> 156:95d6b41a828b 1802
<> 156:95d6b41a828b 1803 }
<> 156:95d6b41a828b 1804
<> 156:95d6b41a828b 1805 /**
<> 144:ef7eb2e8f9f7 1806 * @brief Tx Transfer completed callback.
Anna Bridge 180:96ed750bd169 1807 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 1808 * @retval None
<> 144:ef7eb2e8f9f7 1809 */
<> 156:95d6b41a828b 1810 __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1811 {
<> 144:ef7eb2e8f9f7 1812 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1813 UNUSED(huart);
<> 144:ef7eb2e8f9f7 1814
<> 144:ef7eb2e8f9f7 1815 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1816 the HAL_UART_TxCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1817 */
<> 144:ef7eb2e8f9f7 1818 }
<> 144:ef7eb2e8f9f7 1819
<> 144:ef7eb2e8f9f7 1820 /**
<> 144:ef7eb2e8f9f7 1821 * @brief Tx Half Transfer completed callback.
Anna Bridge 180:96ed750bd169 1822 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 1823 * @retval None
<> 144:ef7eb2e8f9f7 1824 */
<> 156:95d6b41a828b 1825 __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1826 {
<> 144:ef7eb2e8f9f7 1827 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1828 UNUSED(huart);
<> 144:ef7eb2e8f9f7 1829
<> 144:ef7eb2e8f9f7 1830 /* NOTE: This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1831 the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1832 */
<> 144:ef7eb2e8f9f7 1833 }
<> 144:ef7eb2e8f9f7 1834
<> 144:ef7eb2e8f9f7 1835 /**
<> 144:ef7eb2e8f9f7 1836 * @brief Rx Transfer completed callback.
Anna Bridge 180:96ed750bd169 1837 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 1838 * @retval None
<> 144:ef7eb2e8f9f7 1839 */
<> 144:ef7eb2e8f9f7 1840 __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1841 {
<> 144:ef7eb2e8f9f7 1842 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1843 UNUSED(huart);
<> 144:ef7eb2e8f9f7 1844
<> 144:ef7eb2e8f9f7 1845 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1846 the HAL_UART_RxCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1847 */
<> 144:ef7eb2e8f9f7 1848 }
<> 144:ef7eb2e8f9f7 1849
<> 144:ef7eb2e8f9f7 1850 /**
<> 144:ef7eb2e8f9f7 1851 * @brief Rx Half Transfer completed callback.
Anna Bridge 180:96ed750bd169 1852 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 1853 * @retval None
<> 144:ef7eb2e8f9f7 1854 */
<> 144:ef7eb2e8f9f7 1855 __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1856 {
<> 144:ef7eb2e8f9f7 1857 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1858 UNUSED(huart);
<> 144:ef7eb2e8f9f7 1859
<> 144:ef7eb2e8f9f7 1860 /* NOTE: This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1861 the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1862 */
<> 144:ef7eb2e8f9f7 1863 }
<> 144:ef7eb2e8f9f7 1864
<> 144:ef7eb2e8f9f7 1865 /**
<> 144:ef7eb2e8f9f7 1866 * @brief UART error callback.
Anna Bridge 180:96ed750bd169 1867 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 1868 * @retval None
<> 144:ef7eb2e8f9f7 1869 */
<> 156:95d6b41a828b 1870 __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1871 {
<> 144:ef7eb2e8f9f7 1872 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1873 UNUSED(huart);
<> 144:ef7eb2e8f9f7 1874
<> 144:ef7eb2e8f9f7 1875 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1876 the HAL_UART_ErrorCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1877 */
<> 144:ef7eb2e8f9f7 1878 }
<> 144:ef7eb2e8f9f7 1879
<> 144:ef7eb2e8f9f7 1880 /**
<> 156:95d6b41a828b 1881 * @brief UART Abort Complete callback.
<> 156:95d6b41a828b 1882 * @param huart UART handle.
<> 156:95d6b41a828b 1883 * @retval None
<> 156:95d6b41a828b 1884 */
<> 156:95d6b41a828b 1885 __weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1886 {
<> 156:95d6b41a828b 1887 /* Prevent unused argument(s) compilation warning */
<> 156:95d6b41a828b 1888 UNUSED(huart);
<> 156:95d6b41a828b 1889
<> 156:95d6b41a828b 1890 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1891 the HAL_UART_AbortCpltCallback can be implemented in the user file.
<> 156:95d6b41a828b 1892 */
<> 156:95d6b41a828b 1893 }
<> 156:95d6b41a828b 1894
<> 156:95d6b41a828b 1895 /**
<> 156:95d6b41a828b 1896 * @brief UART Abort Complete callback.
<> 156:95d6b41a828b 1897 * @param huart UART handle.
<> 156:95d6b41a828b 1898 * @retval None
<> 156:95d6b41a828b 1899 */
<> 156:95d6b41a828b 1900 __weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1901 {
<> 156:95d6b41a828b 1902 /* Prevent unused argument(s) compilation warning */
<> 156:95d6b41a828b 1903 UNUSED(huart);
<> 156:95d6b41a828b 1904
<> 156:95d6b41a828b 1905 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1906 the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
<> 156:95d6b41a828b 1907 */
<> 156:95d6b41a828b 1908 }
<> 156:95d6b41a828b 1909
<> 156:95d6b41a828b 1910 /**
<> 156:95d6b41a828b 1911 * @brief UART Abort Receive Complete callback.
<> 156:95d6b41a828b 1912 * @param huart UART handle.
<> 156:95d6b41a828b 1913 * @retval None
<> 156:95d6b41a828b 1914 */
<> 156:95d6b41a828b 1915 __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 1916 {
<> 156:95d6b41a828b 1917 /* Prevent unused argument(s) compilation warning */
<> 156:95d6b41a828b 1918 UNUSED(huart);
<> 156:95d6b41a828b 1919
<> 156:95d6b41a828b 1920 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 1921 the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
<> 156:95d6b41a828b 1922 */
<> 156:95d6b41a828b 1923 }
<> 156:95d6b41a828b 1924
<> 156:95d6b41a828b 1925 /**
<> 144:ef7eb2e8f9f7 1926 * @}
<> 144:ef7eb2e8f9f7 1927 */
<> 144:ef7eb2e8f9f7 1928
<> 144:ef7eb2e8f9f7 1929 /** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 1930 * @brief UART control functions
<> 144:ef7eb2e8f9f7 1931 *
<> 144:ef7eb2e8f9f7 1932 @verbatim
<> 144:ef7eb2e8f9f7 1933 ===============================================================================
<> 144:ef7eb2e8f9f7 1934 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1935 ===============================================================================
<> 144:ef7eb2e8f9f7 1936 [..]
<> 144:ef7eb2e8f9f7 1937 This subsection provides a set of functions allowing to control the UART.
<> 144:ef7eb2e8f9f7 1938 (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
<> 144:ef7eb2e8f9f7 1939 (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
<> 144:ef7eb2e8f9f7 1940 (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
<> 144:ef7eb2e8f9f7 1941 (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
<> 144:ef7eb2e8f9f7 1942 (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
<> 144:ef7eb2e8f9f7 1943 @endverbatim
<> 144:ef7eb2e8f9f7 1944 * @{
<> 144:ef7eb2e8f9f7 1945 */
<> 144:ef7eb2e8f9f7 1946
<> 144:ef7eb2e8f9f7 1947 /**
<> 144:ef7eb2e8f9f7 1948 * @brief Enable UART in mute mode (does not mean UART enters mute mode;
<> 144:ef7eb2e8f9f7 1949 * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
Anna Bridge 180:96ed750bd169 1950 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 1951 * @retval HAL status
<> 144:ef7eb2e8f9f7 1952 */
<> 144:ef7eb2e8f9f7 1953 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1954 {
<> 144:ef7eb2e8f9f7 1955 /* Process Locked */
<> 144:ef7eb2e8f9f7 1956 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 1957
<> 144:ef7eb2e8f9f7 1958 huart->gState = HAL_UART_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1959
<> 144:ef7eb2e8f9f7 1960 /* Enable USART mute mode by setting the MME bit in the CR1 register */
<> 156:95d6b41a828b 1961 SET_BIT(huart->Instance->CR1, USART_CR1_MME);
<> 144:ef7eb2e8f9f7 1962
<> 144:ef7eb2e8f9f7 1963 huart->gState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 1964
<> 144:ef7eb2e8f9f7 1965 return (UART_CheckIdleState(huart));
<> 144:ef7eb2e8f9f7 1966 }
<> 144:ef7eb2e8f9f7 1967
<> 144:ef7eb2e8f9f7 1968 /**
<> 156:95d6b41a828b 1969 * @brief Disable UART mute mode (does not mean the UART actually exits mute mode
<> 156:95d6b41a828b 1970 * as it may not have been in mute mode at this very moment).
Anna Bridge 180:96ed750bd169 1971 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 1972 * @retval HAL status
<> 144:ef7eb2e8f9f7 1973 */
<> 144:ef7eb2e8f9f7 1974 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1975 {
<> 144:ef7eb2e8f9f7 1976 /* Process Locked */
<> 144:ef7eb2e8f9f7 1977 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 1978
<> 144:ef7eb2e8f9f7 1979 huart->gState = HAL_UART_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1980
<> 144:ef7eb2e8f9f7 1981 /* Disable USART mute mode by clearing the MME bit in the CR1 register */
<> 156:95d6b41a828b 1982 CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
<> 144:ef7eb2e8f9f7 1983
<> 144:ef7eb2e8f9f7 1984 huart->gState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 1985
<> 144:ef7eb2e8f9f7 1986 return (UART_CheckIdleState(huart));
<> 144:ef7eb2e8f9f7 1987 }
<> 144:ef7eb2e8f9f7 1988
<> 144:ef7eb2e8f9f7 1989 /**
<> 144:ef7eb2e8f9f7 1990 * @brief Enter UART mute mode (means UART actually enters mute mode).
<> 144:ef7eb2e8f9f7 1991 * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
Anna Bridge 180:96ed750bd169 1992 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 1993 * @retval None
<> 144:ef7eb2e8f9f7 1994 */
<> 144:ef7eb2e8f9f7 1995 void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 1996 {
<> 144:ef7eb2e8f9f7 1997 __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
<> 144:ef7eb2e8f9f7 1998 }
<> 144:ef7eb2e8f9f7 1999
<> 144:ef7eb2e8f9f7 2000 /**
<> 144:ef7eb2e8f9f7 2001 * @brief Enable the UART transmitter and disable the UART receiver.
Anna Bridge 180:96ed750bd169 2002 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 2003 * @retval HAL status
<> 144:ef7eb2e8f9f7 2004 */
<> 144:ef7eb2e8f9f7 2005 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2006 {
<> 144:ef7eb2e8f9f7 2007 /* Process Locked */
<> 144:ef7eb2e8f9f7 2008 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 2009 huart->gState = HAL_UART_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2010
<> 144:ef7eb2e8f9f7 2011 /* Clear TE and RE bits */
<> 144:ef7eb2e8f9f7 2012 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
<> 144:ef7eb2e8f9f7 2013 /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
<> 144:ef7eb2e8f9f7 2014 SET_BIT(huart->Instance->CR1, USART_CR1_TE);
<> 144:ef7eb2e8f9f7 2015
<> 144:ef7eb2e8f9f7 2016 huart->gState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 2017
<> 144:ef7eb2e8f9f7 2018 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2019 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 2020
<> 144:ef7eb2e8f9f7 2021 return HAL_OK;
<> 144:ef7eb2e8f9f7 2022 }
<> 144:ef7eb2e8f9f7 2023
<> 144:ef7eb2e8f9f7 2024 /**
<> 144:ef7eb2e8f9f7 2025 * @brief Enable the UART receiver and disable the UART transmitter.
Anna Bridge 180:96ed750bd169 2026 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 2027 * @retval HAL status.
<> 144:ef7eb2e8f9f7 2028 */
<> 144:ef7eb2e8f9f7 2029 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2030 {
<> 144:ef7eb2e8f9f7 2031 /* Process Locked */
<> 144:ef7eb2e8f9f7 2032 __HAL_LOCK(huart);
<> 144:ef7eb2e8f9f7 2033 huart->gState = HAL_UART_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2034
<> 144:ef7eb2e8f9f7 2035 /* Clear TE and RE bits */
<> 144:ef7eb2e8f9f7 2036 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
<> 144:ef7eb2e8f9f7 2037 /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
<> 144:ef7eb2e8f9f7 2038 SET_BIT(huart->Instance->CR1, USART_CR1_RE);
<> 144:ef7eb2e8f9f7 2039
<> 144:ef7eb2e8f9f7 2040 huart->gState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 2041 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2042 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 2043
<> 144:ef7eb2e8f9f7 2044 return HAL_OK;
<> 144:ef7eb2e8f9f7 2045 }
<> 144:ef7eb2e8f9f7 2046
<> 144:ef7eb2e8f9f7 2047 /**
<> 144:ef7eb2e8f9f7 2048 * @}
<> 144:ef7eb2e8f9f7 2049 */
<> 144:ef7eb2e8f9f7 2050
<> 144:ef7eb2e8f9f7 2051 /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 2052 * @brief UART Peripheral State functions
<> 144:ef7eb2e8f9f7 2053 *
<> 144:ef7eb2e8f9f7 2054 @verbatim
<> 144:ef7eb2e8f9f7 2055 ==============================================================================
<> 144:ef7eb2e8f9f7 2056 ##### Peripheral State and Error functions #####
<> 144:ef7eb2e8f9f7 2057 ==============================================================================
<> 144:ef7eb2e8f9f7 2058 [..]
<> 144:ef7eb2e8f9f7 2059 This subsection provides functions allowing to :
<> 144:ef7eb2e8f9f7 2060 (+) Return the UART handle state.
<> 144:ef7eb2e8f9f7 2061 (+) Return the UART handle error code
<> 144:ef7eb2e8f9f7 2062
<> 144:ef7eb2e8f9f7 2063 @endverbatim
<> 144:ef7eb2e8f9f7 2064 * @{
<> 144:ef7eb2e8f9f7 2065 */
<> 144:ef7eb2e8f9f7 2066
<> 144:ef7eb2e8f9f7 2067 /**
<> 144:ef7eb2e8f9f7 2068 * @brief Return the UART handle state.
<> 144:ef7eb2e8f9f7 2069 * @param huart Pointer to a UART_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2070 * the configuration information for the specified UART.
<> 144:ef7eb2e8f9f7 2071 * @retval HAL state
<> 144:ef7eb2e8f9f7 2072 */
<> 144:ef7eb2e8f9f7 2073 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2074 {
<> 156:95d6b41a828b 2075 uint32_t temp1= 0x00U, temp2 = 0x00U;
<> 144:ef7eb2e8f9f7 2076 temp1 = huart->gState;
<> 144:ef7eb2e8f9f7 2077 temp2 = huart->RxState;
<> 156:95d6b41a828b 2078
<> 144:ef7eb2e8f9f7 2079 return (HAL_UART_StateTypeDef)(temp1 | temp2);
<> 144:ef7eb2e8f9f7 2080 }
<> 144:ef7eb2e8f9f7 2081
<> 144:ef7eb2e8f9f7 2082 /**
<> 144:ef7eb2e8f9f7 2083 * @brief Return the UART handle error code.
<> 144:ef7eb2e8f9f7 2084 * @param huart Pointer to a UART_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2085 * the configuration information for the specified UART.
<> 144:ef7eb2e8f9f7 2086 * @retval UART Error Code
<> 144:ef7eb2e8f9f7 2087 */
<> 144:ef7eb2e8f9f7 2088 uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2089 {
<> 144:ef7eb2e8f9f7 2090 return huart->ErrorCode;
<> 144:ef7eb2e8f9f7 2091 }
<> 144:ef7eb2e8f9f7 2092 /**
<> 144:ef7eb2e8f9f7 2093 * @}
<> 144:ef7eb2e8f9f7 2094 */
<> 144:ef7eb2e8f9f7 2095
<> 144:ef7eb2e8f9f7 2096 /**
<> 144:ef7eb2e8f9f7 2097 * @}
<> 144:ef7eb2e8f9f7 2098 */
<> 144:ef7eb2e8f9f7 2099
<> 144:ef7eb2e8f9f7 2100 /** @defgroup UART_Private_Functions UART Private Functions
<> 144:ef7eb2e8f9f7 2101 * @{
<> 144:ef7eb2e8f9f7 2102 */
<> 144:ef7eb2e8f9f7 2103
<> 144:ef7eb2e8f9f7 2104 /**
<> 144:ef7eb2e8f9f7 2105 * @brief Configure the UART peripheral.
Anna Bridge 180:96ed750bd169 2106 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 2107 * @retval HAL status
<> 144:ef7eb2e8f9f7 2108 */
<> 144:ef7eb2e8f9f7 2109 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2110 {
<> 156:95d6b41a828b 2111 uint32_t tmpreg = 0x00000000U;
<> 144:ef7eb2e8f9f7 2112 UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
<> 156:95d6b41a828b 2113 uint16_t brrtemp = 0x0000U;
<> 156:95d6b41a828b 2114 uint16_t usartdiv = 0x0000U;
<> 144:ef7eb2e8f9f7 2115 HAL_StatusTypeDef ret = HAL_OK;
<> 144:ef7eb2e8f9f7 2116
<> 144:ef7eb2e8f9f7 2117 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2118 assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2119 assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
<> 144:ef7eb2e8f9f7 2120 assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
<> 144:ef7eb2e8f9f7 2121 assert_param(IS_UART_PARITY(huart->Init.Parity));
<> 144:ef7eb2e8f9f7 2122 assert_param(IS_UART_MODE(huart->Init.Mode));
<> 144:ef7eb2e8f9f7 2123 assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
<> 144:ef7eb2e8f9f7 2124 assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
<> 144:ef7eb2e8f9f7 2125 assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
<> 144:ef7eb2e8f9f7 2126
<> 144:ef7eb2e8f9f7 2127
<> 144:ef7eb2e8f9f7 2128 /*-------------------------- USART CR1 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 2129 /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
<> 144:ef7eb2e8f9f7 2130 * the UART Word Length, Parity, Mode and oversampling:
<> 144:ef7eb2e8f9f7 2131 * set the M bits according to huart->Init.WordLength value
<> 144:ef7eb2e8f9f7 2132 * set PCE and PS bits according to huart->Init.Parity value
<> 144:ef7eb2e8f9f7 2133 * set TE and RE bits according to huart->Init.Mode value
<> 144:ef7eb2e8f9f7 2134 * set OVER8 bit according to huart->Init.OverSampling value */
<> 144:ef7eb2e8f9f7 2135 tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
<> 144:ef7eb2e8f9f7 2136 MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
<> 144:ef7eb2e8f9f7 2137
<> 144:ef7eb2e8f9f7 2138 /*-------------------------- USART CR2 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 2139 /* Configure the UART Stop Bits: Set STOP[13:12] bits according
<> 144:ef7eb2e8f9f7 2140 * to huart->Init.StopBits value */
<> 144:ef7eb2e8f9f7 2141 MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
<> 144:ef7eb2e8f9f7 2142
<> 144:ef7eb2e8f9f7 2143 /*-------------------------- USART CR3 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 2144 /* Configure
<> 144:ef7eb2e8f9f7 2145 * - UART HardWare Flow Control: set CTSE and RTSE bits according
<> 144:ef7eb2e8f9f7 2146 * to huart->Init.HwFlowCtl value
<> 144:ef7eb2e8f9f7 2147 * - one-bit sampling method versus three samples' majority rule according
<> 144:ef7eb2e8f9f7 2148 * to huart->Init.OneBitSampling */
<> 144:ef7eb2e8f9f7 2149 tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;
<> 144:ef7eb2e8f9f7 2150 MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
<> 144:ef7eb2e8f9f7 2151
<> 144:ef7eb2e8f9f7 2152 /*-------------------------- USART BRR Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 2153 UART_GETCLOCKSOURCE(huart, clocksource);
<> 144:ef7eb2e8f9f7 2154
<> 144:ef7eb2e8f9f7 2155 /* Check UART Over Sampling to set Baud Rate Register */
<> 144:ef7eb2e8f9f7 2156 if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
<> 144:ef7eb2e8f9f7 2157 {
<> 144:ef7eb2e8f9f7 2158 switch (clocksource)
<> 144:ef7eb2e8f9f7 2159 {
<> 144:ef7eb2e8f9f7 2160 case UART_CLOCKSOURCE_PCLK1:
<> 144:ef7eb2e8f9f7 2161 usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2162 break;
<> 144:ef7eb2e8f9f7 2163 case UART_CLOCKSOURCE_HSI:
<> 144:ef7eb2e8f9f7 2164 usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2165 break;
<> 144:ef7eb2e8f9f7 2166 case UART_CLOCKSOURCE_SYSCLK:
<> 144:ef7eb2e8f9f7 2167 usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2168 break;
<> 144:ef7eb2e8f9f7 2169 case UART_CLOCKSOURCE_LSE:
<> 144:ef7eb2e8f9f7 2170 usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2171 break;
<> 144:ef7eb2e8f9f7 2172 case UART_CLOCKSOURCE_UNDEFINED:
<> 144:ef7eb2e8f9f7 2173 default:
<> 144:ef7eb2e8f9f7 2174 ret = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2175 break;
<> 144:ef7eb2e8f9f7 2176 }
<> 144:ef7eb2e8f9f7 2177
<> 156:95d6b41a828b 2178 brrtemp = usartdiv & 0xFFF0U;
<> 156:95d6b41a828b 2179 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
<> 144:ef7eb2e8f9f7 2180 huart->Instance->BRR = brrtemp;
<> 144:ef7eb2e8f9f7 2181 }
<> 144:ef7eb2e8f9f7 2182 else
<> 144:ef7eb2e8f9f7 2183 {
<> 144:ef7eb2e8f9f7 2184 switch (clocksource)
<> 144:ef7eb2e8f9f7 2185 {
<> 144:ef7eb2e8f9f7 2186 case UART_CLOCKSOURCE_PCLK1:
<> 144:ef7eb2e8f9f7 2187 huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2188 break;
<> 144:ef7eb2e8f9f7 2189 case UART_CLOCKSOURCE_HSI:
<> 156:95d6b41a828b 2190 huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2191 break;
<> 144:ef7eb2e8f9f7 2192 case UART_CLOCKSOURCE_SYSCLK:
<> 144:ef7eb2e8f9f7 2193 huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2194 break;
<> 144:ef7eb2e8f9f7 2195 case UART_CLOCKSOURCE_LSE:
<> 156:95d6b41a828b 2196 huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
<> 144:ef7eb2e8f9f7 2197 break;
<> 144:ef7eb2e8f9f7 2198 case UART_CLOCKSOURCE_UNDEFINED:
<> 144:ef7eb2e8f9f7 2199 default:
<> 144:ef7eb2e8f9f7 2200 ret = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2201 break;
<> 144:ef7eb2e8f9f7 2202 }
<> 144:ef7eb2e8f9f7 2203 }
<> 144:ef7eb2e8f9f7 2204
<> 144:ef7eb2e8f9f7 2205 return ret;
<> 144:ef7eb2e8f9f7 2206
<> 144:ef7eb2e8f9f7 2207 }
<> 144:ef7eb2e8f9f7 2208
<> 144:ef7eb2e8f9f7 2209 /**
<> 144:ef7eb2e8f9f7 2210 * @brief Configure the UART peripheral advanced features.
Anna Bridge 180:96ed750bd169 2211 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 2212 * @retval None
<> 144:ef7eb2e8f9f7 2213 */
<> 144:ef7eb2e8f9f7 2214 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2215 {
<> 144:ef7eb2e8f9f7 2216 /* Check whether the set of advanced features to configure is properly set */
<> 144:ef7eb2e8f9f7 2217 assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
<> 144:ef7eb2e8f9f7 2218
<> 144:ef7eb2e8f9f7 2219 /* if required, configure TX pin active level inversion */
<> 144:ef7eb2e8f9f7 2220 if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
<> 144:ef7eb2e8f9f7 2221 {
<> 144:ef7eb2e8f9f7 2222 assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
<> 144:ef7eb2e8f9f7 2223 MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
<> 144:ef7eb2e8f9f7 2224 }
<> 144:ef7eb2e8f9f7 2225
<> 144:ef7eb2e8f9f7 2226 /* if required, configure RX pin active level inversion */
<> 144:ef7eb2e8f9f7 2227 if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
<> 144:ef7eb2e8f9f7 2228 {
<> 144:ef7eb2e8f9f7 2229 assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
<> 144:ef7eb2e8f9f7 2230 MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
<> 144:ef7eb2e8f9f7 2231 }
<> 144:ef7eb2e8f9f7 2232
<> 144:ef7eb2e8f9f7 2233 /* if required, configure data inversion */
<> 144:ef7eb2e8f9f7 2234 if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
<> 144:ef7eb2e8f9f7 2235 {
<> 144:ef7eb2e8f9f7 2236 assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
<> 144:ef7eb2e8f9f7 2237 MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
<> 144:ef7eb2e8f9f7 2238 }
<> 144:ef7eb2e8f9f7 2239
<> 144:ef7eb2e8f9f7 2240 /* if required, configure RX/TX pins swap */
<> 144:ef7eb2e8f9f7 2241 if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
<> 144:ef7eb2e8f9f7 2242 {
<> 144:ef7eb2e8f9f7 2243 assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
<> 144:ef7eb2e8f9f7 2244 MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
<> 144:ef7eb2e8f9f7 2245 }
<> 144:ef7eb2e8f9f7 2246
<> 144:ef7eb2e8f9f7 2247 /* if required, configure RX overrun detection disabling */
<> 144:ef7eb2e8f9f7 2248 if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
<> 144:ef7eb2e8f9f7 2249 {
<> 144:ef7eb2e8f9f7 2250 assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
<> 144:ef7eb2e8f9f7 2251 MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
<> 144:ef7eb2e8f9f7 2252 }
<> 144:ef7eb2e8f9f7 2253
<> 144:ef7eb2e8f9f7 2254 /* if required, configure DMA disabling on reception error */
<> 144:ef7eb2e8f9f7 2255 if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
<> 144:ef7eb2e8f9f7 2256 {
<> 144:ef7eb2e8f9f7 2257 assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
<> 144:ef7eb2e8f9f7 2258 MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
<> 144:ef7eb2e8f9f7 2259 }
<> 144:ef7eb2e8f9f7 2260
<> 144:ef7eb2e8f9f7 2261 /* if required, configure auto Baud rate detection scheme */
<> 144:ef7eb2e8f9f7 2262 if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
<> 144:ef7eb2e8f9f7 2263 {
<> 144:ef7eb2e8f9f7 2264 assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
<> 144:ef7eb2e8f9f7 2265 assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
<> 144:ef7eb2e8f9f7 2266 MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
<> 144:ef7eb2e8f9f7 2267 /* set auto Baudrate detection parameters if detection is enabled */
<> 144:ef7eb2e8f9f7 2268 if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
<> 144:ef7eb2e8f9f7 2269 {
<> 144:ef7eb2e8f9f7 2270 assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
<> 144:ef7eb2e8f9f7 2271 MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
<> 144:ef7eb2e8f9f7 2272 }
<> 144:ef7eb2e8f9f7 2273 }
<> 144:ef7eb2e8f9f7 2274
<> 144:ef7eb2e8f9f7 2275 /* if required, configure MSB first on communication line */
<> 144:ef7eb2e8f9f7 2276 if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
<> 144:ef7eb2e8f9f7 2277 {
<> 144:ef7eb2e8f9f7 2278 assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
<> 144:ef7eb2e8f9f7 2279 MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
<> 144:ef7eb2e8f9f7 2280 }
<> 144:ef7eb2e8f9f7 2281 }
<> 144:ef7eb2e8f9f7 2282
<> 144:ef7eb2e8f9f7 2283 /**
<> 144:ef7eb2e8f9f7 2284 * @brief Check the UART Idle State.
<> 156:95d6b41a828b 2285 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 2286 * @retval HAL status
<> 144:ef7eb2e8f9f7 2287 */
<> 144:ef7eb2e8f9f7 2288 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2289 {
<> 156:95d6b41a828b 2290 #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
<> 156:95d6b41a828b 2291 uint32_t tickstart = 0U;
<> 156:95d6b41a828b 2292 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
<> 156:95d6b41a828b 2293
<> 144:ef7eb2e8f9f7 2294 /* Initialize the UART ErrorCode */
<> 144:ef7eb2e8f9f7 2295 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 144:ef7eb2e8f9f7 2296
<> 156:95d6b41a828b 2297 #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
<> 156:95d6b41a828b 2298 /* Init tickstart for timeout managment*/
<> 156:95d6b41a828b 2299 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 2300
<> 144:ef7eb2e8f9f7 2301 /* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices).
<> 144:ef7eb2e8f9f7 2302 Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature.
<> 144:ef7eb2e8f9f7 2303 */
<> 144:ef7eb2e8f9f7 2304 if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance))
<> 144:ef7eb2e8f9f7 2305 {
<> 144:ef7eb2e8f9f7 2306 /* Check if the Transmitter is enabled */
<> 144:ef7eb2e8f9f7 2307 if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
<> 144:ef7eb2e8f9f7 2308 {
<> 144:ef7eb2e8f9f7 2309 /* Wait until TEACK flag is set */
<> 156:95d6b41a828b 2310 if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 2311 {
<> 144:ef7eb2e8f9f7 2312 /* Timeout occurred */
<> 144:ef7eb2e8f9f7 2313 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2314 }
<> 144:ef7eb2e8f9f7 2315 }
<> 144:ef7eb2e8f9f7 2316
<> 144:ef7eb2e8f9f7 2317 /* Check if the Receiver is enabled */
<> 144:ef7eb2e8f9f7 2318 if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
<> 144:ef7eb2e8f9f7 2319 {
<> 144:ef7eb2e8f9f7 2320 /* Wait until REACK flag is set */
<> 156:95d6b41a828b 2321 if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
<> 144:ef7eb2e8f9f7 2322 {
<> 144:ef7eb2e8f9f7 2323 /* Timeout occurred */
<> 144:ef7eb2e8f9f7 2324 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2325 }
<> 144:ef7eb2e8f9f7 2326 }
<> 144:ef7eb2e8f9f7 2327 }
<> 144:ef7eb2e8f9f7 2328 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 2329
<> 144:ef7eb2e8f9f7 2330 /* Initialize the UART State */
<> 156:95d6b41a828b 2331 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2332 huart->RxState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 2333
<> 144:ef7eb2e8f9f7 2334 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2335 __HAL_UNLOCK(huart);
<> 144:ef7eb2e8f9f7 2336
<> 144:ef7eb2e8f9f7 2337 return HAL_OK;
<> 144:ef7eb2e8f9f7 2338 }
<> 144:ef7eb2e8f9f7 2339
<> 144:ef7eb2e8f9f7 2340 /**
<> 144:ef7eb2e8f9f7 2341 * @brief Handle UART Communication Timeout.
<> 156:95d6b41a828b 2342 * @param huart UART handle.
<> 156:95d6b41a828b 2343 * @param Flag Specifies the UART flag to check
<> 156:95d6b41a828b 2344 * @param Status Flag status (SET or RESET)
<> 156:95d6b41a828b 2345 * @param Tickstart Tick start value
<> 156:95d6b41a828b 2346 * @param Timeout Timeout duration
<> 144:ef7eb2e8f9f7 2347 * @retval HAL status
<> 144:ef7eb2e8f9f7 2348 */
<> 156:95d6b41a828b 2349 HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 2350 {
<> 144:ef7eb2e8f9f7 2351 /* Wait until flag is set */
<> 156:95d6b41a828b 2352 while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
<> 144:ef7eb2e8f9f7 2353 {
<> 156:95d6b41a828b 2354 /* Check for the Timeout */
<> 156:95d6b41a828b 2355 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 2356 {
<> 156:95d6b41a828b 2357 if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 2358 {
<> 156:95d6b41a828b 2359 /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
<> 156:95d6b41a828b 2360 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
<> 156:95d6b41a828b 2361 CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 2362
<> 156:95d6b41a828b 2363 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2364 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2365
<> 156:95d6b41a828b 2366 /* Process Unlocked */
<> 156:95d6b41a828b 2367 __HAL_UNLOCK(huart);
<> 156:95d6b41a828b 2368 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2369 }
<> 144:ef7eb2e8f9f7 2370 }
<> 144:ef7eb2e8f9f7 2371 }
<> 144:ef7eb2e8f9f7 2372 return HAL_OK;
<> 144:ef7eb2e8f9f7 2373 }
<> 144:ef7eb2e8f9f7 2374
<> 156:95d6b41a828b 2375
<> 156:95d6b41a828b 2376 /**
<> 156:95d6b41a828b 2377 * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
<> 156:95d6b41a828b 2378 * @param huart UART handle.
<> 156:95d6b41a828b 2379 * @retval None
<> 156:95d6b41a828b 2380 */
<> 156:95d6b41a828b 2381 static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 2382 {
<> 156:95d6b41a828b 2383 /* Disable TXEIE and TCIE interrupts */
<> 156:95d6b41a828b 2384 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
<> 156:95d6b41a828b 2385
<> 156:95d6b41a828b 2386 /* At end of Tx process, restore huart->gState to Ready */
<> 156:95d6b41a828b 2387 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2388 }
<> 156:95d6b41a828b 2389
<> 156:95d6b41a828b 2390
<> 156:95d6b41a828b 2391 /**
<> 156:95d6b41a828b 2392 * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
<> 156:95d6b41a828b 2393 * @param huart UART handle.
<> 156:95d6b41a828b 2394 * @retval None
<> 156:95d6b41a828b 2395 */
<> 156:95d6b41a828b 2396 static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
<> 156:95d6b41a828b 2397 {
<> 156:95d6b41a828b 2398 /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 2399 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
<> 156:95d6b41a828b 2400 CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 156:95d6b41a828b 2401
<> 156:95d6b41a828b 2402 /* At end of Rx process, restore huart->RxState to Ready */
<> 156:95d6b41a828b 2403 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2404 }
<> 156:95d6b41a828b 2405
<> 156:95d6b41a828b 2406
<> 144:ef7eb2e8f9f7 2407 /**
<> 144:ef7eb2e8f9f7 2408 * @brief DMA UART transmit process complete callback.
<> 156:95d6b41a828b 2409 * @param hdma DMA handle.
<> 144:ef7eb2e8f9f7 2410 * @retval None
<> 144:ef7eb2e8f9f7 2411 */
<> 144:ef7eb2e8f9f7 2412 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2413 {
<> 156:95d6b41a828b 2414 UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
<> 144:ef7eb2e8f9f7 2415
<> 144:ef7eb2e8f9f7 2416 /* DMA Normal mode */
<> 144:ef7eb2e8f9f7 2417 if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
<> 156:95d6b41a828b 2418 {
<> 144:ef7eb2e8f9f7 2419 huart->TxXferCount = 0;
<> 156:95d6b41a828b 2420
<> 144:ef7eb2e8f9f7 2421 /* Disable the DMA transfer for transmit request by resetting the DMAT bit
<> 156:95d6b41a828b 2422 in the UART CR3 register */
<> 156:95d6b41a828b 2423 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 2424
<> 144:ef7eb2e8f9f7 2425 /* Enable the UART Transmit Complete Interrupt */
<> 156:95d6b41a828b 2426 SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 2427 }
<> 144:ef7eb2e8f9f7 2428 /* DMA Circular mode */
<> 144:ef7eb2e8f9f7 2429 else
<> 144:ef7eb2e8f9f7 2430 {
<> 144:ef7eb2e8f9f7 2431 HAL_UART_TxCpltCallback(huart);
<> 144:ef7eb2e8f9f7 2432 }
<> 144:ef7eb2e8f9f7 2433
<> 144:ef7eb2e8f9f7 2434 }
<> 144:ef7eb2e8f9f7 2435
<> 144:ef7eb2e8f9f7 2436 /**
<> 144:ef7eb2e8f9f7 2437 * @brief DMA UART transmit process half complete callback.
<> 156:95d6b41a828b 2438 * @param hdma DMA handle.
<> 144:ef7eb2e8f9f7 2439 * @retval None
<> 144:ef7eb2e8f9f7 2440 */
<> 144:ef7eb2e8f9f7 2441 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2442 {
<> 156:95d6b41a828b 2443 UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
<> 144:ef7eb2e8f9f7 2444
<> 144:ef7eb2e8f9f7 2445 HAL_UART_TxHalfCpltCallback(huart);
<> 144:ef7eb2e8f9f7 2446 }
<> 144:ef7eb2e8f9f7 2447
<> 144:ef7eb2e8f9f7 2448 /**
<> 144:ef7eb2e8f9f7 2449 * @brief DMA UART receive process complete callback.
<> 156:95d6b41a828b 2450 * @param hdma DMA handle.
<> 144:ef7eb2e8f9f7 2451 * @retval None
<> 144:ef7eb2e8f9f7 2452 */
<> 144:ef7eb2e8f9f7 2453 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2454 {
<> 156:95d6b41a828b 2455 UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
<> 156:95d6b41a828b 2456
<> 144:ef7eb2e8f9f7 2457 /* DMA Normal mode */
<> 144:ef7eb2e8f9f7 2458 if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
<> 144:ef7eb2e8f9f7 2459 {
<> 156:95d6b41a828b 2460 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 2461
<> 156:95d6b41a828b 2462 /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<> 156:95d6b41a828b 2463 CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
<> 156:95d6b41a828b 2464 CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 2465
<> 144:ef7eb2e8f9f7 2466 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
<> 144:ef7eb2e8f9f7 2467 in the UART CR3 register */
<> 156:95d6b41a828b 2468 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 2469
<> 144:ef7eb2e8f9f7 2470 /* At end of Rx process, restore huart->RxState to Ready */
<> 144:ef7eb2e8f9f7 2471 huart->RxState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 2472 }
<> 156:95d6b41a828b 2473
<> 144:ef7eb2e8f9f7 2474 HAL_UART_RxCpltCallback(huart);
<> 144:ef7eb2e8f9f7 2475 }
<> 144:ef7eb2e8f9f7 2476
<> 144:ef7eb2e8f9f7 2477 /**
<> 144:ef7eb2e8f9f7 2478 * @brief DMA UART receive process half complete callback.
<> 156:95d6b41a828b 2479 * @param hdma DMA handle.
<> 144:ef7eb2e8f9f7 2480 * @retval None
<> 144:ef7eb2e8f9f7 2481 */
<> 144:ef7eb2e8f9f7 2482 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2483 {
<> 156:95d6b41a828b 2484 UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
<> 144:ef7eb2e8f9f7 2485
<> 144:ef7eb2e8f9f7 2486 HAL_UART_RxHalfCpltCallback(huart);
<> 144:ef7eb2e8f9f7 2487 }
<> 144:ef7eb2e8f9f7 2488
<> 144:ef7eb2e8f9f7 2489 /**
<> 144:ef7eb2e8f9f7 2490 * @brief DMA UART communication error callback.
<> 156:95d6b41a828b 2491 * @param hdma DMA handle.
<> 144:ef7eb2e8f9f7 2492 * @retval None
<> 144:ef7eb2e8f9f7 2493 */
<> 144:ef7eb2e8f9f7 2494 static void UART_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2495 {
<> 156:95d6b41a828b 2496 UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
<> 156:95d6b41a828b 2497
<> 156:95d6b41a828b 2498 /* Stop UART DMA Tx request if ongoing */
<> 156:95d6b41a828b 2499 if ( (huart->gState == HAL_UART_STATE_BUSY_TX)
<> 156:95d6b41a828b 2500 &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) )
<> 156:95d6b41a828b 2501 {
<> 156:95d6b41a828b 2502 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 2503 UART_EndTxTransfer(huart);
<> 156:95d6b41a828b 2504 }
<> 156:95d6b41a828b 2505
<> 156:95d6b41a828b 2506 /* Stop UART DMA Rx request if ongoing */
<> 156:95d6b41a828b 2507 if ( (huart->RxState == HAL_UART_STATE_BUSY_RX)
<> 156:95d6b41a828b 2508 &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) )
<> 156:95d6b41a828b 2509 {
<> 156:95d6b41a828b 2510 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 2511 UART_EndRxTransfer(huart);
<> 156:95d6b41a828b 2512 }
<> 156:95d6b41a828b 2513
<> 144:ef7eb2e8f9f7 2514 huart->ErrorCode |= HAL_UART_ERROR_DMA;
<> 144:ef7eb2e8f9f7 2515 HAL_UART_ErrorCallback(huart);
<> 144:ef7eb2e8f9f7 2516 }
<> 144:ef7eb2e8f9f7 2517
<> 144:ef7eb2e8f9f7 2518 /**
<> 156:95d6b41a828b 2519 * @brief DMA UART communication abort callback, when initiated by HAL services on Error
<> 156:95d6b41a828b 2520 * (To be called at end of DMA Abort procedure following error occurrence).
<> 156:95d6b41a828b 2521 * @param hdma DMA handle.
<> 156:95d6b41a828b 2522 * @retval None
<> 156:95d6b41a828b 2523 */
<> 156:95d6b41a828b 2524 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2525 {
<> 156:95d6b41a828b 2526 UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
<> 156:95d6b41a828b 2527 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 2528 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 2529
<> 156:95d6b41a828b 2530 HAL_UART_ErrorCallback(huart);
<> 156:95d6b41a828b 2531 }
<> 156:95d6b41a828b 2532
<> 156:95d6b41a828b 2533 /**
<> 156:95d6b41a828b 2534 * @brief DMA UART Tx communication abort callback, when initiated by user
<> 156:95d6b41a828b 2535 * (To be called at end of DMA Tx Abort procedure following user abort request).
<> 156:95d6b41a828b 2536 * @note When this callback is executed, User Abort complete call back is called only if no
<> 156:95d6b41a828b 2537 * Abort still ongoing for Rx DMA Handle.
<> 156:95d6b41a828b 2538 * @param hdma DMA handle.
<> 156:95d6b41a828b 2539 * @retval None
<> 156:95d6b41a828b 2540 */
<> 156:95d6b41a828b 2541 static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2542 {
<> 156:95d6b41a828b 2543 UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
<> 156:95d6b41a828b 2544
<> 156:95d6b41a828b 2545 huart->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2546
<> 156:95d6b41a828b 2547 /* Check if an Abort process is still ongoing */
<> 156:95d6b41a828b 2548 if(huart->hdmarx != NULL)
<> 156:95d6b41a828b 2549 {
<> 156:95d6b41a828b 2550 if(huart->hdmarx->XferAbortCallback != NULL)
<> 156:95d6b41a828b 2551 {
<> 156:95d6b41a828b 2552 return;
<> 156:95d6b41a828b 2553 }
<> 156:95d6b41a828b 2554 }
<> 156:95d6b41a828b 2555
<> 156:95d6b41a828b 2556 /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
<> 156:95d6b41a828b 2557 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 2558 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 2559
<> 156:95d6b41a828b 2560 /* Reset errorCode */
<> 156:95d6b41a828b 2561 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 156:95d6b41a828b 2562
<> 156:95d6b41a828b 2563 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 2564 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
<> 156:95d6b41a828b 2565
<> 156:95d6b41a828b 2566 /* Restore huart->gState and huart->RxState to Ready */
<> 156:95d6b41a828b 2567 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2568 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2569
<> 156:95d6b41a828b 2570 /* Call user Abort complete callback */
<> 156:95d6b41a828b 2571 HAL_UART_AbortCpltCallback(huart);
<> 156:95d6b41a828b 2572 }
<> 156:95d6b41a828b 2573
<> 156:95d6b41a828b 2574
<> 156:95d6b41a828b 2575 /**
<> 156:95d6b41a828b 2576 * @brief DMA UART Rx communication abort callback, when initiated by user
<> 156:95d6b41a828b 2577 * (To be called at end of DMA Rx Abort procedure following user abort request).
<> 156:95d6b41a828b 2578 * @note When this callback is executed, User Abort complete call back is called only if no
<> 156:95d6b41a828b 2579 * Abort still ongoing for Tx DMA Handle.
<> 156:95d6b41a828b 2580 * @param hdma DMA handle.
<> 156:95d6b41a828b 2581 * @retval None
<> 156:95d6b41a828b 2582 */
<> 156:95d6b41a828b 2583 static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2584 {
<> 156:95d6b41a828b 2585 UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
<> 156:95d6b41a828b 2586
<> 156:95d6b41a828b 2587 huart->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2588
<> 156:95d6b41a828b 2589 /* Check if an Abort process is still ongoing */
<> 156:95d6b41a828b 2590 if(huart->hdmatx != NULL)
<> 156:95d6b41a828b 2591 {
<> 156:95d6b41a828b 2592 if(huart->hdmatx->XferAbortCallback != NULL)
<> 156:95d6b41a828b 2593 {
<> 156:95d6b41a828b 2594 return;
<> 156:95d6b41a828b 2595 }
<> 156:95d6b41a828b 2596 }
<> 156:95d6b41a828b 2597
<> 156:95d6b41a828b 2598 /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
<> 156:95d6b41a828b 2599 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 2600 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 2601
<> 156:95d6b41a828b 2602 /* Reset errorCode */
<> 156:95d6b41a828b 2603 huart->ErrorCode = HAL_UART_ERROR_NONE;
<> 156:95d6b41a828b 2604
<> 156:95d6b41a828b 2605 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 2606 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
<> 156:95d6b41a828b 2607
<> 156:95d6b41a828b 2608 /* Restore huart->gState and huart->RxState to Ready */
<> 156:95d6b41a828b 2609 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2610 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2611
<> 156:95d6b41a828b 2612 /* Call user Abort complete callback */
<> 156:95d6b41a828b 2613 HAL_UART_AbortCpltCallback(huart);
<> 156:95d6b41a828b 2614 }
<> 156:95d6b41a828b 2615
<> 156:95d6b41a828b 2616
<> 156:95d6b41a828b 2617 /**
<> 156:95d6b41a828b 2618 * @brief DMA UART Tx communication abort callback, when initiated by user by a call to
<> 156:95d6b41a828b 2619 * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
<> 156:95d6b41a828b 2620 * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
<> 156:95d6b41a828b 2621 * and leads to user Tx Abort Complete callback execution).
<> 156:95d6b41a828b 2622 * @param hdma DMA handle.
<> 156:95d6b41a828b 2623 * @retval None
<> 156:95d6b41a828b 2624 */
<> 156:95d6b41a828b 2625 static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2626 {
<> 156:95d6b41a828b 2627 UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
<> 156:95d6b41a828b 2628
<> 156:95d6b41a828b 2629 huart->TxXferCount = 0U;
<> 156:95d6b41a828b 2630
<> 156:95d6b41a828b 2631 /* Restore huart->gState to Ready */
<> 156:95d6b41a828b 2632 huart->gState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2633
<> 156:95d6b41a828b 2634 /* Call user Abort complete callback */
<> 156:95d6b41a828b 2635 HAL_UART_AbortTransmitCpltCallback(huart);
<> 156:95d6b41a828b 2636 }
<> 156:95d6b41a828b 2637
<> 156:95d6b41a828b 2638 /**
<> 156:95d6b41a828b 2639 * @brief DMA UART Rx communication abort callback, when initiated by user by a call to
<> 156:95d6b41a828b 2640 * HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
<> 156:95d6b41a828b 2641 * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
<> 156:95d6b41a828b 2642 * and leads to user Rx Abort Complete callback execution).
<> 156:95d6b41a828b 2643 * @param hdma DMA handle.
<> 156:95d6b41a828b 2644 * @retval None
<> 156:95d6b41a828b 2645 */
<> 156:95d6b41a828b 2646 static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2647 {
<> 156:95d6b41a828b 2648 UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 156:95d6b41a828b 2649
<> 156:95d6b41a828b 2650 huart->RxXferCount = 0U;
<> 156:95d6b41a828b 2651
<> 156:95d6b41a828b 2652 /* Clear the Error flags in the ICR register */
<> 156:95d6b41a828b 2653 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
<> 156:95d6b41a828b 2654
<> 156:95d6b41a828b 2655 /* Restore huart->RxState to Ready */
<> 156:95d6b41a828b 2656 huart->RxState = HAL_UART_STATE_READY;
<> 156:95d6b41a828b 2657
<> 156:95d6b41a828b 2658 /* Call user Abort complete callback */
<> 156:95d6b41a828b 2659 HAL_UART_AbortReceiveCpltCallback(huart);
<> 156:95d6b41a828b 2660 }
<> 156:95d6b41a828b 2661
<> 156:95d6b41a828b 2662 /**
<> 156:95d6b41a828b 2663 * @brief Send an amount of data in interrupt mode.
<> 144:ef7eb2e8f9f7 2664 * @note Function is called under interruption only, once
<> 144:ef7eb2e8f9f7 2665 * interruptions have been enabled by HAL_UART_Transmit_IT().
<> 156:95d6b41a828b 2666 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 2667 * @retval HAL status
<> 144:ef7eb2e8f9f7 2668 */
<> 144:ef7eb2e8f9f7 2669 HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2670 {
<> 144:ef7eb2e8f9f7 2671 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 2672
<> 144:ef7eb2e8f9f7 2673 /* Check that a Tx process is ongoing */
<> 144:ef7eb2e8f9f7 2674 if (huart->gState == HAL_UART_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 2675 {
<> 156:95d6b41a828b 2676 if(huart->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 2677 {
<> 144:ef7eb2e8f9f7 2678 /* Disable the UART Transmit Data Register Empty Interrupt */
<> 156:95d6b41a828b 2679 CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
<> 144:ef7eb2e8f9f7 2680
<> 144:ef7eb2e8f9f7 2681 /* Enable the UART Transmit Complete Interrupt */
<> 156:95d6b41a828b 2682 SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 2683
<> 144:ef7eb2e8f9f7 2684 return HAL_OK;
<> 144:ef7eb2e8f9f7 2685 }
<> 144:ef7eb2e8f9f7 2686 else
<> 144:ef7eb2e8f9f7 2687 {
<> 144:ef7eb2e8f9f7 2688 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 2689 {
<> 144:ef7eb2e8f9f7 2690 tmp = (uint16_t*) huart->pTxBuffPtr;
<> 156:95d6b41a828b 2691 huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
<> 156:95d6b41a828b 2692 huart->pTxBuffPtr += 2U;
<> 144:ef7eb2e8f9f7 2693 }
<> 144:ef7eb2e8f9f7 2694 else
<> 144:ef7eb2e8f9f7 2695 {
<> 156:95d6b41a828b 2696 huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU);
<> 144:ef7eb2e8f9f7 2697 }
<> 144:ef7eb2e8f9f7 2698 huart->TxXferCount--;
<> 144:ef7eb2e8f9f7 2699
<> 144:ef7eb2e8f9f7 2700 return HAL_OK;
<> 144:ef7eb2e8f9f7 2701 }
<> 144:ef7eb2e8f9f7 2702 }
<> 144:ef7eb2e8f9f7 2703 else
<> 144:ef7eb2e8f9f7 2704 {
<> 144:ef7eb2e8f9f7 2705 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2706 }
<> 144:ef7eb2e8f9f7 2707 }
<> 144:ef7eb2e8f9f7 2708
<> 144:ef7eb2e8f9f7 2709 /**
<> 144:ef7eb2e8f9f7 2710 * @brief Wrap up transmission in non-blocking mode.
<> 156:95d6b41a828b 2711 * @param huart pointer to a UART_HandleTypeDef structure that contains
<> 156:95d6b41a828b 2712 * the configuration information for the specified UART module.
<> 144:ef7eb2e8f9f7 2713 * @retval HAL status
<> 144:ef7eb2e8f9f7 2714 */
<> 144:ef7eb2e8f9f7 2715 HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2716 {
<> 144:ef7eb2e8f9f7 2717 /* Disable the UART Transmit Complete Interrupt */
<> 156:95d6b41a828b 2718 CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
<> 144:ef7eb2e8f9f7 2719
<> 144:ef7eb2e8f9f7 2720 /* Tx process is ended, restore huart->gState to Ready */
<> 144:ef7eb2e8f9f7 2721 huart->gState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 2722
<> 144:ef7eb2e8f9f7 2723 HAL_UART_TxCpltCallback(huart);
<> 144:ef7eb2e8f9f7 2724
<> 144:ef7eb2e8f9f7 2725 return HAL_OK;
<> 144:ef7eb2e8f9f7 2726 }
<> 144:ef7eb2e8f9f7 2727
<> 144:ef7eb2e8f9f7 2728 /**
<> 156:95d6b41a828b 2729 * @brief Receive an amount of data in interrupt mode.
<> 144:ef7eb2e8f9f7 2730 * @note Function is called under interruption only, once
<> 144:ef7eb2e8f9f7 2731 * interruptions have been enabled by HAL_UART_Receive_IT()
<> 156:95d6b41a828b 2732 * @param huart UART handle.
<> 144:ef7eb2e8f9f7 2733 * @retval HAL status
<> 144:ef7eb2e8f9f7 2734 */
<> 144:ef7eb2e8f9f7 2735 HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
<> 144:ef7eb2e8f9f7 2736 {
<> 144:ef7eb2e8f9f7 2737 uint16_t* tmp;
<> 156:95d6b41a828b 2738 uint16_t uhMask = huart->Mask;
<> 156:95d6b41a828b 2739 uint16_t uhdata;
<> 144:ef7eb2e8f9f7 2740
<> 144:ef7eb2e8f9f7 2741 /* Check that a Rx process is ongoing */
<> 144:ef7eb2e8f9f7 2742 if(huart->RxState == HAL_UART_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 2743 {
<> 156:95d6b41a828b 2744 uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
<> 144:ef7eb2e8f9f7 2745 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<> 144:ef7eb2e8f9f7 2746 {
<> 144:ef7eb2e8f9f7 2747 tmp = (uint16_t*) huart->pRxBuffPtr ;
<> 156:95d6b41a828b 2748 *tmp = (uint16_t)(uhdata & uhMask);
<> 156:95d6b41a828b 2749 huart->pRxBuffPtr +=2U;
<> 144:ef7eb2e8f9f7 2750 }
<> 144:ef7eb2e8f9f7 2751 else
<> 144:ef7eb2e8f9f7 2752 {
<> 156:95d6b41a828b 2753 *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
<> 144:ef7eb2e8f9f7 2754 }
<> 144:ef7eb2e8f9f7 2755
<> 156:95d6b41a828b 2756 if(--huart->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 2757 {
<> 156:95d6b41a828b 2758 /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
<> 156:95d6b41a828b 2759 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
<> 144:ef7eb2e8f9f7 2760
<> 144:ef7eb2e8f9f7 2761 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
<> 156:95d6b41a828b 2762 CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<> 144:ef7eb2e8f9f7 2763
<> 144:ef7eb2e8f9f7 2764 /* Rx process is completed, restore huart->RxState to Ready */
<> 144:ef7eb2e8f9f7 2765 huart->RxState = HAL_UART_STATE_READY;
<> 144:ef7eb2e8f9f7 2766
<> 144:ef7eb2e8f9f7 2767 HAL_UART_RxCpltCallback(huart);
<> 144:ef7eb2e8f9f7 2768
<> 144:ef7eb2e8f9f7 2769 return HAL_OK;
<> 144:ef7eb2e8f9f7 2770 }
<> 144:ef7eb2e8f9f7 2771
<> 144:ef7eb2e8f9f7 2772 return HAL_OK;
<> 144:ef7eb2e8f9f7 2773 }
<> 144:ef7eb2e8f9f7 2774 else
<> 144:ef7eb2e8f9f7 2775 {
<> 144:ef7eb2e8f9f7 2776 /* Clear RXNE interrupt flag */
<> 144:ef7eb2e8f9f7 2777 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
<> 144:ef7eb2e8f9f7 2778
<> 144:ef7eb2e8f9f7 2779 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2780 }
<> 144:ef7eb2e8f9f7 2781 }
<> 144:ef7eb2e8f9f7 2782
<> 144:ef7eb2e8f9f7 2783 /**
<> 144:ef7eb2e8f9f7 2784 * @}
<> 144:ef7eb2e8f9f7 2785 */
<> 144:ef7eb2e8f9f7 2786
<> 144:ef7eb2e8f9f7 2787 #endif /* HAL_UART_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2788 /**
<> 144:ef7eb2e8f9f7 2789 * @}
<> 144:ef7eb2e8f9f7 2790 */
<> 144:ef7eb2e8f9f7 2791
<> 144:ef7eb2e8f9f7 2792 /**
<> 144:ef7eb2e8f9f7 2793 * @}
<> 144:ef7eb2e8f9f7 2794 */
<> 144:ef7eb2e8f9f7 2795
<> 144:ef7eb2e8f9f7 2796 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/