mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_tsc.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief This file contains all the functions prototypes for the TSC firmware
<> 144:ef7eb2e8f9f7 6 * library.
<> 144:ef7eb2e8f9f7 7 ******************************************************************************
<> 144:ef7eb2e8f9f7 8 * @attention
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 13 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 14 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 15 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 16 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 17 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 18 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 19 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 20 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 21 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 33 *
<> 144:ef7eb2e8f9f7 34 ******************************************************************************
<> 144:ef7eb2e8f9f7 35 */
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 38 #ifndef __STM32F0xx_TSC_H
<> 144:ef7eb2e8f9f7 39 #define __STM32F0xx_TSC_H
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 42 extern "C" {
<> 144:ef7eb2e8f9f7 43 #endif
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 #if defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || \
<> 144:ef7eb2e8f9f7 46 defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
<> 144:ef7eb2e8f9f7 47 defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 50 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 53 * @{
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /** @addtogroup TSC
<> 144:ef7eb2e8f9f7 57 * @{
<> 144:ef7eb2e8f9f7 58 */
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /** @defgroup TSC_Exported_Types TSC Exported Types
<> 144:ef7eb2e8f9f7 63 * @{
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 /**
<> 144:ef7eb2e8f9f7 66 * @brief TSC state structure definition
<> 144:ef7eb2e8f9f7 67 */
<> 144:ef7eb2e8f9f7 68 typedef enum
<> 144:ef7eb2e8f9f7 69 {
<> 156:95d6b41a828b 70 HAL_TSC_STATE_RESET = 0x00U, /*!< TSC registers have their reset value */
<> 156:95d6b41a828b 71 HAL_TSC_STATE_READY = 0x01U, /*!< TSC registers are initialized or acquisition is completed with success */
<> 156:95d6b41a828b 72 HAL_TSC_STATE_BUSY = 0x02U, /*!< TSC initialization or acquisition is on-going */
<> 156:95d6b41a828b 73 HAL_TSC_STATE_ERROR = 0x03U /*!< Acquisition is completed with max count error */
<> 144:ef7eb2e8f9f7 74 } HAL_TSC_StateTypeDef;
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /**
<> 144:ef7eb2e8f9f7 77 * @brief TSC group status structure definition
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79 typedef enum
<> 144:ef7eb2e8f9f7 80 {
<> 156:95d6b41a828b 81 TSC_GROUP_ONGOING = 0x00U, /*!< Acquisition on group is on-going or not started */
<> 156:95d6b41a828b 82 TSC_GROUP_COMPLETED = 0x01U /*!< Acquisition on group is completed with success (no max count error) */
<> 144:ef7eb2e8f9f7 83 } TSC_GroupStatusTypeDef;
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /**
<> 144:ef7eb2e8f9f7 86 * @brief TSC init structure definition
<> 144:ef7eb2e8f9f7 87 */
<> 144:ef7eb2e8f9f7 88 typedef struct
<> 144:ef7eb2e8f9f7 89 {
<> 144:ef7eb2e8f9f7 90 uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length */
<> 144:ef7eb2e8f9f7 91 uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length */
<> 144:ef7eb2e8f9f7 92 uint32_t SpreadSpectrum; /*!< Spread spectrum activation */
<> 144:ef7eb2e8f9f7 93 uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation */
<> 144:ef7eb2e8f9f7 94 uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler */
<> 144:ef7eb2e8f9f7 95 uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler */
<> 144:ef7eb2e8f9f7 96 uint32_t MaxCountValue; /*!< Max count value */
<> 144:ef7eb2e8f9f7 97 uint32_t IODefaultMode; /*!< IO default mode */
<> 144:ef7eb2e8f9f7 98 uint32_t SynchroPinPolarity; /*!< Synchro pin polarity */
<> 144:ef7eb2e8f9f7 99 uint32_t AcquisitionMode; /*!< Acquisition mode */
<> 144:ef7eb2e8f9f7 100 uint32_t MaxCountInterrupt; /*!< Max count interrupt activation */
<> 144:ef7eb2e8f9f7 101 uint32_t ChannelIOs; /*!< Channel IOs mask */
<> 144:ef7eb2e8f9f7 102 uint32_t ShieldIOs; /*!< Shield IOs mask */
<> 144:ef7eb2e8f9f7 103 uint32_t SamplingIOs; /*!< Sampling IOs mask */
<> 144:ef7eb2e8f9f7 104 } TSC_InitTypeDef;
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /**
<> 144:ef7eb2e8f9f7 107 * @brief TSC IOs configuration structure definition
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109 typedef struct
<> 144:ef7eb2e8f9f7 110 {
<> 144:ef7eb2e8f9f7 111 uint32_t ChannelIOs; /*!< Channel IOs mask */
<> 144:ef7eb2e8f9f7 112 uint32_t ShieldIOs; /*!< Shield IOs mask */
<> 144:ef7eb2e8f9f7 113 uint32_t SamplingIOs; /*!< Sampling IOs mask */
<> 144:ef7eb2e8f9f7 114 } TSC_IOConfigTypeDef;
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /**
<> 144:ef7eb2e8f9f7 117 * @brief TSC handle Structure definition
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 typedef struct
<> 144:ef7eb2e8f9f7 120 {
<> 144:ef7eb2e8f9f7 121 TSC_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 122 TSC_InitTypeDef Init; /*!< Initialization parameters */
<> 144:ef7eb2e8f9f7 123 __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */
<> 144:ef7eb2e8f9f7 124 HAL_LockTypeDef Lock; /*!< Lock feature */
<> 144:ef7eb2e8f9f7 125 } TSC_HandleTypeDef;
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /**
<> 144:ef7eb2e8f9f7 128 * @}
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /** @defgroup TSC_Exported_Constants TSC Exported Constants
<> 144:ef7eb2e8f9f7 134 * @{
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /** @defgroup TSC_CTPH_Cycles TSC Charge Transfer Pulse High
<> 144:ef7eb2e8f9f7 138 * @{
<> 144:ef7eb2e8f9f7 139 */
<> 156:95d6b41a828b 140 #define TSC_CTPH_1CYCLE ((uint32_t)( 0U << 28))
<> 156:95d6b41a828b 141 #define TSC_CTPH_2CYCLES ((uint32_t)( 1U << 28))
<> 156:95d6b41a828b 142 #define TSC_CTPH_3CYCLES ((uint32_t)( 2U << 28))
<> 156:95d6b41a828b 143 #define TSC_CTPH_4CYCLES ((uint32_t)( 3U << 28))
<> 156:95d6b41a828b 144 #define TSC_CTPH_5CYCLES ((uint32_t)( 4U << 28))
<> 156:95d6b41a828b 145 #define TSC_CTPH_6CYCLES ((uint32_t)( 5U << 28))
<> 156:95d6b41a828b 146 #define TSC_CTPH_7CYCLES ((uint32_t)( 6U << 28))
<> 156:95d6b41a828b 147 #define TSC_CTPH_8CYCLES ((uint32_t)( 7U << 28))
<> 156:95d6b41a828b 148 #define TSC_CTPH_9CYCLES ((uint32_t)( 8U << 28))
<> 156:95d6b41a828b 149 #define TSC_CTPH_10CYCLES ((uint32_t)( 9U << 28))
<> 156:95d6b41a828b 150 #define TSC_CTPH_11CYCLES ((uint32_t)(10U << 28))
<> 156:95d6b41a828b 151 #define TSC_CTPH_12CYCLES ((uint32_t)(11U << 28))
<> 156:95d6b41a828b 152 #define TSC_CTPH_13CYCLES ((uint32_t)(12U << 28))
<> 156:95d6b41a828b 153 #define TSC_CTPH_14CYCLES ((uint32_t)(13U << 28))
<> 156:95d6b41a828b 154 #define TSC_CTPH_15CYCLES ((uint32_t)(14U << 28))
<> 156:95d6b41a828b 155 #define TSC_CTPH_16CYCLES ((uint32_t)(15U << 28))
<> 144:ef7eb2e8f9f7 156 #define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \
<> 144:ef7eb2e8f9f7 157 ((VAL) == TSC_CTPH_2CYCLES) || \
<> 144:ef7eb2e8f9f7 158 ((VAL) == TSC_CTPH_3CYCLES) || \
<> 144:ef7eb2e8f9f7 159 ((VAL) == TSC_CTPH_4CYCLES) || \
<> 144:ef7eb2e8f9f7 160 ((VAL) == TSC_CTPH_5CYCLES) || \
<> 144:ef7eb2e8f9f7 161 ((VAL) == TSC_CTPH_6CYCLES) || \
<> 144:ef7eb2e8f9f7 162 ((VAL) == TSC_CTPH_7CYCLES) || \
<> 144:ef7eb2e8f9f7 163 ((VAL) == TSC_CTPH_8CYCLES) || \
<> 144:ef7eb2e8f9f7 164 ((VAL) == TSC_CTPH_9CYCLES) || \
<> 144:ef7eb2e8f9f7 165 ((VAL) == TSC_CTPH_10CYCLES) || \
<> 144:ef7eb2e8f9f7 166 ((VAL) == TSC_CTPH_11CYCLES) || \
<> 144:ef7eb2e8f9f7 167 ((VAL) == TSC_CTPH_12CYCLES) || \
<> 144:ef7eb2e8f9f7 168 ((VAL) == TSC_CTPH_13CYCLES) || \
<> 144:ef7eb2e8f9f7 169 ((VAL) == TSC_CTPH_14CYCLES) || \
<> 144:ef7eb2e8f9f7 170 ((VAL) == TSC_CTPH_15CYCLES) || \
<> 144:ef7eb2e8f9f7 171 ((VAL) == TSC_CTPH_16CYCLES))
<> 144:ef7eb2e8f9f7 172 /**
<> 144:ef7eb2e8f9f7 173 * @}
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /** @defgroup TSC_CTPL_Cycles TSC Charge Transfer Pulse Low
<> 144:ef7eb2e8f9f7 177 * @{
<> 144:ef7eb2e8f9f7 178 */
<> 156:95d6b41a828b 179 #define TSC_CTPL_1CYCLE ((uint32_t)( 0U << 24))
<> 156:95d6b41a828b 180 #define TSC_CTPL_2CYCLES ((uint32_t)( 1U << 24))
<> 156:95d6b41a828b 181 #define TSC_CTPL_3CYCLES ((uint32_t)( 2U << 24))
<> 156:95d6b41a828b 182 #define TSC_CTPL_4CYCLES ((uint32_t)( 3U << 24))
<> 156:95d6b41a828b 183 #define TSC_CTPL_5CYCLES ((uint32_t)( 4U << 24))
<> 156:95d6b41a828b 184 #define TSC_CTPL_6CYCLES ((uint32_t)( 5U << 24))
<> 156:95d6b41a828b 185 #define TSC_CTPL_7CYCLES ((uint32_t)( 6U << 24))
<> 156:95d6b41a828b 186 #define TSC_CTPL_8CYCLES ((uint32_t)( 7U << 24))
<> 156:95d6b41a828b 187 #define TSC_CTPL_9CYCLES ((uint32_t)( 8U << 24))
<> 156:95d6b41a828b 188 #define TSC_CTPL_10CYCLES ((uint32_t)( 9U << 24))
<> 156:95d6b41a828b 189 #define TSC_CTPL_11CYCLES ((uint32_t)(10U << 24))
<> 156:95d6b41a828b 190 #define TSC_CTPL_12CYCLES ((uint32_t)(11U << 24))
<> 156:95d6b41a828b 191 #define TSC_CTPL_13CYCLES ((uint32_t)(12U << 24))
<> 156:95d6b41a828b 192 #define TSC_CTPL_14CYCLES ((uint32_t)(13U << 24))
<> 156:95d6b41a828b 193 #define TSC_CTPL_15CYCLES ((uint32_t)(14U << 24))
<> 156:95d6b41a828b 194 #define TSC_CTPL_16CYCLES ((uint32_t)(15U << 24))
<> 144:ef7eb2e8f9f7 195 #define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \
<> 144:ef7eb2e8f9f7 196 ((VAL) == TSC_CTPL_2CYCLES) || \
<> 144:ef7eb2e8f9f7 197 ((VAL) == TSC_CTPL_3CYCLES) || \
<> 144:ef7eb2e8f9f7 198 ((VAL) == TSC_CTPL_4CYCLES) || \
<> 144:ef7eb2e8f9f7 199 ((VAL) == TSC_CTPL_5CYCLES) || \
<> 144:ef7eb2e8f9f7 200 ((VAL) == TSC_CTPL_6CYCLES) || \
<> 144:ef7eb2e8f9f7 201 ((VAL) == TSC_CTPL_7CYCLES) || \
<> 144:ef7eb2e8f9f7 202 ((VAL) == TSC_CTPL_8CYCLES) || \
<> 144:ef7eb2e8f9f7 203 ((VAL) == TSC_CTPL_9CYCLES) || \
<> 144:ef7eb2e8f9f7 204 ((VAL) == TSC_CTPL_10CYCLES) || \
<> 144:ef7eb2e8f9f7 205 ((VAL) == TSC_CTPL_11CYCLES) || \
<> 144:ef7eb2e8f9f7 206 ((VAL) == TSC_CTPL_12CYCLES) || \
<> 144:ef7eb2e8f9f7 207 ((VAL) == TSC_CTPL_13CYCLES) || \
<> 144:ef7eb2e8f9f7 208 ((VAL) == TSC_CTPL_14CYCLES) || \
<> 144:ef7eb2e8f9f7 209 ((VAL) == TSC_CTPL_15CYCLES) || \
<> 144:ef7eb2e8f9f7 210 ((VAL) == TSC_CTPL_16CYCLES))
<> 144:ef7eb2e8f9f7 211 /**
<> 144:ef7eb2e8f9f7 212 * @}
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /** @defgroup TSC_SS_Prescaler_definition TSC Spread spectrum prescaler definition
<> 144:ef7eb2e8f9f7 216 * @{
<> 144:ef7eb2e8f9f7 217 */
<> 156:95d6b41a828b 218 #define TSC_SS_PRESC_DIV1 (0U)
<> 144:ef7eb2e8f9f7 219 #define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC)
<> 144:ef7eb2e8f9f7 220 #define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /**
<> 144:ef7eb2e8f9f7 223 * @}
<> 144:ef7eb2e8f9f7 224 */
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /** @defgroup TSC_PG_Prescaler_definition TSC Pulse Generator prescaler definition
<> 144:ef7eb2e8f9f7 227 * @{
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229 #define TSC_PG_PRESC_DIV1 ((uint32_t)(0 << 12))
<> 144:ef7eb2e8f9f7 230 #define TSC_PG_PRESC_DIV2 ((uint32_t)(1 << 12))
<> 144:ef7eb2e8f9f7 231 #define TSC_PG_PRESC_DIV4 ((uint32_t)(2 << 12))
<> 144:ef7eb2e8f9f7 232 #define TSC_PG_PRESC_DIV8 ((uint32_t)(3 << 12))
<> 144:ef7eb2e8f9f7 233 #define TSC_PG_PRESC_DIV16 ((uint32_t)(4 << 12))
<> 144:ef7eb2e8f9f7 234 #define TSC_PG_PRESC_DIV32 ((uint32_t)(5 << 12))
<> 144:ef7eb2e8f9f7 235 #define TSC_PG_PRESC_DIV64 ((uint32_t)(6 << 12))
<> 144:ef7eb2e8f9f7 236 #define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12))
<> 144:ef7eb2e8f9f7 237 #define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \
<> 144:ef7eb2e8f9f7 238 ((VAL) == TSC_PG_PRESC_DIV2) || \
<> 144:ef7eb2e8f9f7 239 ((VAL) == TSC_PG_PRESC_DIV4) || \
<> 144:ef7eb2e8f9f7 240 ((VAL) == TSC_PG_PRESC_DIV8) || \
<> 144:ef7eb2e8f9f7 241 ((VAL) == TSC_PG_PRESC_DIV16) || \
<> 144:ef7eb2e8f9f7 242 ((VAL) == TSC_PG_PRESC_DIV32) || \
<> 144:ef7eb2e8f9f7 243 ((VAL) == TSC_PG_PRESC_DIV64) || \
<> 144:ef7eb2e8f9f7 244 ((VAL) == TSC_PG_PRESC_DIV128))
<> 144:ef7eb2e8f9f7 245 /**
<> 144:ef7eb2e8f9f7 246 * @}
<> 144:ef7eb2e8f9f7 247 */
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /** @defgroup TSC_MCV_definition TSC Max Count Value definition
<> 144:ef7eb2e8f9f7 250 * @{
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252 #define TSC_MCV_255 ((uint32_t)(0 << 5))
<> 144:ef7eb2e8f9f7 253 #define TSC_MCV_511 ((uint32_t)(1 << 5))
<> 144:ef7eb2e8f9f7 254 #define TSC_MCV_1023 ((uint32_t)(2 << 5))
<> 144:ef7eb2e8f9f7 255 #define TSC_MCV_2047 ((uint32_t)(3 << 5))
<> 144:ef7eb2e8f9f7 256 #define TSC_MCV_4095 ((uint32_t)(4 << 5))
<> 144:ef7eb2e8f9f7 257 #define TSC_MCV_8191 ((uint32_t)(5 << 5))
<> 144:ef7eb2e8f9f7 258 #define TSC_MCV_16383 ((uint32_t)(6 << 5))
<> 144:ef7eb2e8f9f7 259 #define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \
<> 144:ef7eb2e8f9f7 260 ((VAL) == TSC_MCV_511) || \
<> 144:ef7eb2e8f9f7 261 ((VAL) == TSC_MCV_1023) || \
<> 144:ef7eb2e8f9f7 262 ((VAL) == TSC_MCV_2047) || \
<> 144:ef7eb2e8f9f7 263 ((VAL) == TSC_MCV_4095) || \
<> 144:ef7eb2e8f9f7 264 ((VAL) == TSC_MCV_8191) || \
<> 144:ef7eb2e8f9f7 265 ((VAL) == TSC_MCV_16383))
<> 144:ef7eb2e8f9f7 266 /**
<> 144:ef7eb2e8f9f7 267 * @}
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /** @defgroup TSC_IO_default_mode_definition TSC I/O default mode definition
<> 144:ef7eb2e8f9f7 271 * @{
<> 144:ef7eb2e8f9f7 272 */
<> 156:95d6b41a828b 273 #define TSC_IODEF_OUT_PP_LOW (0U)
<> 144:ef7eb2e8f9f7 274 #define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF)
<> 144:ef7eb2e8f9f7 275 #define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
<> 144:ef7eb2e8f9f7 276 /**
<> 144:ef7eb2e8f9f7 277 * @}
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /** @defgroup TSC_Synchronization_pin_polarity TSC Synchronization pin polarity
<> 144:ef7eb2e8f9f7 281 * @{
<> 144:ef7eb2e8f9f7 282 */
<> 156:95d6b41a828b 283 #define TSC_SYNC_POLARITY_FALLING (0U)
<> 144:ef7eb2e8f9f7 284 #define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)
<> 144:ef7eb2e8f9f7 285 #define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
<> 144:ef7eb2e8f9f7 286 /**
<> 144:ef7eb2e8f9f7 287 * @}
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /** @defgroup TSC_Acquisition_mode TSC Acquisition mode
<> 144:ef7eb2e8f9f7 291 * @{
<> 144:ef7eb2e8f9f7 292 */
<> 156:95d6b41a828b 293 #define TSC_ACQ_MODE_NORMAL (0U)
<> 144:ef7eb2e8f9f7 294 #define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
<> 144:ef7eb2e8f9f7 295 #define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
<> 144:ef7eb2e8f9f7 296 /**
<> 144:ef7eb2e8f9f7 297 * @}
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /** @defgroup TSC_IO_mode_definition TSC I/O mode definition
<> 144:ef7eb2e8f9f7 301 * @{
<> 144:ef7eb2e8f9f7 302 */
<> 156:95d6b41a828b 303 #define TSC_IOMODE_UNUSED (0U)
<> 156:95d6b41a828b 304 #define TSC_IOMODE_CHANNEL (1U)
<> 156:95d6b41a828b 305 #define TSC_IOMODE_SHIELD (2U)
<> 156:95d6b41a828b 306 #define TSC_IOMODE_SAMPLING (3U)
<> 144:ef7eb2e8f9f7 307 #define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \
<> 144:ef7eb2e8f9f7 308 ((VAL) == TSC_IOMODE_CHANNEL) || \
<> 144:ef7eb2e8f9f7 309 ((VAL) == TSC_IOMODE_SHIELD) || \
<> 144:ef7eb2e8f9f7 310 ((VAL) == TSC_IOMODE_SAMPLING))
<> 144:ef7eb2e8f9f7 311 /**
<> 144:ef7eb2e8f9f7 312 * @}
<> 144:ef7eb2e8f9f7 313 */
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /** @defgroup TSC_interrupts_definition TSC interrupts definition
<> 144:ef7eb2e8f9f7 316 * @{
<> 144:ef7eb2e8f9f7 317 */
<> 144:ef7eb2e8f9f7 318 #define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
<> 144:ef7eb2e8f9f7 319 #define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)
<> 144:ef7eb2e8f9f7 320 #define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
<> 144:ef7eb2e8f9f7 321 /**
<> 144:ef7eb2e8f9f7 322 * @}
<> 144:ef7eb2e8f9f7 323 */
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /** @defgroup TSC_flags_definition TSC Flags Definition
<> 144:ef7eb2e8f9f7 326 * @{
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328 #define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
<> 144:ef7eb2e8f9f7 329 #define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)
<> 144:ef7eb2e8f9f7 330 /**
<> 144:ef7eb2e8f9f7 331 * @}
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /** @defgroup TSC_groups_definition TSC groups definition
<> 144:ef7eb2e8f9f7 335 * @{
<> 144:ef7eb2e8f9f7 336 */
<> 144:ef7eb2e8f9f7 337 #define TSC_NB_OF_GROUPS (8)
<> 144:ef7eb2e8f9f7 338
<> 156:95d6b41a828b 339 #define TSC_GROUP1 (0x00000001U)
<> 156:95d6b41a828b 340 #define TSC_GROUP2 (0x00000002U)
<> 156:95d6b41a828b 341 #define TSC_GROUP3 (0x00000004U)
<> 156:95d6b41a828b 342 #define TSC_GROUP4 (0x00000008U)
<> 156:95d6b41a828b 343 #define TSC_GROUP5 (0x00000010U)
<> 156:95d6b41a828b 344 #define TSC_GROUP6 (0x00000020U)
<> 156:95d6b41a828b 345 #define TSC_GROUP7 (0x00000040U)
<> 156:95d6b41a828b 346 #define TSC_GROUP8 (0x00000080U)
<> 156:95d6b41a828b 347 #define TSC_ALL_GROUPS (0x000000FFU)
<> 144:ef7eb2e8f9f7 348
<> 156:95d6b41a828b 349 #define TSC_GROUP1_IDX (0U)
<> 156:95d6b41a828b 350 #define TSC_GROUP2_IDX (1U)
<> 156:95d6b41a828b 351 #define TSC_GROUP3_IDX (2U)
<> 156:95d6b41a828b 352 #define TSC_GROUP4_IDX (3U)
<> 156:95d6b41a828b 353 #define TSC_GROUP5_IDX (4U)
<> 156:95d6b41a828b 354 #define TSC_GROUP6_IDX (5U)
<> 156:95d6b41a828b 355 #define TSC_GROUP7_IDX (6U)
<> 156:95d6b41a828b 356 #define TSC_GROUP8_IDX (7U)
<> 156:95d6b41a828b 357 #define IS_GROUP_INDEX(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < TSC_NB_OF_GROUPS)))
<> 144:ef7eb2e8f9f7 358
<> 156:95d6b41a828b 359 #define TSC_GROUP1_IO1 (0x00000001U)
<> 156:95d6b41a828b 360 #define TSC_GROUP1_IO2 (0x00000002U)
<> 156:95d6b41a828b 361 #define TSC_GROUP1_IO3 (0x00000004U)
<> 156:95d6b41a828b 362 #define TSC_GROUP1_IO4 (0x00000008U)
<> 156:95d6b41a828b 363 #define TSC_GROUP1_ALL_IOS (0x0000000FU)
<> 144:ef7eb2e8f9f7 364
<> 156:95d6b41a828b 365 #define TSC_GROUP2_IO1 (0x00000010U)
<> 156:95d6b41a828b 366 #define TSC_GROUP2_IO2 (0x00000020U)
<> 156:95d6b41a828b 367 #define TSC_GROUP2_IO3 (0x00000040U)
<> 156:95d6b41a828b 368 #define TSC_GROUP2_IO4 (0x00000080U)
<> 156:95d6b41a828b 369 #define TSC_GROUP2_ALL_IOS (0x000000F0U)
<> 144:ef7eb2e8f9f7 370
<> 156:95d6b41a828b 371 #define TSC_GROUP3_IO1 (0x00000100U)
<> 156:95d6b41a828b 372 #define TSC_GROUP3_IO2 (0x00000200U)
<> 156:95d6b41a828b 373 #define TSC_GROUP3_IO3 (0x00000400U)
<> 156:95d6b41a828b 374 #define TSC_GROUP3_IO4 (0x00000800U)
<> 156:95d6b41a828b 375 #define TSC_GROUP3_ALL_IOS (0x00000F00U)
<> 144:ef7eb2e8f9f7 376
<> 156:95d6b41a828b 377 #define TSC_GROUP4_IO1 (0x00001000U)
<> 156:95d6b41a828b 378 #define TSC_GROUP4_IO2 (0x00002000U)
<> 156:95d6b41a828b 379 #define TSC_GROUP4_IO3 (0x00004000U)
<> 156:95d6b41a828b 380 #define TSC_GROUP4_IO4 (0x00008000U)
<> 156:95d6b41a828b 381 #define TSC_GROUP4_ALL_IOS (0x0000F000U)
<> 144:ef7eb2e8f9f7 382
<> 156:95d6b41a828b 383 #define TSC_GROUP5_IO1 (0x00010000U)
<> 156:95d6b41a828b 384 #define TSC_GROUP5_IO2 (0x00020000U)
<> 156:95d6b41a828b 385 #define TSC_GROUP5_IO3 (0x00040000U)
<> 156:95d6b41a828b 386 #define TSC_GROUP5_IO4 (0x00080000U)
<> 156:95d6b41a828b 387 #define TSC_GROUP5_ALL_IOS (0x000F0000U)
<> 144:ef7eb2e8f9f7 388
<> 156:95d6b41a828b 389 #define TSC_GROUP6_IO1 (0x00100000U)
<> 156:95d6b41a828b 390 #define TSC_GROUP6_IO2 (0x00200000U)
<> 156:95d6b41a828b 391 #define TSC_GROUP6_IO3 (0x00400000U)
<> 156:95d6b41a828b 392 #define TSC_GROUP6_IO4 (0x00800000U)
<> 156:95d6b41a828b 393 #define TSC_GROUP6_ALL_IOS (0x00F00000U)
<> 144:ef7eb2e8f9f7 394
<> 156:95d6b41a828b 395 #define TSC_GROUP7_IO1 (0x01000000U)
<> 156:95d6b41a828b 396 #define TSC_GROUP7_IO2 (0x02000000U)
<> 156:95d6b41a828b 397 #define TSC_GROUP7_IO3 (0x04000000U)
<> 156:95d6b41a828b 398 #define TSC_GROUP7_IO4 (0x08000000U)
<> 156:95d6b41a828b 399 #define TSC_GROUP7_ALL_IOS (0x0F000000U)
<> 144:ef7eb2e8f9f7 400
<> 156:95d6b41a828b 401 #define TSC_GROUP8_IO1 (0x10000000U)
<> 156:95d6b41a828b 402 #define TSC_GROUP8_IO2 (0x20000000U)
<> 156:95d6b41a828b 403 #define TSC_GROUP8_IO3 (0x40000000U)
<> 156:95d6b41a828b 404 #define TSC_GROUP8_IO4 (0x80000000U)
<> 156:95d6b41a828b 405 #define TSC_GROUP8_ALL_IOS (0xF0000000U)
<> 144:ef7eb2e8f9f7 406
<> 156:95d6b41a828b 407 #define TSC_ALL_GROUPS_ALL_IOS (0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 408 /**
<> 144:ef7eb2e8f9f7 409 * @}
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /**
<> 144:ef7eb2e8f9f7 413 * @}
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /* Private macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 417 /** @defgroup TSC_Private_Macros TSC Private Macros
<> 144:ef7eb2e8f9f7 418 * @{
<> 144:ef7eb2e8f9f7 419 */
<> 144:ef7eb2e8f9f7 420 /** @defgroup TSC_Spread_Spectrum TSC Spread Spectrum
<> 144:ef7eb2e8f9f7 421 * @{
<> 144:ef7eb2e8f9f7 422 */
<> 144:ef7eb2e8f9f7 423 #define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
<> 144:ef7eb2e8f9f7 424
<> 156:95d6b41a828b 425 #define IS_TSC_SSD(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < 128U)))
<> 144:ef7eb2e8f9f7 426 /**
<> 144:ef7eb2e8f9f7 427 * @}
<> 144:ef7eb2e8f9f7 428 */
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /**
<> 144:ef7eb2e8f9f7 431 * @}
<> 144:ef7eb2e8f9f7 432 */
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 435 /** @defgroup TSC_Exported_Macros TSC Exported Macros
<> 144:ef7eb2e8f9f7 436 * @{
<> 144:ef7eb2e8f9f7 437 */
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /** @brief Reset TSC handle state
Anna Bridge 180:96ed750bd169 440 * @param __HANDLE__ TSC handle.
<> 144:ef7eb2e8f9f7 441 * @retval None
<> 144:ef7eb2e8f9f7 442 */
<> 144:ef7eb2e8f9f7 443 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /**
<> 144:ef7eb2e8f9f7 446 * @brief Enable the TSC peripheral.
Anna Bridge 180:96ed750bd169 447 * @param __HANDLE__ TSC handle
<> 144:ef7eb2e8f9f7 448 * @retval None
<> 144:ef7eb2e8f9f7 449 */
<> 144:ef7eb2e8f9f7 450 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /**
<> 144:ef7eb2e8f9f7 453 * @brief Disable the TSC peripheral.
Anna Bridge 180:96ed750bd169 454 * @param __HANDLE__ TSC handle
<> 144:ef7eb2e8f9f7 455 * @retval None
<> 144:ef7eb2e8f9f7 456 */
<> 144:ef7eb2e8f9f7 457 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /**
<> 144:ef7eb2e8f9f7 460 * @brief Start acquisition
Anna Bridge 180:96ed750bd169 461 * @param __HANDLE__ TSC handle
<> 144:ef7eb2e8f9f7 462 * @retval None
<> 144:ef7eb2e8f9f7 463 */
<> 144:ef7eb2e8f9f7 464 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /**
<> 144:ef7eb2e8f9f7 467 * @brief Stop acquisition
Anna Bridge 180:96ed750bd169 468 * @param __HANDLE__ TSC handle
<> 144:ef7eb2e8f9f7 469 * @retval None
<> 144:ef7eb2e8f9f7 470 */
<> 144:ef7eb2e8f9f7 471 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 /**
<> 144:ef7eb2e8f9f7 474 * @brief Set IO default mode to output push-pull low
Anna Bridge 180:96ed750bd169 475 * @param __HANDLE__ TSC handle
<> 144:ef7eb2e8f9f7 476 * @retval None
<> 144:ef7eb2e8f9f7 477 */
<> 144:ef7eb2e8f9f7 478 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /**
<> 144:ef7eb2e8f9f7 481 * @brief Set IO default mode to input floating
Anna Bridge 180:96ed750bd169 482 * @param __HANDLE__ TSC handle
<> 144:ef7eb2e8f9f7 483 * @retval None
<> 144:ef7eb2e8f9f7 484 */
<> 144:ef7eb2e8f9f7 485 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /**
<> 144:ef7eb2e8f9f7 488 * @brief Set synchronization polarity to falling edge
Anna Bridge 180:96ed750bd169 489 * @param __HANDLE__ TSC handle
<> 144:ef7eb2e8f9f7 490 * @retval None
<> 144:ef7eb2e8f9f7 491 */
<> 144:ef7eb2e8f9f7 492 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /**
<> 144:ef7eb2e8f9f7 495 * @brief Set synchronization polarity to rising edge and high level
Anna Bridge 180:96ed750bd169 496 * @param __HANDLE__ TSC handle
<> 144:ef7eb2e8f9f7 497 * @retval None
<> 144:ef7eb2e8f9f7 498 */
<> 144:ef7eb2e8f9f7 499 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /**
<> 144:ef7eb2e8f9f7 502 * @brief Enable TSC interrupt.
Anna Bridge 180:96ed750bd169 503 * @param __HANDLE__ TSC handle
Anna Bridge 180:96ed750bd169 504 * @param __INTERRUPT__ TSC interrupt
<> 144:ef7eb2e8f9f7 505 * @retval None
<> 144:ef7eb2e8f9f7 506 */
<> 144:ef7eb2e8f9f7 507 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /**
<> 144:ef7eb2e8f9f7 510 * @brief Disable TSC interrupt.
Anna Bridge 180:96ed750bd169 511 * @param __HANDLE__ TSC handle
Anna Bridge 180:96ed750bd169 512 * @param __INTERRUPT__ TSC interrupt
<> 144:ef7eb2e8f9f7 513 * @retval None
<> 144:ef7eb2e8f9f7 514 */
<> 144:ef7eb2e8f9f7 515 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /** @brief Check if the specified TSC interrupt source is enabled or disabled.
Anna Bridge 180:96ed750bd169 518 * @param __HANDLE__ TSC Handle
Anna Bridge 180:96ed750bd169 519 * @param __INTERRUPT__ TSC interrupt
<> 144:ef7eb2e8f9f7 520 * @retval SET or RESET
<> 144:ef7eb2e8f9f7 521 */
<> 144:ef7eb2e8f9f7 522 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /**
<> 144:ef7eb2e8f9f7 525 * @brief Get the selected TSC's flag status.
Anna Bridge 180:96ed750bd169 526 * @param __HANDLE__ TSC handle
Anna Bridge 180:96ed750bd169 527 * @param __FLAG__ TSC flag
<> 144:ef7eb2e8f9f7 528 * @retval SET or RESET
<> 144:ef7eb2e8f9f7 529 */
<> 144:ef7eb2e8f9f7 530 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /**
<> 144:ef7eb2e8f9f7 533 * @brief Clear the TSC's pending flag.
Anna Bridge 180:96ed750bd169 534 * @param __HANDLE__ TSC handle
Anna Bridge 180:96ed750bd169 535 * @param __FLAG__ TSC flag
<> 144:ef7eb2e8f9f7 536 * @retval None
<> 144:ef7eb2e8f9f7 537 */
<> 144:ef7eb2e8f9f7 538 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /**
<> 144:ef7eb2e8f9f7 541 * @brief Enable schmitt trigger hysteresis on a group of IOs
Anna Bridge 180:96ed750bd169 542 * @param __HANDLE__ TSC handle
Anna Bridge 180:96ed750bd169 543 * @param __GX_IOY_MASK__ IOs mask
<> 144:ef7eb2e8f9f7 544 * @retval None
<> 144:ef7eb2e8f9f7 545 */
<> 144:ef7eb2e8f9f7 546 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 /**
<> 144:ef7eb2e8f9f7 549 * @brief Disable schmitt trigger hysteresis on a group of IOs
Anna Bridge 180:96ed750bd169 550 * @param __HANDLE__ TSC handle
Anna Bridge 180:96ed750bd169 551 * @param __GX_IOY_MASK__ IOs mask
<> 144:ef7eb2e8f9f7 552 * @retval None
<> 144:ef7eb2e8f9f7 553 */
<> 144:ef7eb2e8f9f7 554 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /**
<> 144:ef7eb2e8f9f7 557 * @brief Open analog switch on a group of IOs
Anna Bridge 180:96ed750bd169 558 * @param __HANDLE__ TSC handle
Anna Bridge 180:96ed750bd169 559 * @param __GX_IOY_MASK__ IOs mask
<> 144:ef7eb2e8f9f7 560 * @retval None
<> 144:ef7eb2e8f9f7 561 */
<> 144:ef7eb2e8f9f7 562 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 /**
<> 144:ef7eb2e8f9f7 565 * @brief Close analog switch on a group of IOs
Anna Bridge 180:96ed750bd169 566 * @param __HANDLE__ TSC handle
Anna Bridge 180:96ed750bd169 567 * @param __GX_IOY_MASK__ IOs mask
<> 144:ef7eb2e8f9f7 568 * @retval None
<> 144:ef7eb2e8f9f7 569 */
<> 144:ef7eb2e8f9f7 570 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /**
<> 144:ef7eb2e8f9f7 573 * @brief Enable a group of IOs in channel mode
Anna Bridge 180:96ed750bd169 574 * @param __HANDLE__ TSC handle
Anna Bridge 180:96ed750bd169 575 * @param __GX_IOY_MASK__ IOs mask
<> 144:ef7eb2e8f9f7 576 * @retval None
<> 144:ef7eb2e8f9f7 577 */
<> 144:ef7eb2e8f9f7 578 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /**
<> 144:ef7eb2e8f9f7 581 * @brief Disable a group of channel IOs
Anna Bridge 180:96ed750bd169 582 * @param __HANDLE__ TSC handle
Anna Bridge 180:96ed750bd169 583 * @param __GX_IOY_MASK__ IOs mask
<> 144:ef7eb2e8f9f7 584 * @retval None
<> 144:ef7eb2e8f9f7 585 */
<> 144:ef7eb2e8f9f7 586 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /**
<> 144:ef7eb2e8f9f7 589 * @brief Enable a group of IOs in sampling mode
Anna Bridge 180:96ed750bd169 590 * @param __HANDLE__ TSC handle
Anna Bridge 180:96ed750bd169 591 * @param __GX_IOY_MASK__ IOs mask
<> 144:ef7eb2e8f9f7 592 * @retval None
<> 144:ef7eb2e8f9f7 593 */
<> 144:ef7eb2e8f9f7 594 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /**
<> 144:ef7eb2e8f9f7 597 * @brief Disable a group of sampling IOs
Anna Bridge 180:96ed750bd169 598 * @param __HANDLE__ TSC handle
Anna Bridge 180:96ed750bd169 599 * @param __GX_IOY_MASK__ IOs mask
<> 144:ef7eb2e8f9f7 600 * @retval None
<> 144:ef7eb2e8f9f7 601 */
<> 144:ef7eb2e8f9f7 602 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /**
<> 144:ef7eb2e8f9f7 605 * @brief Enable acquisition groups
Anna Bridge 180:96ed750bd169 606 * @param __HANDLE__ TSC handle
Anna Bridge 180:96ed750bd169 607 * @param __GX_MASK__ Groups mask
<> 144:ef7eb2e8f9f7 608 * @retval None
<> 144:ef7eb2e8f9f7 609 */
<> 144:ef7eb2e8f9f7 610 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /**
<> 144:ef7eb2e8f9f7 613 * @brief Disable acquisition groups
Anna Bridge 180:96ed750bd169 614 * @param __HANDLE__ TSC handle
Anna Bridge 180:96ed750bd169 615 * @param __GX_MASK__ Groups mask
<> 144:ef7eb2e8f9f7 616 * @retval None
<> 144:ef7eb2e8f9f7 617 */
<> 144:ef7eb2e8f9f7 618 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /** @brief Gets acquisition group status
Anna Bridge 180:96ed750bd169 621 * @param __HANDLE__ TSC Handle
Anna Bridge 180:96ed750bd169 622 * @param __GX_INDEX__ Group index
<> 144:ef7eb2e8f9f7 623 * @retval SET or RESET
<> 144:ef7eb2e8f9f7 624 */
<> 144:ef7eb2e8f9f7 625 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
<> 144:ef7eb2e8f9f7 626 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /**
<> 144:ef7eb2e8f9f7 629 * @}
<> 144:ef7eb2e8f9f7 630 */
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 633 /** @addtogroup TSC_Exported_Functions TSC Exported Functions
<> 144:ef7eb2e8f9f7 634 * @{
<> 144:ef7eb2e8f9f7 635 */
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /** @addtogroup TSC_Exported_Functions_Group1 Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 638 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 639 * @{
<> 144:ef7eb2e8f9f7 640 */
<> 144:ef7eb2e8f9f7 641 /* Initialization and de-initialization functions *****************************/
<> 144:ef7eb2e8f9f7 642 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 643 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
<> 144:ef7eb2e8f9f7 644 void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 645 void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 646 /**
<> 144:ef7eb2e8f9f7 647 * @}
<> 144:ef7eb2e8f9f7 648 */
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /** @addtogroup TSC_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 651 * @brief IO operation functions * @{
<> 144:ef7eb2e8f9f7 652 */
<> 144:ef7eb2e8f9f7 653 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 654 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 655 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 656 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 657 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 658 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index);
<> 144:ef7eb2e8f9f7 659 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index);
<> 144:ef7eb2e8f9f7 660 /**
<> 144:ef7eb2e8f9f7 661 * @}
<> 144:ef7eb2e8f9f7 662 */
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 665 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 666 * @{
<> 144:ef7eb2e8f9f7 667 */
<> 144:ef7eb2e8f9f7 668 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 669 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config);
<> 144:ef7eb2e8f9f7 670 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice);
<> 144:ef7eb2e8f9f7 671 /**
<> 144:ef7eb2e8f9f7 672 * @}
<> 144:ef7eb2e8f9f7 673 */
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /** @addtogroup TSC_Exported_Functions_Group4 State functions
<> 144:ef7eb2e8f9f7 676 * @brief State functions
<> 144:ef7eb2e8f9f7 677 * @{
<> 144:ef7eb2e8f9f7 678 */
<> 144:ef7eb2e8f9f7 679 /* Peripheral State and Error functions ***************************************/
<> 144:ef7eb2e8f9f7 680 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 681 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 682 void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 683 /**
<> 144:ef7eb2e8f9f7 684 * @}
<> 144:ef7eb2e8f9f7 685 */
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /** @addtogroup TSC_Exported_Functions_Group5 Callback functions
<> 144:ef7eb2e8f9f7 688 * @brief Callback functions
<> 144:ef7eb2e8f9f7 689 * @{
<> 144:ef7eb2e8f9f7 690 */
<> 144:ef7eb2e8f9f7 691 /* Callback functions *********************************************************/
<> 144:ef7eb2e8f9f7 692 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 693 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc);
<> 144:ef7eb2e8f9f7 694 /**
<> 144:ef7eb2e8f9f7 695 * @}
<> 144:ef7eb2e8f9f7 696 */
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /**
<> 144:ef7eb2e8f9f7 699 * @}
<> 144:ef7eb2e8f9f7 700 */
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /**
<> 144:ef7eb2e8f9f7 703 * @}
<> 144:ef7eb2e8f9f7 704 */
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /**
<> 144:ef7eb2e8f9f7 707 * @}
<> 144:ef7eb2e8f9f7 708 */
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 #endif /* defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || */
<> 144:ef7eb2e8f9f7 711 /* defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || */
<> 144:ef7eb2e8f9f7 712 /* defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx) */
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 716 }
<> 144:ef7eb2e8f9f7 717 #endif
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 #endif /*__STM32F0xx_TSC_H */
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 722