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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_tim_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief TIM HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the Timer Extended peripheral:
<> 144:ef7eb2e8f9f7 8 * + Time Hall Sensor Interface Initialization
<> 144:ef7eb2e8f9f7 9 * + Time Hall Sensor Interface Start
<> 144:ef7eb2e8f9f7 10 * + Time Complementary signal bread and dead time configuration
<> 144:ef7eb2e8f9f7 11 * + Time Master and Slave synchronization configuration
<> 144:ef7eb2e8f9f7 12 * + Timer remapping capabilities configuration
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### TIMER Extended features #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 The Timer Extended features include:
<> 144:ef7eb2e8f9f7 19 (#) Complementary outputs with programmable dead-time for :
<> 144:ef7eb2e8f9f7 20 (++) Output Compare
<> 144:ef7eb2e8f9f7 21 (++) PWM generation (Edge and Center-aligned Mode)
<> 144:ef7eb2e8f9f7 22 (++) One-pulse mode output
<> 144:ef7eb2e8f9f7 23 (#) Synchronization circuit to control the timer with external signals and to
<> 144:ef7eb2e8f9f7 24 interconnect several timers together.
<> 144:ef7eb2e8f9f7 25 (#) Break input to put the timer output signals in reset state or in a known state.
<> 144:ef7eb2e8f9f7 26 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
<> 144:ef7eb2e8f9f7 27 positioning purposes
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 30 ==============================================================================
<> 144:ef7eb2e8f9f7 31 [..]
<> 144:ef7eb2e8f9f7 32 (#) Initialize the TIM low level resources by implementing the following functions
<> 144:ef7eb2e8f9f7 33 depending from feature used :
<> 144:ef7eb2e8f9f7 34 (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
<> 144:ef7eb2e8f9f7 35 (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
<> 144:ef7eb2e8f9f7 36 (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<> 144:ef7eb2e8f9f7 37 (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 (#) Initialize the TIM low level resources :
<> 144:ef7eb2e8f9f7 40 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 41 (##) TIM pins configuration
<> 144:ef7eb2e8f9f7 42 (+++) Enable the clock for the TIM GPIOs using the following function:
<> 144:ef7eb2e8f9f7 43 __HAL_RCC_GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 44 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 (#) The external Clock can be configured, if needed (the default clock is the
<> 144:ef7eb2e8f9f7 47 internal clock from the APBx), using the following function:
<> 144:ef7eb2e8f9f7 48 HAL_TIM_ConfigClockSource, the clock configuration should be done before
<> 144:ef7eb2e8f9f7 49 any start function.
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 (#) Configure the TIM in the desired functioning mode using one of the
<> 144:ef7eb2e8f9f7 52 initialization function of this driver:
<> 144:ef7eb2e8f9f7 53 (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
<> 144:ef7eb2e8f9f7 54 Timer Hall Sensor Interface and the commutation event with the corresponding
<> 144:ef7eb2e8f9f7 55 Interrupt and DMA request if needed (Note that One Timer is used to interface
<> 144:ef7eb2e8f9f7 56 with the Hall sensor Interface and another Timer should be used to use
<> 144:ef7eb2e8f9f7 57 the commutation event).
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 (#) Activate the TIM peripheral using one of the start functions:
<> 144:ef7eb2e8f9f7 60 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
<> 144:ef7eb2e8f9f7 61 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
<> 144:ef7eb2e8f9f7 62 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
<> 144:ef7eb2e8f9f7 63 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 @endverbatim
<> 144:ef7eb2e8f9f7 67 ******************************************************************************
<> 144:ef7eb2e8f9f7 68 * @attention
<> 144:ef7eb2e8f9f7 69 *
<> 144:ef7eb2e8f9f7 70 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 71 *
<> 144:ef7eb2e8f9f7 72 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 73 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 74 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 75 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 76 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 77 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 78 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 79 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 80 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 81 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 82 *
<> 144:ef7eb2e8f9f7 83 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 84 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 86 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 89 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 90 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 91 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 92 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 93 *
<> 144:ef7eb2e8f9f7 94 ******************************************************************************
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 98 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 101 * @{
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /** @defgroup TIMEx TIMEx
<> 144:ef7eb2e8f9f7 105 * @brief TIM Extended HAL module driver
<> 144:ef7eb2e8f9f7 106 * @{
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 #ifdef HAL_TIM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 112 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 113 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 114 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
<> 144:ef7eb2e8f9f7 118 * @{
<> 144:ef7eb2e8f9f7 119 */
<> 144:ef7eb2e8f9f7 120 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
<> 144:ef7eb2e8f9f7 121 /**
<> 144:ef7eb2e8f9f7 122 * @}
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
<> 144:ef7eb2e8f9f7 128 * @{
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 132 * @brief Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 133 *
<> 144:ef7eb2e8f9f7 134 @verbatim
<> 144:ef7eb2e8f9f7 135 ==============================================================================
<> 144:ef7eb2e8f9f7 136 ##### Timer Hall Sensor functions #####
<> 144:ef7eb2e8f9f7 137 ==============================================================================
<> 144:ef7eb2e8f9f7 138 [..]
<> 144:ef7eb2e8f9f7 139 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 140 (+) Initialize and configure TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 141 (+) De-initialize TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 142 (+) Start the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 143 (+) Stop the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 144 (+) Start the Hall Sensor Interface and enable interrupts.
<> 144:ef7eb2e8f9f7 145 (+) Stop the Hall Sensor Interface and disable interrupts.
<> 144:ef7eb2e8f9f7 146 (+) Start the Hall Sensor Interface and enable DMA transfers.
<> 144:ef7eb2e8f9f7 147 (+) Stop the Hall Sensor Interface and disable DMA transfers.
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 @endverbatim
<> 144:ef7eb2e8f9f7 150 * @{
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152 /**
<> 144:ef7eb2e8f9f7 153 * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
Anna Bridge 180:96ed750bd169 154 * @param htim TIM Encoder Interface handle
Anna Bridge 180:96ed750bd169 155 * @param sConfig TIM Hall Sensor configuration structure
<> 144:ef7eb2e8f9f7 156 * @retval HAL status
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 159 {
<> 144:ef7eb2e8f9f7 160 TIM_OC_InitTypeDef OC_Config;
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 163 if(htim == NULL)
<> 144:ef7eb2e8f9f7 164 {
<> 144:ef7eb2e8f9f7 165 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 166 }
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 169 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 170 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 171 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<> 144:ef7eb2e8f9f7 172 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<> 144:ef7eb2e8f9f7 173 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<> 156:95d6b41a828b 174 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 177 {
<> 144:ef7eb2e8f9f7 178 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 179 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 182 HAL_TIMEx_HallSensor_MspInit(htim);
<> 144:ef7eb2e8f9f7 183 }
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 186 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /* Configure the Time base in the Encoder Mode */
<> 144:ef7eb2e8f9f7 189 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
<> 144:ef7eb2e8f9f7 192 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 195 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 196 /* Set the IC1PSC value */
<> 144:ef7eb2e8f9f7 197 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /* Enable the Hall sensor interface (XOR function of the three inputs) */
<> 144:ef7eb2e8f9f7 200 htim->Instance->CR2 |= TIM_CR2_TI1S;
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
<> 144:ef7eb2e8f9f7 203 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 204 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
<> 144:ef7eb2e8f9f7 207 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 208 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
<> 144:ef7eb2e8f9f7 211 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
<> 144:ef7eb2e8f9f7 212 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 213 OC_Config.OCMode = TIM_OCMODE_PWM2;
<> 144:ef7eb2e8f9f7 214 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 215 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 216 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 217 OC_Config.Pulse = sConfig->Commutation_Delay;
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
<> 144:ef7eb2e8f9f7 222 register to 101 */
<> 144:ef7eb2e8f9f7 223 htim->Instance->CR2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 224 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 227 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 return HAL_OK;
<> 144:ef7eb2e8f9f7 230 }
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /**
<> 144:ef7eb2e8f9f7 233 * @brief DeInitializes the TIM Hall Sensor interface
Anna Bridge 180:96ed750bd169 234 * @param htim TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 235 * @retval HAL status
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 /* Check the parameters */
<> 144:ef7eb2e8f9f7 240 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 245 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 248 HAL_TIMEx_HallSensor_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /* Change TIM state */
<> 144:ef7eb2e8f9f7 251 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /* Release Lock */
<> 144:ef7eb2e8f9f7 254 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 return HAL_OK;
<> 144:ef7eb2e8f9f7 257 }
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /**
<> 144:ef7eb2e8f9f7 260 * @brief Initializes the TIM Hall Sensor MSP.
Anna Bridge 180:96ed750bd169 261 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 262 * @retval None
<> 144:ef7eb2e8f9f7 263 */
<> 144:ef7eb2e8f9f7 264 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 265 {
<> 144:ef7eb2e8f9f7 266 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 267 UNUSED(htim);
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 270 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @brief DeInitializes TIM Hall Sensor MSP.
Anna Bridge 180:96ed750bd169 276 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 277 * @retval None
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 282 UNUSED(htim);
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 285 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /**
<> 144:ef7eb2e8f9f7 290 * @brief Starts the TIM Hall Sensor Interface.
Anna Bridge 180:96ed750bd169 291 * @param htim TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 292 * @retval HAL status
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 295 {
<> 144:ef7eb2e8f9f7 296 /* Check the parameters */
<> 144:ef7eb2e8f9f7 297 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /* Enable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 300 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 301 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 304 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /* Return function status */
<> 144:ef7eb2e8f9f7 307 return HAL_OK;
<> 144:ef7eb2e8f9f7 308 }
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /**
<> 144:ef7eb2e8f9f7 311 * @brief Stops the TIM Hall sensor Interface.
Anna Bridge 180:96ed750bd169 312 * @param htim TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 313 * @retval HAL status
<> 144:ef7eb2e8f9f7 314 */
<> 144:ef7eb2e8f9f7 315 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 316 {
<> 144:ef7eb2e8f9f7 317 /* Check the parameters */
<> 144:ef7eb2e8f9f7 318 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /* Disable the Input Capture channels 1, 2 and 3
<> 144:ef7eb2e8f9f7 321 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 322 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 325 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /* Return function status */
<> 144:ef7eb2e8f9f7 328 return HAL_OK;
<> 144:ef7eb2e8f9f7 329 }
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /**
<> 144:ef7eb2e8f9f7 332 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
Anna Bridge 180:96ed750bd169 333 * @param htim TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 334 * @retval HAL status
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 337 {
<> 144:ef7eb2e8f9f7 338 /* Check the parameters */
<> 144:ef7eb2e8f9f7 339 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /* Enable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 342 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /* Enable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 345 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 346 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 349 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /* Return function status */
<> 144:ef7eb2e8f9f7 352 return HAL_OK;
<> 144:ef7eb2e8f9f7 353 }
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /**
<> 144:ef7eb2e8f9f7 356 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
Anna Bridge 180:96ed750bd169 357 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 358 * @retval HAL status
<> 144:ef7eb2e8f9f7 359 */
<> 144:ef7eb2e8f9f7 360 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 361 {
<> 144:ef7eb2e8f9f7 362 /* Check the parameters */
<> 144:ef7eb2e8f9f7 363 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /* Disable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 366 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 367 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* Disable the capture compare Interrupts event */
<> 144:ef7eb2e8f9f7 370 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 373 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* Return function status */
<> 144:ef7eb2e8f9f7 376 return HAL_OK;
<> 144:ef7eb2e8f9f7 377 }
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /**
<> 144:ef7eb2e8f9f7 380 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
Anna Bridge 180:96ed750bd169 381 * @param htim TIM Hall Sensor handle
Anna Bridge 180:96ed750bd169 382 * @param pData The destination Buffer address.
Anna Bridge 180:96ed750bd169 383 * @param Length The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 384 * @retval HAL status
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 387 {
<> 144:ef7eb2e8f9f7 388 /* Check the parameters */
<> 144:ef7eb2e8f9f7 389 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 392 {
<> 144:ef7eb2e8f9f7 393 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 394 }
<> 144:ef7eb2e8f9f7 395 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 396 {
<> 156:95d6b41a828b 397 if(((uint32_t)pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 398 {
<> 144:ef7eb2e8f9f7 399 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 400 }
<> 144:ef7eb2e8f9f7 401 else
<> 144:ef7eb2e8f9f7 402 {
<> 144:ef7eb2e8f9f7 403 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406 /* Enable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 407 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 408 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /* Set the DMA Input Capture 1 Callback */
<> 144:ef7eb2e8f9f7 411 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 412 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 413 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /* Enable the DMA channel for Capture 1*/
<> 144:ef7eb2e8f9f7 416 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /* Enable the capture compare 1 Interrupt */
<> 144:ef7eb2e8f9f7 419 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 422 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Return function status */
<> 144:ef7eb2e8f9f7 425 return HAL_OK;
<> 144:ef7eb2e8f9f7 426 }
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /**
<> 144:ef7eb2e8f9f7 429 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
Anna Bridge 180:96ed750bd169 430 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 431 * @retval HAL status
<> 144:ef7eb2e8f9f7 432 */
<> 144:ef7eb2e8f9f7 433 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 434 {
<> 144:ef7eb2e8f9f7 435 /* Check the parameters */
<> 144:ef7eb2e8f9f7 436 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /* Disable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 439 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 440 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /* Disable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 444 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 447 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /* Return function status */
<> 144:ef7eb2e8f9f7 450 return HAL_OK;
<> 144:ef7eb2e8f9f7 451 }
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /**
<> 144:ef7eb2e8f9f7 454 * @}
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 458 * @brief Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 459 *
<> 144:ef7eb2e8f9f7 460 @verbatim
<> 144:ef7eb2e8f9f7 461 ==============================================================================
<> 144:ef7eb2e8f9f7 462 ##### Timer Complementary Output Compare functions #####
<> 144:ef7eb2e8f9f7 463 ==============================================================================
<> 144:ef7eb2e8f9f7 464 [..]
<> 144:ef7eb2e8f9f7 465 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 466 (+) Start the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 467 (+) Stop the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 468 (+) Start the Complementary Output Compare/PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 469 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 470 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 471 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 @endverbatim
<> 144:ef7eb2e8f9f7 474 * @{
<> 144:ef7eb2e8f9f7 475 */
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /**
<> 144:ef7eb2e8f9f7 478 * @brief Starts the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 479 * output.
Anna Bridge 180:96ed750bd169 480 * @param htim TIM Output Compare handle
Anna Bridge 180:96ed750bd169 481 * @param Channel TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 482 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 483 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 484 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 485 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 486 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 487 * @retval HAL status
<> 144:ef7eb2e8f9f7 488 */
<> 144:ef7eb2e8f9f7 489 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 490 {
<> 144:ef7eb2e8f9f7 491 /* Check the parameters */
<> 144:ef7eb2e8f9f7 492 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 495 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 498 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 501 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* Return function status */
<> 144:ef7eb2e8f9f7 504 return HAL_OK;
<> 144:ef7eb2e8f9f7 505 }
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /**
<> 144:ef7eb2e8f9f7 508 * @brief Stops the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 509 * output.
Anna Bridge 180:96ed750bd169 510 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 511 * @param Channel TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 512 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 513 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 514 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 515 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 516 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 517 * @retval HAL status
<> 144:ef7eb2e8f9f7 518 */
<> 144:ef7eb2e8f9f7 519 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 /* Check the parameters */
<> 144:ef7eb2e8f9f7 522 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 525 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 528 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 531 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /* Return function status */
<> 144:ef7eb2e8f9f7 534 return HAL_OK;
<> 144:ef7eb2e8f9f7 535 }
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /**
<> 144:ef7eb2e8f9f7 538 * @brief Starts the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 539 * on the complementary output.
Anna Bridge 180:96ed750bd169 540 * @param htim TIM OC handle
Anna Bridge 180:96ed750bd169 541 * @param Channel TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 542 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 543 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 544 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 545 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 546 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 547 * @retval HAL status
<> 144:ef7eb2e8f9f7 548 */
<> 144:ef7eb2e8f9f7 549 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 550 {
<> 144:ef7eb2e8f9f7 551 /* Check the parameters */
<> 144:ef7eb2e8f9f7 552 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 switch (Channel)
<> 144:ef7eb2e8f9f7 555 {
<> 144:ef7eb2e8f9f7 556 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 559 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 560 }
<> 144:ef7eb2e8f9f7 561 break;
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 564 {
<> 144:ef7eb2e8f9f7 565 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 566 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 567 }
<> 144:ef7eb2e8f9f7 568 break;
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 571 {
<> 144:ef7eb2e8f9f7 572 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 573 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 574 }
<> 144:ef7eb2e8f9f7 575 break;
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 578 {
<> 144:ef7eb2e8f9f7 579 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 580 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 581 }
<> 144:ef7eb2e8f9f7 582 break;
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 default:
<> 144:ef7eb2e8f9f7 585 break;
<> 144:ef7eb2e8f9f7 586 }
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 589 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 592 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 595 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 598 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /* Return function status */
<> 144:ef7eb2e8f9f7 601 return HAL_OK;
<> 144:ef7eb2e8f9f7 602 }
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /**
<> 144:ef7eb2e8f9f7 605 * @brief Stops the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 606 * on the complementary output.
Anna Bridge 180:96ed750bd169 607 * @param htim TIM Output Compare handle
Anna Bridge 180:96ed750bd169 608 * @param Channel TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 609 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 610 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 611 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 612 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 613 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 614 * @retval HAL status
<> 144:ef7eb2e8f9f7 615 */
<> 144:ef7eb2e8f9f7 616 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 617 {
<> 156:95d6b41a828b 618 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /* Check the parameters */
<> 144:ef7eb2e8f9f7 621 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 switch (Channel)
<> 144:ef7eb2e8f9f7 624 {
<> 144:ef7eb2e8f9f7 625 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 626 {
<> 144:ef7eb2e8f9f7 627 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 628 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 629 }
<> 144:ef7eb2e8f9f7 630 break;
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 633 {
<> 144:ef7eb2e8f9f7 634 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 635 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 636 }
<> 144:ef7eb2e8f9f7 637 break;
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 640 {
<> 144:ef7eb2e8f9f7 641 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 642 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 643 }
<> 144:ef7eb2e8f9f7 644 break;
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 647 {
<> 144:ef7eb2e8f9f7 648 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 649 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 650 }
<> 144:ef7eb2e8f9f7 651 break;
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 default:
<> 144:ef7eb2e8f9f7 654 break;
<> 144:ef7eb2e8f9f7 655 }
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 658 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 661 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 662 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 663 {
<> 144:ef7eb2e8f9f7 664 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 665 }
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 668 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 671 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /* Return function status */
<> 144:ef7eb2e8f9f7 674 return HAL_OK;
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /**
<> 144:ef7eb2e8f9f7 678 * @brief Starts the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 679 * on the complementary output.
Anna Bridge 180:96ed750bd169 680 * @param htim TIM Output Compare handle
Anna Bridge 180:96ed750bd169 681 * @param Channel TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 682 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 683 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 684 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 685 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 686 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
Anna Bridge 180:96ed750bd169 687 * @param pData The source Buffer address.
Anna Bridge 180:96ed750bd169 688 * @param Length The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 689 * @retval HAL status
<> 144:ef7eb2e8f9f7 690 */
<> 144:ef7eb2e8f9f7 691 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 692 {
<> 144:ef7eb2e8f9f7 693 /* Check the parameters */
<> 144:ef7eb2e8f9f7 694 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 697 {
<> 144:ef7eb2e8f9f7 698 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 699 }
<> 144:ef7eb2e8f9f7 700 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 701 {
<> 156:95d6b41a828b 702 if(((uint32_t)pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 703 {
<> 144:ef7eb2e8f9f7 704 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 705 }
<> 144:ef7eb2e8f9f7 706 else
<> 144:ef7eb2e8f9f7 707 {
<> 144:ef7eb2e8f9f7 708 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 709 }
<> 144:ef7eb2e8f9f7 710 }
<> 144:ef7eb2e8f9f7 711 switch (Channel)
<> 144:ef7eb2e8f9f7 712 {
<> 144:ef7eb2e8f9f7 713 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 714 {
<> 144:ef7eb2e8f9f7 715 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 716 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 719 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 722 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 725 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 726 }
<> 144:ef7eb2e8f9f7 727 break;
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 732 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 735 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 738 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 741 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 742 }
<> 144:ef7eb2e8f9f7 743 break;
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 746 {
<> 144:ef7eb2e8f9f7 747 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 748 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 751 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 754 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 757 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 758 }
<> 144:ef7eb2e8f9f7 759 break;
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 762 {
<> 144:ef7eb2e8f9f7 763 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 764 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 767 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 770 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 773 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 774 }
<> 144:ef7eb2e8f9f7 775 break;
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 default:
<> 144:ef7eb2e8f9f7 778 break;
<> 144:ef7eb2e8f9f7 779 }
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 782 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 785 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 788 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 /* Return function status */
<> 144:ef7eb2e8f9f7 791 return HAL_OK;
<> 144:ef7eb2e8f9f7 792 }
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794 /**
<> 144:ef7eb2e8f9f7 795 * @brief Stops the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 796 * on the complementary output.
Anna Bridge 180:96ed750bd169 797 * @param htim TIM Output Compare handle
Anna Bridge 180:96ed750bd169 798 * @param Channel TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 799 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 800 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 801 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 802 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 803 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 804 * @retval HAL status
<> 144:ef7eb2e8f9f7 805 */
<> 144:ef7eb2e8f9f7 806 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 807 {
<> 144:ef7eb2e8f9f7 808 /* Check the parameters */
<> 144:ef7eb2e8f9f7 809 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 switch (Channel)
<> 144:ef7eb2e8f9f7 812 {
<> 144:ef7eb2e8f9f7 813 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 814 {
<> 144:ef7eb2e8f9f7 815 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 816 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 817 }
<> 144:ef7eb2e8f9f7 818 break;
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 821 {
<> 144:ef7eb2e8f9f7 822 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 823 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 824 }
<> 144:ef7eb2e8f9f7 825 break;
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 828 {
<> 144:ef7eb2e8f9f7 829 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 830 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 831 }
<> 144:ef7eb2e8f9f7 832 break;
<> 144:ef7eb2e8f9f7 833
<> 144:ef7eb2e8f9f7 834 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 835 {
<> 144:ef7eb2e8f9f7 836 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 837 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 838 }
<> 144:ef7eb2e8f9f7 839 break;
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 default:
<> 144:ef7eb2e8f9f7 842 break;
<> 144:ef7eb2e8f9f7 843 }
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 846 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 849 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 852 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 /* Change the htim state */
<> 144:ef7eb2e8f9f7 855 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 /* Return function status */
<> 144:ef7eb2e8f9f7 858 return HAL_OK;
<> 144:ef7eb2e8f9f7 859 }
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /**
<> 144:ef7eb2e8f9f7 862 * @}
<> 144:ef7eb2e8f9f7 863 */
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 866 * @brief Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 867 *
<> 144:ef7eb2e8f9f7 868 @verbatim
<> 144:ef7eb2e8f9f7 869 ==============================================================================
<> 144:ef7eb2e8f9f7 870 ##### Timer Complementary PWM functions #####
<> 144:ef7eb2e8f9f7 871 ==============================================================================
<> 144:ef7eb2e8f9f7 872 [..]
<> 144:ef7eb2e8f9f7 873 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 874 (+) Start the Complementary PWM.
<> 144:ef7eb2e8f9f7 875 (+) Stop the Complementary PWM.
<> 144:ef7eb2e8f9f7 876 (+) Start the Complementary PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 877 (+) Stop the Complementary PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 878 (+) Start the Complementary PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 879 (+) Stop the Complementary PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 880 (+) Start the Complementary Input Capture measurement.
<> 144:ef7eb2e8f9f7 881 (+) Stop the Complementary Input Capture.
<> 144:ef7eb2e8f9f7 882 (+) Start the Complementary Input Capture and enable interrupts.
<> 144:ef7eb2e8f9f7 883 (+) Stop the Complementary Input Capture and disable interrupts.
<> 144:ef7eb2e8f9f7 884 (+) Start the Complementary Input Capture and enable DMA transfers.
<> 144:ef7eb2e8f9f7 885 (+) Stop the Complementary Input Capture and disable DMA transfers.
<> 144:ef7eb2e8f9f7 886 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 887 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 888 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 889 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 @endverbatim
<> 144:ef7eb2e8f9f7 892 * @{
<> 144:ef7eb2e8f9f7 893 */
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 /**
<> 144:ef7eb2e8f9f7 896 * @brief Starts the PWM signal generation on the complementary output.
Anna Bridge 180:96ed750bd169 897 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 898 * @param Channel TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 899 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 900 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 901 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 902 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 903 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 904 * @retval HAL status
<> 144:ef7eb2e8f9f7 905 */
<> 144:ef7eb2e8f9f7 906 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 907 {
<> 144:ef7eb2e8f9f7 908 /* Check the parameters */
<> 144:ef7eb2e8f9f7 909 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 912 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 915 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 918 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 /* Return function status */
<> 144:ef7eb2e8f9f7 921 return HAL_OK;
<> 144:ef7eb2e8f9f7 922 }
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /**
<> 144:ef7eb2e8f9f7 925 * @brief Stops the PWM signal generation on the complementary output.
Anna Bridge 180:96ed750bd169 926 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 927 * @param Channel TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 928 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 929 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 930 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 931 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 932 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 933 * @retval HAL status
<> 144:ef7eb2e8f9f7 934 */
<> 144:ef7eb2e8f9f7 935 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 936 {
<> 144:ef7eb2e8f9f7 937 /* Check the parameters */
<> 144:ef7eb2e8f9f7 938 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 939
<> 144:ef7eb2e8f9f7 940 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 941 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 942
<> 144:ef7eb2e8f9f7 943 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 944 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 945
<> 144:ef7eb2e8f9f7 946 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 947 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949 /* Return function status */
<> 144:ef7eb2e8f9f7 950 return HAL_OK;
<> 144:ef7eb2e8f9f7 951 }
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /**
<> 144:ef7eb2e8f9f7 954 * @brief Starts the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 955 * complementary output.
Anna Bridge 180:96ed750bd169 956 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 957 * @param Channel TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 958 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 959 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 960 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 961 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 962 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 963 * @retval HAL status
<> 144:ef7eb2e8f9f7 964 */
<> 144:ef7eb2e8f9f7 965 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 966 {
<> 144:ef7eb2e8f9f7 967 /* Check the parameters */
<> 144:ef7eb2e8f9f7 968 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 969
<> 144:ef7eb2e8f9f7 970 switch (Channel)
<> 144:ef7eb2e8f9f7 971 {
<> 144:ef7eb2e8f9f7 972 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 973 {
<> 144:ef7eb2e8f9f7 974 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 975 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 976 }
<> 144:ef7eb2e8f9f7 977 break;
<> 144:ef7eb2e8f9f7 978
<> 144:ef7eb2e8f9f7 979 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 980 {
<> 144:ef7eb2e8f9f7 981 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 982 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 983 }
<> 144:ef7eb2e8f9f7 984 break;
<> 144:ef7eb2e8f9f7 985
<> 144:ef7eb2e8f9f7 986 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 987 {
<> 144:ef7eb2e8f9f7 988 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 989 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 990 }
<> 144:ef7eb2e8f9f7 991 break;
<> 144:ef7eb2e8f9f7 992
<> 144:ef7eb2e8f9f7 993 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 994 {
<> 144:ef7eb2e8f9f7 995 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 996 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 997 }
<> 144:ef7eb2e8f9f7 998 break;
<> 144:ef7eb2e8f9f7 999
<> 144:ef7eb2e8f9f7 1000 default:
<> 144:ef7eb2e8f9f7 1001 break;
<> 144:ef7eb2e8f9f7 1002 }
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 1005 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1008 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1011 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1014 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 /* Return function status */
<> 144:ef7eb2e8f9f7 1017 return HAL_OK;
<> 144:ef7eb2e8f9f7 1018 }
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 /**
<> 144:ef7eb2e8f9f7 1021 * @brief Stops the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1022 * complementary output.
Anna Bridge 180:96ed750bd169 1023 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 1024 * @param Channel TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1025 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1026 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1027 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1028 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1029 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1030 * @retval HAL status
<> 144:ef7eb2e8f9f7 1031 */
<> 144:ef7eb2e8f9f7 1032 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1033 {
<> 156:95d6b41a828b 1034 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 1035
<> 144:ef7eb2e8f9f7 1036 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1037 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1038
<> 144:ef7eb2e8f9f7 1039 switch (Channel)
<> 144:ef7eb2e8f9f7 1040 {
<> 144:ef7eb2e8f9f7 1041 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1042 {
<> 144:ef7eb2e8f9f7 1043 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1044 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1045 }
<> 144:ef7eb2e8f9f7 1046 break;
<> 144:ef7eb2e8f9f7 1047
<> 144:ef7eb2e8f9f7 1048 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1049 {
<> 144:ef7eb2e8f9f7 1050 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1051 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1052 }
<> 144:ef7eb2e8f9f7 1053 break;
<> 144:ef7eb2e8f9f7 1054
<> 144:ef7eb2e8f9f7 1055 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1056 {
<> 144:ef7eb2e8f9f7 1057 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1058 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1059 }
<> 144:ef7eb2e8f9f7 1060 break;
<> 144:ef7eb2e8f9f7 1061
<> 144:ef7eb2e8f9f7 1062 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1063 {
<> 144:ef7eb2e8f9f7 1064 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1065 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1066 }
<> 144:ef7eb2e8f9f7 1067 break;
<> 144:ef7eb2e8f9f7 1068
<> 144:ef7eb2e8f9f7 1069 default:
<> 144:ef7eb2e8f9f7 1070 break;
<> 144:ef7eb2e8f9f7 1071 }
<> 144:ef7eb2e8f9f7 1072
<> 144:ef7eb2e8f9f7 1073 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1074 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1075
<> 144:ef7eb2e8f9f7 1076 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 1077 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 1078 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 1079 {
<> 144:ef7eb2e8f9f7 1080 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1081 }
<> 144:ef7eb2e8f9f7 1082
<> 144:ef7eb2e8f9f7 1083 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1084 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1085
<> 144:ef7eb2e8f9f7 1086 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1087 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1088
<> 144:ef7eb2e8f9f7 1089 /* Return function status */
<> 144:ef7eb2e8f9f7 1090 return HAL_OK;
<> 144:ef7eb2e8f9f7 1091 }
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /**
<> 144:ef7eb2e8f9f7 1094 * @brief Starts the TIM PWM signal generation in DMA mode on the
<> 144:ef7eb2e8f9f7 1095 * complementary output
Anna Bridge 180:96ed750bd169 1096 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 1097 * @param Channel TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1098 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1099 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1100 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1101 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1102 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
Anna Bridge 180:96ed750bd169 1103 * @param pData The source Buffer address.
Anna Bridge 180:96ed750bd169 1104 * @param Length The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 1105 * @retval HAL status
<> 144:ef7eb2e8f9f7 1106 */
<> 144:ef7eb2e8f9f7 1107 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1108 {
<> 144:ef7eb2e8f9f7 1109 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1110 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1111
<> 144:ef7eb2e8f9f7 1112 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1113 {
<> 144:ef7eb2e8f9f7 1114 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1115 }
<> 144:ef7eb2e8f9f7 1116 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1117 {
<> 156:95d6b41a828b 1118 if(((uint32_t)pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 1119 {
<> 144:ef7eb2e8f9f7 1120 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1121 }
<> 144:ef7eb2e8f9f7 1122 else
<> 144:ef7eb2e8f9f7 1123 {
<> 144:ef7eb2e8f9f7 1124 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1125 }
<> 144:ef7eb2e8f9f7 1126 }
<> 144:ef7eb2e8f9f7 1127 switch (Channel)
<> 144:ef7eb2e8f9f7 1128 {
<> 144:ef7eb2e8f9f7 1129 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1130 {
<> 144:ef7eb2e8f9f7 1131 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1132 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1133
<> 144:ef7eb2e8f9f7 1134 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1135 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1136
<> 144:ef7eb2e8f9f7 1137 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1138 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 1139
<> 144:ef7eb2e8f9f7 1140 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1141 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1142 }
<> 144:ef7eb2e8f9f7 1143 break;
<> 144:ef7eb2e8f9f7 1144
<> 144:ef7eb2e8f9f7 1145 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1146 {
<> 144:ef7eb2e8f9f7 1147 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1148 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1149
<> 144:ef7eb2e8f9f7 1150 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1151 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1152
<> 144:ef7eb2e8f9f7 1153 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1154 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1157 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1158 }
<> 144:ef7eb2e8f9f7 1159 break;
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1162 {
<> 144:ef7eb2e8f9f7 1163 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1164 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1165
<> 144:ef7eb2e8f9f7 1166 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1167 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1168
<> 144:ef7eb2e8f9f7 1169 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1170 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 1171
<> 144:ef7eb2e8f9f7 1172 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1173 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1174 }
<> 144:ef7eb2e8f9f7 1175 break;
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1178 {
<> 144:ef7eb2e8f9f7 1179 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1180 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1183 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1184
<> 144:ef7eb2e8f9f7 1185 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1186 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 1187
<> 144:ef7eb2e8f9f7 1188 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1189 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1190 }
<> 144:ef7eb2e8f9f7 1191 break;
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 default:
<> 144:ef7eb2e8f9f7 1194 break;
<> 144:ef7eb2e8f9f7 1195 }
<> 144:ef7eb2e8f9f7 1196
<> 144:ef7eb2e8f9f7 1197 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1198 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1199
<> 144:ef7eb2e8f9f7 1200 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1201 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1202
<> 144:ef7eb2e8f9f7 1203 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1204 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1205
<> 144:ef7eb2e8f9f7 1206 /* Return function status */
<> 144:ef7eb2e8f9f7 1207 return HAL_OK;
<> 144:ef7eb2e8f9f7 1208 }
<> 144:ef7eb2e8f9f7 1209
<> 144:ef7eb2e8f9f7 1210 /**
<> 144:ef7eb2e8f9f7 1211 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
<> 144:ef7eb2e8f9f7 1212 * output
Anna Bridge 180:96ed750bd169 1213 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 1214 * @param Channel TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1215 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1216 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1217 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1218 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1219 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1220 * @retval HAL status
<> 144:ef7eb2e8f9f7 1221 */
<> 144:ef7eb2e8f9f7 1222 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1223 {
<> 144:ef7eb2e8f9f7 1224 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1225 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1226
<> 144:ef7eb2e8f9f7 1227 switch (Channel)
<> 144:ef7eb2e8f9f7 1228 {
<> 144:ef7eb2e8f9f7 1229 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1230 {
<> 144:ef7eb2e8f9f7 1231 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1232 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1233 }
<> 144:ef7eb2e8f9f7 1234 break;
<> 144:ef7eb2e8f9f7 1235
<> 144:ef7eb2e8f9f7 1236 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1237 {
<> 144:ef7eb2e8f9f7 1238 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1239 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1240 }
<> 144:ef7eb2e8f9f7 1241 break;
<> 144:ef7eb2e8f9f7 1242
<> 144:ef7eb2e8f9f7 1243 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1244 {
<> 144:ef7eb2e8f9f7 1245 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1246 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1247 }
<> 144:ef7eb2e8f9f7 1248 break;
<> 144:ef7eb2e8f9f7 1249
<> 144:ef7eb2e8f9f7 1250 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1251 {
<> 144:ef7eb2e8f9f7 1252 /* Disable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1253 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1254 }
<> 144:ef7eb2e8f9f7 1255 break;
<> 144:ef7eb2e8f9f7 1256
<> 144:ef7eb2e8f9f7 1257 default:
<> 144:ef7eb2e8f9f7 1258 break;
<> 144:ef7eb2e8f9f7 1259 }
<> 144:ef7eb2e8f9f7 1260
<> 144:ef7eb2e8f9f7 1261 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1262 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1263
<> 144:ef7eb2e8f9f7 1264 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1265 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1266
<> 144:ef7eb2e8f9f7 1267 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1268 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1269
<> 144:ef7eb2e8f9f7 1270 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1271 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1272
<> 144:ef7eb2e8f9f7 1273 /* Return function status */
<> 144:ef7eb2e8f9f7 1274 return HAL_OK;
<> 144:ef7eb2e8f9f7 1275 }
<> 144:ef7eb2e8f9f7 1276
<> 144:ef7eb2e8f9f7 1277 /**
<> 144:ef7eb2e8f9f7 1278 * @}
<> 144:ef7eb2e8f9f7 1279 */
<> 144:ef7eb2e8f9f7 1280
<> 144:ef7eb2e8f9f7 1281 /** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1282 * @brief Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1283 *
<> 144:ef7eb2e8f9f7 1284 @verbatim
<> 144:ef7eb2e8f9f7 1285 ==============================================================================
<> 144:ef7eb2e8f9f7 1286 ##### Timer Complementary One Pulse functions #####
<> 144:ef7eb2e8f9f7 1287 ==============================================================================
<> 144:ef7eb2e8f9f7 1288 [..]
<> 144:ef7eb2e8f9f7 1289 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1290 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 1291 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 1292 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 1293 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 1294
<> 144:ef7eb2e8f9f7 1295 @endverbatim
<> 144:ef7eb2e8f9f7 1296 * @{
<> 144:ef7eb2e8f9f7 1297 */
<> 144:ef7eb2e8f9f7 1298
<> 144:ef7eb2e8f9f7 1299 /**
<> 144:ef7eb2e8f9f7 1300 * @brief Starts the TIM One Pulse signal generation on the complemetary
<> 144:ef7eb2e8f9f7 1301 * output.
Anna Bridge 180:96ed750bd169 1302 * @param htim TIM One Pulse handle
Anna Bridge 180:96ed750bd169 1303 * @param OutputChannel TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1304 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1305 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1306 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1307 * @retval HAL status
<> 144:ef7eb2e8f9f7 1308 */
<> 144:ef7eb2e8f9f7 1309 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1310 {
<> 144:ef7eb2e8f9f7 1311 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1312 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1313
<> 144:ef7eb2e8f9f7 1314 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1315 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1316
<> 144:ef7eb2e8f9f7 1317 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1318 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1319
<> 144:ef7eb2e8f9f7 1320 /* Return function status */
<> 144:ef7eb2e8f9f7 1321 return HAL_OK;
<> 144:ef7eb2e8f9f7 1322 }
<> 144:ef7eb2e8f9f7 1323
<> 144:ef7eb2e8f9f7 1324 /**
<> 144:ef7eb2e8f9f7 1325 * @brief Stops the TIM One Pulse signal generation on the complementary
<> 144:ef7eb2e8f9f7 1326 * output.
Anna Bridge 180:96ed750bd169 1327 * @param htim TIM One Pulse handle
Anna Bridge 180:96ed750bd169 1328 * @param OutputChannel TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1329 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1330 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1331 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1332 * @retval HAL status
<> 144:ef7eb2e8f9f7 1333 */
<> 144:ef7eb2e8f9f7 1334 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1335 {
<> 144:ef7eb2e8f9f7 1336
<> 144:ef7eb2e8f9f7 1337 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1338 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1339
<> 144:ef7eb2e8f9f7 1340 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1341 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1342
<> 144:ef7eb2e8f9f7 1343 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1344 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1345
<> 144:ef7eb2e8f9f7 1346 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1347 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1348
<> 144:ef7eb2e8f9f7 1349 /* Return function status */
<> 144:ef7eb2e8f9f7 1350 return HAL_OK;
<> 144:ef7eb2e8f9f7 1351 }
<> 144:ef7eb2e8f9f7 1352
<> 144:ef7eb2e8f9f7 1353 /**
<> 144:ef7eb2e8f9f7 1354 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1355 * complementary channel.
Anna Bridge 180:96ed750bd169 1356 * @param htim TIM One Pulse handle
Anna Bridge 180:96ed750bd169 1357 * @param OutputChannel TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1358 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1359 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1360 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1361 * @retval HAL status
<> 144:ef7eb2e8f9f7 1362 */
<> 144:ef7eb2e8f9f7 1363 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1364 {
<> 144:ef7eb2e8f9f7 1365 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1366 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1367
<> 144:ef7eb2e8f9f7 1368 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1369 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1370
<> 144:ef7eb2e8f9f7 1371 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1372 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1373
<> 144:ef7eb2e8f9f7 1374 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1375 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1376
<> 144:ef7eb2e8f9f7 1377 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1378 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1379
<> 144:ef7eb2e8f9f7 1380 /* Return function status */
<> 144:ef7eb2e8f9f7 1381 return HAL_OK;
<> 144:ef7eb2e8f9f7 1382 }
<> 144:ef7eb2e8f9f7 1383
<> 144:ef7eb2e8f9f7 1384 /**
<> 144:ef7eb2e8f9f7 1385 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1386 * complementary channel.
Anna Bridge 180:96ed750bd169 1387 * @param htim TIM One Pulse handle
Anna Bridge 180:96ed750bd169 1388 * @param OutputChannel TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1389 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1390 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1391 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1392 * @retval HAL status
<> 144:ef7eb2e8f9f7 1393 */
<> 144:ef7eb2e8f9f7 1394 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1395 {
<> 144:ef7eb2e8f9f7 1396 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1397 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1398
<> 144:ef7eb2e8f9f7 1399 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1400 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1401
<> 144:ef7eb2e8f9f7 1402 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1403 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1404
<> 144:ef7eb2e8f9f7 1405 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1406 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1407
<> 144:ef7eb2e8f9f7 1408 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1409 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1410
<> 144:ef7eb2e8f9f7 1411 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1412 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1413
<> 144:ef7eb2e8f9f7 1414 /* Return function status */
<> 144:ef7eb2e8f9f7 1415 return HAL_OK;
<> 144:ef7eb2e8f9f7 1416 }
<> 144:ef7eb2e8f9f7 1417
<> 144:ef7eb2e8f9f7 1418 /**
<> 144:ef7eb2e8f9f7 1419 * @}
<> 144:ef7eb2e8f9f7 1420 */
<> 144:ef7eb2e8f9f7 1421 /** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
<> 144:ef7eb2e8f9f7 1422 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 1423 *
<> 144:ef7eb2e8f9f7 1424 @verbatim
<> 144:ef7eb2e8f9f7 1425 ==============================================================================
<> 144:ef7eb2e8f9f7 1426 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1427 ==============================================================================
<> 144:ef7eb2e8f9f7 1428 [..]
<> 144:ef7eb2e8f9f7 1429 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1430 (+) Configure the commutation event in case of use of the Hall sensor interface.
<> 144:ef7eb2e8f9f7 1431 (+) Configure Complementary channels, break features and dead time.
<> 144:ef7eb2e8f9f7 1432 (+) Configure Master synchronization.
<> 144:ef7eb2e8f9f7 1433 (+) Configure timer remapping capabilities.
<> 144:ef7eb2e8f9f7 1434
<> 144:ef7eb2e8f9f7 1435 @endverbatim
<> 144:ef7eb2e8f9f7 1436 * @{
<> 144:ef7eb2e8f9f7 1437 */
<> 144:ef7eb2e8f9f7 1438 /**
<> 144:ef7eb2e8f9f7 1439 * @brief Configure the TIM commutation event sequence.
<> 144:ef7eb2e8f9f7 1440 * @note: this function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1441 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1442 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1443 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1444 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1445 * the TI1 of the Interface Timer detect a commutation at its input TI1.
Anna Bridge 180:96ed750bd169 1446 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 1447 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<> 144:ef7eb2e8f9f7 1448 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1449 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1450 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1451 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1452 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1453 * @arg TIM_TS_NONE: No trigger is needed
Anna Bridge 180:96ed750bd169 1454 * @param CommutationSource the Commutation Event source
<> 144:ef7eb2e8f9f7 1455 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1456 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1457 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1458 * @retval HAL status
<> 144:ef7eb2e8f9f7 1459 */
<> 144:ef7eb2e8f9f7 1460 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1461 {
<> 144:ef7eb2e8f9f7 1462 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1463 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1464 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1465
<> 144:ef7eb2e8f9f7 1466 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1467
<> 144:ef7eb2e8f9f7 1468 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1469 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1470 {
<> 144:ef7eb2e8f9f7 1471 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1472 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1473 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1474 }
<> 144:ef7eb2e8f9f7 1475
<> 144:ef7eb2e8f9f7 1476 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1477 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1478 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1479 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1480 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1481
<> 144:ef7eb2e8f9f7 1482 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1483
<> 144:ef7eb2e8f9f7 1484 return HAL_OK;
<> 144:ef7eb2e8f9f7 1485 }
<> 144:ef7eb2e8f9f7 1486
<> 144:ef7eb2e8f9f7 1487 /**
<> 144:ef7eb2e8f9f7 1488 * @brief Configure the TIM commutation event sequence with interrupt.
<> 144:ef7eb2e8f9f7 1489 * @note: this function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1490 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1491 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1492 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1493 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1494 * the TI1 of the Interface Timer detect a commutation at its input TI1.
Anna Bridge 180:96ed750bd169 1495 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 1496 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<> 144:ef7eb2e8f9f7 1497 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1498 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1499 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1500 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1501 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1502 * @arg TIM_TS_NONE: No trigger is needed
Anna Bridge 180:96ed750bd169 1503 * @param CommutationSource the Commutation Event source
<> 144:ef7eb2e8f9f7 1504 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1505 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1506 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1507 * @retval HAL status
<> 144:ef7eb2e8f9f7 1508 */
<> 144:ef7eb2e8f9f7 1509 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1510 {
<> 144:ef7eb2e8f9f7 1511 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1512 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1513 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1514
<> 144:ef7eb2e8f9f7 1515 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1516
<> 144:ef7eb2e8f9f7 1517 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1518 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1519 {
<> 144:ef7eb2e8f9f7 1520 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1521 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1522 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1523 }
<> 144:ef7eb2e8f9f7 1524
<> 144:ef7eb2e8f9f7 1525 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1526 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1527 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1528 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1529 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1530
<> 144:ef7eb2e8f9f7 1531 /* Enable the Commutation Interrupt Request */
<> 144:ef7eb2e8f9f7 1532 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
<> 144:ef7eb2e8f9f7 1533
<> 144:ef7eb2e8f9f7 1534 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1535
<> 144:ef7eb2e8f9f7 1536 return HAL_OK;
<> 144:ef7eb2e8f9f7 1537 }
<> 144:ef7eb2e8f9f7 1538
<> 144:ef7eb2e8f9f7 1539 /**
<> 144:ef7eb2e8f9f7 1540 * @brief Configure the TIM commutation event sequence with DMA.
<> 144:ef7eb2e8f9f7 1541 * @note: this function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1542 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1543 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1544 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1545 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1546 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1547 * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
Anna Bridge 180:96ed750bd169 1548 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 1549 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<> 144:ef7eb2e8f9f7 1550 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1551 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1552 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1553 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1554 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1555 * @arg TIM_TS_NONE: No trigger is needed
Anna Bridge 180:96ed750bd169 1556 * @param CommutationSource the Commutation Event source
<> 144:ef7eb2e8f9f7 1557 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1558 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1559 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1560 * @retval HAL status
<> 144:ef7eb2e8f9f7 1561 */
<> 144:ef7eb2e8f9f7 1562 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1563 {
<> 144:ef7eb2e8f9f7 1564 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1565 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1566 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1567
<> 144:ef7eb2e8f9f7 1568 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1569
<> 144:ef7eb2e8f9f7 1570 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1571 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1572 {
<> 144:ef7eb2e8f9f7 1573 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1574 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1575 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1576 }
<> 144:ef7eb2e8f9f7 1577
<> 144:ef7eb2e8f9f7 1578 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1579 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1580 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1581 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1582 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1583
<> 144:ef7eb2e8f9f7 1584 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1585 /* Set the DMA Commutation Callback */
<> 144:ef7eb2e8f9f7 1586 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 1587 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1588 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
<> 144:ef7eb2e8f9f7 1589
<> 144:ef7eb2e8f9f7 1590 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1591 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
<> 144:ef7eb2e8f9f7 1592
<> 144:ef7eb2e8f9f7 1593 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1594
<> 144:ef7eb2e8f9f7 1595 return HAL_OK;
<> 144:ef7eb2e8f9f7 1596 }
<> 144:ef7eb2e8f9f7 1597
<> 144:ef7eb2e8f9f7 1598 /**
<> 144:ef7eb2e8f9f7 1599 * @brief Configures the TIM in master mode.
Anna Bridge 180:96ed750bd169 1600 * @param htim TIM handle.
Anna Bridge 180:96ed750bd169 1601 * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 1602 * contains the selected trigger output (TRGO) and the Master/Slave
<> 144:ef7eb2e8f9f7 1603 * mode.
<> 144:ef7eb2e8f9f7 1604 * @retval HAL status
<> 144:ef7eb2e8f9f7 1605 */
<> 144:ef7eb2e8f9f7 1606 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
<> 144:ef7eb2e8f9f7 1607 {
<> 144:ef7eb2e8f9f7 1608 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1609 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1610 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
<> 144:ef7eb2e8f9f7 1611 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
<> 144:ef7eb2e8f9f7 1612
<> 144:ef7eb2e8f9f7 1613 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1614
<> 144:ef7eb2e8f9f7 1615 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1616
<> 144:ef7eb2e8f9f7 1617 /* Reset the MMS Bits */
<> 144:ef7eb2e8f9f7 1618 htim->Instance->CR2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 1619 /* Select the TRGO source */
<> 144:ef7eb2e8f9f7 1620 htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
<> 144:ef7eb2e8f9f7 1621
<> 144:ef7eb2e8f9f7 1622 /* Reset the MSM Bit */
<> 144:ef7eb2e8f9f7 1623 htim->Instance->SMCR &= ~TIM_SMCR_MSM;
<> 144:ef7eb2e8f9f7 1624 /* Set or Reset the MSM Bit */
<> 144:ef7eb2e8f9f7 1625 htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
<> 144:ef7eb2e8f9f7 1626
<> 144:ef7eb2e8f9f7 1627 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1628
<> 144:ef7eb2e8f9f7 1629 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1630
<> 144:ef7eb2e8f9f7 1631 return HAL_OK;
<> 144:ef7eb2e8f9f7 1632 }
<> 144:ef7eb2e8f9f7 1633
<> 144:ef7eb2e8f9f7 1634 /**
<> 144:ef7eb2e8f9f7 1635 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
<> 144:ef7eb2e8f9f7 1636 * and the AOE(automatic output enable).
Anna Bridge 180:96ed750bd169 1637 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 1638 * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 1639 * contains the BDTR Register configuration information for the TIM peripheral.
<> 144:ef7eb2e8f9f7 1640 * @retval HAL status
<> 144:ef7eb2e8f9f7 1641 */
<> 144:ef7eb2e8f9f7 1642 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 1643 TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
<> 144:ef7eb2e8f9f7 1644 {
<> 156:95d6b41a828b 1645 uint32_t tmpbdtr = 0;
<> 156:95d6b41a828b 1646
<> 144:ef7eb2e8f9f7 1647 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1648 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1649 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
<> 144:ef7eb2e8f9f7 1650 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
<> 144:ef7eb2e8f9f7 1651 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
<> 144:ef7eb2e8f9f7 1652 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
<> 144:ef7eb2e8f9f7 1653 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
<> 144:ef7eb2e8f9f7 1654 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
<> 144:ef7eb2e8f9f7 1655 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
<> 144:ef7eb2e8f9f7 1656
<> 144:ef7eb2e8f9f7 1657 /* Process Locked */
<> 144:ef7eb2e8f9f7 1658 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1659
<> 144:ef7eb2e8f9f7 1660 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1661
<> 144:ef7eb2e8f9f7 1662 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
<> 144:ef7eb2e8f9f7 1663 the OSSI State, the dead time value and the Automatic Output Enable Bit */
<> 156:95d6b41a828b 1664
<> 156:95d6b41a828b 1665 /* Set the BDTR bits */
<> 156:95d6b41a828b 1666 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
<> 156:95d6b41a828b 1667 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
<> 156:95d6b41a828b 1668 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
<> 156:95d6b41a828b 1669 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
<> 156:95d6b41a828b 1670 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
<> 156:95d6b41a828b 1671 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
<> 156:95d6b41a828b 1672 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
<> 156:95d6b41a828b 1673 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
<> 156:95d6b41a828b 1674
<> 156:95d6b41a828b 1675 /* Set TIMx_BDTR */
<> 156:95d6b41a828b 1676 htim->Instance->BDTR = tmpbdtr;
<> 156:95d6b41a828b 1677
<> 144:ef7eb2e8f9f7 1678 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1679
<> 144:ef7eb2e8f9f7 1680 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1681
<> 144:ef7eb2e8f9f7 1682 return HAL_OK;
<> 144:ef7eb2e8f9f7 1683 }
<> 144:ef7eb2e8f9f7 1684
<> 144:ef7eb2e8f9f7 1685 /**
<> 144:ef7eb2e8f9f7 1686 * @brief Configures the TIM14 Remapping input capabilities.
Anna Bridge 180:96ed750bd169 1687 * @param htim TIM handle.
Anna Bridge 180:96ed750bd169 1688 * @param Remap specifies the TIM remapping source.
<> 144:ef7eb2e8f9f7 1689 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1690 * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
<> 144:ef7eb2e8f9f7 1691 * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
<> 144:ef7eb2e8f9f7 1692 * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32
<> 144:ef7eb2e8f9f7 1693 * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
<> 144:ef7eb2e8f9f7 1694 * @retval HAL status
<> 144:ef7eb2e8f9f7 1695 */
<> 144:ef7eb2e8f9f7 1696 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
<> 144:ef7eb2e8f9f7 1697 {
<> 144:ef7eb2e8f9f7 1698 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1699
<> 144:ef7eb2e8f9f7 1700 /* Check parameters */
<> 144:ef7eb2e8f9f7 1701 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1702 assert_param(IS_TIM_REMAP(Remap));
<> 144:ef7eb2e8f9f7 1703
<> 144:ef7eb2e8f9f7 1704 /* Set the Timer remapping configuration */
<> 144:ef7eb2e8f9f7 1705 htim->Instance->OR = Remap;
<> 144:ef7eb2e8f9f7 1706
<> 144:ef7eb2e8f9f7 1707 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1708
<> 144:ef7eb2e8f9f7 1709 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1710
<> 144:ef7eb2e8f9f7 1711 return HAL_OK;
<> 144:ef7eb2e8f9f7 1712 }
<> 144:ef7eb2e8f9f7 1713
<> 144:ef7eb2e8f9f7 1714 /**
<> 144:ef7eb2e8f9f7 1715 * @}
<> 144:ef7eb2e8f9f7 1716 */
<> 144:ef7eb2e8f9f7 1717
<> 156:95d6b41a828b 1718 /** @addtogroup TIM_Exported_Functions_Group8
<> 144:ef7eb2e8f9f7 1719 * @{
<> 144:ef7eb2e8f9f7 1720 */
<> 156:95d6b41a828b 1721 #if defined(STM32F051x8) || defined(STM32F058xx) || \
<> 144:ef7eb2e8f9f7 1722 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 1723 defined(STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 1724 /**
<> 144:ef7eb2e8f9f7 1725 * @brief Configures the OCRef clear feature
Anna Bridge 180:96ed750bd169 1726 * @param htim TIM handle
Anna Bridge 180:96ed750bd169 1727 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 1728 * contains the OCREF clear feature and parameters for the TIM peripheral.
Anna Bridge 180:96ed750bd169 1729 * @param Channel specifies the TIM Channel
<> 144:ef7eb2e8f9f7 1730 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1731 * @arg TIM_CHANNEL_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 1732 * @arg TIM_CHANNEL_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 1733 * @arg TIM_CHANNEL_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 1734 * @arg TIM_CHANNEL_4: TIM Channel 4
<> 144:ef7eb2e8f9f7 1735 * @arg TIM_Channel_5: TIM Channel 5
<> 144:ef7eb2e8f9f7 1736 * @retval None
<> 144:ef7eb2e8f9f7 1737 */
<> 144:ef7eb2e8f9f7 1738 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 1739 TIM_ClearInputConfigTypeDef *sClearInputConfig,
<> 144:ef7eb2e8f9f7 1740 uint32_t Channel)
<> 144:ef7eb2e8f9f7 1741 {
<> 156:95d6b41a828b 1742 uint32_t tmpsmcr = 0U;
<> 144:ef7eb2e8f9f7 1743
<> 144:ef7eb2e8f9f7 1744 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1745 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1746 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
<> 144:ef7eb2e8f9f7 1747
<> 144:ef7eb2e8f9f7 1748 /* Check input state */
<> 144:ef7eb2e8f9f7 1749 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1750
<> 144:ef7eb2e8f9f7 1751 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1752
<> 144:ef7eb2e8f9f7 1753 switch (sClearInputConfig->ClearInputSource)
<> 144:ef7eb2e8f9f7 1754 {
<> 144:ef7eb2e8f9f7 1755 case TIM_CLEARINPUTSOURCE_NONE:
<> 144:ef7eb2e8f9f7 1756 {
<> 144:ef7eb2e8f9f7 1757 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 1758 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 1759
<> 144:ef7eb2e8f9f7 1760 /* Clear the OCREF clear selection bit */
<> 144:ef7eb2e8f9f7 1761 tmpsmcr &= ~TIM_SMCR_OCCS;
<> 144:ef7eb2e8f9f7 1762
<> 144:ef7eb2e8f9f7 1763 /* Clear the ETR Bits */
<> 144:ef7eb2e8f9f7 1764 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 144:ef7eb2e8f9f7 1765
<> 144:ef7eb2e8f9f7 1766 /* Set TIMx_SMCR */
<> 144:ef7eb2e8f9f7 1767 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 1768 }
<> 144:ef7eb2e8f9f7 1769 break;
<> 144:ef7eb2e8f9f7 1770
<> 144:ef7eb2e8f9f7 1771 case TIM_CLEARINPUTSOURCE_OCREFCLR:
<> 144:ef7eb2e8f9f7 1772 {
<> 144:ef7eb2e8f9f7 1773 /* Clear the OCREF clear selection bit */
<> 144:ef7eb2e8f9f7 1774 htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
<> 144:ef7eb2e8f9f7 1775 }
<> 144:ef7eb2e8f9f7 1776 break;
<> 144:ef7eb2e8f9f7 1777
<> 144:ef7eb2e8f9f7 1778 case TIM_CLEARINPUTSOURCE_ETR:
<> 144:ef7eb2e8f9f7 1779 {
<> 144:ef7eb2e8f9f7 1780 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1781 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
<> 144:ef7eb2e8f9f7 1782 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
<> 144:ef7eb2e8f9f7 1783 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
<> 144:ef7eb2e8f9f7 1784
<> 144:ef7eb2e8f9f7 1785 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 1786 sClearInputConfig->ClearInputPrescaler,
<> 144:ef7eb2e8f9f7 1787 sClearInputConfig->ClearInputPolarity,
<> 144:ef7eb2e8f9f7 1788 sClearInputConfig->ClearInputFilter);
<> 144:ef7eb2e8f9f7 1789
<> 144:ef7eb2e8f9f7 1790 /* Set the OCREF clear selection bit */
<> 144:ef7eb2e8f9f7 1791 htim->Instance->SMCR |= TIM_SMCR_OCCS;
<> 144:ef7eb2e8f9f7 1792 }
<> 144:ef7eb2e8f9f7 1793 break;
<> 144:ef7eb2e8f9f7 1794 default:
<> 144:ef7eb2e8f9f7 1795 break;
<> 144:ef7eb2e8f9f7 1796 }
<> 144:ef7eb2e8f9f7 1797
<> 144:ef7eb2e8f9f7 1798 switch (Channel)
<> 144:ef7eb2e8f9f7 1799 {
<> 144:ef7eb2e8f9f7 1800 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1801 {
<> 144:ef7eb2e8f9f7 1802 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 1803 {
<> 144:ef7eb2e8f9f7 1804 /* Enable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 1805 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 1806 }
<> 144:ef7eb2e8f9f7 1807 else
<> 144:ef7eb2e8f9f7 1808 {
<> 144:ef7eb2e8f9f7 1809 /* Disable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 1810 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 1811 }
<> 144:ef7eb2e8f9f7 1812 }
<> 144:ef7eb2e8f9f7 1813 break;
<> 144:ef7eb2e8f9f7 1814 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1815 {
<> 144:ef7eb2e8f9f7 1816 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 1817 {
<> 144:ef7eb2e8f9f7 1818 /* Enable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 1819 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 1820 }
<> 144:ef7eb2e8f9f7 1821 else
<> 144:ef7eb2e8f9f7 1822 {
<> 144:ef7eb2e8f9f7 1823 /* Disable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 1824 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 1825 }
<> 144:ef7eb2e8f9f7 1826 }
<> 144:ef7eb2e8f9f7 1827 break;
<> 144:ef7eb2e8f9f7 1828 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1829 {
<> 144:ef7eb2e8f9f7 1830 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 1831 {
<> 144:ef7eb2e8f9f7 1832 /* Enable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 1833 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 1834 }
<> 144:ef7eb2e8f9f7 1835 else
<> 144:ef7eb2e8f9f7 1836 {
<> 144:ef7eb2e8f9f7 1837 /* Disable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 1838 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 1839 }
<> 144:ef7eb2e8f9f7 1840 }
<> 144:ef7eb2e8f9f7 1841 break;
<> 144:ef7eb2e8f9f7 1842 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1843 {
<> 144:ef7eb2e8f9f7 1844 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 1845 {
<> 144:ef7eb2e8f9f7 1846 /* Enable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 1847 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 1848 }
<> 144:ef7eb2e8f9f7 1849 else
<> 144:ef7eb2e8f9f7 1850 {
<> 144:ef7eb2e8f9f7 1851 /* Disable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 1852 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 1853 }
<> 144:ef7eb2e8f9f7 1854 }
<> 144:ef7eb2e8f9f7 1855 break;
<> 144:ef7eb2e8f9f7 1856 default:
<> 144:ef7eb2e8f9f7 1857 break;
<> 144:ef7eb2e8f9f7 1858 }
<> 144:ef7eb2e8f9f7 1859
<> 144:ef7eb2e8f9f7 1860 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1861
<> 144:ef7eb2e8f9f7 1862 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1863
<> 144:ef7eb2e8f9f7 1864 return HAL_OK;
<> 144:ef7eb2e8f9f7 1865 }
<> 156:95d6b41a828b 1866 #endif /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1867 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 156:95d6b41a828b 1868 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1869 /**
<> 144:ef7eb2e8f9f7 1870 * @}
<> 144:ef7eb2e8f9f7 1871 */
<> 144:ef7eb2e8f9f7 1872
<> 144:ef7eb2e8f9f7 1873 /** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
<> 144:ef7eb2e8f9f7 1874 * @brief Extension Callbacks functions
<> 144:ef7eb2e8f9f7 1875 *
<> 144:ef7eb2e8f9f7 1876 @verbatim
<> 144:ef7eb2e8f9f7 1877 ==============================================================================
<> 144:ef7eb2e8f9f7 1878 ##### Extension Callbacks functions #####
<> 144:ef7eb2e8f9f7 1879 ==============================================================================
<> 144:ef7eb2e8f9f7 1880 [..]
<> 144:ef7eb2e8f9f7 1881 This section provides Extension TIM callback functions:
<> 144:ef7eb2e8f9f7 1882 (+) Timer Commutation callback
<> 144:ef7eb2e8f9f7 1883 (+) Timer Break callback
<> 144:ef7eb2e8f9f7 1884
<> 144:ef7eb2e8f9f7 1885 @endverbatim
<> 144:ef7eb2e8f9f7 1886 * @{
<> 144:ef7eb2e8f9f7 1887 */
<> 144:ef7eb2e8f9f7 1888
<> 144:ef7eb2e8f9f7 1889 /**
<> 144:ef7eb2e8f9f7 1890 * @brief Hall commutation changed callback in non blocking mode
Anna Bridge 180:96ed750bd169 1891 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 1892 * @retval None
<> 144:ef7eb2e8f9f7 1893 */
<> 144:ef7eb2e8f9f7 1894 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1895 {
<> 144:ef7eb2e8f9f7 1896 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1897 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1898
<> 144:ef7eb2e8f9f7 1899 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1900 the HAL_TIMEx_CommutationCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1901 */
<> 144:ef7eb2e8f9f7 1902 }
<> 144:ef7eb2e8f9f7 1903
<> 144:ef7eb2e8f9f7 1904 /**
<> 144:ef7eb2e8f9f7 1905 * @brief Hall Break detection callback in non blocking mode
Anna Bridge 180:96ed750bd169 1906 * @param htim TIM handle
<> 144:ef7eb2e8f9f7 1907 * @retval None
<> 144:ef7eb2e8f9f7 1908 */
<> 144:ef7eb2e8f9f7 1909 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1910 {
<> 144:ef7eb2e8f9f7 1911 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1912 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1913
<> 144:ef7eb2e8f9f7 1914 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1915 the HAL_TIMEx_BreakCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1916 */
<> 144:ef7eb2e8f9f7 1917 }
<> 144:ef7eb2e8f9f7 1918
<> 144:ef7eb2e8f9f7 1919 /**
<> 144:ef7eb2e8f9f7 1920 * @brief TIM DMA Commutation callback.
Anna Bridge 180:96ed750bd169 1921 * @param hdma pointer to DMA handle.
<> 144:ef7eb2e8f9f7 1922 * @retval None
<> 144:ef7eb2e8f9f7 1923 */
<> 144:ef7eb2e8f9f7 1924 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1925 {
<> 144:ef7eb2e8f9f7 1926 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1927
<> 144:ef7eb2e8f9f7 1928 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1929
<> 144:ef7eb2e8f9f7 1930 HAL_TIMEx_CommutationCallback(htim);
<> 144:ef7eb2e8f9f7 1931 }
<> 144:ef7eb2e8f9f7 1932
<> 144:ef7eb2e8f9f7 1933 /**
<> 144:ef7eb2e8f9f7 1934 * @}
<> 144:ef7eb2e8f9f7 1935 */
<> 144:ef7eb2e8f9f7 1936
<> 144:ef7eb2e8f9f7 1937 /** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
<> 144:ef7eb2e8f9f7 1938 * @brief Extension Peripheral State functions
<> 144:ef7eb2e8f9f7 1939 *
<> 144:ef7eb2e8f9f7 1940 @verbatim
<> 144:ef7eb2e8f9f7 1941 ==============================================================================
<> 144:ef7eb2e8f9f7 1942 ##### Extension Peripheral State functions #####
<> 144:ef7eb2e8f9f7 1943 ==============================================================================
<> 144:ef7eb2e8f9f7 1944 [..]
<> 144:ef7eb2e8f9f7 1945 This subsection permit to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 1946 and the data flow.
<> 144:ef7eb2e8f9f7 1947
<> 144:ef7eb2e8f9f7 1948 @endverbatim
<> 144:ef7eb2e8f9f7 1949 * @{
<> 144:ef7eb2e8f9f7 1950 */
<> 144:ef7eb2e8f9f7 1951
<> 144:ef7eb2e8f9f7 1952 /**
<> 144:ef7eb2e8f9f7 1953 * @brief Return the TIM Hall Sensor interface state
Anna Bridge 180:96ed750bd169 1954 * @param htim TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 1955 * @retval HAL state
<> 144:ef7eb2e8f9f7 1956 */
<> 144:ef7eb2e8f9f7 1957 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1958 {
<> 144:ef7eb2e8f9f7 1959 return htim->State;
<> 144:ef7eb2e8f9f7 1960 }
<> 144:ef7eb2e8f9f7 1961
<> 144:ef7eb2e8f9f7 1962 /**
<> 144:ef7eb2e8f9f7 1963 * @}
<> 144:ef7eb2e8f9f7 1964 */
<> 144:ef7eb2e8f9f7 1965
<> 144:ef7eb2e8f9f7 1966 /**
<> 144:ef7eb2e8f9f7 1967 * @}
<> 144:ef7eb2e8f9f7 1968 */
<> 144:ef7eb2e8f9f7 1969
<> 144:ef7eb2e8f9f7 1970 /** @addtogroup TIMEx_Private_Functions
<> 144:ef7eb2e8f9f7 1971 * @{
<> 144:ef7eb2e8f9f7 1972 */
<> 144:ef7eb2e8f9f7 1973
<> 144:ef7eb2e8f9f7 1974 /**
<> 144:ef7eb2e8f9f7 1975 * @brief Enables or disables the TIM Capture Compare Channel xN.
<> 144:ef7eb2e8f9f7 1976 * @param TIMx to select the TIM peripheral
Anna Bridge 180:96ed750bd169 1977 * @param Channel specifies the TIM Channel
<> 144:ef7eb2e8f9f7 1978 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1979 * @arg TIM_CHANNEL_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 1980 * @arg TIM_CHANNEL_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 1981 * @arg TIM_CHANNEL_3: TIM Channel 3
Anna Bridge 180:96ed750bd169 1982 * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
<> 144:ef7eb2e8f9f7 1983 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
<> 144:ef7eb2e8f9f7 1984 * @retval None
<> 144:ef7eb2e8f9f7 1985 */
<> 144:ef7eb2e8f9f7 1986 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
<> 144:ef7eb2e8f9f7 1987 {
<> 156:95d6b41a828b 1988 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 1989
<> 144:ef7eb2e8f9f7 1990 tmp = TIM_CCER_CC1NE << Channel;
<> 144:ef7eb2e8f9f7 1991
<> 144:ef7eb2e8f9f7 1992 /* Reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 1993 TIMx->CCER &= ~tmp;
<> 144:ef7eb2e8f9f7 1994
<> 144:ef7eb2e8f9f7 1995 /* Set or reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 1996 TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
<> 144:ef7eb2e8f9f7 1997 }
<> 144:ef7eb2e8f9f7 1998
<> 144:ef7eb2e8f9f7 1999 /**
<> 144:ef7eb2e8f9f7 2000 * @}
<> 144:ef7eb2e8f9f7 2001 */
<> 144:ef7eb2e8f9f7 2002
<> 144:ef7eb2e8f9f7 2003 #endif /* HAL_TIM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2004 /**
<> 144:ef7eb2e8f9f7 2005 * @}
<> 144:ef7eb2e8f9f7 2006 */
<> 144:ef7eb2e8f9f7 2007
<> 144:ef7eb2e8f9f7 2008 /**
<> 144:ef7eb2e8f9f7 2009 * @}
<> 144:ef7eb2e8f9f7 2010 */
<> 144:ef7eb2e8f9f7 2011
<> 144:ef7eb2e8f9f7 2012 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/