mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 156:95d6b41a828b 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_spi.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of SPI HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F0xx_HAL_SPI_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F0xx_HAL_SPI_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 156:95d6b41a828b 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup SPI
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56 /** @defgroup SPI_Exported_Types SPI Exported Types
<> 144:ef7eb2e8f9f7 57 * @{
<> 144:ef7eb2e8f9f7 58 */
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /**
<> 144:ef7eb2e8f9f7 61 * @brief SPI Configuration Structure definition
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63 typedef struct
<> 144:ef7eb2e8f9f7 64 {
<> 144:ef7eb2e8f9f7 65 uint32_t Mode; /*!< Specifies the SPI operating mode.
<> 144:ef7eb2e8f9f7 66 This parameter can be a value of @ref SPI_Mode */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
<> 144:ef7eb2e8f9f7 69 This parameter can be a value of @ref SPI_Direction */
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 uint32_t DataSize; /*!< Specifies the SPI data size.
<> 144:ef7eb2e8f9f7 72 This parameter can be a value of @ref SPI_Data_Size */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
<> 144:ef7eb2e8f9f7 75 This parameter can be a value of @ref SPI_Clock_Polarity */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
<> 144:ef7eb2e8f9f7 78 This parameter can be a value of @ref SPI_Clock_Phase */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
<> 144:ef7eb2e8f9f7 81 hardware (NSS pin) or by software using the SSI bit.
<> 144:ef7eb2e8f9f7 82 This parameter can be a value of @ref SPI_Slave_Select_management */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
<> 144:ef7eb2e8f9f7 85 used to configure the transmit and receive SCK clock.
<> 144:ef7eb2e8f9f7 86 This parameter can be a value of @ref SPI_BaudRate_Prescaler
<> 144:ef7eb2e8f9f7 87 @note The communication clock is derived from the master
<> 144:ef7eb2e8f9f7 88 clock. The slave clock does not need to be set. */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
<> 144:ef7eb2e8f9f7 91 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
<> 144:ef7eb2e8f9f7 92
<> 156:95d6b41a828b 93 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
<> 144:ef7eb2e8f9f7 94 This parameter can be a value of @ref SPI_TI_mode */
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
<> 144:ef7eb2e8f9f7 97 This parameter can be a value of @ref SPI_CRC_Calculation */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
Anna Bridge 180:96ed750bd169 100 This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
<> 144:ef7eb2e8f9f7 103 CRC Length is only used with Data8 and Data16, not other data size
<> 144:ef7eb2e8f9f7 104 This parameter can be a value of @ref SPI_CRC_length */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
<> 144:ef7eb2e8f9f7 107 This parameter can be a value of @ref SPI_NSSP_Mode
<> 144:ef7eb2e8f9f7 108 This mode is activated by the NSSP bit in the SPIx_CR2 register and
<> 144:ef7eb2e8f9f7 109 it takes effect only if the SPI interface is configured as Motorola SPI
<> 144:ef7eb2e8f9f7 110 master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
<> 144:ef7eb2e8f9f7 111 CPOL setting is ignored).. */
<> 144:ef7eb2e8f9f7 112 } SPI_InitTypeDef;
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /**
<> 156:95d6b41a828b 115 * @brief HAL SPI State structure definition
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117 typedef enum
<> 144:ef7eb2e8f9f7 118 {
<> 156:95d6b41a828b 119 HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
<> 156:95d6b41a828b 120 HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
<> 156:95d6b41a828b 121 HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
<> 156:95d6b41a828b 122 HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
<> 156:95d6b41a828b 123 HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
<> 156:95d6b41a828b 124 HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
<> 156:95d6b41a828b 125 HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
<> 156:95d6b41a828b 126 HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
<> 156:95d6b41a828b 127 } HAL_SPI_StateTypeDef;
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /**
<> 144:ef7eb2e8f9f7 130 * @brief SPI handle Structure definition
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132 typedef struct __SPI_HandleTypeDef
<> 144:ef7eb2e8f9f7 133 {
<> 144:ef7eb2e8f9f7 134 SPI_TypeDef *Instance; /*!< SPI registers base address */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 SPI_InitTypeDef Init; /*!< SPI communication parameters */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 uint16_t TxXferSize; /*!< SPI Tx Transfer size */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 uint16_t RxXferSize; /*!< SPI Rx Transfer size */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
<> 144:ef7eb2e8f9f7 151
<> 156:95d6b41a828b 152 void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
<> 144:ef7eb2e8f9f7 153
<> 156:95d6b41a828b 154 void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 HAL_LockTypeDef Lock; /*!< Locking object */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 __IO uint32_t ErrorCode; /*!< SPI Error code */
<> 144:ef7eb2e8f9f7 165
<> 156:95d6b41a828b 166 } SPI_HandleTypeDef;
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /**
<> 144:ef7eb2e8f9f7 169 * @}
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 173 /** @defgroup SPI_Exported_Constants SPI Exported Constants
<> 144:ef7eb2e8f9f7 174 * @{
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /** @defgroup SPI_Error_Code SPI Error Code
<> 144:ef7eb2e8f9f7 178 * @{
<> 144:ef7eb2e8f9f7 179 */
<> 156:95d6b41a828b 180 #define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
<> 156:95d6b41a828b 181 #define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
<> 156:95d6b41a828b 182 #define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
<> 156:95d6b41a828b 183 #define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
<> 156:95d6b41a828b 184 #define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */
<> 156:95d6b41a828b 185 #define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
<> 156:95d6b41a828b 186 #define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
<> 156:95d6b41a828b 187 #define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
<> 144:ef7eb2e8f9f7 188 /**
<> 144:ef7eb2e8f9f7 189 * @}
<> 144:ef7eb2e8f9f7 190 */
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /** @defgroup SPI_Mode SPI Mode
<> 144:ef7eb2e8f9f7 193 * @{
<> 144:ef7eb2e8f9f7 194 */
<> 156:95d6b41a828b 195 #define SPI_MODE_SLAVE (0x00000000U)
<> 144:ef7eb2e8f9f7 196 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
<> 144:ef7eb2e8f9f7 197 /**
<> 144:ef7eb2e8f9f7 198 * @}
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /** @defgroup SPI_Direction SPI Direction Mode
<> 144:ef7eb2e8f9f7 202 * @{
<> 144:ef7eb2e8f9f7 203 */
<> 156:95d6b41a828b 204 #define SPI_DIRECTION_2LINES (0x00000000U)
<> 144:ef7eb2e8f9f7 205 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
<> 144:ef7eb2e8f9f7 206 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
<> 144:ef7eb2e8f9f7 207 /**
<> 144:ef7eb2e8f9f7 208 * @}
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /** @defgroup SPI_Data_Size SPI Data Size
<> 144:ef7eb2e8f9f7 212 * @{
<> 144:ef7eb2e8f9f7 213 */
<> 156:95d6b41a828b 214 #define SPI_DATASIZE_4BIT (0x00000300U)
<> 156:95d6b41a828b 215 #define SPI_DATASIZE_5BIT (0x00000400U)
<> 156:95d6b41a828b 216 #define SPI_DATASIZE_6BIT (0x00000500U)
<> 156:95d6b41a828b 217 #define SPI_DATASIZE_7BIT (0x00000600U)
<> 156:95d6b41a828b 218 #define SPI_DATASIZE_8BIT (0x00000700U)
<> 156:95d6b41a828b 219 #define SPI_DATASIZE_9BIT (0x00000800U)
<> 156:95d6b41a828b 220 #define SPI_DATASIZE_10BIT (0x00000900U)
<> 156:95d6b41a828b 221 #define SPI_DATASIZE_11BIT (0x00000A00U)
<> 156:95d6b41a828b 222 #define SPI_DATASIZE_12BIT (0x00000B00U)
<> 156:95d6b41a828b 223 #define SPI_DATASIZE_13BIT (0x00000C00U)
<> 156:95d6b41a828b 224 #define SPI_DATASIZE_14BIT (0x00000D00U)
<> 156:95d6b41a828b 225 #define SPI_DATASIZE_15BIT (0x00000E00U)
<> 156:95d6b41a828b 226 #define SPI_DATASIZE_16BIT (0x00000F00U)
<> 144:ef7eb2e8f9f7 227 /**
<> 144:ef7eb2e8f9f7 228 * @}
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
<> 144:ef7eb2e8f9f7 232 * @{
<> 144:ef7eb2e8f9f7 233 */
<> 156:95d6b41a828b 234 #define SPI_POLARITY_LOW (0x00000000U)
<> 156:95d6b41a828b 235 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
<> 144:ef7eb2e8f9f7 236 /**
<> 144:ef7eb2e8f9f7 237 * @}
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /** @defgroup SPI_Clock_Phase SPI Clock Phase
<> 144:ef7eb2e8f9f7 241 * @{
<> 144:ef7eb2e8f9f7 242 */
<> 156:95d6b41a828b 243 #define SPI_PHASE_1EDGE (0x00000000U)
<> 156:95d6b41a828b 244 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
<> 144:ef7eb2e8f9f7 245 /**
<> 144:ef7eb2e8f9f7 246 * @}
<> 144:ef7eb2e8f9f7 247 */
<> 144:ef7eb2e8f9f7 248
<> 156:95d6b41a828b 249 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management
<> 144:ef7eb2e8f9f7 250 * @{
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252 #define SPI_NSS_SOFT SPI_CR1_SSM
<> 156:95d6b41a828b 253 #define SPI_NSS_HARD_INPUT (0x00000000U)
Anna Bridge 180:96ed750bd169 254 #define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
<> 144:ef7eb2e8f9f7 255 /**
<> 144:ef7eb2e8f9f7 256 * @}
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
<> 144:ef7eb2e8f9f7 260 * @{
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262 #define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
<> 156:95d6b41a828b 263 #define SPI_NSS_PULSE_DISABLE (0x00000000U)
<> 144:ef7eb2e8f9f7 264 /**
<> 144:ef7eb2e8f9f7 265 * @}
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
<> 144:ef7eb2e8f9f7 269 * @{
<> 144:ef7eb2e8f9f7 270 */
<> 156:95d6b41a828b 271 #define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
Anna Bridge 180:96ed750bd169 272 #define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
Anna Bridge 180:96ed750bd169 273 #define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
Anna Bridge 180:96ed750bd169 274 #define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
Anna Bridge 180:96ed750bd169 275 #define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
Anna Bridge 180:96ed750bd169 276 #define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
Anna Bridge 180:96ed750bd169 277 #define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
Anna Bridge 180:96ed750bd169 278 #define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
<> 144:ef7eb2e8f9f7 279 /**
<> 144:ef7eb2e8f9f7 280 * @}
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282
<> 156:95d6b41a828b 283 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
<> 144:ef7eb2e8f9f7 284 * @{
<> 144:ef7eb2e8f9f7 285 */
<> 156:95d6b41a828b 286 #define SPI_FIRSTBIT_MSB (0x00000000U)
<> 144:ef7eb2e8f9f7 287 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
<> 144:ef7eb2e8f9f7 288 /**
<> 144:ef7eb2e8f9f7 289 * @}
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291
<> 156:95d6b41a828b 292 /** @defgroup SPI_TI_mode SPI TI Mode
<> 144:ef7eb2e8f9f7 293 * @{
<> 144:ef7eb2e8f9f7 294 */
<> 156:95d6b41a828b 295 #define SPI_TIMODE_DISABLE (0x00000000U)
<> 144:ef7eb2e8f9f7 296 #define SPI_TIMODE_ENABLE SPI_CR2_FRF
<> 144:ef7eb2e8f9f7 297 /**
<> 144:ef7eb2e8f9f7 298 * @}
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
<> 144:ef7eb2e8f9f7 302 * @{
<> 144:ef7eb2e8f9f7 303 */
<> 156:95d6b41a828b 304 #define SPI_CRCCALCULATION_DISABLE (0x00000000U)
<> 144:ef7eb2e8f9f7 305 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
<> 144:ef7eb2e8f9f7 306 /**
<> 144:ef7eb2e8f9f7 307 * @}
<> 144:ef7eb2e8f9f7 308 */
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /** @defgroup SPI_CRC_length SPI CRC Length
<> 144:ef7eb2e8f9f7 311 * @{
<> 144:ef7eb2e8f9f7 312 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 313 * SPI_CRC_LENGTH_DATASIZE: aligned with the data size
<> 144:ef7eb2e8f9f7 314 * SPI_CRC_LENGTH_8BIT : CRC 8bit
<> 144:ef7eb2e8f9f7 315 * SPI_CRC_LENGTH_16BIT : CRC 16bit
<> 144:ef7eb2e8f9f7 316 */
<> 156:95d6b41a828b 317 #define SPI_CRC_LENGTH_DATASIZE (0x00000000U)
<> 156:95d6b41a828b 318 #define SPI_CRC_LENGTH_8BIT (0x00000001U)
<> 156:95d6b41a828b 319 #define SPI_CRC_LENGTH_16BIT (0x00000002U)
<> 144:ef7eb2e8f9f7 320 /**
<> 144:ef7eb2e8f9f7 321 * @}
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
<> 144:ef7eb2e8f9f7 325 * @{
<> 144:ef7eb2e8f9f7 326 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 327 * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
<> 144:ef7eb2e8f9f7 328 * RXNE event is generated if the FIFO
<> 144:ef7eb2e8f9f7 329 * level is greater or equal to 1/2(16-bits).
<> 144:ef7eb2e8f9f7 330 * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
<> 144:ef7eb2e8f9f7 331 * level is greater or equal to 1/4(8 bits). */
<> 144:ef7eb2e8f9f7 332 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
<> 144:ef7eb2e8f9f7 333 #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
<> 156:95d6b41a828b 334 #define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /**
<> 144:ef7eb2e8f9f7 337 * @}
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339
<> 156:95d6b41a828b 340 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
<> 144:ef7eb2e8f9f7 341 * @{
<> 144:ef7eb2e8f9f7 342 */
<> 144:ef7eb2e8f9f7 343 #define SPI_IT_TXE SPI_CR2_TXEIE
<> 144:ef7eb2e8f9f7 344 #define SPI_IT_RXNE SPI_CR2_RXNEIE
<> 144:ef7eb2e8f9f7 345 #define SPI_IT_ERR SPI_CR2_ERRIE
<> 144:ef7eb2e8f9f7 346 /**
<> 144:ef7eb2e8f9f7 347 * @}
<> 144:ef7eb2e8f9f7 348 */
<> 144:ef7eb2e8f9f7 349
<> 156:95d6b41a828b 350 /** @defgroup SPI_Flags_definition SPI Flags Definition
<> 144:ef7eb2e8f9f7 351 * @{
<> 144:ef7eb2e8f9f7 352 */
<> 156:95d6b41a828b 353 #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
<> 156:95d6b41a828b 354 #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
<> 156:95d6b41a828b 355 #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
<> 156:95d6b41a828b 356 #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
<> 156:95d6b41a828b 357 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
<> 156:95d6b41a828b 358 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
<> 144:ef7eb2e8f9f7 359 #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
<> 156:95d6b41a828b 360 #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
<> 156:95d6b41a828b 361 #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
<> 144:ef7eb2e8f9f7 362 /**
<> 144:ef7eb2e8f9f7 363 * @}
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
<> 144:ef7eb2e8f9f7 367 * @{
<> 144:ef7eb2e8f9f7 368 */
Anna Bridge 180:96ed750bd169 369 #define SPI_FTLVL_EMPTY (0x00000000U)
Anna Bridge 180:96ed750bd169 370 #define SPI_FTLVL_QUARTER_FULL (0x00000800U)
Anna Bridge 180:96ed750bd169 371 #define SPI_FTLVL_HALF_FULL (0x00001000U)
Anna Bridge 180:96ed750bd169 372 #define SPI_FTLVL_FULL (0x00001800U)
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /**
<> 144:ef7eb2e8f9f7 375 * @}
<> 144:ef7eb2e8f9f7 376 */
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
<> 144:ef7eb2e8f9f7 379 * @{
<> 144:ef7eb2e8f9f7 380 */
Anna Bridge 180:96ed750bd169 381 #define SPI_FRLVL_EMPTY (0x00000000U)
Anna Bridge 180:96ed750bd169 382 #define SPI_FRLVL_QUARTER_FULL (0x00000200U)
Anna Bridge 180:96ed750bd169 383 #define SPI_FRLVL_HALF_FULL (0x00000400U)
Anna Bridge 180:96ed750bd169 384 #define SPI_FRLVL_FULL (0x00000600U)
<> 144:ef7eb2e8f9f7 385 /**
<> 144:ef7eb2e8f9f7 386 * @}
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /**
<> 144:ef7eb2e8f9f7 390 * @}
<> 144:ef7eb2e8f9f7 391 */
Anna Bridge 180:96ed750bd169 392
<> 156:95d6b41a828b 393 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 394 /** @defgroup SPI_Exported_Macros SPI Exported Macros
<> 144:ef7eb2e8f9f7 395 * @{
<> 144:ef7eb2e8f9f7 396 */
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 /** @brief Reset SPI handle state.
Anna Bridge 180:96ed750bd169 399 * @param __HANDLE__ specifies the SPI Handle.
<> 156:95d6b41a828b 400 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 401 * @retval None
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
<> 144:ef7eb2e8f9f7 404
Anna Bridge 180:96ed750bd169 405 /** @brief Enable the specified SPI interrupts.
Anna Bridge 180:96ed750bd169 406 * @param __HANDLE__ specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 407 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Anna Bridge 180:96ed750bd169 408 * @param __INTERRUPT__ specifies the interrupt source to enable.
<> 156:95d6b41a828b 409 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 410 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 411 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 412 * @arg SPI_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 413 * @retval None
<> 144:ef7eb2e8f9f7 414 */
Anna Bridge 180:96ed750bd169 415 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Anna Bridge 180:96ed750bd169 416
Anna Bridge 180:96ed750bd169 417 /** @brief Disable the specified SPI interrupts.
Anna Bridge 180:96ed750bd169 418 * @param __HANDLE__ specifies the SPI handle.
Anna Bridge 180:96ed750bd169 419 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
Anna Bridge 180:96ed750bd169 420 * @param __INTERRUPT__ specifies the interrupt source to disable.
Anna Bridge 180:96ed750bd169 421 * This parameter can be one of the following values:
Anna Bridge 180:96ed750bd169 422 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
Anna Bridge 180:96ed750bd169 423 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
Anna Bridge 180:96ed750bd169 424 * @arg SPI_IT_ERR: Error interrupt enable
Anna Bridge 180:96ed750bd169 425 * @retval None
Anna Bridge 180:96ed750bd169 426 */
Anna Bridge 180:96ed750bd169 427 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /** @brief Check whether the specified SPI interrupt source is enabled or not.
Anna Bridge 180:96ed750bd169 430 * @param __HANDLE__ specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 431 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Anna Bridge 180:96ed750bd169 432 * @param __INTERRUPT__ specifies the SPI interrupt source to check.
<> 144:ef7eb2e8f9f7 433 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 434 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 435 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 436 * @arg SPI_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 437 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 438 */
<> 144:ef7eb2e8f9f7 439 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /** @brief Check whether the specified SPI flag is set or not.
Anna Bridge 180:96ed750bd169 442 * @param __HANDLE__ specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 443 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Anna Bridge 180:96ed750bd169 444 * @param __FLAG__ specifies the flag to check.
<> 156:95d6b41a828b 445 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 446 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
<> 144:ef7eb2e8f9f7 447 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
<> 144:ef7eb2e8f9f7 448 * @arg SPI_FLAG_CRCERR: CRC error flag
<> 144:ef7eb2e8f9f7 449 * @arg SPI_FLAG_MODF: Mode fault flag
<> 144:ef7eb2e8f9f7 450 * @arg SPI_FLAG_OVR: Overrun flag
<> 144:ef7eb2e8f9f7 451 * @arg SPI_FLAG_BSY: Busy flag
<> 144:ef7eb2e8f9f7 452 * @arg SPI_FLAG_FRE: Frame format error flag
<> 144:ef7eb2e8f9f7 453 * @arg SPI_FLAG_FTLVL: SPI fifo transmission level
<> 144:ef7eb2e8f9f7 454 * @arg SPI_FLAG_FRLVL: SPI fifo reception level
<> 144:ef7eb2e8f9f7 455 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 456 */
<> 144:ef7eb2e8f9f7 457 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /** @brief Clear the SPI CRCERR pending flag.
Anna Bridge 180:96ed750bd169 460 * @param __HANDLE__ specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 461 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 462 * @retval None
<> 144:ef7eb2e8f9f7 463 */
<> 144:ef7eb2e8f9f7 464 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /** @brief Clear the SPI MODF pending flag.
Anna Bridge 180:96ed750bd169 467 * @param __HANDLE__ specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 468 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 469 * @retval None
<> 144:ef7eb2e8f9f7 470 */
Anna Bridge 180:96ed750bd169 471 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
Anna Bridge 180:96ed750bd169 472 do{ \
Anna Bridge 180:96ed750bd169 473 __IO uint32_t tmpreg_modf = 0x00U; \
Anna Bridge 180:96ed750bd169 474 tmpreg_modf = (__HANDLE__)->Instance->SR; \
Anna Bridge 180:96ed750bd169 475 CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
Anna Bridge 180:96ed750bd169 476 UNUSED(tmpreg_modf); \
Anna Bridge 180:96ed750bd169 477 } while(0U)
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /** @brief Clear the SPI OVR pending flag.
Anna Bridge 180:96ed750bd169 480 * @param __HANDLE__ specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 481 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 482 * @retval None
<> 144:ef7eb2e8f9f7 483 */
<> 156:95d6b41a828b 484 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
<> 156:95d6b41a828b 485 do{ \
<> 156:95d6b41a828b 486 __IO uint32_t tmpreg_ovr = 0x00U; \
<> 156:95d6b41a828b 487 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
<> 156:95d6b41a828b 488 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
<> 156:95d6b41a828b 489 UNUSED(tmpreg_ovr); \
Anna Bridge 180:96ed750bd169 490 } while(0U)
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 /** @brief Clear the SPI FRE pending flag.
Anna Bridge 180:96ed750bd169 493 * @param __HANDLE__ specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 494 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 495 * @retval None
<> 144:ef7eb2e8f9f7 496 */
<> 156:95d6b41a828b 497 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
<> 156:95d6b41a828b 498 do{ \
<> 156:95d6b41a828b 499 __IO uint32_t tmpreg_fre = 0x00U; \
<> 156:95d6b41a828b 500 tmpreg_fre = (__HANDLE__)->Instance->SR; \
<> 156:95d6b41a828b 501 UNUSED(tmpreg_fre); \
Anna Bridge 180:96ed750bd169 502 }while(0U)
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /** @brief Enable the SPI peripheral.
Anna Bridge 180:96ed750bd169 505 * @param __HANDLE__ specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 506 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 507 * @retval None
<> 144:ef7eb2e8f9f7 508 */
Anna Bridge 180:96ed750bd169 509 #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /** @brief Disable the SPI peripheral.
Anna Bridge 180:96ed750bd169 512 * @param __HANDLE__ specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 513 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 514 * @retval None
<> 144:ef7eb2e8f9f7 515 */
Anna Bridge 180:96ed750bd169 516 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /**
<> 144:ef7eb2e8f9f7 519 * @}
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521
<> 156:95d6b41a828b 522 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 523 /** @defgroup SPI_Private_Macros SPI Private Macros
<> 144:ef7eb2e8f9f7 524 * @{
<> 144:ef7eb2e8f9f7 525 */
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /** @brief Set the SPI transmit-only mode.
Anna Bridge 180:96ed750bd169 528 * @param __HANDLE__ specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 529 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 530 * @retval None
<> 144:ef7eb2e8f9f7 531 */
Anna Bridge 180:96ed750bd169 532 #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /** @brief Set the SPI receive-only mode.
Anna Bridge 180:96ed750bd169 535 * @param __HANDLE__ specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 536 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 537 * @retval None
<> 144:ef7eb2e8f9f7 538 */
Anna Bridge 180:96ed750bd169 539 #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /** @brief Reset the CRC calculation of the SPI.
Anna Bridge 180:96ed750bd169 542 * @param __HANDLE__ specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 543 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 544 * @retval None
<> 144:ef7eb2e8f9f7 545 */
Anna Bridge 180:96ed750bd169 546 #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
Anna Bridge 180:96ed750bd169 547 SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
<> 144:ef7eb2e8f9f7 550 ((MODE) == SPI_MODE_MASTER))
<> 144:ef7eb2e8f9f7 551
<> 156:95d6b41a828b 552 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
<> 156:95d6b41a828b 553 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
<> 156:95d6b41a828b 554 ((MODE) == SPI_DIRECTION_1LINE))
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 557
<> 156:95d6b41a828b 558 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
<> 156:95d6b41a828b 559 ((MODE) == SPI_DIRECTION_1LINE))
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
<> 144:ef7eb2e8f9f7 562 ((DATASIZE) == SPI_DATASIZE_15BIT) || \
<> 144:ef7eb2e8f9f7 563 ((DATASIZE) == SPI_DATASIZE_14BIT) || \
<> 144:ef7eb2e8f9f7 564 ((DATASIZE) == SPI_DATASIZE_13BIT) || \
<> 144:ef7eb2e8f9f7 565 ((DATASIZE) == SPI_DATASIZE_12BIT) || \
<> 144:ef7eb2e8f9f7 566 ((DATASIZE) == SPI_DATASIZE_11BIT) || \
<> 144:ef7eb2e8f9f7 567 ((DATASIZE) == SPI_DATASIZE_10BIT) || \
<> 144:ef7eb2e8f9f7 568 ((DATASIZE) == SPI_DATASIZE_9BIT) || \
<> 144:ef7eb2e8f9f7 569 ((DATASIZE) == SPI_DATASIZE_8BIT) || \
<> 144:ef7eb2e8f9f7 570 ((DATASIZE) == SPI_DATASIZE_7BIT) || \
<> 144:ef7eb2e8f9f7 571 ((DATASIZE) == SPI_DATASIZE_6BIT) || \
<> 144:ef7eb2e8f9f7 572 ((DATASIZE) == SPI_DATASIZE_5BIT) || \
<> 144:ef7eb2e8f9f7 573 ((DATASIZE) == SPI_DATASIZE_4BIT))
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
<> 144:ef7eb2e8f9f7 576 ((CPOL) == SPI_POLARITY_HIGH))
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
<> 144:ef7eb2e8f9f7 579 ((CPHA) == SPI_PHASE_2EDGE))
<> 144:ef7eb2e8f9f7 580
<> 156:95d6b41a828b 581 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
<> 144:ef7eb2e8f9f7 582 ((NSS) == SPI_NSS_HARD_INPUT) || \
<> 144:ef7eb2e8f9f7 583 ((NSS) == SPI_NSS_HARD_OUTPUT))
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
<> 144:ef7eb2e8f9f7 586 ((NSSP) == SPI_NSS_PULSE_DISABLE))
<> 144:ef7eb2e8f9f7 587
<> 156:95d6b41a828b 588 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
<> 156:95d6b41a828b 589 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
<> 156:95d6b41a828b 590 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
<> 156:95d6b41a828b 591 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
<> 156:95d6b41a828b 592 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
<> 156:95d6b41a828b 593 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
<> 144:ef7eb2e8f9f7 594 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
<> 144:ef7eb2e8f9f7 595 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
<> 144:ef7eb2e8f9f7 598 ((BIT) == SPI_FIRSTBIT_LSB))
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 601 ((MODE) == SPI_TIMODE_ENABLE))
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
<> 144:ef7eb2e8f9f7 604 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
<> 144:ef7eb2e8f9f7 607 ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
<> 144:ef7eb2e8f9f7 608 ((LENGTH) == SPI_CRC_LENGTH_16BIT))
<> 144:ef7eb2e8f9f7 609
<> 156:95d6b41a828b 610 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
<> 144:ef7eb2e8f9f7 611
Anna Bridge 180:96ed750bd169 612 #define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL)
Anna Bridge 180:96ed750bd169 613
Anna Bridge 180:96ed750bd169 614 #define IS_SPI_16BIT_ALIGNED_ADDRESS(DATA) (((uint32_t)(DATA) % 2U) == 0U)
Anna Bridge 180:96ed750bd169 615
<> 144:ef7eb2e8f9f7 616 /**
<> 144:ef7eb2e8f9f7 617 * @}
<> 144:ef7eb2e8f9f7 618 */
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /* Include SPI HAL Extended module */
<> 144:ef7eb2e8f9f7 621 #include "stm32f0xx_hal_spi_ex.h"
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 624 /** @addtogroup SPI_Exported_Functions
<> 144:ef7eb2e8f9f7 625 * @{
<> 144:ef7eb2e8f9f7 626 */
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /** @addtogroup SPI_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 629 * @{
<> 144:ef7eb2e8f9f7 630 */
<> 156:95d6b41a828b 631 /* Initialization/de-initialization functions ********************************/
<> 144:ef7eb2e8f9f7 632 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 633 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 634 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 635 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 636 /**
<> 144:ef7eb2e8f9f7 637 * @}
<> 144:ef7eb2e8f9f7 638 */
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /** @addtogroup SPI_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 641 * @{
<> 144:ef7eb2e8f9f7 642 */
<> 156:95d6b41a828b 643 /* I/O operation functions ***************************************************/
<> 144:ef7eb2e8f9f7 644 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 645 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 156:95d6b41a828b 646 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
<> 156:95d6b41a828b 647 uint32_t Timeout);
<> 144:ef7eb2e8f9f7 648 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 649 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 156:95d6b41a828b 650 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
<> 156:95d6b41a828b 651 uint16_t Size);
<> 144:ef7eb2e8f9f7 652 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 653 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 156:95d6b41a828b 654 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
<> 156:95d6b41a828b 655 uint16_t Size);
<> 144:ef7eb2e8f9f7 656 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 657 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 658 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 659 /* Transfer Abort functions */
<> 156:95d6b41a828b 660 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 661 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 664 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 665 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 666 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 667 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 668 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 669 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 670 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 671 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 672 /**
<> 144:ef7eb2e8f9f7 673 * @}
<> 144:ef7eb2e8f9f7 674 */
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /** @addtogroup SPI_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 677 * @{
<> 144:ef7eb2e8f9f7 678 */
<> 156:95d6b41a828b 679 /* Peripheral State and Error functions ***************************************/
<> 144:ef7eb2e8f9f7 680 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 681 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 682 /**
<> 144:ef7eb2e8f9f7 683 * @}
<> 144:ef7eb2e8f9f7 684 */
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /**
<> 144:ef7eb2e8f9f7 687 * @}
<> 144:ef7eb2e8f9f7 688 */
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /**
<> 144:ef7eb2e8f9f7 691 * @}
<> 144:ef7eb2e8f9f7 692 */
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /**
<> 144:ef7eb2e8f9f7 695 * @}
<> 144:ef7eb2e8f9f7 696 */
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 699 }
<> 144:ef7eb2e8f9f7 700 #endif
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 #endif /* __STM32F0xx_HAL_SPI_H */
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/