mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_spi.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief SPI HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
<> 144:ef7eb2e8f9f7 8 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 9 * + IO operation functions
<> 144:ef7eb2e8f9f7 10 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 The SPI HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (#) Declare a SPI_HandleTypeDef handle structure, for example:
<> 144:ef7eb2e8f9f7 21 SPI_HandleTypeDef hspi;
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
<> 144:ef7eb2e8f9f7 24 (##) Enable the SPIx interface clock
<> 144:ef7eb2e8f9f7 25 (##) SPI pins configuration
<> 144:ef7eb2e8f9f7 26 (+++) Enable the clock for the SPI GPIOs
<> 144:ef7eb2e8f9f7 27 (+++) Configure these SPI pins as alternate function push-pull
<> 144:ef7eb2e8f9f7 28 (##) NVIC configuration if you need to use interrupt process
<> 144:ef7eb2e8f9f7 29 (+++) Configure the SPIx interrupt priority
<> 144:ef7eb2e8f9f7 30 (+++) Enable the NVIC SPI IRQ handle
<> 144:ef7eb2e8f9f7 31 (##) DMA Configuration if you need to use DMA process
<> 156:95d6b41a828b 32 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
<> 144:ef7eb2e8f9f7 33 (+++) Enable the DMAx clock
<> 144:ef7eb2e8f9f7 34 (+++) Configure the DMA handle parameters
<> 156:95d6b41a828b 35 (+++) Configure the DMA Tx or Rx Stream/Channel
<> 144:ef7eb2e8f9f7 36 (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
<> 156:95d6b41a828b 37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
<> 144:ef7eb2e8f9f7 40 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
<> 144:ef7eb2e8f9f7 43 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<> 144:ef7eb2e8f9f7 44 by calling the customized HAL_SPI_MspInit() API.
<> 144:ef7eb2e8f9f7 45 [..]
<> 144:ef7eb2e8f9f7 46 Circular mode restriction:
<> 144:ef7eb2e8f9f7 47 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
<> 144:ef7eb2e8f9f7 48 (##) Master 2Lines RxOnly
<> 144:ef7eb2e8f9f7 49 (##) Master 1Line Rx
<> 144:ef7eb2e8f9f7 50 (#) The CRC feature is not managed when the DMA circular mode is enabled
<> 144:ef7eb2e8f9f7 51 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
<> 144:ef7eb2e8f9f7 52 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
<> 156:95d6b41a828b 53 [..]
<> 156:95d6b41a828b 54 Master Receive mode restriction:
<> 156:95d6b41a828b 55 (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
<> 156:95d6b41a828b 56 bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
<> 156:95d6b41a828b 57 does not initiate a new transfer the following procedure has to be respected:
<> 156:95d6b41a828b 58 (##) HAL_SPI_DeInit()
<> 156:95d6b41a828b 59 (##) HAL_SPI_Init()
<> 156:95d6b41a828b 60 [..]
Anna Bridge 180:96ed750bd169 61 The HAL drivers do not allow reaching all supported SPI frequencies in the different SPI
Anna Bridge 180:96ed750bd169 62 modes. Refer to the source code (stm32xxxx_hal_spi.c header) to get a summary of the
Anna Bridge 180:96ed750bd169 63 maximum SPI frequency that can be reached with a data size of 8 or 16 bits, depending on
Anna Bridge 180:96ed750bd169 64 the APBx peripheral clock frequency (fPCLK) used by the SPI instance.
Anna Bridge 180:96ed750bd169 65
Anna Bridge 180:96ed750bd169 66 [..]
Anna Bridge 180:96ed750bd169 67 Data buffer address alignment restriction:
Anna Bridge 180:96ed750bd169 68 (#) In case more than 1 byte is requested to be transferred, the HAL SPI uses 16-bit access for data buffer.
Anna Bridge 180:96ed750bd169 69 But there is no support for unaligned accesses on the Cortex-M0 processor.
Anna Bridge 180:96ed750bd169 70 So, if the user wants to transfer more than 1 byte, it shall ensure that 16-bit aligned address is used for:
Anna Bridge 180:96ed750bd169 71 (##) pData parameter in HAL_SPI_Transmit(), HAL_SPI_Transmit_IT(), HAL_SPI_Receive() and HAL_SPI_Receive_IT()
Anna Bridge 180:96ed750bd169 72 (##) pTxData and pRxData parameters in HAL_SPI_TransmitReceive() and HAL_SPI_TransmitReceive_IT()
Anna Bridge 180:96ed750bd169 73 (#) There is no such restriction when going through DMA by using HAL_SPI_Transmit_DMA(), HAL_SPI_Receive_DMA()
Anna Bridge 180:96ed750bd169 74 and HAL_SPI_TransmitReceive_DMA().
Anna Bridge 180:96ed750bd169 75
Anna Bridge 180:96ed750bd169 76 @endverbatim
Anna Bridge 180:96ed750bd169 77
Anna Bridge 180:96ed750bd169 78 Additional table :
<> 156:95d6b41a828b 79
<> 156:95d6b41a828b 80 DataSize = SPI_DATASIZE_8BIT:
<> 156:95d6b41a828b 81 +----------------------------------------------------------------------------------------------+
<> 156:95d6b41a828b 82 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
<> 156:95d6b41a828b 83 | Process | Tranfert mode |---------------------|----------------------|----------------------|
<> 156:95d6b41a828b 84 | | | Master | Slave | Master | Slave | Master | Slave |
<> 156:95d6b41a828b 85 |==============================================================================================|
<> 156:95d6b41a828b 86 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
<> 156:95d6b41a828b 87 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 88 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
<> 156:95d6b41a828b 89 | R |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 90 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
<> 156:95d6b41a828b 91 |=========|================|==========|==========|===========|==========|===========|==========|
<> 156:95d6b41a828b 92 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
<> 156:95d6b41a828b 93 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 94 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
<> 156:95d6b41a828b 95 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 96 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
<> 156:95d6b41a828b 97 |=========|================|==========|==========|===========|==========|===========|==========|
<> 156:95d6b41a828b 98 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
<> 156:95d6b41a828b 99 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 100 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
<> 156:95d6b41a828b 101 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 102 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
<> 156:95d6b41a828b 103 +----------------------------------------------------------------------------------------------+
<> 156:95d6b41a828b 104
<> 156:95d6b41a828b 105 DataSize = SPI_DATASIZE_16BIT:
<> 156:95d6b41a828b 106 +----------------------------------------------------------------------------------------------+
<> 156:95d6b41a828b 107 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
<> 156:95d6b41a828b 108 | Process | Tranfert mode |---------------------|----------------------|----------------------|
<> 156:95d6b41a828b 109 | | | Master | Slave | Master | Slave | Master | Slave |
<> 156:95d6b41a828b 110 |==============================================================================================|
<> 156:95d6b41a828b 111 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
<> 156:95d6b41a828b 112 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 113 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
<> 156:95d6b41a828b 114 | R |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 115 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
<> 156:95d6b41a828b 116 |=========|================|==========|==========|===========|==========|===========|==========|
<> 156:95d6b41a828b 117 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
<> 156:95d6b41a828b 118 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 119 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
<> 156:95d6b41a828b 120 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 121 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
<> 156:95d6b41a828b 122 |=========|================|==========|==========|===========|==========|===========|==========|
<> 156:95d6b41a828b 123 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
<> 156:95d6b41a828b 124 | |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 125 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
<> 156:95d6b41a828b 126 | X |----------------|----------|----------|-----------|----------|-----------|----------|
<> 156:95d6b41a828b 127 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
<> 156:95d6b41a828b 128 +----------------------------------------------------------------------------------------------+
<> 156:95d6b41a828b 129 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
<> 156:95d6b41a828b 130 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
<> 156:95d6b41a828b 131 @note
<> 156:95d6b41a828b 132 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
<> 156:95d6b41a828b 133 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
<> 156:95d6b41a828b 134 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 ******************************************************************************
<> 144:ef7eb2e8f9f7 137 * @attention
<> 144:ef7eb2e8f9f7 138 *
<> 144:ef7eb2e8f9f7 139 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 140 *
<> 144:ef7eb2e8f9f7 141 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 142 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 143 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 144 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 145 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 146 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 147 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 148 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 149 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 150 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 151 *
<> 144:ef7eb2e8f9f7 152 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 153 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 154 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 155 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 156 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 157 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 158 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 159 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 160 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 161 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 162 *
<> 144:ef7eb2e8f9f7 163 ******************************************************************************
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 167 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 170 * @{
<> 144:ef7eb2e8f9f7 171 */
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /** @defgroup SPI SPI
<> 144:ef7eb2e8f9f7 174 * @brief SPI HAL module driver
<> 144:ef7eb2e8f9f7 175 * @{
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177 #ifdef HAL_SPI_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 180 /* Private defines -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 181 /** @defgroup SPI_Private_Constants SPI Private Constants
<> 144:ef7eb2e8f9f7 182 * @{
<> 144:ef7eb2e8f9f7 183 */
<> 156:95d6b41a828b 184 #define SPI_DEFAULT_TIMEOUT 100U
<> 144:ef7eb2e8f9f7 185 /**
<> 144:ef7eb2e8f9f7 186 * @}
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 190 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 191 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 192 /** @defgroup SPI_Private_Functions SPI Private Functions
<> 144:ef7eb2e8f9f7 193 * @{
<> 144:ef7eb2e8f9f7 194 */
<> 144:ef7eb2e8f9f7 195 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 196 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 197 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 198 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 199 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 200 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 201 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 202 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 203 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 204 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
<> 156:95d6b41a828b 205 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
<> 156:95d6b41a828b 206 uint32_t Timeout, uint32_t Tickstart);
<> 156:95d6b41a828b 207 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
<> 156:95d6b41a828b 208 uint32_t Timeout, uint32_t Tickstart);
<> 144:ef7eb2e8f9f7 209 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 210 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 211 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 212 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 213 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 214 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 215 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 216 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 217 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 218 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 219 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 220 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 221 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 222 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 223 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 224 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 225 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 226 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 227 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 228 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
<> 156:95d6b41a828b 229 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
<> 144:ef7eb2e8f9f7 230 /**
<> 144:ef7eb2e8f9f7 231 * @}
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233
<> 156:95d6b41a828b 234 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 235 /** @defgroup SPI_Exported_Functions SPI Exported Functions
<> 144:ef7eb2e8f9f7 236 * @{
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 240 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 241 *
<> 144:ef7eb2e8f9f7 242 @verbatim
<> 144:ef7eb2e8f9f7 243 ===============================================================================
<> 144:ef7eb2e8f9f7 244 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 245 ===============================================================================
<> 144:ef7eb2e8f9f7 246 [..] This subsection provides a set of functions allowing to initialize and
<> 144:ef7eb2e8f9f7 247 de-initialize the SPIx peripheral:
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 (+) User must implement HAL_SPI_MspInit() function in which he configures
<> 144:ef7eb2e8f9f7 250 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 (+) Call the function HAL_SPI_Init() to configure the selected device with
<> 144:ef7eb2e8f9f7 253 the selected configuration:
<> 144:ef7eb2e8f9f7 254 (++) Mode
<> 144:ef7eb2e8f9f7 255 (++) Direction
<> 144:ef7eb2e8f9f7 256 (++) Data Size
<> 144:ef7eb2e8f9f7 257 (++) Clock Polarity and Phase
<> 144:ef7eb2e8f9f7 258 (++) NSS Management
<> 144:ef7eb2e8f9f7 259 (++) BaudRate Prescaler
<> 144:ef7eb2e8f9f7 260 (++) FirstBit
<> 144:ef7eb2e8f9f7 261 (++) TIMode
<> 144:ef7eb2e8f9f7 262 (++) CRC Calculation
<> 144:ef7eb2e8f9f7 263 (++) CRC Polynomial if CRC enabled
<> 144:ef7eb2e8f9f7 264 (++) CRC Length, used only with Data8 and Data16
<> 144:ef7eb2e8f9f7 265 (++) FIFO reception threshold
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
<> 144:ef7eb2e8f9f7 268 of the selected SPIx peripheral.
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 @endverbatim
<> 144:ef7eb2e8f9f7 271 * @{
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @brief Initialize the SPI according to the specified parameters
<> 144:ef7eb2e8f9f7 276 * in the SPI_InitTypeDef and initialize the associated handle.
Anna Bridge 180:96ed750bd169 277 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 278 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 279 * @retval HAL status
<> 144:ef7eb2e8f9f7 280 */
<> 144:ef7eb2e8f9f7 281 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 282 {
<> 144:ef7eb2e8f9f7 283 uint32_t frxth;
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /* Check the SPI handle allocation */
<> 156:95d6b41a828b 286 if (hspi == NULL)
<> 144:ef7eb2e8f9f7 287 {
<> 144:ef7eb2e8f9f7 288 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 289 }
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /* Check the parameters */
<> 144:ef7eb2e8f9f7 292 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
<> 144:ef7eb2e8f9f7 293 assert_param(IS_SPI_MODE(hspi->Init.Mode));
<> 144:ef7eb2e8f9f7 294 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 295 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
<> 144:ef7eb2e8f9f7 296 assert_param(IS_SPI_NSS(hspi->Init.NSS));
<> 144:ef7eb2e8f9f7 297 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
<> 144:ef7eb2e8f9f7 298 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
<> 144:ef7eb2e8f9f7 299 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
<> 144:ef7eb2e8f9f7 300 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
<> 156:95d6b41a828b 301 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
<> 156:95d6b41a828b 302 {
<> 156:95d6b41a828b 303 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
<> 156:95d6b41a828b 304 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
<> 156:95d6b41a828b 305 }
<> 156:95d6b41a828b 306 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 307 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
<> 156:95d6b41a828b 308 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 156:95d6b41a828b 309 {
<> 156:95d6b41a828b 310 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
<> 156:95d6b41a828b 311 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
<> 156:95d6b41a828b 312 }
<> 156:95d6b41a828b 313 #else
<> 156:95d6b41a828b 314 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
<> 156:95d6b41a828b 315 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 316
<> 156:95d6b41a828b 317 if (hspi->State == HAL_SPI_STATE_RESET)
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 320 hspi->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 323 HAL_SPI_MspInit(hspi);
<> 144:ef7eb2e8f9f7 324 }
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 hspi->State = HAL_SPI_STATE_BUSY;
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /* Disable the selected SPI peripheral */
<> 144:ef7eb2e8f9f7 329 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /* Align by default the rs fifo threshold on the data size */
<> 156:95d6b41a828b 332 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 333 {
<> 144:ef7eb2e8f9f7 334 frxth = SPI_RXFIFO_THRESHOLD_HF;
<> 144:ef7eb2e8f9f7 335 }
<> 144:ef7eb2e8f9f7 336 else
<> 144:ef7eb2e8f9f7 337 {
<> 144:ef7eb2e8f9f7 338 frxth = SPI_RXFIFO_THRESHOLD_QF;
<> 144:ef7eb2e8f9f7 339 }
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /* CRC calculation is valid only for 16Bit and 8 Bit */
<> 156:95d6b41a828b 342 if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
<> 144:ef7eb2e8f9f7 343 {
<> 144:ef7eb2e8f9f7 344 /* CRC must be disabled */
<> 144:ef7eb2e8f9f7 345 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
<> 144:ef7eb2e8f9f7 346 }
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /* Align the CRC Length on the data size */
<> 156:95d6b41a828b 349 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
<> 144:ef7eb2e8f9f7 350 {
<> 144:ef7eb2e8f9f7 351 /* CRC Length aligned on the data size : value set by default */
<> 156:95d6b41a828b 352 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 353 {
<> 144:ef7eb2e8f9f7 354 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
<> 144:ef7eb2e8f9f7 355 }
<> 144:ef7eb2e8f9f7 356 else
<> 144:ef7eb2e8f9f7 357 {
<> 144:ef7eb2e8f9f7 358 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
<> 144:ef7eb2e8f9f7 359 }
<> 144:ef7eb2e8f9f7 360 }
<> 144:ef7eb2e8f9f7 361
<> 156:95d6b41a828b 362 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
<> 144:ef7eb2e8f9f7 363 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
Anna Bridge 180:96ed750bd169 364 Communication speed, First bit and CRC calculation state */
<> 156:95d6b41a828b 365 WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
<> 156:95d6b41a828b 366 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
<> 156:95d6b41a828b 367 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
<> 156:95d6b41a828b 368 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 369 /* Configure : CRC Length */
<> 156:95d6b41a828b 370 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
<> 144:ef7eb2e8f9f7 371 {
<> 156:95d6b41a828b 372 hspi->Instance->CR1 |= SPI_CR1_CRCL;
<> 144:ef7eb2e8f9f7 373 }
<> 156:95d6b41a828b 374 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 375
Anna Bridge 180:96ed750bd169 376 /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo Threshold */
<> 156:95d6b41a828b 377 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
<> 156:95d6b41a828b 378 hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
<> 156:95d6b41a828b 379
<> 156:95d6b41a828b 380 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 381 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
<> 144:ef7eb2e8f9f7 382 /* Configure : CRC Polynomial */
<> 156:95d6b41a828b 383 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 156:95d6b41a828b 384 {
<> 156:95d6b41a828b 385 WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
<> 156:95d6b41a828b 386 }
<> 156:95d6b41a828b 387 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 388
<> 156:95d6b41a828b 389 #if defined(SPI_I2SCFGR_I2SMOD)
<> 144:ef7eb2e8f9f7 390 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
<> 156:95d6b41a828b 391 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
<> 156:95d6b41a828b 392 #endif /* SPI_I2SCFGR_I2SMOD */
<> 156:95d6b41a828b 393
<> 144:ef7eb2e8f9f7 394 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 395 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 return HAL_OK;
<> 144:ef7eb2e8f9f7 398 }
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /**
<> 156:95d6b41a828b 401 * @brief De-Initialize the SPI peripheral.
Anna Bridge 180:96ed750bd169 402 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 403 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 404 * @retval HAL status
<> 144:ef7eb2e8f9f7 405 */
<> 144:ef7eb2e8f9f7 406 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 407 {
<> 144:ef7eb2e8f9f7 408 /* Check the SPI handle allocation */
<> 156:95d6b41a828b 409 if (hspi == NULL)
<> 144:ef7eb2e8f9f7 410 {
<> 144:ef7eb2e8f9f7 411 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 412 }
<> 144:ef7eb2e8f9f7 413
<> 156:95d6b41a828b 414 /* Check SPI Instance parameter */
<> 144:ef7eb2e8f9f7 415 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
<> 156:95d6b41a828b 416
<> 144:ef7eb2e8f9f7 417 hspi->State = HAL_SPI_STATE_BUSY;
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Disable the SPI Peripheral Clock */
<> 144:ef7eb2e8f9f7 420 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 423 HAL_SPI_MspDeInit(hspi);
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 426 hspi->State = HAL_SPI_STATE_RESET;
<> 144:ef7eb2e8f9f7 427
<> 156:95d6b41a828b 428 /* Release Lock */
<> 144:ef7eb2e8f9f7 429 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 return HAL_OK;
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /**
<> 144:ef7eb2e8f9f7 435 * @brief Initialize the SPI MSP.
Anna Bridge 180:96ed750bd169 436 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 437 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 438 * @retval None
<> 144:ef7eb2e8f9f7 439 */
<> 144:ef7eb2e8f9f7 440 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 441 {
<> 144:ef7eb2e8f9f7 442 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 443 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 444
<> 156:95d6b41a828b 445 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 446 the HAL_SPI_MspInit should be implemented in the user file
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448 }
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /**
<> 156:95d6b41a828b 451 * @brief De-Initialize the SPI MSP.
Anna Bridge 180:96ed750bd169 452 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 453 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 454 * @retval None
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 457 {
<> 144:ef7eb2e8f9f7 458 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 459 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 462 the HAL_SPI_MspDeInit should be implemented in the user file
<> 144:ef7eb2e8f9f7 463 */
<> 144:ef7eb2e8f9f7 464 }
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /**
<> 144:ef7eb2e8f9f7 467 * @}
<> 144:ef7eb2e8f9f7 468 */
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 471 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 472 *
<> 144:ef7eb2e8f9f7 473 @verbatim
<> 144:ef7eb2e8f9f7 474 ==============================================================================
<> 144:ef7eb2e8f9f7 475 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 476 ===============================================================================
<> 144:ef7eb2e8f9f7 477 [..]
<> 144:ef7eb2e8f9f7 478 This subsection provides a set of functions allowing to manage the SPI
<> 144:ef7eb2e8f9f7 479 data transfers.
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 [..] The SPI supports master and slave mode :
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 484 (++) Blocking mode: The communication is performed in polling mode.
<> 144:ef7eb2e8f9f7 485 The HAL status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 486 after finishing transfer.
<> 144:ef7eb2e8f9f7 487 (++) No-Blocking mode: The communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 488 or DMA, These APIs return the HAL status.
<> 144:ef7eb2e8f9f7 489 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 490 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 491 using DMA mode.
<> 144:ef7eb2e8f9f7 492 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
<> 144:ef7eb2e8f9f7 493 will be executed respectively at the end of the transmit or Receive process
<> 144:ef7eb2e8f9f7 494 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
<> 144:ef7eb2e8f9f7 497 exist for 1Line (simplex) and 2Lines (full duplex) modes.
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 @endverbatim
<> 144:ef7eb2e8f9f7 500 * @{
<> 144:ef7eb2e8f9f7 501 */
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /**
<> 144:ef7eb2e8f9f7 504 * @brief Transmit an amount of data in blocking mode.
Anna Bridge 180:96ed750bd169 505 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 506 * the configuration information for SPI module.
Anna Bridge 180:96ed750bd169 507 * @param pData pointer to data buffer
Anna Bridge 180:96ed750bd169 508 * @param Size amount of data to be sent
Anna Bridge 180:96ed750bd169 509 * @param Timeout Timeout duration
<> 144:ef7eb2e8f9f7 510 * @retval HAL status
<> 144:ef7eb2e8f9f7 511 */
<> 144:ef7eb2e8f9f7 512 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 513 {
<> 156:95d6b41a828b 514 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 515 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 516
Anna Bridge 180:96ed750bd169 517 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U))
Anna Bridge 180:96ed750bd169 518 {
Anna Bridge 180:96ed750bd169 519 /* in this case, 16-bit access is performed on Data
Anna Bridge 180:96ed750bd169 520 So, check Data is 16-bit aligned address */
Anna Bridge 180:96ed750bd169 521 assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
Anna Bridge 180:96ed750bd169 522 }
Anna Bridge 180:96ed750bd169 523
<> 156:95d6b41a828b 524 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 525 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /* Process Locked */
<> 144:ef7eb2e8f9f7 528 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 529
<> 156:95d6b41a828b 530 /* Init tickstart for timeout management*/
<> 156:95d6b41a828b 531 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 532
<> 156:95d6b41a828b 533 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 534 {
<> 144:ef7eb2e8f9f7 535 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 536 goto error;
<> 144:ef7eb2e8f9f7 537 }
<> 144:ef7eb2e8f9f7 538
<> 156:95d6b41a828b 539 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 540 {
<> 144:ef7eb2e8f9f7 541 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 542 goto error;
<> 144:ef7eb2e8f9f7 543 }
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 546 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 547 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 548 hspi->pTxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 549 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 550 hspi->TxXferCount = Size;
<> 156:95d6b41a828b 551
<> 156:95d6b41a828b 552 /*Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 553 hspi->pRxBuffPtr = (uint8_t *)NULL;
<> 156:95d6b41a828b 554 hspi->RxXferSize = 0U;
<> 156:95d6b41a828b 555 hspi->RxXferCount = 0U;
<> 156:95d6b41a828b 556 hspi->TxISR = NULL;
<> 156:95d6b41a828b 557 hspi->RxISR = NULL;
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /* Configure communication direction : 1Line */
<> 156:95d6b41a828b 560 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 561 {
<> 144:ef7eb2e8f9f7 562 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 563 }
<> 144:ef7eb2e8f9f7 564
<> 156:95d6b41a828b 565 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 566 /* Reset CRC Calculation */
<> 156:95d6b41a828b 567 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 568 {
<> 144:ef7eb2e8f9f7 569 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 570 }
<> 156:95d6b41a828b 571 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 /* Check if the SPI is already enabled */
<> 156:95d6b41a828b 574 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 575 {
<> 144:ef7eb2e8f9f7 576 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 577 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /* Transmit data in 16 Bit mode */
<> 156:95d6b41a828b 581 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 582 {
Anna Bridge 180:96ed750bd169 583 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
<> 156:95d6b41a828b 584 {
<> 156:95d6b41a828b 585 hspi->Instance->DR = *((uint16_t *)pData);
<> 156:95d6b41a828b 586 pData += sizeof(uint16_t);
<> 156:95d6b41a828b 587 hspi->TxXferCount--;
<> 156:95d6b41a828b 588 }
<> 144:ef7eb2e8f9f7 589 /* Transmit data in 16 Bit mode */
<> 156:95d6b41a828b 590 while (hspi->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 591 {
<> 144:ef7eb2e8f9f7 592 /* Wait until TXE flag is set to send data */
<> 156:95d6b41a828b 593 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
<> 144:ef7eb2e8f9f7 594 {
<> 156:95d6b41a828b 595 hspi->Instance->DR = *((uint16_t *)pData);
<> 156:95d6b41a828b 596 pData += sizeof(uint16_t);
<> 156:95d6b41a828b 597 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 598 }
<> 144:ef7eb2e8f9f7 599 else
<> 144:ef7eb2e8f9f7 600 {
<> 144:ef7eb2e8f9f7 601 /* Timeout management */
<> 156:95d6b41a828b 602 if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 603 {
<> 144:ef7eb2e8f9f7 604 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 605 goto error;
<> 144:ef7eb2e8f9f7 606 }
<> 144:ef7eb2e8f9f7 607 }
<> 144:ef7eb2e8f9f7 608 }
<> 144:ef7eb2e8f9f7 609 }
<> 144:ef7eb2e8f9f7 610 /* Transmit data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 611 else
<> 144:ef7eb2e8f9f7 612 {
Anna Bridge 180:96ed750bd169 613 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
<> 156:95d6b41a828b 614 {
<> 156:95d6b41a828b 615 if (hspi->TxXferCount > 1U)
<> 156:95d6b41a828b 616 {
<> 156:95d6b41a828b 617 /* write on the data register in packing mode */
<> 156:95d6b41a828b 618 hspi->Instance->DR = *((uint16_t *)pData);
<> 156:95d6b41a828b 619 pData += sizeof(uint16_t);
<> 156:95d6b41a828b 620 hspi->TxXferCount -= 2U;
<> 156:95d6b41a828b 621 }
<> 156:95d6b41a828b 622 else
<> 156:95d6b41a828b 623 {
<> 156:95d6b41a828b 624 *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
<> 156:95d6b41a828b 625 hspi->TxXferCount--;
<> 156:95d6b41a828b 626 }
<> 156:95d6b41a828b 627 }
<> 156:95d6b41a828b 628 while (hspi->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 629 {
<> 144:ef7eb2e8f9f7 630 /* Wait until TXE flag is set to send data */
<> 156:95d6b41a828b 631 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
<> 144:ef7eb2e8f9f7 632 {
<> 156:95d6b41a828b 633 if (hspi->TxXferCount > 1U)
<> 144:ef7eb2e8f9f7 634 {
<> 144:ef7eb2e8f9f7 635 /* write on the data register in packing mode */
<> 156:95d6b41a828b 636 hspi->Instance->DR = *((uint16_t *)pData);
<> 156:95d6b41a828b 637 pData += sizeof(uint16_t);
<> 156:95d6b41a828b 638 hspi->TxXferCount -= 2U;
<> 144:ef7eb2e8f9f7 639 }
<> 144:ef7eb2e8f9f7 640 else
<> 144:ef7eb2e8f9f7 641 {
<> 156:95d6b41a828b 642 *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
<> 144:ef7eb2e8f9f7 643 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 644 }
<> 144:ef7eb2e8f9f7 645 }
<> 144:ef7eb2e8f9f7 646 else
<> 144:ef7eb2e8f9f7 647 {
<> 144:ef7eb2e8f9f7 648 /* Timeout management */
<> 156:95d6b41a828b 649 if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 650 {
<> 144:ef7eb2e8f9f7 651 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 652 goto error;
<> 144:ef7eb2e8f9f7 653 }
<> 144:ef7eb2e8f9f7 654 }
<> 144:ef7eb2e8f9f7 655 }
<> 144:ef7eb2e8f9f7 656 }
<> 156:95d6b41a828b 657 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 658 /* Enable CRC Transmission */
<> 156:95d6b41a828b 659 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 660 {
<> 156:95d6b41a828b 661 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 662 }
<> 156:95d6b41a828b 663 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 /* Check the end of the transaction */
<> 156:95d6b41a828b 666 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 667 {
<> 144:ef7eb2e8f9f7 668 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 669 }
<> 156:95d6b41a828b 670
<> 144:ef7eb2e8f9f7 671 /* Clear overrun flag in 2 Lines communication mode because received is not read */
<> 156:95d6b41a828b 672 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 673 {
<> 144:ef7eb2e8f9f7 674 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676
<> 156:95d6b41a828b 677 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 678 {
<> 144:ef7eb2e8f9f7 679 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 680 }
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 error:
<> 144:ef7eb2e8f9f7 683 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 684 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 685 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 686 return errorcode;
<> 144:ef7eb2e8f9f7 687 }
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /**
<> 144:ef7eb2e8f9f7 690 * @brief Receive an amount of data in blocking mode.
Anna Bridge 180:96ed750bd169 691 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 692 * the configuration information for SPI module.
Anna Bridge 180:96ed750bd169 693 * @param pData pointer to data buffer
Anna Bridge 180:96ed750bd169 694 * @param Size amount of data to be received
Anna Bridge 180:96ed750bd169 695 * @param Timeout Timeout duration
<> 144:ef7eb2e8f9f7 696 * @retval HAL status
<> 144:ef7eb2e8f9f7 697 */
<> 144:ef7eb2e8f9f7 698 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 699 {
<> 156:95d6b41a828b 700 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 701 __IO uint16_t tmpreg = 0U;
<> 156:95d6b41a828b 702 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 703 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 704 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 705
Anna Bridge 180:96ed750bd169 706 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U))
Anna Bridge 180:96ed750bd169 707 {
Anna Bridge 180:96ed750bd169 708 /* in this case, 16-bit access is performed on Data
Anna Bridge 180:96ed750bd169 709 So, check Data is 16-bit aligned address */
Anna Bridge 180:96ed750bd169 710 assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
Anna Bridge 180:96ed750bd169 711 }
Anna Bridge 180:96ed750bd169 712
<> 156:95d6b41a828b 713 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
<> 144:ef7eb2e8f9f7 714 {
<> 156:95d6b41a828b 715 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 156:95d6b41a828b 716 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<> 156:95d6b41a828b 717 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
<> 144:ef7eb2e8f9f7 718 }
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /* Process Locked */
<> 144:ef7eb2e8f9f7 721 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 722
<> 156:95d6b41a828b 723 /* Init tickstart for timeout management*/
<> 156:95d6b41a828b 724 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 725
<> 156:95d6b41a828b 726 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 727 {
<> 144:ef7eb2e8f9f7 728 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 729 goto error;
<> 144:ef7eb2e8f9f7 730 }
<> 144:ef7eb2e8f9f7 731
<> 156:95d6b41a828b 732 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 733 {
<> 144:ef7eb2e8f9f7 734 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 735 goto error;
<> 144:ef7eb2e8f9f7 736 }
<> 144:ef7eb2e8f9f7 737
<> 156:95d6b41a828b 738 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 739 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 740 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 741 hspi->pRxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 742 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 743 hspi->RxXferCount = Size;
<> 156:95d6b41a828b 744
<> 156:95d6b41a828b 745 /*Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 746 hspi->pTxBuffPtr = (uint8_t *)NULL;
<> 156:95d6b41a828b 747 hspi->TxXferSize = 0U;
<> 156:95d6b41a828b 748 hspi->TxXferCount = 0U;
<> 156:95d6b41a828b 749 hspi->RxISR = NULL;
<> 156:95d6b41a828b 750 hspi->TxISR = NULL;
<> 156:95d6b41a828b 751
<> 156:95d6b41a828b 752 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 753 /* Reset CRC Calculation */
<> 156:95d6b41a828b 754 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 755 {
<> 144:ef7eb2e8f9f7 756 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 757 /* this is done to handle the CRCNEXT before the latest data */
<> 144:ef7eb2e8f9f7 758 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 759 }
<> 156:95d6b41a828b 760 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 761
Anna Bridge 180:96ed750bd169 762 /* Set the Rx FiFo threshold */
<> 156:95d6b41a828b 763 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 764 {
<> 144:ef7eb2e8f9f7 765 /* set fiforxthresold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 766 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 767 }
<> 144:ef7eb2e8f9f7 768 else
<> 144:ef7eb2e8f9f7 769 {
<> 144:ef7eb2e8f9f7 770 /* set fiforxthresold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 771 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 772 }
<> 144:ef7eb2e8f9f7 773
<> 156:95d6b41a828b 774 /* Configure communication direction: 1Line */
<> 156:95d6b41a828b 775 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 776 {
<> 144:ef7eb2e8f9f7 777 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 778 }
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 /* Check if the SPI is already enabled */
<> 156:95d6b41a828b 781 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 782 {
<> 144:ef7eb2e8f9f7 783 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 784 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 785 }
<> 144:ef7eb2e8f9f7 786
<> 156:95d6b41a828b 787 /* Receive data in 8 Bit mode */
<> 156:95d6b41a828b 788 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 789 {
<> 144:ef7eb2e8f9f7 790 /* Transfer loop */
<> 156:95d6b41a828b 791 while (hspi->RxXferCount > 0U)
<> 144:ef7eb2e8f9f7 792 {
<> 144:ef7eb2e8f9f7 793 /* Check the RXNE flag */
<> 156:95d6b41a828b 794 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
<> 144:ef7eb2e8f9f7 795 {
<> 144:ef7eb2e8f9f7 796 /* read the received data */
<> 156:95d6b41a828b 797 (* (uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
<> 156:95d6b41a828b 798 pData += sizeof(uint8_t);
<> 144:ef7eb2e8f9f7 799 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 800 }
<> 144:ef7eb2e8f9f7 801 else
<> 144:ef7eb2e8f9f7 802 {
<> 144:ef7eb2e8f9f7 803 /* Timeout management */
<> 156:95d6b41a828b 804 if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 805 {
<> 144:ef7eb2e8f9f7 806 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 807 goto error;
<> 144:ef7eb2e8f9f7 808 }
<> 144:ef7eb2e8f9f7 809 }
<> 144:ef7eb2e8f9f7 810 }
<> 144:ef7eb2e8f9f7 811 }
<> 144:ef7eb2e8f9f7 812 else
<> 144:ef7eb2e8f9f7 813 {
<> 144:ef7eb2e8f9f7 814 /* Transfer loop */
<> 156:95d6b41a828b 815 while (hspi->RxXferCount > 0U)
<> 144:ef7eb2e8f9f7 816 {
<> 144:ef7eb2e8f9f7 817 /* Check the RXNE flag */
<> 156:95d6b41a828b 818 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
<> 144:ef7eb2e8f9f7 819 {
<> 156:95d6b41a828b 820 *((uint16_t *)pData) = hspi->Instance->DR;
<> 156:95d6b41a828b 821 pData += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 822 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 823 }
<> 144:ef7eb2e8f9f7 824 else
<> 144:ef7eb2e8f9f7 825 {
<> 144:ef7eb2e8f9f7 826 /* Timeout management */
<> 156:95d6b41a828b 827 if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
<> 144:ef7eb2e8f9f7 828 {
<> 144:ef7eb2e8f9f7 829 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 830 goto error;
<> 144:ef7eb2e8f9f7 831 }
<> 144:ef7eb2e8f9f7 832 }
<> 144:ef7eb2e8f9f7 833 }
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835
<> 156:95d6b41a828b 836 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 837 /* Handle the CRC Transmission */
<> 156:95d6b41a828b 838 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 839 {
<> 144:ef7eb2e8f9f7 840 /* freeze the CRC before the latest data */
<> 156:95d6b41a828b 841 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /* Read the latest data */
<> 156:95d6b41a828b 844 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 845 {
<> 144:ef7eb2e8f9f7 846 /* the latest data has not been received */
<> 144:ef7eb2e8f9f7 847 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 848 goto error;
<> 144:ef7eb2e8f9f7 849 }
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /* Receive last data in 16 Bit mode */
<> 156:95d6b41a828b 852 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 853 {
<> 156:95d6b41a828b 854 *((uint16_t *)pData) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 855 }
<> 144:ef7eb2e8f9f7 856 /* Receive last data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 857 else
<> 144:ef7eb2e8f9f7 858 {
<> 156:95d6b41a828b 859 (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 860 }
<> 144:ef7eb2e8f9f7 861
<> 156:95d6b41a828b 862 /* Wait the CRC data */
<> 156:95d6b41a828b 863 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 864 {
<> 156:95d6b41a828b 865 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 866 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 867 goto error;
<> 144:ef7eb2e8f9f7 868 }
<> 144:ef7eb2e8f9f7 869
<> 156:95d6b41a828b 870 /* Read CRC to Flush DR and RXNE flag */
<> 156:95d6b41a828b 871 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
<> 144:ef7eb2e8f9f7 872 {
<> 144:ef7eb2e8f9f7 873 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 874 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 875 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 876 }
<> 144:ef7eb2e8f9f7 877 else
<> 144:ef7eb2e8f9f7 878 {
<> 144:ef7eb2e8f9f7 879 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 880 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 881 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 882
<> 156:95d6b41a828b 883 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
<> 144:ef7eb2e8f9f7 884 {
<> 156:95d6b41a828b 885 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 886 {
<> 144:ef7eb2e8f9f7 887 /* Error on the CRC reception */
<> 156:95d6b41a828b 888 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 889 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 890 goto error;
<> 144:ef7eb2e8f9f7 891 }
<> 144:ef7eb2e8f9f7 892 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 893 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 894 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 895 }
<> 144:ef7eb2e8f9f7 896 }
<> 144:ef7eb2e8f9f7 897 }
<> 156:95d6b41a828b 898 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 899
<> 144:ef7eb2e8f9f7 900 /* Check the end of the transaction */
<> 156:95d6b41a828b 901 if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 902 {
<> 144:ef7eb2e8f9f7 903 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 904 }
<> 144:ef7eb2e8f9f7 905
<> 156:95d6b41a828b 906 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 907 /* Check if CRC error occurred */
<> 156:95d6b41a828b 908 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 909 {
<> 156:95d6b41a828b 910 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 911 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 912 }
<> 156:95d6b41a828b 913 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 914
<> 156:95d6b41a828b 915 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 916 {
<> 144:ef7eb2e8f9f7 917 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 918 }
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 error :
<> 144:ef7eb2e8f9f7 921 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 922 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 923 return errorcode;
<> 144:ef7eb2e8f9f7 924 }
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 /**
<> 144:ef7eb2e8f9f7 927 * @brief Transmit and Receive an amount of data in blocking mode.
Anna Bridge 180:96ed750bd169 928 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 929 * the configuration information for SPI module.
Anna Bridge 180:96ed750bd169 930 * @param pTxData pointer to transmission data buffer
Anna Bridge 180:96ed750bd169 931 * @param pRxData pointer to reception data buffer
Anna Bridge 180:96ed750bd169 932 * @param Size amount of data to be sent and received
Anna Bridge 180:96ed750bd169 933 * @param Timeout Timeout duration
<> 144:ef7eb2e8f9f7 934 * @retval HAL status
<> 144:ef7eb2e8f9f7 935 */
<> 156:95d6b41a828b 936 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
<> 156:95d6b41a828b 937 uint32_t Timeout)
<> 144:ef7eb2e8f9f7 938 {
<> 156:95d6b41a828b 939 uint32_t tmp = 0U, tmp1 = 0U;
<> 156:95d6b41a828b 940 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 941 __IO uint16_t tmpreg = 0U;
<> 156:95d6b41a828b 942 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 943 uint32_t tickstart = 0U;
<> 156:95d6b41a828b 944 /* Variable used to alternate Rx and Tx during transfer */
<> 156:95d6b41a828b 945 uint32_t txallowed = 1U;
<> 144:ef7eb2e8f9f7 946 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 947
Anna Bridge 180:96ed750bd169 948 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U))
Anna Bridge 180:96ed750bd169 949 {
Anna Bridge 180:96ed750bd169 950 /* in this case, 16-bit access is performed on Data
Anna Bridge 180:96ed750bd169 951 So, check Data is 16-bit aligned address */
Anna Bridge 180:96ed750bd169 952 assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData));
Anna Bridge 180:96ed750bd169 953 assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData));
Anna Bridge 180:96ed750bd169 954 }
Anna Bridge 180:96ed750bd169 955
<> 156:95d6b41a828b 956 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 957 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /* Process Locked */
<> 144:ef7eb2e8f9f7 960 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 961
<> 156:95d6b41a828b 962 /* Init tickstart for timeout management*/
<> 156:95d6b41a828b 963 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 964
<> 156:95d6b41a828b 965 tmp = hspi->State;
<> 156:95d6b41a828b 966 tmp1 = hspi->Init.Mode;
<> 156:95d6b41a828b 967
<> 156:95d6b41a828b 968 if (!((tmp == HAL_SPI_STATE_READY) || \
<> 156:95d6b41a828b 969 ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
<> 144:ef7eb2e8f9f7 970 {
<> 144:ef7eb2e8f9f7 971 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 972 goto error;
<> 144:ef7eb2e8f9f7 973 }
<> 144:ef7eb2e8f9f7 974
<> 156:95d6b41a828b 975 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 976 {
<> 144:ef7eb2e8f9f7 977 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 978 goto error;
<> 144:ef7eb2e8f9f7 979 }
<> 144:ef7eb2e8f9f7 980
<> 156:95d6b41a828b 981 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<> 156:95d6b41a828b 982 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
<> 156:95d6b41a828b 983 {
<> 156:95d6b41a828b 984 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 156:95d6b41a828b 985 }
<> 156:95d6b41a828b 986
<> 156:95d6b41a828b 987 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 988 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 989 hspi->pRxBuffPtr = (uint8_t *)pRxData;
<> 144:ef7eb2e8f9f7 990 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 991 hspi->RxXferSize = Size;
<> 156:95d6b41a828b 992 hspi->pTxBuffPtr = (uint8_t *)pTxData;
<> 144:ef7eb2e8f9f7 993 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 994 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 995
<> 156:95d6b41a828b 996 /*Init field not used in handle to zero */
<> 156:95d6b41a828b 997 hspi->RxISR = NULL;
<> 156:95d6b41a828b 998 hspi->TxISR = NULL;
<> 156:95d6b41a828b 999
<> 156:95d6b41a828b 1000 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1001 /* Reset CRC Calculation */
<> 156:95d6b41a828b 1002 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1003 {
<> 144:ef7eb2e8f9f7 1004 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1005 }
<> 156:95d6b41a828b 1006 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1007
Anna Bridge 180:96ed750bd169 1008 /* Set the Rx Fifo threshold */
Anna Bridge 180:96ed750bd169 1009 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U))
<> 144:ef7eb2e8f9f7 1010 {
<> 144:ef7eb2e8f9f7 1011 /* set fiforxthreshold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 1012 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1013 }
<> 144:ef7eb2e8f9f7 1014 else
<> 144:ef7eb2e8f9f7 1015 {
<> 144:ef7eb2e8f9f7 1016 /* set fiforxthreshold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 1017 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1018 }
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 /* Check if the SPI is already enabled */
<> 156:95d6b41a828b 1021 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1022 {
<> 144:ef7eb2e8f9f7 1023 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1024 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1025 }
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 /* Transmit and Receive data in 16 Bit mode */
<> 156:95d6b41a828b 1028 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1029 {
<> 156:95d6b41a828b 1030 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
<> 156:95d6b41a828b 1031 {
<> 156:95d6b41a828b 1032 hspi->Instance->DR = *((uint16_t *)pTxData);
<> 156:95d6b41a828b 1033 pTxData += sizeof(uint16_t);
<> 156:95d6b41a828b 1034 hspi->TxXferCount--;
<> 156:95d6b41a828b 1035 }
<> 156:95d6b41a828b 1036 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
<> 144:ef7eb2e8f9f7 1037 {
<> 144:ef7eb2e8f9f7 1038 /* Check TXE flag */
<> 156:95d6b41a828b 1039 if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
<> 144:ef7eb2e8f9f7 1040 {
<> 156:95d6b41a828b 1041 hspi->Instance->DR = *((uint16_t *)pTxData);
<> 156:95d6b41a828b 1042 pTxData += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 1043 hspi->TxXferCount--;
<> 156:95d6b41a828b 1044 /* Next Data is a reception (Rx). Tx not allowed */
<> 156:95d6b41a828b 1045 txallowed = 0U;
<> 156:95d6b41a828b 1046
<> 156:95d6b41a828b 1047 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1048 /* Enable CRC Transmission */
<> 156:95d6b41a828b 1049 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 1050 {
<> 144:ef7eb2e8f9f7 1051 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
<> 156:95d6b41a828b 1052 if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
<> 144:ef7eb2e8f9f7 1053 {
<> 156:95d6b41a828b 1054 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
<> 144:ef7eb2e8f9f7 1055 }
<> 156:95d6b41a828b 1056 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 1057 }
<> 156:95d6b41a828b 1058 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1059 }
<> 144:ef7eb2e8f9f7 1060
<> 144:ef7eb2e8f9f7 1061 /* Check RXNE flag */
<> 156:95d6b41a828b 1062 if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
<> 144:ef7eb2e8f9f7 1063 {
<> 156:95d6b41a828b 1064 *((uint16_t *)pRxData) = hspi->Instance->DR;
<> 156:95d6b41a828b 1065 pRxData += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 1066 hspi->RxXferCount--;
<> 156:95d6b41a828b 1067 /* Next Data is a Transmission (Tx). Tx is allowed */
<> 156:95d6b41a828b 1068 txallowed = 1U;
<> 144:ef7eb2e8f9f7 1069 }
<> 156:95d6b41a828b 1070 if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
<> 144:ef7eb2e8f9f7 1071 {
<> 144:ef7eb2e8f9f7 1072 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1073 goto error;
<> 144:ef7eb2e8f9f7 1074 }
<> 144:ef7eb2e8f9f7 1075 }
<> 144:ef7eb2e8f9f7 1076 }
<> 144:ef7eb2e8f9f7 1077 /* Transmit and Receive data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 1078 else
<> 144:ef7eb2e8f9f7 1079 {
<> 156:95d6b41a828b 1080 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
<> 156:95d6b41a828b 1081 {
<> 156:95d6b41a828b 1082 if (hspi->TxXferCount > 1U)
<> 156:95d6b41a828b 1083 {
<> 156:95d6b41a828b 1084 hspi->Instance->DR = *((uint16_t *)pTxData);
<> 156:95d6b41a828b 1085 pTxData += sizeof(uint16_t);
<> 156:95d6b41a828b 1086 hspi->TxXferCount -= 2U;
<> 156:95d6b41a828b 1087 }
<> 156:95d6b41a828b 1088 else
<> 156:95d6b41a828b 1089 {
<> 156:95d6b41a828b 1090 *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
<> 156:95d6b41a828b 1091 hspi->TxXferCount--;
<> 156:95d6b41a828b 1092 }
<> 156:95d6b41a828b 1093 }
<> 156:95d6b41a828b 1094 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
<> 144:ef7eb2e8f9f7 1095 {
<> 144:ef7eb2e8f9f7 1096 /* check TXE flag */
<> 156:95d6b41a828b 1097 if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
<> 144:ef7eb2e8f9f7 1098 {
<> 156:95d6b41a828b 1099 if (hspi->TxXferCount > 1U)
<> 144:ef7eb2e8f9f7 1100 {
<> 156:95d6b41a828b 1101 hspi->Instance->DR = *((uint16_t *)pTxData);
<> 156:95d6b41a828b 1102 pTxData += sizeof(uint16_t);
<> 156:95d6b41a828b 1103 hspi->TxXferCount -= 2U;
<> 144:ef7eb2e8f9f7 1104 }
<> 144:ef7eb2e8f9f7 1105 else
<> 144:ef7eb2e8f9f7 1106 {
<> 156:95d6b41a828b 1107 *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
<> 144:ef7eb2e8f9f7 1108 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 1109 }
<> 156:95d6b41a828b 1110 /* Next Data is a reception (Rx). Tx not allowed */
<> 156:95d6b41a828b 1111 txallowed = 0U;
<> 156:95d6b41a828b 1112
<> 156:95d6b41a828b 1113 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1114 /* Enable CRC Transmission */
<> 156:95d6b41a828b 1115 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 1116 {
<> 144:ef7eb2e8f9f7 1117 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
<> 156:95d6b41a828b 1118 if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
<> 144:ef7eb2e8f9f7 1119 {
<> 156:95d6b41a828b 1120 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
<> 144:ef7eb2e8f9f7 1121 }
<> 156:95d6b41a828b 1122 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 1123 }
<> 156:95d6b41a828b 1124 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1125 }
<> 144:ef7eb2e8f9f7 1126
<> 144:ef7eb2e8f9f7 1127 /* Wait until RXNE flag is reset */
<> 156:95d6b41a828b 1128 if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
<> 144:ef7eb2e8f9f7 1129 {
<> 156:95d6b41a828b 1130 if (hspi->RxXferCount > 1U)
<> 144:ef7eb2e8f9f7 1131 {
<> 156:95d6b41a828b 1132 *((uint16_t *)pRxData) = hspi->Instance->DR;
<> 156:95d6b41a828b 1133 pRxData += sizeof(uint16_t);
<> 156:95d6b41a828b 1134 hspi->RxXferCount -= 2U;
<> 156:95d6b41a828b 1135 if (hspi->RxXferCount <= 1U)
<> 144:ef7eb2e8f9f7 1136 {
<> 144:ef7eb2e8f9f7 1137 /* set fiforxthresold before to switch on 8 bit data size */
<> 144:ef7eb2e8f9f7 1138 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1139 }
<> 144:ef7eb2e8f9f7 1140 }
<> 144:ef7eb2e8f9f7 1141 else
<> 144:ef7eb2e8f9f7 1142 {
<> 156:95d6b41a828b 1143 (*(uint8_t *)pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 1144 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 1145 }
<> 156:95d6b41a828b 1146 /* Next Data is a Transmission (Tx). Tx is allowed */
<> 156:95d6b41a828b 1147 txallowed = 1U;
<> 144:ef7eb2e8f9f7 1148 }
<> 156:95d6b41a828b 1149 if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
<> 144:ef7eb2e8f9f7 1150 {
<> 144:ef7eb2e8f9f7 1151 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1152 goto error;
<> 144:ef7eb2e8f9f7 1153 }
<> 144:ef7eb2e8f9f7 1154 }
<> 144:ef7eb2e8f9f7 1155 }
<> 144:ef7eb2e8f9f7 1156
<> 156:95d6b41a828b 1157 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1158 /* Read CRC from DR to close CRC calculation process */
<> 156:95d6b41a828b 1159 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1160 {
<> 144:ef7eb2e8f9f7 1161 /* Wait until TXE flag */
<> 156:95d6b41a828b 1162 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1163 {
<> 144:ef7eb2e8f9f7 1164 /* Error on the CRC reception */
<> 156:95d6b41a828b 1165 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 1166 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1167 goto error;
<> 144:ef7eb2e8f9f7 1168 }
<> 156:95d6b41a828b 1169 /* Read CRC */
<> 156:95d6b41a828b 1170 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
<> 144:ef7eb2e8f9f7 1171 {
<> 144:ef7eb2e8f9f7 1172 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 1173 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 1174 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 1175 }
<> 144:ef7eb2e8f9f7 1176 else
<> 144:ef7eb2e8f9f7 1177 {
<> 144:ef7eb2e8f9f7 1178 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 1179 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 1180 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 1181
<> 156:95d6b41a828b 1182 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
<> 144:ef7eb2e8f9f7 1183 {
<> 156:95d6b41a828b 1184 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1185 {
<> 144:ef7eb2e8f9f7 1186 /* Error on the CRC reception */
<> 156:95d6b41a828b 1187 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 1188 errorcode = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1189 goto error;
<> 144:ef7eb2e8f9f7 1190 }
<> 144:ef7eb2e8f9f7 1191 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 1192 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 1193 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 1194 }
<> 144:ef7eb2e8f9f7 1195 }
<> 144:ef7eb2e8f9f7 1196 }
<> 144:ef7eb2e8f9f7 1197
<> 144:ef7eb2e8f9f7 1198 /* Check if CRC error occurred */
<> 156:95d6b41a828b 1199 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 1200 {
<> 156:95d6b41a828b 1201 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 1202 /* Clear CRC Flag */
<> 144:ef7eb2e8f9f7 1203 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 1204
<> 144:ef7eb2e8f9f7 1205 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1206 }
<> 156:95d6b41a828b 1207 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /* Check the end of the transaction */
<> 156:95d6b41a828b 1210 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1211 {
<> 144:ef7eb2e8f9f7 1212 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 1213 }
<> 144:ef7eb2e8f9f7 1214
<> 156:95d6b41a828b 1215 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1216 {
<> 144:ef7eb2e8f9f7 1217 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1218 }
<> 144:ef7eb2e8f9f7 1219
<> 144:ef7eb2e8f9f7 1220 error :
<> 144:ef7eb2e8f9f7 1221 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 1222 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1223 return errorcode;
<> 144:ef7eb2e8f9f7 1224 }
<> 144:ef7eb2e8f9f7 1225
<> 144:ef7eb2e8f9f7 1226 /**
<> 144:ef7eb2e8f9f7 1227 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
Anna Bridge 180:96ed750bd169 1228 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1229 * the configuration information for SPI module.
Anna Bridge 180:96ed750bd169 1230 * @param pData pointer to data buffer
Anna Bridge 180:96ed750bd169 1231 * @param Size amount of data to be sent
<> 144:ef7eb2e8f9f7 1232 * @retval HAL status
<> 144:ef7eb2e8f9f7 1233 */
<> 144:ef7eb2e8f9f7 1234 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1235 {
<> 144:ef7eb2e8f9f7 1236 HAL_StatusTypeDef errorcode = HAL_OK;
<> 156:95d6b41a828b 1237
Anna Bridge 180:96ed750bd169 1238 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U))
Anna Bridge 180:96ed750bd169 1239 {
Anna Bridge 180:96ed750bd169 1240 /* in this case, 16-bit access is performed on Data
Anna Bridge 180:96ed750bd169 1241 So, check Data is 16-bit aligned address */
Anna Bridge 180:96ed750bd169 1242 assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
Anna Bridge 180:96ed750bd169 1243 }
Anna Bridge 180:96ed750bd169 1244
<> 156:95d6b41a828b 1245 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 1246 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1247
<> 144:ef7eb2e8f9f7 1248 /* Process Locked */
<> 144:ef7eb2e8f9f7 1249 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1250
<> 156:95d6b41a828b 1251 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1252 {
<> 144:ef7eb2e8f9f7 1253 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1254 goto error;
<> 144:ef7eb2e8f9f7 1255 }
<> 144:ef7eb2e8f9f7 1256
<> 156:95d6b41a828b 1257 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1258 {
<> 144:ef7eb2e8f9f7 1259 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1260 goto error;
<> 144:ef7eb2e8f9f7 1261 }
<> 144:ef7eb2e8f9f7 1262
<> 156:95d6b41a828b 1263 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1264 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1265 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 1266 hspi->pTxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 1267 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1268 hspi->TxXferCount = Size;
<> 156:95d6b41a828b 1269
<> 156:95d6b41a828b 1270 /* Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 1271 hspi->pRxBuffPtr = (uint8_t *)NULL;
<> 156:95d6b41a828b 1272 hspi->RxXferSize = 0U;
<> 156:95d6b41a828b 1273 hspi->RxXferCount = 0U;
<> 156:95d6b41a828b 1274 hspi->RxISR = NULL;
<> 156:95d6b41a828b 1275
<> 144:ef7eb2e8f9f7 1276 /* Set the function for IT treatment */
<> 156:95d6b41a828b 1277 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1278 {
<> 144:ef7eb2e8f9f7 1279 hspi->TxISR = SPI_TxISR_16BIT;
<> 144:ef7eb2e8f9f7 1280 }
<> 144:ef7eb2e8f9f7 1281 else
<> 144:ef7eb2e8f9f7 1282 {
<> 144:ef7eb2e8f9f7 1283 hspi->TxISR = SPI_TxISR_8BIT;
<> 144:ef7eb2e8f9f7 1284 }
<> 144:ef7eb2e8f9f7 1285
<> 144:ef7eb2e8f9f7 1286 /* Configure communication direction : 1Line */
<> 156:95d6b41a828b 1287 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1288 {
<> 144:ef7eb2e8f9f7 1289 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 1290 }
<> 144:ef7eb2e8f9f7 1291
<> 156:95d6b41a828b 1292 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1293 /* Reset CRC Calculation */
<> 156:95d6b41a828b 1294 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1295 {
<> 144:ef7eb2e8f9f7 1296 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1297 }
<> 156:95d6b41a828b 1298 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1299
<> 144:ef7eb2e8f9f7 1300 /* Enable TXE and ERR interrupt */
<> 156:95d6b41a828b 1301 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1302
<> 144:ef7eb2e8f9f7 1303
<> 144:ef7eb2e8f9f7 1304 /* Check if the SPI is already enabled */
<> 156:95d6b41a828b 1305 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1306 {
<> 144:ef7eb2e8f9f7 1307 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1308 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1309 }
<> 144:ef7eb2e8f9f7 1310
<> 144:ef7eb2e8f9f7 1311 error :
<> 144:ef7eb2e8f9f7 1312 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1313 return errorcode;
<> 144:ef7eb2e8f9f7 1314 }
<> 144:ef7eb2e8f9f7 1315
<> 144:ef7eb2e8f9f7 1316 /**
<> 144:ef7eb2e8f9f7 1317 * @brief Receive an amount of data in non-blocking mode with Interrupt.
Anna Bridge 180:96ed750bd169 1318 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1319 * the configuration information for SPI module.
Anna Bridge 180:96ed750bd169 1320 * @param pData pointer to data buffer
Anna Bridge 180:96ed750bd169 1321 * @param Size amount of data to be sent
<> 144:ef7eb2e8f9f7 1322 * @retval HAL status
<> 144:ef7eb2e8f9f7 1323 */
<> 144:ef7eb2e8f9f7 1324 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1325 {
<> 144:ef7eb2e8f9f7 1326 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 1327
Anna Bridge 180:96ed750bd169 1328 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U))
Anna Bridge 180:96ed750bd169 1329 {
Anna Bridge 180:96ed750bd169 1330 /* in this case, 16-bit access is performed on Data
Anna Bridge 180:96ed750bd169 1331 So, check Data is 16-bit aligned address */
Anna Bridge 180:96ed750bd169 1332 assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
Anna Bridge 180:96ed750bd169 1333 }
Anna Bridge 180:96ed750bd169 1334
<> 156:95d6b41a828b 1335 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
<> 156:95d6b41a828b 1336 {
<> 156:95d6b41a828b 1337 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 156:95d6b41a828b 1338 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<> 156:95d6b41a828b 1339 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
<> 156:95d6b41a828b 1340 }
<> 156:95d6b41a828b 1341
<> 144:ef7eb2e8f9f7 1342 /* Process Locked */
<> 144:ef7eb2e8f9f7 1343 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1344
<> 156:95d6b41a828b 1345 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1346 {
<> 144:ef7eb2e8f9f7 1347 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1348 goto error;
<> 144:ef7eb2e8f9f7 1349 }
<> 156:95d6b41a828b 1350
<> 156:95d6b41a828b 1351 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1352 {
<> 144:ef7eb2e8f9f7 1353 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1354 goto error;
<> 144:ef7eb2e8f9f7 1355 }
<> 144:ef7eb2e8f9f7 1356
<> 156:95d6b41a828b 1357 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1358 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1359 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 1360 hspi->pRxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 1361 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1362 hspi->RxXferCount = Size;
<> 156:95d6b41a828b 1363
<> 156:95d6b41a828b 1364 /* Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 1365 hspi->pTxBuffPtr = (uint8_t *)NULL;
<> 156:95d6b41a828b 1366 hspi->TxXferSize = 0U;
<> 156:95d6b41a828b 1367 hspi->TxXferCount = 0U;
<> 156:95d6b41a828b 1368 hspi->TxISR = NULL;
<> 156:95d6b41a828b 1369
Anna Bridge 180:96ed750bd169 1370 /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
<> 156:95d6b41a828b 1371 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1372 {
Anna Bridge 180:96ed750bd169 1373 /* Set fiforxthresold according the reception data length: 16 bit */
<> 144:ef7eb2e8f9f7 1374 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1375 hspi->RxISR = SPI_RxISR_16BIT;
<> 144:ef7eb2e8f9f7 1376 }
<> 144:ef7eb2e8f9f7 1377 else
<> 144:ef7eb2e8f9f7 1378 {
Anna Bridge 180:96ed750bd169 1379 /* Set fiforxthresold according the reception data length: 8 bit */
<> 144:ef7eb2e8f9f7 1380 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1381 hspi->RxISR = SPI_RxISR_8BIT;
<> 144:ef7eb2e8f9f7 1382 }
<> 144:ef7eb2e8f9f7 1383
<> 144:ef7eb2e8f9f7 1384 /* Configure communication direction : 1Line */
<> 156:95d6b41a828b 1385 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1386 {
<> 144:ef7eb2e8f9f7 1387 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 1388 }
<> 144:ef7eb2e8f9f7 1389
<> 156:95d6b41a828b 1390 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1391 /* Reset CRC Calculation */
<> 156:95d6b41a828b 1392 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1393 {
<> 156:95d6b41a828b 1394 hspi->CRCSize = 1U;
<> 156:95d6b41a828b 1395 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
<> 156:95d6b41a828b 1396 {
<> 156:95d6b41a828b 1397 hspi->CRCSize = 2U;
<> 156:95d6b41a828b 1398 }
<> 144:ef7eb2e8f9f7 1399 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1400 }
<> 156:95d6b41a828b 1401 else
<> 156:95d6b41a828b 1402 {
<> 156:95d6b41a828b 1403 hspi->CRCSize = 0U;
<> 156:95d6b41a828b 1404 }
<> 156:95d6b41a828b 1405 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1406
<> 144:ef7eb2e8f9f7 1407 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1408 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1409
<> 156:95d6b41a828b 1410 /* Note : The SPI must be enabled after unlocking current process
<> 156:95d6b41a828b 1411 to avoid the risk of SPI interrupt handle execution before current
<> 156:95d6b41a828b 1412 process unlock */
<> 156:95d6b41a828b 1413
<> 144:ef7eb2e8f9f7 1414 /* Check if the SPI is already enabled */
<> 156:95d6b41a828b 1415 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1416 {
<> 144:ef7eb2e8f9f7 1417 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1418 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1419 }
<> 144:ef7eb2e8f9f7 1420
<> 144:ef7eb2e8f9f7 1421 error :
<> 144:ef7eb2e8f9f7 1422 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1423 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1424 return errorcode;
<> 144:ef7eb2e8f9f7 1425 }
<> 144:ef7eb2e8f9f7 1426
<> 144:ef7eb2e8f9f7 1427 /**
<> 144:ef7eb2e8f9f7 1428 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
Anna Bridge 180:96ed750bd169 1429 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1430 * the configuration information for SPI module.
Anna Bridge 180:96ed750bd169 1431 * @param pTxData pointer to transmission data buffer
Anna Bridge 180:96ed750bd169 1432 * @param pRxData pointer to reception data buffer
Anna Bridge 180:96ed750bd169 1433 * @param Size amount of data to be sent and received
<> 144:ef7eb2e8f9f7 1434 * @retval HAL status
<> 144:ef7eb2e8f9f7 1435 */
<> 144:ef7eb2e8f9f7 1436 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1437 {
<> 156:95d6b41a828b 1438 uint32_t tmp = 0U, tmp1 = 0U;
<> 144:ef7eb2e8f9f7 1439 HAL_StatusTypeDef errorcode = HAL_OK;
<> 156:95d6b41a828b 1440
Anna Bridge 180:96ed750bd169 1441 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U))
Anna Bridge 180:96ed750bd169 1442 {
Anna Bridge 180:96ed750bd169 1443 /* in this case, 16-bit access is performed on Data
Anna Bridge 180:96ed750bd169 1444 So, check Data is 16-bit aligned address */
Anna Bridge 180:96ed750bd169 1445 assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData));
Anna Bridge 180:96ed750bd169 1446 assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData));
Anna Bridge 180:96ed750bd169 1447 }
Anna Bridge 180:96ed750bd169 1448
<> 156:95d6b41a828b 1449 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 1450 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1451
<> 144:ef7eb2e8f9f7 1452 /* Process locked */
<> 144:ef7eb2e8f9f7 1453 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1454
<> 156:95d6b41a828b 1455 tmp = hspi->State;
<> 156:95d6b41a828b 1456 tmp1 = hspi->Init.Mode;
<> 156:95d6b41a828b 1457
<> 156:95d6b41a828b 1458 if (!((tmp == HAL_SPI_STATE_READY) || \
<> 156:95d6b41a828b 1459 ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
<> 144:ef7eb2e8f9f7 1460 {
<> 144:ef7eb2e8f9f7 1461 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1462 goto error;
<> 144:ef7eb2e8f9f7 1463 }
<> 144:ef7eb2e8f9f7 1464
<> 156:95d6b41a828b 1465 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1466 {
<> 144:ef7eb2e8f9f7 1467 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1468 goto error;
<> 144:ef7eb2e8f9f7 1469 }
<> 144:ef7eb2e8f9f7 1470
<> 156:95d6b41a828b 1471 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<> 156:95d6b41a828b 1472 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1473 {
<> 144:ef7eb2e8f9f7 1474 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 1475 }
<> 144:ef7eb2e8f9f7 1476
<> 156:95d6b41a828b 1477 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1478 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 1479 hspi->pTxBuffPtr = (uint8_t *)pTxData;
<> 144:ef7eb2e8f9f7 1480 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1481 hspi->TxXferCount = Size;
<> 156:95d6b41a828b 1482 hspi->pRxBuffPtr = (uint8_t *)pRxData;
<> 144:ef7eb2e8f9f7 1483 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1484 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 1485
<> 144:ef7eb2e8f9f7 1486 /* Set the function for IT treatment */
<> 156:95d6b41a828b 1487 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1488 {
<> 156:95d6b41a828b 1489 hspi->RxISR = SPI_2linesRxISR_16BIT;
<> 156:95d6b41a828b 1490 hspi->TxISR = SPI_2linesTxISR_16BIT;
<> 144:ef7eb2e8f9f7 1491 }
<> 144:ef7eb2e8f9f7 1492 else
<> 144:ef7eb2e8f9f7 1493 {
<> 156:95d6b41a828b 1494 hspi->RxISR = SPI_2linesRxISR_8BIT;
<> 156:95d6b41a828b 1495 hspi->TxISR = SPI_2linesTxISR_8BIT;
<> 144:ef7eb2e8f9f7 1496 }
<> 144:ef7eb2e8f9f7 1497
<> 156:95d6b41a828b 1498 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1499 /* Reset CRC Calculation */
<> 156:95d6b41a828b 1500 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1501 {
<> 156:95d6b41a828b 1502 hspi->CRCSize = 1U;
<> 156:95d6b41a828b 1503 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
<> 156:95d6b41a828b 1504 {
<> 156:95d6b41a828b 1505 hspi->CRCSize = 2U;
<> 156:95d6b41a828b 1506 }
<> 144:ef7eb2e8f9f7 1507 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1508 }
<> 156:95d6b41a828b 1509 else
<> 156:95d6b41a828b 1510 {
<> 156:95d6b41a828b 1511 hspi->CRCSize = 0U;
<> 156:95d6b41a828b 1512 }
<> 156:95d6b41a828b 1513 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1514
Anna Bridge 180:96ed750bd169 1515 /* Check if packing mode is enabled and if there is more than 2 data to receive */
<> 156:95d6b41a828b 1516 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U))
<> 144:ef7eb2e8f9f7 1517 {
Anna Bridge 180:96ed750bd169 1518 /* Set fiforxthresold according the reception data length: 16 bit */
<> 144:ef7eb2e8f9f7 1519 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1520 }
<> 144:ef7eb2e8f9f7 1521 else
<> 144:ef7eb2e8f9f7 1522 {
Anna Bridge 180:96ed750bd169 1523 /* Set fiforxthresold according the reception data length: 8 bit */
<> 144:ef7eb2e8f9f7 1524 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1525 }
<> 144:ef7eb2e8f9f7 1526
<> 144:ef7eb2e8f9f7 1527 /* Enable TXE, RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1528 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1529
<> 144:ef7eb2e8f9f7 1530 /* Check if the SPI is already enabled */
<> 156:95d6b41a828b 1531 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1532 {
<> 144:ef7eb2e8f9f7 1533 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1534 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1535 }
<> 144:ef7eb2e8f9f7 1536
<> 144:ef7eb2e8f9f7 1537 error :
<> 144:ef7eb2e8f9f7 1538 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1539 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1540 return errorcode;
<> 144:ef7eb2e8f9f7 1541 }
<> 144:ef7eb2e8f9f7 1542
<> 144:ef7eb2e8f9f7 1543 /**
<> 144:ef7eb2e8f9f7 1544 * @brief Transmit an amount of data in non-blocking mode with DMA.
Anna Bridge 180:96ed750bd169 1545 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1546 * the configuration information for SPI module.
Anna Bridge 180:96ed750bd169 1547 * @param pData pointer to data buffer
Anna Bridge 180:96ed750bd169 1548 * @param Size amount of data to be sent
<> 144:ef7eb2e8f9f7 1549 * @retval HAL status
<> 144:ef7eb2e8f9f7 1550 */
<> 144:ef7eb2e8f9f7 1551 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1552 {
<> 144:ef7eb2e8f9f7 1553 HAL_StatusTypeDef errorcode = HAL_OK;
<> 156:95d6b41a828b 1554
Anna Bridge 180:96ed750bd169 1555 /* check tx dma handle */
Anna Bridge 180:96ed750bd169 1556 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
Anna Bridge 180:96ed750bd169 1557
<> 156:95d6b41a828b 1558 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 1559 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1560
<> 144:ef7eb2e8f9f7 1561 /* Process Locked */
<> 144:ef7eb2e8f9f7 1562 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1563
<> 156:95d6b41a828b 1564 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1565 {
<> 144:ef7eb2e8f9f7 1566 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1567 goto error;
<> 144:ef7eb2e8f9f7 1568 }
<> 144:ef7eb2e8f9f7 1569
<> 156:95d6b41a828b 1570 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1571 {
<> 144:ef7eb2e8f9f7 1572 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1573 goto error;
<> 144:ef7eb2e8f9f7 1574 }
<> 144:ef7eb2e8f9f7 1575
<> 156:95d6b41a828b 1576 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1577 hspi->State = HAL_SPI_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1578 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 1579 hspi->pTxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 1580 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1581 hspi->TxXferCount = Size;
<> 156:95d6b41a828b 1582
<> 156:95d6b41a828b 1583 /* Init field not used in handle to zero */
<> 144:ef7eb2e8f9f7 1584 hspi->pRxBuffPtr = (uint8_t *)NULL;
<> 156:95d6b41a828b 1585 hspi->TxISR = NULL;
<> 156:95d6b41a828b 1586 hspi->RxISR = NULL;
<> 156:95d6b41a828b 1587 hspi->RxXferSize = 0U;
<> 156:95d6b41a828b 1588 hspi->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1589
<> 144:ef7eb2e8f9f7 1590 /* Configure communication direction : 1Line */
<> 156:95d6b41a828b 1591 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1592 {
<> 144:ef7eb2e8f9f7 1593 SPI_1LINE_TX(hspi);
<> 144:ef7eb2e8f9f7 1594 }
<> 144:ef7eb2e8f9f7 1595
<> 156:95d6b41a828b 1596 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1597 /* Reset CRC Calculation */
<> 156:95d6b41a828b 1598 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1599 {
<> 144:ef7eb2e8f9f7 1600 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1601 }
<> 156:95d6b41a828b 1602 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 1603
<> 144:ef7eb2e8f9f7 1604 /* Set the SPI TxDMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1605 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
<> 144:ef7eb2e8f9f7 1606
<> 144:ef7eb2e8f9f7 1607 /* Set the SPI TxDMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1608 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
<> 144:ef7eb2e8f9f7 1609
<> 144:ef7eb2e8f9f7 1610 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1611 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1612
<> 156:95d6b41a828b 1613 /* Set the DMA AbortCpltCallback */
<> 156:95d6b41a828b 1614 hspi->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1615
<> 144:ef7eb2e8f9f7 1616 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
Anna Bridge 180:96ed750bd169 1617 /* Packing mode is enabled only if the DMA setting is HALWORD */
<> 156:95d6b41a828b 1618 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
<> 144:ef7eb2e8f9f7 1619 {
<> 144:ef7eb2e8f9f7 1620 /* Check the even/odd of the data size + crc if enabled */
<> 156:95d6b41a828b 1621 if ((hspi->TxXferCount & 0x1U) == 0U)
<> 144:ef7eb2e8f9f7 1622 {
<> 144:ef7eb2e8f9f7 1623 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 156:95d6b41a828b 1624 hspi->TxXferCount = (hspi->TxXferCount >> 1U);
<> 144:ef7eb2e8f9f7 1625 }
<> 144:ef7eb2e8f9f7 1626 else
<> 144:ef7eb2e8f9f7 1627 {
<> 144:ef7eb2e8f9f7 1628 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 156:95d6b41a828b 1629 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
<> 144:ef7eb2e8f9f7 1630 }
<> 144:ef7eb2e8f9f7 1631 }
<> 144:ef7eb2e8f9f7 1632
<> 156:95d6b41a828b 1633 /* Enable the Tx DMA Stream/Channel */
<> 144:ef7eb2e8f9f7 1634 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<> 144:ef7eb2e8f9f7 1635
<> 144:ef7eb2e8f9f7 1636 /* Check if the SPI is already enabled */
<> 156:95d6b41a828b 1637 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1638 {
<> 144:ef7eb2e8f9f7 1639 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1640 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1641 }
<> 144:ef7eb2e8f9f7 1642
<> 156:95d6b41a828b 1643 /* Enable the SPI Error Interrupt Bit */
<> 156:95d6b41a828b 1644 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
<> 156:95d6b41a828b 1645
<> 144:ef7eb2e8f9f7 1646 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1647 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1648
<> 144:ef7eb2e8f9f7 1649 error :
<> 144:ef7eb2e8f9f7 1650 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1651 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1652 return errorcode;
<> 144:ef7eb2e8f9f7 1653 }
<> 144:ef7eb2e8f9f7 1654
<> 144:ef7eb2e8f9f7 1655 /**
<> 144:ef7eb2e8f9f7 1656 * @brief Receive an amount of data in non-blocking mode with DMA.
Anna Bridge 180:96ed750bd169 1657 * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
Anna Bridge 180:96ed750bd169 1658 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1659 * the configuration information for SPI module.
Anna Bridge 180:96ed750bd169 1660 * @param pData pointer to data buffer
<> 144:ef7eb2e8f9f7 1661 * @note When the CRC feature is enabled the pData Length must be Size + 1.
Anna Bridge 180:96ed750bd169 1662 * @param Size amount of data to be sent
<> 144:ef7eb2e8f9f7 1663 * @retval HAL status
<> 144:ef7eb2e8f9f7 1664 */
<> 144:ef7eb2e8f9f7 1665 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1666 {
<> 144:ef7eb2e8f9f7 1667 HAL_StatusTypeDef errorcode = HAL_OK;
<> 144:ef7eb2e8f9f7 1668
Anna Bridge 180:96ed750bd169 1669 /* check rx dma handle */
Anna Bridge 180:96ed750bd169 1670 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
Anna Bridge 180:96ed750bd169 1671
<> 156:95d6b41a828b 1672 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
<> 156:95d6b41a828b 1673 {
<> 156:95d6b41a828b 1674 hspi->State = HAL_SPI_STATE_BUSY_RX;
Anna Bridge 180:96ed750bd169 1675
Anna Bridge 180:96ed750bd169 1676 /* check tx dma handle */
Anna Bridge 180:96ed750bd169 1677 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
Anna Bridge 180:96ed750bd169 1678
<> 156:95d6b41a828b 1679 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
<> 156:95d6b41a828b 1680 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
<> 156:95d6b41a828b 1681 }
<> 156:95d6b41a828b 1682
<> 144:ef7eb2e8f9f7 1683 /* Process Locked */
<> 144:ef7eb2e8f9f7 1684 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1685
<> 156:95d6b41a828b 1686 if (hspi->State != HAL_SPI_STATE_READY)
<> 144:ef7eb2e8f9f7 1687 {
<> 144:ef7eb2e8f9f7 1688 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1689 goto error;
<> 144:ef7eb2e8f9f7 1690 }
<> 144:ef7eb2e8f9f7 1691
<> 156:95d6b41a828b 1692 if ((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1693 {
<> 144:ef7eb2e8f9f7 1694 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1695 goto error;
<> 144:ef7eb2e8f9f7 1696 }
<> 144:ef7eb2e8f9f7 1697
<> 156:95d6b41a828b 1698 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1699 hspi->State = HAL_SPI_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1700 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 1701 hspi->pRxBuffPtr = (uint8_t *)pData;
<> 144:ef7eb2e8f9f7 1702 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1703 hspi->RxXferCount = Size;
<> 156:95d6b41a828b 1704
<> 156:95d6b41a828b 1705 /*Init field not used in handle to zero */
<> 156:95d6b41a828b 1706 hspi->RxISR = NULL;
<> 156:95d6b41a828b 1707 hspi->TxISR = NULL;
<> 156:95d6b41a828b 1708 hspi->TxXferSize = 0U;
<> 156:95d6b41a828b 1709 hspi->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1710
<> 144:ef7eb2e8f9f7 1711 /* Configure communication direction : 1Line */
<> 156:95d6b41a828b 1712 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 144:ef7eb2e8f9f7 1713 {
<> 144:ef7eb2e8f9f7 1714 SPI_1LINE_RX(hspi);
<> 144:ef7eb2e8f9f7 1715 }
<> 144:ef7eb2e8f9f7 1716
<> 156:95d6b41a828b 1717 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 1718 /* Reset CRC Calculation */
<> 156:95d6b41a828b 1719 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1720 {
<> 144:ef7eb2e8f9f7 1721 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1722 }
<> 156:95d6b41a828b 1723 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 1724
<> 156:95d6b41a828b 1725 #if defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6)|| defined (STM32F038xx) || defined (STM32F051x8) || defined (STM32F058xx)
Anna Bridge 180:96ed750bd169 1726 /* Packing mode management is enabled by the DMA settings */
<> 156:95d6b41a828b 1727 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
<> 144:ef7eb2e8f9f7 1728 {
<> 144:ef7eb2e8f9f7 1729 /* Restriction the DMA data received is not allowed in this mode */
<> 144:ef7eb2e8f9f7 1730 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1731 goto error;
<> 144:ef7eb2e8f9f7 1732 }
<> 156:95d6b41a828b 1733 #endif
<> 144:ef7eb2e8f9f7 1734
<> 144:ef7eb2e8f9f7 1735 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
<> 156:95d6b41a828b 1736 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1737 {
Anna Bridge 180:96ed750bd169 1738 /* Set fiforxthresold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 1739 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1740 }
<> 144:ef7eb2e8f9f7 1741 else
<> 144:ef7eb2e8f9f7 1742 {
Anna Bridge 180:96ed750bd169 1743 /* Set fiforxthresold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 1744 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
Anna Bridge 180:96ed750bd169 1745
<> 156:95d6b41a828b 1746 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
<> 156:95d6b41a828b 1747 {
<> 156:95d6b41a828b 1748 /* set fiforxthresold according the reception data length: 16bit */
<> 156:95d6b41a828b 1749 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 156:95d6b41a828b 1750
<> 156:95d6b41a828b 1751 if ((hspi->RxXferCount & 0x1U) == 0x0U)
<> 156:95d6b41a828b 1752 {
<> 156:95d6b41a828b 1753 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
<> 156:95d6b41a828b 1754 hspi->RxXferCount = hspi->RxXferCount >> 1U;
<> 156:95d6b41a828b 1755 }
<> 156:95d6b41a828b 1756 else
<> 156:95d6b41a828b 1757 {
<> 156:95d6b41a828b 1758 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
<> 156:95d6b41a828b 1759 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
<> 156:95d6b41a828b 1760 }
<> 156:95d6b41a828b 1761 }
<> 144:ef7eb2e8f9f7 1762 }
<> 144:ef7eb2e8f9f7 1763
<> 144:ef7eb2e8f9f7 1764 /* Set the SPI RxDMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1765 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<> 144:ef7eb2e8f9f7 1766
<> 144:ef7eb2e8f9f7 1767 /* Set the SPI Rx DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1768 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 1769
<> 144:ef7eb2e8f9f7 1770 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1771 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1772
<> 156:95d6b41a828b 1773 /* Set the DMA AbortCpltCallback */
<> 156:95d6b41a828b 1774 hspi->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1775
<> 156:95d6b41a828b 1776 /* Enable the Rx DMA Stream/Channel */
<> 144:ef7eb2e8f9f7 1777 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<> 144:ef7eb2e8f9f7 1778
<> 144:ef7eb2e8f9f7 1779 /* Check if the SPI is already enabled */
<> 156:95d6b41a828b 1780 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1781 {
<> 144:ef7eb2e8f9f7 1782 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1783 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1784 }
<> 144:ef7eb2e8f9f7 1785
<> 156:95d6b41a828b 1786 /* Enable the SPI Error Interrupt Bit */
<> 156:95d6b41a828b 1787 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
<> 156:95d6b41a828b 1788
<> 156:95d6b41a828b 1789 /* Enable Rx DMA Request */
<> 156:95d6b41a828b 1790 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 156:95d6b41a828b 1791
<> 144:ef7eb2e8f9f7 1792 error:
<> 144:ef7eb2e8f9f7 1793 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1794 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1795 return errorcode;
<> 144:ef7eb2e8f9f7 1796 }
<> 144:ef7eb2e8f9f7 1797
<> 144:ef7eb2e8f9f7 1798 /**
<> 144:ef7eb2e8f9f7 1799 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
Anna Bridge 180:96ed750bd169 1800 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1801 * the configuration information for SPI module.
Anna Bridge 180:96ed750bd169 1802 * @param pTxData pointer to transmission data buffer
Anna Bridge 180:96ed750bd169 1803 * @param pRxData pointer to reception data buffer
<> 144:ef7eb2e8f9f7 1804 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
Anna Bridge 180:96ed750bd169 1805 * @param Size amount of data to be sent
<> 144:ef7eb2e8f9f7 1806 * @retval HAL status
<> 144:ef7eb2e8f9f7 1807 */
<> 156:95d6b41a828b 1808 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
<> 156:95d6b41a828b 1809 uint16_t Size)
<> 144:ef7eb2e8f9f7 1810 {
<> 156:95d6b41a828b 1811 uint32_t tmp = 0U, tmp1 = 0U;
<> 144:ef7eb2e8f9f7 1812 HAL_StatusTypeDef errorcode = HAL_OK;
<> 156:95d6b41a828b 1813
Anna Bridge 180:96ed750bd169 1814 /* check rx & tx dma handles */
Anna Bridge 180:96ed750bd169 1815 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
Anna Bridge 180:96ed750bd169 1816 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
Anna Bridge 180:96ed750bd169 1817
<> 156:95d6b41a828b 1818 /* Check Direction parameter */
<> 144:ef7eb2e8f9f7 1819 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
<> 144:ef7eb2e8f9f7 1820
<> 144:ef7eb2e8f9f7 1821 /* Process locked */
<> 144:ef7eb2e8f9f7 1822 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 1823
<> 156:95d6b41a828b 1824 tmp = hspi->State;
<> 156:95d6b41a828b 1825 tmp1 = hspi->Init.Mode;
<> 156:95d6b41a828b 1826 if (!((tmp == HAL_SPI_STATE_READY) ||
<> 156:95d6b41a828b 1827 ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
<> 144:ef7eb2e8f9f7 1828 {
<> 144:ef7eb2e8f9f7 1829 errorcode = HAL_BUSY;
<> 144:ef7eb2e8f9f7 1830 goto error;
<> 144:ef7eb2e8f9f7 1831 }
<> 144:ef7eb2e8f9f7 1832
<> 156:95d6b41a828b 1833 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 1834 {
<> 144:ef7eb2e8f9f7 1835 errorcode = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1836 goto error;
<> 144:ef7eb2e8f9f7 1837 }
<> 144:ef7eb2e8f9f7 1838
<> 156:95d6b41a828b 1839 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
<> 156:95d6b41a828b 1840 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1841 {
<> 144:ef7eb2e8f9f7 1842 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 1843 }
<> 144:ef7eb2e8f9f7 1844
<> 156:95d6b41a828b 1845 /* Set the transaction information */
<> 144:ef7eb2e8f9f7 1846 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1847 hspi->pTxBuffPtr = (uint8_t *)pTxData;
<> 144:ef7eb2e8f9f7 1848 hspi->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 1849 hspi->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 1850 hspi->pRxBuffPtr = (uint8_t *)pRxData;
<> 144:ef7eb2e8f9f7 1851 hspi->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 1852 hspi->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 1853
<> 156:95d6b41a828b 1854 /* Init field not used in handle to zero */
<> 156:95d6b41a828b 1855 hspi->RxISR = NULL;
<> 156:95d6b41a828b 1856 hspi->TxISR = NULL;
<> 156:95d6b41a828b 1857
<> 156:95d6b41a828b 1858 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 1859 /* Reset CRC Calculation */
<> 156:95d6b41a828b 1860 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 1861 {
<> 144:ef7eb2e8f9f7 1862 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 1863 }
<> 156:95d6b41a828b 1864 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 1865
<> 156:95d6b41a828b 1866 #if defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F051x8) || defined (STM32F058xx)
<> 156:95d6b41a828b 1867 /* packing mode management is enabled by the DMA settings */
<> 156:95d6b41a828b 1868 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
<> 156:95d6b41a828b 1869 {
<> 156:95d6b41a828b 1870 /* Restriction the DMA data received is not allowed in this mode */
<> 156:95d6b41a828b 1871 errorcode = HAL_ERROR;
<> 156:95d6b41a828b 1872 goto error;
<> 156:95d6b41a828b 1873 }
<> 156:95d6b41a828b 1874 #endif
<> 144:ef7eb2e8f9f7 1875
Anna Bridge 180:96ed750bd169 1876
<> 144:ef7eb2e8f9f7 1877 /* Reset the threshold bit */
<> 144:ef7eb2e8f9f7 1878 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
<> 144:ef7eb2e8f9f7 1879
Anna Bridge 180:96ed750bd169 1880 /* The packing mode management is enabled by the DMA settings according the spi data size */
<> 156:95d6b41a828b 1881 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 1882 {
Anna Bridge 180:96ed750bd169 1883 /* Set fiforxthreshold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 1884 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1885 }
<> 144:ef7eb2e8f9f7 1886 else
<> 144:ef7eb2e8f9f7 1887 {
Anna Bridge 180:96ed750bd169 1888 /* Set fiforxthresold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 1889 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1890
<> 156:95d6b41a828b 1891 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
<> 144:ef7eb2e8f9f7 1892 {
<> 156:95d6b41a828b 1893 if ((hspi->TxXferSize & 0x1U) == 0x0U)
<> 144:ef7eb2e8f9f7 1894 {
<> 144:ef7eb2e8f9f7 1895 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 156:95d6b41a828b 1896 hspi->TxXferCount = hspi->TxXferCount >> 1U;
<> 144:ef7eb2e8f9f7 1897 }
<> 144:ef7eb2e8f9f7 1898 else
<> 144:ef7eb2e8f9f7 1899 {
<> 144:ef7eb2e8f9f7 1900 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
<> 156:95d6b41a828b 1901 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
<> 144:ef7eb2e8f9f7 1902 }
<> 144:ef7eb2e8f9f7 1903 }
<> 144:ef7eb2e8f9f7 1904
<> 156:95d6b41a828b 1905 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
<> 144:ef7eb2e8f9f7 1906 {
Anna Bridge 180:96ed750bd169 1907 /* Set fiforxthresold according the reception data length: 16bit */
<> 144:ef7eb2e8f9f7 1908 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 1909
<> 156:95d6b41a828b 1910 if ((hspi->RxXferCount & 0x1U) == 0x0U)
<> 144:ef7eb2e8f9f7 1911 {
<> 144:ef7eb2e8f9f7 1912 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
<> 156:95d6b41a828b 1913 hspi->RxXferCount = hspi->RxXferCount >> 1U;
<> 144:ef7eb2e8f9f7 1914 }
<> 144:ef7eb2e8f9f7 1915 else
<> 144:ef7eb2e8f9f7 1916 {
<> 144:ef7eb2e8f9f7 1917 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
<> 156:95d6b41a828b 1918 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
<> 144:ef7eb2e8f9f7 1919 }
<> 144:ef7eb2e8f9f7 1920 }
<> 144:ef7eb2e8f9f7 1921 }
<> 144:ef7eb2e8f9f7 1922
<> 156:95d6b41a828b 1923 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
<> 156:95d6b41a828b 1924 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1925 {
<> 144:ef7eb2e8f9f7 1926 /* Set the SPI Rx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1927 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
<> 156:95d6b41a828b 1928 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 1929 }
<> 144:ef7eb2e8f9f7 1930 else
<> 144:ef7eb2e8f9f7 1931 {
<> 156:95d6b41a828b 1932 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 1933 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
<> 156:95d6b41a828b 1934 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
<> 144:ef7eb2e8f9f7 1935 }
<> 144:ef7eb2e8f9f7 1936
<> 144:ef7eb2e8f9f7 1937 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1938 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
<> 144:ef7eb2e8f9f7 1939
<> 156:95d6b41a828b 1940 /* Set the DMA AbortCpltCallback */
<> 156:95d6b41a828b 1941 hspi->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1942
<> 156:95d6b41a828b 1943 /* Enable the Rx DMA Stream/Channel */
<> 156:95d6b41a828b 1944 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
<> 156:95d6b41a828b 1945
<> 144:ef7eb2e8f9f7 1946 /* Enable Rx DMA Request */
<> 144:ef7eb2e8f9f7 1947 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1948
<> 144:ef7eb2e8f9f7 1949 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
<> 144:ef7eb2e8f9f7 1950 is performed in DMA reception complete callback */
<> 144:ef7eb2e8f9f7 1951 hspi->hdmatx->XferHalfCpltCallback = NULL;
<> 156:95d6b41a828b 1952 hspi->hdmatx->XferCpltCallback = NULL;
<> 156:95d6b41a828b 1953 hspi->hdmatx->XferErrorCallback = NULL;
<> 156:95d6b41a828b 1954 hspi->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 1955
<> 156:95d6b41a828b 1956 /* Enable the Tx DMA Stream/Channel */
<> 144:ef7eb2e8f9f7 1957 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
<> 144:ef7eb2e8f9f7 1958
<> 144:ef7eb2e8f9f7 1959 /* Check if the SPI is already enabled */
<> 156:95d6b41a828b 1960 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 1961 {
<> 144:ef7eb2e8f9f7 1962 /* Enable SPI peripheral */
<> 144:ef7eb2e8f9f7 1963 __HAL_SPI_ENABLE(hspi);
<> 144:ef7eb2e8f9f7 1964 }
<> 156:95d6b41a828b 1965 /* Enable the SPI Error Interrupt Bit */
<> 156:95d6b41a828b 1966 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 1967
<> 144:ef7eb2e8f9f7 1968 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1969 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1970
<> 144:ef7eb2e8f9f7 1971 error :
<> 144:ef7eb2e8f9f7 1972 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1973 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 1974 return errorcode;
<> 144:ef7eb2e8f9f7 1975 }
<> 144:ef7eb2e8f9f7 1976
<> 144:ef7eb2e8f9f7 1977 /**
<> 156:95d6b41a828b 1978 * @brief Abort ongoing transfer (blocking mode).
<> 156:95d6b41a828b 1979 * @param hspi SPI handle.
<> 156:95d6b41a828b 1980 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
<> 156:95d6b41a828b 1981 * started in Interrupt or DMA mode.
<> 156:95d6b41a828b 1982 * This procedure performs following operations :
<> 156:95d6b41a828b 1983 * - Disable SPI Interrupts (depending of transfer direction)
<> 156:95d6b41a828b 1984 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 1985 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
<> 156:95d6b41a828b 1986 * - Set handle State to READY
<> 156:95d6b41a828b 1987 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
<> 156:95d6b41a828b 1988 * @retval HAL status
<> 156:95d6b41a828b 1989 */
<> 156:95d6b41a828b 1990 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
<> 156:95d6b41a828b 1991 {
<> 156:95d6b41a828b 1992 HAL_StatusTypeDef errorcode;
Anna Bridge 180:96ed750bd169 1993 __IO uint32_t count, resetcount;
<> 156:95d6b41a828b 1994
<> 156:95d6b41a828b 1995 /* Initialized local variable */
<> 156:95d6b41a828b 1996 errorcode = HAL_OK;
Anna Bridge 180:96ed750bd169 1997 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
Anna Bridge 180:96ed750bd169 1998 count = resetcount;
<> 156:95d6b41a828b 1999
<> 156:95d6b41a828b 2000 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
<> 156:95d6b41a828b 2001 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
<> 156:95d6b41a828b 2002 {
<> 156:95d6b41a828b 2003 hspi->TxISR = SPI_AbortTx_ISR;
Anna Bridge 180:96ed750bd169 2004 /* Wait HAL_SPI_STATE_ABORT state */
Anna Bridge 180:96ed750bd169 2005 do
<> 156:95d6b41a828b 2006 {
Anna Bridge 180:96ed750bd169 2007 if (count-- == 0U)
Anna Bridge 180:96ed750bd169 2008 {
Anna Bridge 180:96ed750bd169 2009 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
Anna Bridge 180:96ed750bd169 2010 break;
Anna Bridge 180:96ed750bd169 2011 }
<> 156:95d6b41a828b 2012 }
Anna Bridge 180:96ed750bd169 2013 while (hspi->State != HAL_SPI_STATE_ABORT);
Anna Bridge 180:96ed750bd169 2014 /* Reset Timeout Counter */
Anna Bridge 180:96ed750bd169 2015 count = resetcount;
<> 156:95d6b41a828b 2016 }
<> 156:95d6b41a828b 2017
<> 156:95d6b41a828b 2018 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
<> 156:95d6b41a828b 2019 {
<> 156:95d6b41a828b 2020 hspi->RxISR = SPI_AbortRx_ISR;
Anna Bridge 180:96ed750bd169 2021 /* Wait HAL_SPI_STATE_ABORT state */
Anna Bridge 180:96ed750bd169 2022 do
<> 156:95d6b41a828b 2023 {
Anna Bridge 180:96ed750bd169 2024 if (count-- == 0U)
Anna Bridge 180:96ed750bd169 2025 {
Anna Bridge 180:96ed750bd169 2026 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
Anna Bridge 180:96ed750bd169 2027 break;
Anna Bridge 180:96ed750bd169 2028 }
<> 156:95d6b41a828b 2029 }
Anna Bridge 180:96ed750bd169 2030 while (hspi->State != HAL_SPI_STATE_ABORT);
Anna Bridge 180:96ed750bd169 2031 /* Reset Timeout Counter */
Anna Bridge 180:96ed750bd169 2032 count = resetcount;
<> 156:95d6b41a828b 2033 }
<> 156:95d6b41a828b 2034
<> 156:95d6b41a828b 2035 /* Clear ERRIE interrupts in case of DMA Mode */
<> 156:95d6b41a828b 2036 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
<> 156:95d6b41a828b 2037
<> 156:95d6b41a828b 2038 /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
<> 156:95d6b41a828b 2039 if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
<> 156:95d6b41a828b 2040 {
<> 156:95d6b41a828b 2041 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
<> 156:95d6b41a828b 2042 if (hspi->hdmatx != NULL)
<> 156:95d6b41a828b 2043 {
<> 156:95d6b41a828b 2044 /* Set the SPI DMA Abort callback :
<> 156:95d6b41a828b 2045 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 2046 hspi->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2047
<> 156:95d6b41a828b 2048 /* Abort DMA Tx Handle linked to SPI Peripheral */
<> 156:95d6b41a828b 2049 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
<> 156:95d6b41a828b 2050 {
<> 156:95d6b41a828b 2051 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2052 }
<> 156:95d6b41a828b 2053
<> 156:95d6b41a828b 2054 /* Disable Tx DMA Request */
<> 156:95d6b41a828b 2055 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
<> 156:95d6b41a828b 2056
<> 156:95d6b41a828b 2057 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 2058 {
<> 156:95d6b41a828b 2059 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2060 }
<> 156:95d6b41a828b 2061
<> 156:95d6b41a828b 2062 /* Disable SPI Peripheral */
<> 156:95d6b41a828b 2063 __HAL_SPI_DISABLE(hspi);
<> 156:95d6b41a828b 2064
<> 156:95d6b41a828b 2065 /* Empty the FRLVL fifo */
<> 156:95d6b41a828b 2066 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 2067 {
<> 156:95d6b41a828b 2068 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2069 }
<> 156:95d6b41a828b 2070 }
<> 156:95d6b41a828b 2071 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
<> 156:95d6b41a828b 2072 if (hspi->hdmarx != NULL)
<> 156:95d6b41a828b 2073 {
<> 156:95d6b41a828b 2074 /* Set the SPI DMA Abort callback :
<> 156:95d6b41a828b 2075 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 2076 hspi->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2077
<> 156:95d6b41a828b 2078 /* Abort DMA Rx Handle linked to SPI Peripheral */
<> 156:95d6b41a828b 2079 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
<> 156:95d6b41a828b 2080 {
<> 156:95d6b41a828b 2081 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2082 }
<> 156:95d6b41a828b 2083
<> 156:95d6b41a828b 2084 /* Disable peripheral */
<> 156:95d6b41a828b 2085 __HAL_SPI_DISABLE(hspi);
<> 156:95d6b41a828b 2086
<> 156:95d6b41a828b 2087 /* Control the BSY flag */
<> 156:95d6b41a828b 2088 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 2089 {
<> 156:95d6b41a828b 2090 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2091 }
<> 156:95d6b41a828b 2092
<> 156:95d6b41a828b 2093 /* Empty the FRLVL fifo */
<> 156:95d6b41a828b 2094 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 2095 {
<> 156:95d6b41a828b 2096 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2097 }
<> 156:95d6b41a828b 2098
<> 156:95d6b41a828b 2099 /* Disable Rx DMA Request */
<> 156:95d6b41a828b 2100 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
<> 156:95d6b41a828b 2101 }
<> 156:95d6b41a828b 2102 }
<> 156:95d6b41a828b 2103 /* Reset Tx and Rx transfer counters */
<> 156:95d6b41a828b 2104 hspi->RxXferCount = 0U;
<> 156:95d6b41a828b 2105 hspi->TxXferCount = 0U;
<> 156:95d6b41a828b 2106
<> 156:95d6b41a828b 2107 /* Check error during Abort procedure */
<> 156:95d6b41a828b 2108 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
<> 156:95d6b41a828b 2109 {
<> 156:95d6b41a828b 2110 /* return HAL_Error in case of error during Abort procedure */
<> 156:95d6b41a828b 2111 errorcode = HAL_ERROR;
<> 156:95d6b41a828b 2112 }
<> 156:95d6b41a828b 2113 else
<> 156:95d6b41a828b 2114 {
<> 156:95d6b41a828b 2115 /* Reset errorCode */
<> 156:95d6b41a828b 2116 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 2117 }
<> 156:95d6b41a828b 2118
<> 156:95d6b41a828b 2119 /* Clear the Error flags in the SR register */
<> 156:95d6b41a828b 2120 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 156:95d6b41a828b 2121 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 156:95d6b41a828b 2122
<> 156:95d6b41a828b 2123 /* Restore hspi->state to ready */
<> 156:95d6b41a828b 2124 hspi->State = HAL_SPI_STATE_READY;
<> 156:95d6b41a828b 2125
<> 156:95d6b41a828b 2126 return errorcode;
<> 156:95d6b41a828b 2127 }
<> 156:95d6b41a828b 2128
<> 156:95d6b41a828b 2129 /**
<> 156:95d6b41a828b 2130 * @brief Abort ongoing transfer (Interrupt mode).
<> 156:95d6b41a828b 2131 * @param hspi SPI handle.
<> 156:95d6b41a828b 2132 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
<> 156:95d6b41a828b 2133 * started in Interrupt or DMA mode.
<> 156:95d6b41a828b 2134 * This procedure performs following operations :
<> 156:95d6b41a828b 2135 * - Disable SPI Interrupts (depending of transfer direction)
<> 156:95d6b41a828b 2136 * - Disable the DMA transfer in the peripheral register (if enabled)
<> 156:95d6b41a828b 2137 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
<> 156:95d6b41a828b 2138 * - Set handle State to READY
<> 156:95d6b41a828b 2139 * - At abort completion, call user abort complete callback
<> 156:95d6b41a828b 2140 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
<> 156:95d6b41a828b 2141 * considered as completed only when user abort complete callback is executed (not when exiting function).
<> 156:95d6b41a828b 2142 * @retval HAL status
<> 156:95d6b41a828b 2143 */
<> 156:95d6b41a828b 2144 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
<> 156:95d6b41a828b 2145 {
<> 156:95d6b41a828b 2146 HAL_StatusTypeDef errorcode;
<> 156:95d6b41a828b 2147 uint32_t abortcplt ;
Anna Bridge 180:96ed750bd169 2148 __IO uint32_t count, resetcount;
<> 156:95d6b41a828b 2149
<> 156:95d6b41a828b 2150 /* Initialized local variable */
<> 156:95d6b41a828b 2151 errorcode = HAL_OK;
<> 156:95d6b41a828b 2152 abortcplt = 1U;
Anna Bridge 180:96ed750bd169 2153 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
Anna Bridge 180:96ed750bd169 2154 count = resetcount;
<> 156:95d6b41a828b 2155
<> 156:95d6b41a828b 2156 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
<> 156:95d6b41a828b 2157 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
<> 156:95d6b41a828b 2158 {
<> 156:95d6b41a828b 2159 hspi->TxISR = SPI_AbortTx_ISR;
Anna Bridge 180:96ed750bd169 2160 /* Wait HAL_SPI_STATE_ABORT state */
Anna Bridge 180:96ed750bd169 2161 do
<> 156:95d6b41a828b 2162 {
Anna Bridge 180:96ed750bd169 2163 if (count-- == 0U)
Anna Bridge 180:96ed750bd169 2164 {
Anna Bridge 180:96ed750bd169 2165 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
Anna Bridge 180:96ed750bd169 2166 break;
Anna Bridge 180:96ed750bd169 2167 }
<> 156:95d6b41a828b 2168 }
Anna Bridge 180:96ed750bd169 2169 while (hspi->State != HAL_SPI_STATE_ABORT);
Anna Bridge 180:96ed750bd169 2170 /* Reset Timeout Counter */
Anna Bridge 180:96ed750bd169 2171 count = resetcount;
<> 156:95d6b41a828b 2172 }
<> 156:95d6b41a828b 2173
<> 156:95d6b41a828b 2174 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
<> 156:95d6b41a828b 2175 {
<> 156:95d6b41a828b 2176 hspi->RxISR = SPI_AbortRx_ISR;
Anna Bridge 180:96ed750bd169 2177 /* Wait HAL_SPI_STATE_ABORT state */
Anna Bridge 180:96ed750bd169 2178 do
<> 156:95d6b41a828b 2179 {
Anna Bridge 180:96ed750bd169 2180 if (count-- == 0U)
Anna Bridge 180:96ed750bd169 2181 {
Anna Bridge 180:96ed750bd169 2182 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
Anna Bridge 180:96ed750bd169 2183 break;
Anna Bridge 180:96ed750bd169 2184 }
<> 156:95d6b41a828b 2185 }
Anna Bridge 180:96ed750bd169 2186 while (hspi->State != HAL_SPI_STATE_ABORT);
Anna Bridge 180:96ed750bd169 2187 /* Reset Timeout Counter */
Anna Bridge 180:96ed750bd169 2188 count = resetcount;
<> 156:95d6b41a828b 2189 }
<> 156:95d6b41a828b 2190
<> 156:95d6b41a828b 2191 /* Clear ERRIE interrupts in case of DMA Mode */
<> 156:95d6b41a828b 2192 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
<> 156:95d6b41a828b 2193
<> 156:95d6b41a828b 2194 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
<> 156:95d6b41a828b 2195 before any call to DMA Abort functions */
<> 156:95d6b41a828b 2196 /* DMA Tx Handle is valid */
<> 156:95d6b41a828b 2197 if (hspi->hdmatx != NULL)
<> 156:95d6b41a828b 2198 {
<> 156:95d6b41a828b 2199 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
<> 156:95d6b41a828b 2200 Otherwise, set it to NULL */
<> 156:95d6b41a828b 2201 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
<> 156:95d6b41a828b 2202 {
<> 156:95d6b41a828b 2203 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
<> 156:95d6b41a828b 2204 }
<> 156:95d6b41a828b 2205 else
<> 156:95d6b41a828b 2206 {
<> 156:95d6b41a828b 2207 hspi->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2208 }
<> 156:95d6b41a828b 2209 }
<> 156:95d6b41a828b 2210 /* DMA Rx Handle is valid */
<> 156:95d6b41a828b 2211 if (hspi->hdmarx != NULL)
<> 156:95d6b41a828b 2212 {
<> 156:95d6b41a828b 2213 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
<> 156:95d6b41a828b 2214 Otherwise, set it to NULL */
<> 156:95d6b41a828b 2215 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
<> 156:95d6b41a828b 2216 {
<> 156:95d6b41a828b 2217 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
<> 156:95d6b41a828b 2218 }
<> 156:95d6b41a828b 2219 else
<> 156:95d6b41a828b 2220 {
<> 156:95d6b41a828b 2221 hspi->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2222 }
<> 156:95d6b41a828b 2223 }
<> 156:95d6b41a828b 2224
<> 156:95d6b41a828b 2225 /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
<> 156:95d6b41a828b 2226 if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
<> 156:95d6b41a828b 2227 {
<> 156:95d6b41a828b 2228 /* Abort the SPI DMA Tx Stream/Channel */
<> 156:95d6b41a828b 2229 if (hspi->hdmatx != NULL)
<> 156:95d6b41a828b 2230 {
<> 156:95d6b41a828b 2231 /* Abort DMA Tx Handle linked to SPI Peripheral */
<> 156:95d6b41a828b 2232 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
<> 156:95d6b41a828b 2233 {
<> 156:95d6b41a828b 2234 hspi->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2235 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2236 }
<> 156:95d6b41a828b 2237 else
<> 156:95d6b41a828b 2238 {
<> 156:95d6b41a828b 2239 abortcplt = 0U;
<> 156:95d6b41a828b 2240 }
<> 156:95d6b41a828b 2241 }
<> 156:95d6b41a828b 2242 /* Abort the SPI DMA Rx Stream/Channel */
<> 156:95d6b41a828b 2243 if (hspi->hdmarx != NULL)
<> 156:95d6b41a828b 2244 {
<> 156:95d6b41a828b 2245 /* Abort DMA Rx Handle linked to SPI Peripheral */
<> 156:95d6b41a828b 2246 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
<> 156:95d6b41a828b 2247 {
<> 156:95d6b41a828b 2248 hspi->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2249 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2250 abortcplt = 1U;
<> 156:95d6b41a828b 2251 }
<> 156:95d6b41a828b 2252 else
<> 156:95d6b41a828b 2253 {
<> 156:95d6b41a828b 2254 abortcplt = 0U;
<> 156:95d6b41a828b 2255 }
<> 156:95d6b41a828b 2256 }
<> 156:95d6b41a828b 2257 }
<> 156:95d6b41a828b 2258
<> 156:95d6b41a828b 2259 /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
<> 156:95d6b41a828b 2260 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
<> 156:95d6b41a828b 2261 {
<> 156:95d6b41a828b 2262 /* Abort the SPI DMA Tx Stream/Channel */
<> 156:95d6b41a828b 2263 if (hspi->hdmatx != NULL)
<> 156:95d6b41a828b 2264 {
<> 156:95d6b41a828b 2265 /* Abort DMA Tx Handle linked to SPI Peripheral */
<> 156:95d6b41a828b 2266 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
<> 156:95d6b41a828b 2267 {
<> 156:95d6b41a828b 2268 hspi->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2269 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2270 }
<> 156:95d6b41a828b 2271 else
<> 156:95d6b41a828b 2272 {
<> 156:95d6b41a828b 2273 abortcplt = 0U;
<> 156:95d6b41a828b 2274 }
<> 156:95d6b41a828b 2275 }
<> 156:95d6b41a828b 2276 }
<> 156:95d6b41a828b 2277 /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
<> 156:95d6b41a828b 2278 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
<> 156:95d6b41a828b 2279 {
<> 156:95d6b41a828b 2280 /* Abort the SPI DMA Rx Stream/Channel */
<> 156:95d6b41a828b 2281 if (hspi->hdmarx != NULL)
<> 156:95d6b41a828b 2282 {
<> 156:95d6b41a828b 2283 /* Abort DMA Rx Handle linked to SPI Peripheral */
<> 156:95d6b41a828b 2284 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
<> 156:95d6b41a828b 2285 {
<> 156:95d6b41a828b 2286 hspi->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2287 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2288 }
<> 156:95d6b41a828b 2289 else
<> 156:95d6b41a828b 2290 {
<> 156:95d6b41a828b 2291 abortcplt = 0U;
<> 156:95d6b41a828b 2292 }
<> 156:95d6b41a828b 2293 }
<> 156:95d6b41a828b 2294 }
<> 156:95d6b41a828b 2295
<> 156:95d6b41a828b 2296 if (abortcplt == 1U)
<> 156:95d6b41a828b 2297 {
<> 156:95d6b41a828b 2298 /* Reset Tx and Rx transfer counters */
<> 156:95d6b41a828b 2299 hspi->RxXferCount = 0U;
<> 156:95d6b41a828b 2300 hspi->TxXferCount = 0U;
<> 156:95d6b41a828b 2301
<> 156:95d6b41a828b 2302 /* Check error during Abort procedure */
<> 156:95d6b41a828b 2303 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
<> 156:95d6b41a828b 2304 {
<> 156:95d6b41a828b 2305 /* return HAL_Error in case of error during Abort procedure */
<> 156:95d6b41a828b 2306 errorcode = HAL_ERROR;
<> 156:95d6b41a828b 2307 }
<> 156:95d6b41a828b 2308 else
<> 156:95d6b41a828b 2309 {
<> 156:95d6b41a828b 2310 /* Reset errorCode */
<> 156:95d6b41a828b 2311 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 2312 }
<> 156:95d6b41a828b 2313
<> 156:95d6b41a828b 2314 /* Clear the Error flags in the SR register */
<> 156:95d6b41a828b 2315 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 156:95d6b41a828b 2316 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 156:95d6b41a828b 2317
<> 156:95d6b41a828b 2318 /* Restore hspi->State to Ready */
<> 156:95d6b41a828b 2319 hspi->State = HAL_SPI_STATE_READY;
<> 156:95d6b41a828b 2320
<> 156:95d6b41a828b 2321 /* As no DMA to be aborted, call directly user Abort complete callback */
<> 156:95d6b41a828b 2322 HAL_SPI_AbortCpltCallback(hspi);
<> 156:95d6b41a828b 2323 }
<> 156:95d6b41a828b 2324
<> 156:95d6b41a828b 2325 return errorcode;
<> 156:95d6b41a828b 2326 }
<> 156:95d6b41a828b 2327
<> 156:95d6b41a828b 2328 /**
<> 144:ef7eb2e8f9f7 2329 * @brief Pause the DMA Transfer.
Anna Bridge 180:96ed750bd169 2330 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2331 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 2332 * @retval HAL status
<> 144:ef7eb2e8f9f7 2333 */
<> 144:ef7eb2e8f9f7 2334 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2335 {
<> 144:ef7eb2e8f9f7 2336 /* Process Locked */
<> 144:ef7eb2e8f9f7 2337 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 2338
<> 144:ef7eb2e8f9f7 2339 /* Disable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 2340 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2341
<> 144:ef7eb2e8f9f7 2342 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2343 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 2344
<> 144:ef7eb2e8f9f7 2345 return HAL_OK;
<> 144:ef7eb2e8f9f7 2346 }
<> 144:ef7eb2e8f9f7 2347
<> 144:ef7eb2e8f9f7 2348 /**
<> 144:ef7eb2e8f9f7 2349 * @brief Resume the DMA Transfer.
Anna Bridge 180:96ed750bd169 2350 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2351 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 2352 * @retval HAL status
<> 144:ef7eb2e8f9f7 2353 */
<> 144:ef7eb2e8f9f7 2354 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2355 {
<> 144:ef7eb2e8f9f7 2356 /* Process Locked */
<> 144:ef7eb2e8f9f7 2357 __HAL_LOCK(hspi);
<> 144:ef7eb2e8f9f7 2358
<> 144:ef7eb2e8f9f7 2359 /* Enable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 2360 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2361
<> 144:ef7eb2e8f9f7 2362 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2363 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 2364
<> 144:ef7eb2e8f9f7 2365 return HAL_OK;
<> 144:ef7eb2e8f9f7 2366 }
<> 144:ef7eb2e8f9f7 2367
<> 144:ef7eb2e8f9f7 2368 /**
<> 144:ef7eb2e8f9f7 2369 * @brief Stop the DMA Transfer.
Anna Bridge 180:96ed750bd169 2370 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2371 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 2372 * @retval HAL status
<> 144:ef7eb2e8f9f7 2373 */
<> 144:ef7eb2e8f9f7 2374 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2375 {
<> 144:ef7eb2e8f9f7 2376 /* The Lock is not implemented on this API to allow the user application
<> 144:ef7eb2e8f9f7 2377 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
<> 144:ef7eb2e8f9f7 2378 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
<> 144:ef7eb2e8f9f7 2379 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
<> 144:ef7eb2e8f9f7 2380 */
<> 144:ef7eb2e8f9f7 2381
<> 156:95d6b41a828b 2382 /* Abort the SPI DMA tx Stream/Channel */
<> 156:95d6b41a828b 2383 if (hspi->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 2384 {
<> 144:ef7eb2e8f9f7 2385 HAL_DMA_Abort(hspi->hdmatx);
<> 144:ef7eb2e8f9f7 2386 }
<> 156:95d6b41a828b 2387 /* Abort the SPI DMA rx Stream/Channel */
<> 156:95d6b41a828b 2388 if (hspi->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 2389 {
<> 144:ef7eb2e8f9f7 2390 HAL_DMA_Abort(hspi->hdmarx);
<> 144:ef7eb2e8f9f7 2391 }
<> 144:ef7eb2e8f9f7 2392
<> 144:ef7eb2e8f9f7 2393 /* Disable the SPI DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 2394 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2395 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2396 return HAL_OK;
<> 144:ef7eb2e8f9f7 2397 }
<> 144:ef7eb2e8f9f7 2398
<> 144:ef7eb2e8f9f7 2399 /**
<> 144:ef7eb2e8f9f7 2400 * @brief Handle SPI interrupt request.
Anna Bridge 180:96ed750bd169 2401 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2402 * the configuration information for the specified SPI module.
<> 144:ef7eb2e8f9f7 2403 * @retval None
<> 144:ef7eb2e8f9f7 2404 */
<> 144:ef7eb2e8f9f7 2405 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2406 {
<> 144:ef7eb2e8f9f7 2407 uint32_t itsource = hspi->Instance->CR2;
<> 144:ef7eb2e8f9f7 2408 uint32_t itflag = hspi->Instance->SR;
<> 144:ef7eb2e8f9f7 2409
<> 144:ef7eb2e8f9f7 2410 /* SPI in mode Receiver ----------------------------------------------------*/
<> 156:95d6b41a828b 2411 if (((itflag & SPI_FLAG_OVR) == RESET) &&
<> 156:95d6b41a828b 2412 ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
<> 144:ef7eb2e8f9f7 2413 {
<> 144:ef7eb2e8f9f7 2414 hspi->RxISR(hspi);
<> 144:ef7eb2e8f9f7 2415 return;
<> 144:ef7eb2e8f9f7 2416 }
<> 144:ef7eb2e8f9f7 2417
<> 156:95d6b41a828b 2418 /* SPI in mode Transmitter -------------------------------------------------*/
<> 156:95d6b41a828b 2419 if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
<> 144:ef7eb2e8f9f7 2420 {
<> 144:ef7eb2e8f9f7 2421 hspi->TxISR(hspi);
<> 144:ef7eb2e8f9f7 2422 return;
<> 144:ef7eb2e8f9f7 2423 }
<> 144:ef7eb2e8f9f7 2424
<> 156:95d6b41a828b 2425 /* SPI in Error Treatment --------------------------------------------------*/
<> 156:95d6b41a828b 2426 if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
<> 144:ef7eb2e8f9f7 2427 {
<> 156:95d6b41a828b 2428 /* SPI Overrun error interrupt occurred ----------------------------------*/
<> 156:95d6b41a828b 2429 if ((itflag & SPI_FLAG_OVR) != RESET)
<> 144:ef7eb2e8f9f7 2430 {
<> 156:95d6b41a828b 2431 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 2432 {
<> 156:95d6b41a828b 2433 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
<> 144:ef7eb2e8f9f7 2434 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2435 }
<> 144:ef7eb2e8f9f7 2436 else
<> 144:ef7eb2e8f9f7 2437 {
<> 156:95d6b41a828b 2438 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2439 return;
<> 144:ef7eb2e8f9f7 2440 }
<> 144:ef7eb2e8f9f7 2441 }
<> 144:ef7eb2e8f9f7 2442
<> 156:95d6b41a828b 2443 /* SPI Mode Fault error interrupt occurred -------------------------------*/
<> 156:95d6b41a828b 2444 if ((itflag & SPI_FLAG_MODF) != RESET)
<> 144:ef7eb2e8f9f7 2445 {
<> 156:95d6b41a828b 2446 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
<> 144:ef7eb2e8f9f7 2447 __HAL_SPI_CLEAR_MODFFLAG(hspi);
<> 144:ef7eb2e8f9f7 2448 }
<> 144:ef7eb2e8f9f7 2449
<> 156:95d6b41a828b 2450 /* SPI Frame error interrupt occurred ------------------------------------*/
<> 156:95d6b41a828b 2451 if ((itflag & SPI_FLAG_FRE) != RESET)
<> 144:ef7eb2e8f9f7 2452 {
<> 156:95d6b41a828b 2453 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
<> 144:ef7eb2e8f9f7 2454 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 144:ef7eb2e8f9f7 2455 }
<> 144:ef7eb2e8f9f7 2456
<> 156:95d6b41a828b 2457 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 156:95d6b41a828b 2458 {
<> 156:95d6b41a828b 2459 /* Disable all interrupts */
<> 156:95d6b41a828b 2460 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
<> 156:95d6b41a828b 2461
<> 156:95d6b41a828b 2462 hspi->State = HAL_SPI_STATE_READY;
<> 156:95d6b41a828b 2463 /* Disable the SPI DMA requests if enabled */
<> 156:95d6b41a828b 2464 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
<> 156:95d6b41a828b 2465 {
<> 156:95d6b41a828b 2466 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
<> 156:95d6b41a828b 2467
<> 156:95d6b41a828b 2468 /* Abort the SPI DMA Rx channel */
<> 156:95d6b41a828b 2469 if (hspi->hdmarx != NULL)
<> 156:95d6b41a828b 2470 {
<> 156:95d6b41a828b 2471 /* Set the SPI DMA Abort callback :
<> 156:95d6b41a828b 2472 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 2473 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
<> 156:95d6b41a828b 2474 HAL_DMA_Abort_IT(hspi->hdmarx);
<> 156:95d6b41a828b 2475 }
<> 156:95d6b41a828b 2476 /* Abort the SPI DMA Tx channel */
<> 156:95d6b41a828b 2477 if (hspi->hdmatx != NULL)
<> 156:95d6b41a828b 2478 {
<> 156:95d6b41a828b 2479 /* Set the SPI DMA Abort callback :
<> 156:95d6b41a828b 2480 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
<> 156:95d6b41a828b 2481 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
<> 156:95d6b41a828b 2482 HAL_DMA_Abort_IT(hspi->hdmatx);
<> 156:95d6b41a828b 2483 }
<> 156:95d6b41a828b 2484 }
<> 156:95d6b41a828b 2485 else
<> 156:95d6b41a828b 2486 {
<> 156:95d6b41a828b 2487 /* Call user error callback */
<> 156:95d6b41a828b 2488 HAL_SPI_ErrorCallback(hspi);
<> 156:95d6b41a828b 2489 }
<> 156:95d6b41a828b 2490 }
<> 144:ef7eb2e8f9f7 2491 return;
<> 144:ef7eb2e8f9f7 2492 }
<> 144:ef7eb2e8f9f7 2493 }
<> 144:ef7eb2e8f9f7 2494
<> 144:ef7eb2e8f9f7 2495 /**
<> 144:ef7eb2e8f9f7 2496 * @brief Tx Transfer completed callback.
Anna Bridge 180:96ed750bd169 2497 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2498 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2499 * @retval None
<> 144:ef7eb2e8f9f7 2500 */
<> 144:ef7eb2e8f9f7 2501 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2502 {
<> 144:ef7eb2e8f9f7 2503 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2504 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2505
<> 144:ef7eb2e8f9f7 2506 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2507 the HAL_SPI_TxCpltCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 2508 */
<> 144:ef7eb2e8f9f7 2509 }
<> 144:ef7eb2e8f9f7 2510
<> 144:ef7eb2e8f9f7 2511 /**
<> 144:ef7eb2e8f9f7 2512 * @brief Rx Transfer completed callback.
Anna Bridge 180:96ed750bd169 2513 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2514 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2515 * @retval None
<> 144:ef7eb2e8f9f7 2516 */
<> 144:ef7eb2e8f9f7 2517 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2518 {
<> 144:ef7eb2e8f9f7 2519 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2520 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2521
<> 144:ef7eb2e8f9f7 2522 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2523 the HAL_SPI_RxCpltCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 2524 */
<> 144:ef7eb2e8f9f7 2525 }
<> 144:ef7eb2e8f9f7 2526
<> 144:ef7eb2e8f9f7 2527 /**
<> 144:ef7eb2e8f9f7 2528 * @brief Tx and Rx Transfer completed callback.
Anna Bridge 180:96ed750bd169 2529 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2530 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2531 * @retval None
<> 144:ef7eb2e8f9f7 2532 */
<> 144:ef7eb2e8f9f7 2533 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2534 {
<> 144:ef7eb2e8f9f7 2535 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2536 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2537
<> 144:ef7eb2e8f9f7 2538 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2539 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 2540 */
<> 144:ef7eb2e8f9f7 2541 }
<> 144:ef7eb2e8f9f7 2542
<> 144:ef7eb2e8f9f7 2543 /**
<> 144:ef7eb2e8f9f7 2544 * @brief Tx Half Transfer completed callback.
Anna Bridge 180:96ed750bd169 2545 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2546 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2547 * @retval None
<> 144:ef7eb2e8f9f7 2548 */
<> 144:ef7eb2e8f9f7 2549 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2550 {
<> 144:ef7eb2e8f9f7 2551 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2552 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2553
<> 144:ef7eb2e8f9f7 2554 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2555 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 2556 */
<> 144:ef7eb2e8f9f7 2557 }
<> 144:ef7eb2e8f9f7 2558
<> 144:ef7eb2e8f9f7 2559 /**
<> 144:ef7eb2e8f9f7 2560 * @brief Rx Half Transfer completed callback.
Anna Bridge 180:96ed750bd169 2561 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2562 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2563 * @retval None
<> 144:ef7eb2e8f9f7 2564 */
<> 144:ef7eb2e8f9f7 2565 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2566 {
<> 144:ef7eb2e8f9f7 2567 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2568 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2569
<> 144:ef7eb2e8f9f7 2570 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2571 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
<> 144:ef7eb2e8f9f7 2572 */
<> 144:ef7eb2e8f9f7 2573 }
<> 144:ef7eb2e8f9f7 2574
<> 144:ef7eb2e8f9f7 2575 /**
<> 144:ef7eb2e8f9f7 2576 * @brief Tx and Rx Half Transfer callback.
Anna Bridge 180:96ed750bd169 2577 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2578 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2579 * @retval None
<> 144:ef7eb2e8f9f7 2580 */
<> 144:ef7eb2e8f9f7 2581 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2582 {
<> 144:ef7eb2e8f9f7 2583 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2584 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2585
<> 144:ef7eb2e8f9f7 2586 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2587 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
<> 144:ef7eb2e8f9f7 2588 */
<> 144:ef7eb2e8f9f7 2589 }
<> 144:ef7eb2e8f9f7 2590
<> 144:ef7eb2e8f9f7 2591 /**
<> 144:ef7eb2e8f9f7 2592 * @brief SPI error callback.
Anna Bridge 180:96ed750bd169 2593 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2594 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2595 * @retval None
<> 144:ef7eb2e8f9f7 2596 */
<> 156:95d6b41a828b 2597 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2598 {
<> 144:ef7eb2e8f9f7 2599 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2600 UNUSED(hspi);
<> 144:ef7eb2e8f9f7 2601
<> 144:ef7eb2e8f9f7 2602 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2603 the HAL_SPI_ErrorCallback should be implemented in the user file
<> 144:ef7eb2e8f9f7 2604 */
<> 144:ef7eb2e8f9f7 2605 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
<> 144:ef7eb2e8f9f7 2606 and user can use HAL_SPI_GetError() API to check the latest error occurred
<> 144:ef7eb2e8f9f7 2607 */
<> 144:ef7eb2e8f9f7 2608 }
<> 144:ef7eb2e8f9f7 2609
<> 144:ef7eb2e8f9f7 2610 /**
<> 156:95d6b41a828b 2611 * @brief SPI Abort Complete callback.
<> 156:95d6b41a828b 2612 * @param hspi SPI handle.
<> 156:95d6b41a828b 2613 * @retval None
<> 156:95d6b41a828b 2614 */
<> 156:95d6b41a828b 2615 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
<> 156:95d6b41a828b 2616 {
<> 156:95d6b41a828b 2617 /* Prevent unused argument(s) compilation warning */
<> 156:95d6b41a828b 2618 UNUSED(hspi);
<> 156:95d6b41a828b 2619
<> 156:95d6b41a828b 2620 /* NOTE : This function should not be modified, when the callback is needed,
<> 156:95d6b41a828b 2621 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
<> 156:95d6b41a828b 2622 */
<> 156:95d6b41a828b 2623 }
<> 156:95d6b41a828b 2624
<> 156:95d6b41a828b 2625 /**
<> 144:ef7eb2e8f9f7 2626 * @}
<> 144:ef7eb2e8f9f7 2627 */
<> 144:ef7eb2e8f9f7 2628
<> 144:ef7eb2e8f9f7 2629 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 2630 * @brief SPI control functions
<> 144:ef7eb2e8f9f7 2631 *
<> 144:ef7eb2e8f9f7 2632 @verbatim
<> 144:ef7eb2e8f9f7 2633 ===============================================================================
<> 144:ef7eb2e8f9f7 2634 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 2635 ===============================================================================
<> 144:ef7eb2e8f9f7 2636 [..]
<> 144:ef7eb2e8f9f7 2637 This subsection provides a set of functions allowing to control the SPI.
<> 144:ef7eb2e8f9f7 2638 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
<> 144:ef7eb2e8f9f7 2639 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
<> 144:ef7eb2e8f9f7 2640 @endverbatim
<> 144:ef7eb2e8f9f7 2641 * @{
<> 144:ef7eb2e8f9f7 2642 */
<> 144:ef7eb2e8f9f7 2643
<> 144:ef7eb2e8f9f7 2644 /**
<> 144:ef7eb2e8f9f7 2645 * @brief Return the SPI handle state.
Anna Bridge 180:96ed750bd169 2646 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2647 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2648 * @retval SPI state
<> 144:ef7eb2e8f9f7 2649 */
<> 144:ef7eb2e8f9f7 2650 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2651 {
<> 144:ef7eb2e8f9f7 2652 /* Return SPI handle state */
<> 144:ef7eb2e8f9f7 2653 return hspi->State;
<> 144:ef7eb2e8f9f7 2654 }
<> 144:ef7eb2e8f9f7 2655
<> 144:ef7eb2e8f9f7 2656 /**
<> 144:ef7eb2e8f9f7 2657 * @brief Return the SPI error code.
Anna Bridge 180:96ed750bd169 2658 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2659 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 2660 * @retval SPI error code in bitmap format
<> 144:ef7eb2e8f9f7 2661 */
<> 144:ef7eb2e8f9f7 2662 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 2663 {
<> 156:95d6b41a828b 2664 /* Return SPI ErrorCode */
<> 144:ef7eb2e8f9f7 2665 return hspi->ErrorCode;
<> 144:ef7eb2e8f9f7 2666 }
<> 144:ef7eb2e8f9f7 2667
<> 144:ef7eb2e8f9f7 2668 /**
<> 144:ef7eb2e8f9f7 2669 * @}
<> 144:ef7eb2e8f9f7 2670 */
<> 144:ef7eb2e8f9f7 2671
<> 144:ef7eb2e8f9f7 2672 /**
<> 144:ef7eb2e8f9f7 2673 * @}
<> 144:ef7eb2e8f9f7 2674 */
<> 144:ef7eb2e8f9f7 2675
<> 144:ef7eb2e8f9f7 2676 /** @addtogroup SPI_Private_Functions
<> 156:95d6b41a828b 2677 * @brief Private functions
<> 144:ef7eb2e8f9f7 2678 * @{
<> 144:ef7eb2e8f9f7 2679 */
<> 144:ef7eb2e8f9f7 2680
<> 144:ef7eb2e8f9f7 2681 /**
<> 144:ef7eb2e8f9f7 2682 * @brief DMA SPI transmit process complete callback.
Anna Bridge 180:96ed750bd169 2683 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2684 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2685 * @retval None
<> 144:ef7eb2e8f9f7 2686 */
<> 144:ef7eb2e8f9f7 2687 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2688 {
<> 156:95d6b41a828b 2689 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 156:95d6b41a828b 2690 uint32_t tickstart = 0U;
<> 156:95d6b41a828b 2691
<> 156:95d6b41a828b 2692 /* Init tickstart for timeout managment*/
<> 156:95d6b41a828b 2693 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 2694
<> 156:95d6b41a828b 2695 /* DMA Normal Mode */
<> 156:95d6b41a828b 2696 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
<> 144:ef7eb2e8f9f7 2697 {
<> 156:95d6b41a828b 2698 /* Disable ERR interrupt */
<> 156:95d6b41a828b 2699 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
<> 156:95d6b41a828b 2700
<> 144:ef7eb2e8f9f7 2701 /* Disable Tx DMA Request */
<> 144:ef7eb2e8f9f7 2702 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 2703
<> 144:ef7eb2e8f9f7 2704 /* Check the end of the transaction */
<> 156:95d6b41a828b 2705 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2706 {
<> 156:95d6b41a828b 2707 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 2708 }
<> 144:ef7eb2e8f9f7 2709
<> 144:ef7eb2e8f9f7 2710 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
<> 156:95d6b41a828b 2711 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 2712 {
<> 144:ef7eb2e8f9f7 2713 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2714 }
<> 144:ef7eb2e8f9f7 2715
<> 156:95d6b41a828b 2716 hspi->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 2717 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2718
<> 156:95d6b41a828b 2719 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2720 {
<> 144:ef7eb2e8f9f7 2721 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2722 return;
<> 144:ef7eb2e8f9f7 2723 }
<> 144:ef7eb2e8f9f7 2724 }
<> 144:ef7eb2e8f9f7 2725 HAL_SPI_TxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2726 }
<> 144:ef7eb2e8f9f7 2727
<> 144:ef7eb2e8f9f7 2728 /**
<> 144:ef7eb2e8f9f7 2729 * @brief DMA SPI receive process complete callback.
Anna Bridge 180:96ed750bd169 2730 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2731 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2732 * @retval None
<> 144:ef7eb2e8f9f7 2733 */
<> 144:ef7eb2e8f9f7 2734 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2735 {
<> 156:95d6b41a828b 2736 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 156:95d6b41a828b 2737 uint32_t tickstart = 0U;
<> 156:95d6b41a828b 2738 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 2739 __IO uint16_t tmpreg = 0U;
<> 156:95d6b41a828b 2740 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 2741
<> 156:95d6b41a828b 2742 /* Init tickstart for timeout management*/
<> 156:95d6b41a828b 2743 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 2744
<> 156:95d6b41a828b 2745 /* DMA Normal Mode */
<> 156:95d6b41a828b 2746 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
<> 144:ef7eb2e8f9f7 2747 {
<> 156:95d6b41a828b 2748 /* Disable ERR interrupt */
<> 156:95d6b41a828b 2749 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
<> 156:95d6b41a828b 2750
<> 156:95d6b41a828b 2751 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 2752 /* CRC handling */
<> 156:95d6b41a828b 2753 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2754 {
<> 156:95d6b41a828b 2755 /* Wait until RXNE flag */
<> 156:95d6b41a828b 2756 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2757 {
<> 144:ef7eb2e8f9f7 2758 /* Error on the CRC reception */
<> 156:95d6b41a828b 2759 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2760 }
<> 156:95d6b41a828b 2761 /* Read CRC */
<> 156:95d6b41a828b 2762 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
<> 144:ef7eb2e8f9f7 2763 {
<> 144:ef7eb2e8f9f7 2764 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2765 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2766 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2767 }
<> 144:ef7eb2e8f9f7 2768 else
<> 144:ef7eb2e8f9f7 2769 {
<> 144:ef7eb2e8f9f7 2770 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2771 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2772 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2773
<> 156:95d6b41a828b 2774 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
<> 144:ef7eb2e8f9f7 2775 {
<> 156:95d6b41a828b 2776 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2777 {
<> 144:ef7eb2e8f9f7 2778 /* Error on the CRC reception */
<> 156:95d6b41a828b 2779 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2780 }
<> 144:ef7eb2e8f9f7 2781 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2782 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2783 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2784 }
<> 144:ef7eb2e8f9f7 2785 }
<> 144:ef7eb2e8f9f7 2786 }
<> 156:95d6b41a828b 2787 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 2788
<> 144:ef7eb2e8f9f7 2789 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
<> 144:ef7eb2e8f9f7 2790 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2791
<> 144:ef7eb2e8f9f7 2792 /* Check the end of the transaction */
<> 156:95d6b41a828b 2793 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2794 {
<> 156:95d6b41a828b 2795 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
<> 144:ef7eb2e8f9f7 2796 }
<> 144:ef7eb2e8f9f7 2797
<> 156:95d6b41a828b 2798 hspi->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 2799 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2800
<> 156:95d6b41a828b 2801 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 2802 /* Check if CRC error occurred */
<> 156:95d6b41a828b 2803 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 2804 {
<> 156:95d6b41a828b 2805 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2806 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2807 }
<> 156:95d6b41a828b 2808 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 2809
<> 156:95d6b41a828b 2810 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2811 {
<> 144:ef7eb2e8f9f7 2812 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2813 return;
<> 144:ef7eb2e8f9f7 2814 }
<> 144:ef7eb2e8f9f7 2815 }
<> 144:ef7eb2e8f9f7 2816 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2817 }
<> 144:ef7eb2e8f9f7 2818
<> 144:ef7eb2e8f9f7 2819 /**
<> 144:ef7eb2e8f9f7 2820 * @brief DMA SPI transmit receive process complete callback.
Anna Bridge 180:96ed750bd169 2821 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2822 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2823 * @retval None
<> 144:ef7eb2e8f9f7 2824 */
<> 144:ef7eb2e8f9f7 2825 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2826 {
<> 156:95d6b41a828b 2827 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 156:95d6b41a828b 2828 uint32_t tickstart = 0U;
<> 156:95d6b41a828b 2829 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 2830 __IO int16_t tmpreg = 0U;
<> 156:95d6b41a828b 2831 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 2832 /* Init tickstart for timeout management*/
<> 156:95d6b41a828b 2833 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 2834
<> 156:95d6b41a828b 2835 /* DMA Normal Mode */
<> 156:95d6b41a828b 2836 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
<> 144:ef7eb2e8f9f7 2837 {
<> 156:95d6b41a828b 2838 /* Disable ERR interrupt */
<> 156:95d6b41a828b 2839 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
<> 156:95d6b41a828b 2840
<> 156:95d6b41a828b 2841 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 2842 /* CRC handling */
<> 156:95d6b41a828b 2843 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 2844 {
<> 156:95d6b41a828b 2845 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
<> 144:ef7eb2e8f9f7 2846 {
<> 156:95d6b41a828b 2847 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
<> 156:95d6b41a828b 2848 tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2849 {
<> 144:ef7eb2e8f9f7 2850 /* Error on the CRC reception */
<> 156:95d6b41a828b 2851 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2852 }
<> 156:95d6b41a828b 2853 /* Read CRC to Flush DR and RXNE flag */
<> 144:ef7eb2e8f9f7 2854 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2855 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2856 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2857 }
<> 144:ef7eb2e8f9f7 2858 else
<> 144:ef7eb2e8f9f7 2859 {
<> 156:95d6b41a828b 2860 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2861 {
<> 144:ef7eb2e8f9f7 2862 /* Error on the CRC reception */
<> 156:95d6b41a828b 2863 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2864 }
<> 156:95d6b41a828b 2865 /* Read CRC to Flush DR and RXNE flag */
<> 144:ef7eb2e8f9f7 2866 tmpreg = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 2867 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2868 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 2869 }
<> 144:ef7eb2e8f9f7 2870 }
<> 156:95d6b41a828b 2871 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 2872
<> 144:ef7eb2e8f9f7 2873 /* Check the end of the transaction */
<> 156:95d6b41a828b 2874 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2875 {
<> 156:95d6b41a828b 2876 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 2877 }
<> 156:95d6b41a828b 2878
<> 144:ef7eb2e8f9f7 2879 /* Disable Rx/Tx DMA Request */
<> 144:ef7eb2e8f9f7 2880 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2881
<> 156:95d6b41a828b 2882 hspi->TxXferCount = 0U;
<> 156:95d6b41a828b 2883 hspi->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 2884 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2885
<> 156:95d6b41a828b 2886 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 2887 /* Check if CRC error occurred */
<> 156:95d6b41a828b 2888 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 2889 {
<> 156:95d6b41a828b 2890 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 2891 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 2892 }
<> 156:95d6b41a828b 2893 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 2894
<> 156:95d6b41a828b 2895 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2896 {
<> 144:ef7eb2e8f9f7 2897 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2898 return;
<> 144:ef7eb2e8f9f7 2899 }
<> 144:ef7eb2e8f9f7 2900 }
<> 144:ef7eb2e8f9f7 2901 HAL_SPI_TxRxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2902 }
<> 144:ef7eb2e8f9f7 2903
<> 144:ef7eb2e8f9f7 2904 /**
<> 144:ef7eb2e8f9f7 2905 * @brief DMA SPI half transmit process complete callback.
Anna Bridge 180:96ed750bd169 2906 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2907 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2908 * @retval None
<> 144:ef7eb2e8f9f7 2909 */
<> 144:ef7eb2e8f9f7 2910 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2911 {
<> 156:95d6b41a828b 2912 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2913
<> 144:ef7eb2e8f9f7 2914 HAL_SPI_TxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2915 }
<> 144:ef7eb2e8f9f7 2916
<> 144:ef7eb2e8f9f7 2917 /**
<> 144:ef7eb2e8f9f7 2918 * @brief DMA SPI half receive process complete callback
Anna Bridge 180:96ed750bd169 2919 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2920 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2921 * @retval None
<> 144:ef7eb2e8f9f7 2922 */
<> 144:ef7eb2e8f9f7 2923 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2924 {
<> 156:95d6b41a828b 2925 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2926
<> 144:ef7eb2e8f9f7 2927 HAL_SPI_RxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2928 }
<> 144:ef7eb2e8f9f7 2929
<> 144:ef7eb2e8f9f7 2930 /**
<> 144:ef7eb2e8f9f7 2931 * @brief DMA SPI half transmit receive process complete callback.
Anna Bridge 180:96ed750bd169 2932 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2933 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2934 * @retval None
<> 144:ef7eb2e8f9f7 2935 */
<> 144:ef7eb2e8f9f7 2936 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2937 {
<> 156:95d6b41a828b 2938 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2939
<> 144:ef7eb2e8f9f7 2940 HAL_SPI_TxRxHalfCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 2941 }
<> 144:ef7eb2e8f9f7 2942
<> 144:ef7eb2e8f9f7 2943 /**
<> 144:ef7eb2e8f9f7 2944 * @brief DMA SPI communication error callback.
Anna Bridge 180:96ed750bd169 2945 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2946 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 2947 * @retval None
<> 144:ef7eb2e8f9f7 2948 */
<> 144:ef7eb2e8f9f7 2949 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2950 {
<> 156:95d6b41a828b 2951 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2952
<> 144:ef7eb2e8f9f7 2953 /* Stop the disable DMA transfer on SPI side */
<> 144:ef7eb2e8f9f7 2954 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 2955
<> 156:95d6b41a828b 2956 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
<> 144:ef7eb2e8f9f7 2957 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 2958 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 2959 }
<> 144:ef7eb2e8f9f7 2960
<> 144:ef7eb2e8f9f7 2961 /**
<> 156:95d6b41a828b 2962 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
<> 156:95d6b41a828b 2963 * (To be called at end of DMA Abort procedure following error occurrence).
<> 156:95d6b41a828b 2964 * @param hdma DMA handle.
<> 156:95d6b41a828b 2965 * @retval None
<> 156:95d6b41a828b 2966 */
<> 156:95d6b41a828b 2967 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2968 {
<> 156:95d6b41a828b 2969 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 156:95d6b41a828b 2970 hspi->RxXferCount = 0U;
<> 156:95d6b41a828b 2971 hspi->TxXferCount = 0U;
<> 156:95d6b41a828b 2972
<> 156:95d6b41a828b 2973 HAL_SPI_ErrorCallback(hspi);
<> 156:95d6b41a828b 2974 }
<> 156:95d6b41a828b 2975
<> 156:95d6b41a828b 2976 /**
<> 156:95d6b41a828b 2977 * @brief DMA SPI Tx communication abort callback, when initiated by user
<> 156:95d6b41a828b 2978 * (To be called at end of DMA Tx Abort procedure following user abort request).
<> 156:95d6b41a828b 2979 * @note When this callback is executed, User Abort complete call back is called only if no
<> 156:95d6b41a828b 2980 * Abort still ongoing for Rx DMA Handle.
<> 156:95d6b41a828b 2981 * @param hdma DMA handle.
<> 156:95d6b41a828b 2982 * @retval None
<> 156:95d6b41a828b 2983 */
<> 156:95d6b41a828b 2984 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 2985 {
<> 156:95d6b41a828b 2986 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 156:95d6b41a828b 2987
<> 156:95d6b41a828b 2988 hspi->hdmatx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 2989
<> 156:95d6b41a828b 2990 /* Disable Tx DMA Request */
<> 156:95d6b41a828b 2991 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
<> 156:95d6b41a828b 2992
<> 156:95d6b41a828b 2993 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 2994 {
<> 156:95d6b41a828b 2995 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 2996 }
<> 156:95d6b41a828b 2997
<> 156:95d6b41a828b 2998 /* Disable SPI Peripheral */
<> 156:95d6b41a828b 2999 __HAL_SPI_DISABLE(hspi);
<> 156:95d6b41a828b 3000
<> 156:95d6b41a828b 3001 /* Empty the FRLVL fifo */
<> 156:95d6b41a828b 3002 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 3003 {
<> 156:95d6b41a828b 3004 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 3005 }
<> 156:95d6b41a828b 3006
<> 156:95d6b41a828b 3007 /* Check if an Abort process is still ongoing */
<> 156:95d6b41a828b 3008 if (hspi->hdmarx != NULL)
<> 156:95d6b41a828b 3009 {
<> 156:95d6b41a828b 3010 if (hspi->hdmarx->XferAbortCallback != NULL)
<> 156:95d6b41a828b 3011 {
<> 156:95d6b41a828b 3012 return;
<> 156:95d6b41a828b 3013 }
<> 156:95d6b41a828b 3014 }
<> 156:95d6b41a828b 3015
<> 156:95d6b41a828b 3016 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
<> 156:95d6b41a828b 3017 hspi->RxXferCount = 0U;
<> 156:95d6b41a828b 3018 hspi->TxXferCount = 0U;
<> 156:95d6b41a828b 3019
<> 156:95d6b41a828b 3020 /* Check no error during Abort procedure */
<> 156:95d6b41a828b 3021 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
<> 156:95d6b41a828b 3022 {
<> 156:95d6b41a828b 3023 /* Reset errorCode */
<> 156:95d6b41a828b 3024 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 3025 }
<> 156:95d6b41a828b 3026
<> 156:95d6b41a828b 3027 /* Clear the Error flags in the SR register */
<> 156:95d6b41a828b 3028 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 156:95d6b41a828b 3029 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 156:95d6b41a828b 3030
<> 156:95d6b41a828b 3031 /* Restore hspi->State to Ready */
<> 156:95d6b41a828b 3032 hspi->State = HAL_SPI_STATE_READY;
<> 156:95d6b41a828b 3033
<> 156:95d6b41a828b 3034 /* Call user Abort complete callback */
<> 156:95d6b41a828b 3035 HAL_SPI_AbortCpltCallback(hspi);
<> 156:95d6b41a828b 3036 }
<> 156:95d6b41a828b 3037
<> 156:95d6b41a828b 3038 /**
<> 156:95d6b41a828b 3039 * @brief DMA SPI Rx communication abort callback, when initiated by user
<> 156:95d6b41a828b 3040 * (To be called at end of DMA Rx Abort procedure following user abort request).
<> 156:95d6b41a828b 3041 * @note When this callback is executed, User Abort complete call back is called only if no
<> 156:95d6b41a828b 3042 * Abort still ongoing for Tx DMA Handle.
<> 156:95d6b41a828b 3043 * @param hdma DMA handle.
<> 156:95d6b41a828b 3044 * @retval None
<> 156:95d6b41a828b 3045 */
<> 156:95d6b41a828b 3046 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
<> 156:95d6b41a828b 3047 {
<> 156:95d6b41a828b 3048 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
<> 156:95d6b41a828b 3049
<> 156:95d6b41a828b 3050 /* Disable SPI Peripheral */
<> 156:95d6b41a828b 3051 __HAL_SPI_DISABLE(hspi);
<> 156:95d6b41a828b 3052
<> 156:95d6b41a828b 3053 hspi->hdmarx->XferAbortCallback = NULL;
<> 156:95d6b41a828b 3054
<> 156:95d6b41a828b 3055 /* Disable Rx DMA Request */
<> 156:95d6b41a828b 3056 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
<> 156:95d6b41a828b 3057
<> 156:95d6b41a828b 3058 /* Control the BSY flag */
<> 156:95d6b41a828b 3059 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 3060 {
<> 156:95d6b41a828b 3061 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 3062 }
<> 156:95d6b41a828b 3063
<> 156:95d6b41a828b 3064 /* Empty the FRLVL fifo */
<> 156:95d6b41a828b 3065 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 3066 {
<> 156:95d6b41a828b 3067 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 3068 }
<> 156:95d6b41a828b 3069
<> 156:95d6b41a828b 3070 /* Check if an Abort process is still ongoing */
<> 156:95d6b41a828b 3071 if (hspi->hdmatx != NULL)
<> 156:95d6b41a828b 3072 {
<> 156:95d6b41a828b 3073 if (hspi->hdmatx->XferAbortCallback != NULL)
<> 156:95d6b41a828b 3074 {
<> 156:95d6b41a828b 3075 return;
<> 156:95d6b41a828b 3076 }
<> 156:95d6b41a828b 3077 }
<> 156:95d6b41a828b 3078
<> 156:95d6b41a828b 3079 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
<> 156:95d6b41a828b 3080 hspi->RxXferCount = 0U;
<> 156:95d6b41a828b 3081 hspi->TxXferCount = 0U;
<> 156:95d6b41a828b 3082
<> 156:95d6b41a828b 3083 /* Check no error during Abort procedure */
<> 156:95d6b41a828b 3084 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
<> 156:95d6b41a828b 3085 {
<> 156:95d6b41a828b 3086 /* Reset errorCode */
<> 156:95d6b41a828b 3087 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 156:95d6b41a828b 3088 }
<> 156:95d6b41a828b 3089
<> 156:95d6b41a828b 3090 /* Clear the Error flags in the SR register */
<> 156:95d6b41a828b 3091 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 156:95d6b41a828b 3092 __HAL_SPI_CLEAR_FREFLAG(hspi);
<> 156:95d6b41a828b 3093
<> 156:95d6b41a828b 3094 /* Restore hspi->State to Ready */
<> 156:95d6b41a828b 3095 hspi->State = HAL_SPI_STATE_READY;
<> 156:95d6b41a828b 3096
<> 156:95d6b41a828b 3097 /* Call user Abort complete callback */
<> 156:95d6b41a828b 3098 HAL_SPI_AbortCpltCallback(hspi);
<> 156:95d6b41a828b 3099 }
<> 156:95d6b41a828b 3100
<> 156:95d6b41a828b 3101 /**
<> 144:ef7eb2e8f9f7 3102 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
Anna Bridge 180:96ed750bd169 3103 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3104 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3105 * @retval None
<> 144:ef7eb2e8f9f7 3106 */
<> 144:ef7eb2e8f9f7 3107 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3108 {
<> 144:ef7eb2e8f9f7 3109 /* Receive data in packing mode */
<> 156:95d6b41a828b 3110 if (hspi->RxXferCount > 1U)
<> 144:ef7eb2e8f9f7 3111 {
<> 156:95d6b41a828b 3112 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 3113 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 156:95d6b41a828b 3114 hspi->RxXferCount -= 2U;
<> 156:95d6b41a828b 3115 if (hspi->RxXferCount == 1U)
<> 144:ef7eb2e8f9f7 3116 {
<> 144:ef7eb2e8f9f7 3117 /* set fiforxthresold according the reception data length: 8bit */
<> 144:ef7eb2e8f9f7 3118 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 3119 }
<> 144:ef7eb2e8f9f7 3120 }
<> 144:ef7eb2e8f9f7 3121 /* Receive data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 3122 else
<> 144:ef7eb2e8f9f7 3123 {
<> 144:ef7eb2e8f9f7 3124 *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
<> 144:ef7eb2e8f9f7 3125 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 3126 }
<> 144:ef7eb2e8f9f7 3127
<> 144:ef7eb2e8f9f7 3128 /* check end of the reception */
<> 156:95d6b41a828b 3129 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3130 {
<> 156:95d6b41a828b 3131 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3132 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3133 {
<> 144:ef7eb2e8f9f7 3134 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
<> 144:ef7eb2e8f9f7 3135 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
<> 144:ef7eb2e8f9f7 3136 return;
<> 144:ef7eb2e8f9f7 3137 }
<> 156:95d6b41a828b 3138 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 3139
<> 156:95d6b41a828b 3140 /* Disable RXNE and ERR interrupt */
<> 156:95d6b41a828b 3141 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 156:95d6b41a828b 3142
<> 156:95d6b41a828b 3143 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3144 {
<> 144:ef7eb2e8f9f7 3145 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3146 }
<> 144:ef7eb2e8f9f7 3147 }
<> 144:ef7eb2e8f9f7 3148 }
<> 144:ef7eb2e8f9f7 3149
<> 156:95d6b41a828b 3150 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3151 /**
<> 144:ef7eb2e8f9f7 3152 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
Anna Bridge 180:96ed750bd169 3153 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3154 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3155 * @retval None
<> 144:ef7eb2e8f9f7 3156 */
<> 144:ef7eb2e8f9f7 3157 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3158 {
<> 156:95d6b41a828b 3159 __IO uint8_t tmpreg = 0U;
<> 156:95d6b41a828b 3160
<> 156:95d6b41a828b 3161 /* Read data register to flush CRC */
<> 156:95d6b41a828b 3162 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
<> 156:95d6b41a828b 3163
<> 144:ef7eb2e8f9f7 3164 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 3165 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 3166
<> 144:ef7eb2e8f9f7 3167 hspi->CRCSize--;
<> 144:ef7eb2e8f9f7 3168
<> 144:ef7eb2e8f9f7 3169 /* check end of the reception */
<> 156:95d6b41a828b 3170 if (hspi->CRCSize == 0U)
<> 144:ef7eb2e8f9f7 3171 {
<> 156:95d6b41a828b 3172 /* Disable RXNE and ERR interrupt */
<> 156:95d6b41a828b 3173 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 156:95d6b41a828b 3174
<> 156:95d6b41a828b 3175 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3176 {
<> 144:ef7eb2e8f9f7 3177 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3178 }
<> 144:ef7eb2e8f9f7 3179 }
<> 144:ef7eb2e8f9f7 3180 }
<> 156:95d6b41a828b 3181 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3182
<> 144:ef7eb2e8f9f7 3183 /**
<> 144:ef7eb2e8f9f7 3184 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
Anna Bridge 180:96ed750bd169 3185 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3186 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3187 * @retval None
<> 144:ef7eb2e8f9f7 3188 */
<> 144:ef7eb2e8f9f7 3189 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3190 {
<> 144:ef7eb2e8f9f7 3191 /* Transmit data in packing Bit mode */
<> 156:95d6b41a828b 3192 if (hspi->TxXferCount >= 2U)
<> 144:ef7eb2e8f9f7 3193 {
<> 144:ef7eb2e8f9f7 3194 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 3195 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 156:95d6b41a828b 3196 hspi->TxXferCount -= 2U;
<> 144:ef7eb2e8f9f7 3197 }
<> 144:ef7eb2e8f9f7 3198 /* Transmit data in 8 Bit mode */
<> 144:ef7eb2e8f9f7 3199 else
<> 144:ef7eb2e8f9f7 3200 {
<> 144:ef7eb2e8f9f7 3201 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 3202 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 3203 }
<> 144:ef7eb2e8f9f7 3204
<> 144:ef7eb2e8f9f7 3205 /* check the end of the transmission */
<> 156:95d6b41a828b 3206 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3207 {
<> 156:95d6b41a828b 3208 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3209 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3210 {
<> 156:95d6b41a828b 3211 /* Set CRC Next Bit to send CRC */
<> 144:ef7eb2e8f9f7 3212 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 156:95d6b41a828b 3213 /* Disable TXE interrupt */
<> 144:ef7eb2e8f9f7 3214 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 144:ef7eb2e8f9f7 3215 return;
<> 144:ef7eb2e8f9f7 3216 }
<> 156:95d6b41a828b 3217 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 3218
<> 144:ef7eb2e8f9f7 3219 /* Disable TXE interrupt */
<> 144:ef7eb2e8f9f7 3220 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 144:ef7eb2e8f9f7 3221
<> 156:95d6b41a828b 3222 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3223 {
<> 144:ef7eb2e8f9f7 3224 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3225 }
<> 144:ef7eb2e8f9f7 3226 }
<> 144:ef7eb2e8f9f7 3227 }
<> 144:ef7eb2e8f9f7 3228
<> 144:ef7eb2e8f9f7 3229 /**
<> 144:ef7eb2e8f9f7 3230 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
Anna Bridge 180:96ed750bd169 3231 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3232 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3233 * @retval None
<> 144:ef7eb2e8f9f7 3234 */
<> 144:ef7eb2e8f9f7 3235 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3236 {
<> 144:ef7eb2e8f9f7 3237 /* Receive data in 16 Bit mode */
<> 156:95d6b41a828b 3238 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 3239 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 3240 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 3241
<> 156:95d6b41a828b 3242 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3243 {
<> 156:95d6b41a828b 3244 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3245 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3246 {
<> 144:ef7eb2e8f9f7 3247 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
<> 144:ef7eb2e8f9f7 3248 return;
<> 144:ef7eb2e8f9f7 3249 }
<> 156:95d6b41a828b 3250 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3251
<> 144:ef7eb2e8f9f7 3252 /* Disable RXNE interrupt */
<> 144:ef7eb2e8f9f7 3253 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<> 144:ef7eb2e8f9f7 3254
<> 156:95d6b41a828b 3255 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3256 {
<> 144:ef7eb2e8f9f7 3257 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3258 }
<> 144:ef7eb2e8f9f7 3259 }
<> 144:ef7eb2e8f9f7 3260 }
<> 144:ef7eb2e8f9f7 3261
<> 156:95d6b41a828b 3262 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3263 /**
<> 144:ef7eb2e8f9f7 3264 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
Anna Bridge 180:96ed750bd169 3265 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3266 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3267 * @retval None
<> 144:ef7eb2e8f9f7 3268 */
<> 144:ef7eb2e8f9f7 3269 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3270 {
<> 144:ef7eb2e8f9f7 3271 /* Receive data in 16 Bit mode */
<> 156:95d6b41a828b 3272 __IO uint16_t tmpreg = 0U;
<> 156:95d6b41a828b 3273
<> 156:95d6b41a828b 3274 /* Read data register to flush CRC */
<> 156:95d6b41a828b 3275 tmpreg = hspi->Instance->DR;
<> 156:95d6b41a828b 3276
<> 144:ef7eb2e8f9f7 3277 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 3278 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 3279
<> 144:ef7eb2e8f9f7 3280 /* Disable RXNE interrupt */
<> 144:ef7eb2e8f9f7 3281 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
<> 144:ef7eb2e8f9f7 3282
<> 144:ef7eb2e8f9f7 3283 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3284 }
<> 156:95d6b41a828b 3285 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3286
<> 144:ef7eb2e8f9f7 3287 /**
<> 144:ef7eb2e8f9f7 3288 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
Anna Bridge 180:96ed750bd169 3289 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3290 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3291 * @retval None
<> 144:ef7eb2e8f9f7 3292 */
<> 144:ef7eb2e8f9f7 3293 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3294 {
<> 144:ef7eb2e8f9f7 3295 /* Transmit data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 3296 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 3297 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 3298 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 3299
<> 144:ef7eb2e8f9f7 3300 /* Enable CRC Transmission */
<> 156:95d6b41a828b 3301 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3302 {
<> 156:95d6b41a828b 3303 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3304 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3305 {
<> 156:95d6b41a828b 3306 /* Set CRC Next Bit to send CRC */
<> 144:ef7eb2e8f9f7 3307 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 156:95d6b41a828b 3308 /* Disable TXE interrupt */
<> 144:ef7eb2e8f9f7 3309 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 144:ef7eb2e8f9f7 3310 return;
<> 144:ef7eb2e8f9f7 3311 }
<> 156:95d6b41a828b 3312 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 3313
<> 144:ef7eb2e8f9f7 3314 /* Disable TXE interrupt */
<> 144:ef7eb2e8f9f7 3315 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
<> 144:ef7eb2e8f9f7 3316
<> 156:95d6b41a828b 3317 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3318 {
<> 144:ef7eb2e8f9f7 3319 SPI_CloseRxTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3320 }
<> 144:ef7eb2e8f9f7 3321 }
<> 144:ef7eb2e8f9f7 3322 }
<> 144:ef7eb2e8f9f7 3323
<> 156:95d6b41a828b 3324 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3325 /**
<> 144:ef7eb2e8f9f7 3326 * @brief Manage the CRC 8-bit receive in Interrupt context.
Anna Bridge 180:96ed750bd169 3327 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3328 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3329 * @retval None
<> 144:ef7eb2e8f9f7 3330 */
<> 144:ef7eb2e8f9f7 3331 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3332 {
<> 156:95d6b41a828b 3333 __IO uint8_t tmpreg = 0U;
<> 156:95d6b41a828b 3334
<> 156:95d6b41a828b 3335 /* Read data register to flush CRC */
<> 156:95d6b41a828b 3336 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
<> 156:95d6b41a828b 3337
<> 144:ef7eb2e8f9f7 3338 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 3339 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 3340
<> 144:ef7eb2e8f9f7 3341 hspi->CRCSize--;
<> 144:ef7eb2e8f9f7 3342
<> 156:95d6b41a828b 3343 if (hspi->CRCSize == 0U)
<> 144:ef7eb2e8f9f7 3344 {
<> 144:ef7eb2e8f9f7 3345 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3346 }
<> 144:ef7eb2e8f9f7 3347 }
<> 156:95d6b41a828b 3348 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3349
<> 144:ef7eb2e8f9f7 3350 /**
<> 144:ef7eb2e8f9f7 3351 * @brief Manage the receive 8-bit in Interrupt context.
Anna Bridge 180:96ed750bd169 3352 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3353 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3354 * @retval None
<> 144:ef7eb2e8f9f7 3355 */
<> 144:ef7eb2e8f9f7 3356 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3357 {
<> 144:ef7eb2e8f9f7 3358 *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
<> 144:ef7eb2e8f9f7 3359 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 3360
<> 156:95d6b41a828b 3361 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3362 /* Enable CRC Transmission */
<> 156:95d6b41a828b 3363 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 3364 {
<> 156:95d6b41a828b 3365 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 3366 }
<> 156:95d6b41a828b 3367 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 3368
<> 156:95d6b41a828b 3369 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3370 {
<> 156:95d6b41a828b 3371 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3372 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3373 {
<> 144:ef7eb2e8f9f7 3374 hspi->RxISR = SPI_RxISR_8BITCRC;
<> 144:ef7eb2e8f9f7 3375 return;
<> 144:ef7eb2e8f9f7 3376 }
<> 156:95d6b41a828b 3377 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3378 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3379 }
<> 144:ef7eb2e8f9f7 3380 }
<> 144:ef7eb2e8f9f7 3381
<> 156:95d6b41a828b 3382 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3383 /**
<> 144:ef7eb2e8f9f7 3384 * @brief Manage the CRC 16-bit receive in Interrupt context.
Anna Bridge 180:96ed750bd169 3385 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3386 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3387 * @retval None
<> 144:ef7eb2e8f9f7 3388 */
<> 144:ef7eb2e8f9f7 3389 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3390 {
<> 156:95d6b41a828b 3391 __IO uint16_t tmpreg = 0U;
<> 156:95d6b41a828b 3392
<> 156:95d6b41a828b 3393 /* Read data register to flush CRC */
<> 144:ef7eb2e8f9f7 3394 tmpreg = hspi->Instance->DR;
<> 156:95d6b41a828b 3395
<> 144:ef7eb2e8f9f7 3396 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 3397 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 3398
<> 144:ef7eb2e8f9f7 3399 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 3400 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 3401
<> 144:ef7eb2e8f9f7 3402 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3403 }
<> 156:95d6b41a828b 3404 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3405
<> 144:ef7eb2e8f9f7 3406 /**
<> 144:ef7eb2e8f9f7 3407 * @brief Manage the 16-bit receive in Interrupt context.
Anna Bridge 180:96ed750bd169 3408 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3409 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3410 * @retval None
<> 144:ef7eb2e8f9f7 3411 */
<> 144:ef7eb2e8f9f7 3412 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3413 {
<> 144:ef7eb2e8f9f7 3414 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
<> 144:ef7eb2e8f9f7 3415 hspi->pRxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 3416 hspi->RxXferCount--;
<> 144:ef7eb2e8f9f7 3417
<> 156:95d6b41a828b 3418 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3419 /* Enable CRC Transmission */
<> 156:95d6b41a828b 3420 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 3421 {
<> 156:95d6b41a828b 3422 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 3423 }
<> 156:95d6b41a828b 3424 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 3425
<> 156:95d6b41a828b 3426 if (hspi->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3427 {
<> 156:95d6b41a828b 3428 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3429 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3430 {
<> 144:ef7eb2e8f9f7 3431 hspi->RxISR = SPI_RxISR_16BITCRC;
<> 144:ef7eb2e8f9f7 3432 return;
<> 144:ef7eb2e8f9f7 3433 }
<> 156:95d6b41a828b 3434 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3435 SPI_CloseRx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3436 }
<> 144:ef7eb2e8f9f7 3437 }
<> 144:ef7eb2e8f9f7 3438
<> 144:ef7eb2e8f9f7 3439 /**
<> 144:ef7eb2e8f9f7 3440 * @brief Handle the data 8-bit transmit in Interrupt mode.
Anna Bridge 180:96ed750bd169 3441 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3442 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3443 * @retval None
<> 144:ef7eb2e8f9f7 3444 */
<> 144:ef7eb2e8f9f7 3445 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3446 {
<> 144:ef7eb2e8f9f7 3447 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 3448 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 3449
<> 156:95d6b41a828b 3450 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3451 {
<> 156:95d6b41a828b 3452 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3453 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3454 {
<> 144:ef7eb2e8f9f7 3455 /* Enable CRC Transmission */
<> 156:95d6b41a828b 3456 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 3457 }
<> 156:95d6b41a828b 3458 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3459 SPI_CloseTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3460 }
<> 144:ef7eb2e8f9f7 3461 }
<> 144:ef7eb2e8f9f7 3462
<> 144:ef7eb2e8f9f7 3463 /**
<> 144:ef7eb2e8f9f7 3464 * @brief Handle the data 16-bit transmit in Interrupt mode.
Anna Bridge 180:96ed750bd169 3465 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3466 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3467 * @retval None
<> 144:ef7eb2e8f9f7 3468 */
<> 144:ef7eb2e8f9f7 3469 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3470 {
<> 144:ef7eb2e8f9f7 3471 /* Transmit data in 16 Bit mode */
<> 144:ef7eb2e8f9f7 3472 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
<> 144:ef7eb2e8f9f7 3473 hspi->pTxBuffPtr += sizeof(uint16_t);
<> 144:ef7eb2e8f9f7 3474 hspi->TxXferCount--;
<> 144:ef7eb2e8f9f7 3475
<> 156:95d6b41a828b 3476 if (hspi->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 3477 {
<> 156:95d6b41a828b 3478 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3479 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3480 {
<> 144:ef7eb2e8f9f7 3481 /* Enable CRC Transmission */
<> 156:95d6b41a828b 3482 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
<> 144:ef7eb2e8f9f7 3483 }
<> 156:95d6b41a828b 3484 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3485 SPI_CloseTx_ISR(hspi);
<> 144:ef7eb2e8f9f7 3486 }
<> 144:ef7eb2e8f9f7 3487 }
<> 144:ef7eb2e8f9f7 3488
<> 144:ef7eb2e8f9f7 3489 /**
<> 144:ef7eb2e8f9f7 3490 * @brief Handle SPI Communication Timeout.
Anna Bridge 180:96ed750bd169 3491 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 156:95d6b41a828b 3492 * the configuration information for SPI module.
Anna Bridge 180:96ed750bd169 3493 * @param Flag SPI flag to check
Anna Bridge 180:96ed750bd169 3494 * @param State flag state to check
Anna Bridge 180:96ed750bd169 3495 * @param Timeout Timeout duration
Anna Bridge 180:96ed750bd169 3496 * @param Tickstart tick start value
<> 144:ef7eb2e8f9f7 3497 * @retval HAL status
<> 144:ef7eb2e8f9f7 3498 */
<> 156:95d6b41a828b 3499 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
<> 156:95d6b41a828b 3500 uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 3501 {
<> 156:95d6b41a828b 3502 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
<> 144:ef7eb2e8f9f7 3503 {
<> 156:95d6b41a828b 3504 if (Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 3505 {
<> 156:95d6b41a828b 3506 if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
<> 144:ef7eb2e8f9f7 3507 {
<> 144:ef7eb2e8f9f7 3508 /* Disable the SPI and reset the CRC: the CRC value should be cleared
<> 144:ef7eb2e8f9f7 3509 on both master and slave sides in order to resynchronize the master
<> 144:ef7eb2e8f9f7 3510 and slave for their respective CRC calculation */
<> 144:ef7eb2e8f9f7 3511
<> 144:ef7eb2e8f9f7 3512 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 3513 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 3514
<> 156:95d6b41a828b 3515 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 156:95d6b41a828b 3516 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 3517 {
<> 144:ef7eb2e8f9f7 3518 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 3519 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 3520 }
<> 144:ef7eb2e8f9f7 3521
<> 144:ef7eb2e8f9f7 3522 /* Reset CRC Calculation */
<> 156:95d6b41a828b 3523 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3524 {
<> 144:ef7eb2e8f9f7 3525 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 3526 }
<> 144:ef7eb2e8f9f7 3527
<> 156:95d6b41a828b 3528 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 3529
<> 144:ef7eb2e8f9f7 3530 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3531 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 3532
<> 144:ef7eb2e8f9f7 3533 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3534 }
<> 144:ef7eb2e8f9f7 3535 }
<> 144:ef7eb2e8f9f7 3536 }
<> 144:ef7eb2e8f9f7 3537
<> 144:ef7eb2e8f9f7 3538 return HAL_OK;
<> 144:ef7eb2e8f9f7 3539 }
<> 144:ef7eb2e8f9f7 3540
<> 144:ef7eb2e8f9f7 3541 /**
<> 144:ef7eb2e8f9f7 3542 * @brief Handle SPI FIFO Communication Timeout.
Anna Bridge 180:96ed750bd169 3543 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 156:95d6b41a828b 3544 * the configuration information for SPI module.
Anna Bridge 180:96ed750bd169 3545 * @param Fifo Fifo to check
Anna Bridge 180:96ed750bd169 3546 * @param State Fifo state to check
Anna Bridge 180:96ed750bd169 3547 * @param Timeout Timeout duration
Anna Bridge 180:96ed750bd169 3548 * @param Tickstart tick start value
<> 144:ef7eb2e8f9f7 3549 * @retval HAL status
<> 144:ef7eb2e8f9f7 3550 */
<> 156:95d6b41a828b 3551 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
<> 156:95d6b41a828b 3552 uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 3553 {
<> 144:ef7eb2e8f9f7 3554 __IO uint8_t tmpreg;
<> 156:95d6b41a828b 3555
<> 156:95d6b41a828b 3556 while ((hspi->Instance->SR & Fifo) != State)
<> 144:ef7eb2e8f9f7 3557 {
<> 156:95d6b41a828b 3558 if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
<> 144:ef7eb2e8f9f7 3559 {
<> 156:95d6b41a828b 3560 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
<> 144:ef7eb2e8f9f7 3561 /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 3562 UNUSED(tmpreg);
<> 144:ef7eb2e8f9f7 3563 }
<> 144:ef7eb2e8f9f7 3564
<> 156:95d6b41a828b 3565 if (Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 3566 {
<> 156:95d6b41a828b 3567 if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
<> 144:ef7eb2e8f9f7 3568 {
<> 144:ef7eb2e8f9f7 3569 /* Disable the SPI and reset the CRC: the CRC value should be cleared
<> 144:ef7eb2e8f9f7 3570 on both master and slave sides in order to resynchronize the master
<> 144:ef7eb2e8f9f7 3571 and slave for their respective CRC calculation */
<> 144:ef7eb2e8f9f7 3572
<> 144:ef7eb2e8f9f7 3573 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 3574 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 3575
<> 156:95d6b41a828b 3576 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 156:95d6b41a828b 3577 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 3578 {
<> 144:ef7eb2e8f9f7 3579 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 3580 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 3581 }
<> 144:ef7eb2e8f9f7 3582
<> 144:ef7eb2e8f9f7 3583 /* Reset CRC Calculation */
<> 156:95d6b41a828b 3584 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
<> 144:ef7eb2e8f9f7 3585 {
<> 144:ef7eb2e8f9f7 3586 SPI_RESET_CRC(hspi);
<> 144:ef7eb2e8f9f7 3587 }
<> 144:ef7eb2e8f9f7 3588
<> 144:ef7eb2e8f9f7 3589 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 3590
<> 144:ef7eb2e8f9f7 3591 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3592 __HAL_UNLOCK(hspi);
<> 144:ef7eb2e8f9f7 3593
<> 144:ef7eb2e8f9f7 3594 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3595 }
<> 144:ef7eb2e8f9f7 3596 }
<> 144:ef7eb2e8f9f7 3597 }
<> 144:ef7eb2e8f9f7 3598
<> 144:ef7eb2e8f9f7 3599 return HAL_OK;
<> 144:ef7eb2e8f9f7 3600 }
<> 144:ef7eb2e8f9f7 3601
<> 144:ef7eb2e8f9f7 3602 /**
<> 144:ef7eb2e8f9f7 3603 * @brief Handle the check of the RX transaction complete.
Anna Bridge 180:96ed750bd169 3604 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3605 * the configuration information for SPI module.
Anna Bridge 180:96ed750bd169 3606 * @param Timeout Timeout duration
Anna Bridge 180:96ed750bd169 3607 * @param Tickstart tick start value
<> 156:95d6b41a828b 3608 * @retval HAL status
<> 144:ef7eb2e8f9f7 3609 */
<> 156:95d6b41a828b 3610 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 3611 {
<> 156:95d6b41a828b 3612 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 156:95d6b41a828b 3613 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 3614 {
<> 144:ef7eb2e8f9f7 3615 /* Disable SPI peripheral */
<> 144:ef7eb2e8f9f7 3616 __HAL_SPI_DISABLE(hspi);
<> 144:ef7eb2e8f9f7 3617 }
<> 156:95d6b41a828b 3618
<> 144:ef7eb2e8f9f7 3619 /* Control the BSY flag */
<> 156:95d6b41a828b 3620 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3621 {
<> 156:95d6b41a828b 3622 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3623 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3624 }
<> 144:ef7eb2e8f9f7 3625
<> 156:95d6b41a828b 3626 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
<> 156:95d6b41a828b 3627 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
<> 144:ef7eb2e8f9f7 3628 {
<> 144:ef7eb2e8f9f7 3629 /* Empty the FRLVL fifo */
<> 156:95d6b41a828b 3630 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3631 {
<> 156:95d6b41a828b 3632 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3633 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3634 }
<> 144:ef7eb2e8f9f7 3635 }
<> 144:ef7eb2e8f9f7 3636 return HAL_OK;
<> 144:ef7eb2e8f9f7 3637 }
<> 144:ef7eb2e8f9f7 3638
<> 144:ef7eb2e8f9f7 3639 /**
<> 156:95d6b41a828b 3640 * @brief Handle the check of the RXTX or TX transaction complete.
Anna Bridge 180:96ed750bd169 3641 * @param hspi SPI handle
Anna Bridge 180:96ed750bd169 3642 * @param Timeout Timeout duration
Anna Bridge 180:96ed750bd169 3643 * @param Tickstart tick start value
<> 156:95d6b41a828b 3644 * @retval HAL status
<> 144:ef7eb2e8f9f7 3645 */
<> 156:95d6b41a828b 3646 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 3647 {
<> 144:ef7eb2e8f9f7 3648 /* Control if the TX fifo is empty */
<> 156:95d6b41a828b 3649 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3650 {
<> 156:95d6b41a828b 3651 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3652 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3653 }
Anna Bridge 180:96ed750bd169 3654
<> 144:ef7eb2e8f9f7 3655 /* Control the BSY flag */
<> 156:95d6b41a828b 3656 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3657 {
<> 156:95d6b41a828b 3658 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3659 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3660 }
Anna Bridge 180:96ed750bd169 3661
Anna Bridge 180:96ed750bd169 3662 /* Control if the RX fifo is empty */
Anna Bridge 180:96ed750bd169 3663 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
Anna Bridge 180:96ed750bd169 3664 {
Anna Bridge 180:96ed750bd169 3665 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
Anna Bridge 180:96ed750bd169 3666 return HAL_TIMEOUT;
Anna Bridge 180:96ed750bd169 3667 }
<> 144:ef7eb2e8f9f7 3668 return HAL_OK;
<> 144:ef7eb2e8f9f7 3669 }
<> 144:ef7eb2e8f9f7 3670
<> 144:ef7eb2e8f9f7 3671 /**
<> 144:ef7eb2e8f9f7 3672 * @brief Handle the end of the RXTX transaction.
Anna Bridge 180:96ed750bd169 3673 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3674 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3675 * @retval None
<> 144:ef7eb2e8f9f7 3676 */
<> 144:ef7eb2e8f9f7 3677 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3678 {
<> 156:95d6b41a828b 3679 uint32_t tickstart = 0U;
<> 156:95d6b41a828b 3680
<> 156:95d6b41a828b 3681 /* Init tickstart for timeout managment*/
<> 156:95d6b41a828b 3682 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 3683
<> 144:ef7eb2e8f9f7 3684 /* Disable ERR interrupt */
<> 144:ef7eb2e8f9f7 3685 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
<> 144:ef7eb2e8f9f7 3686
<> 144:ef7eb2e8f9f7 3687 /* Check the end of the transaction */
<> 156:95d6b41a828b 3688 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3689 {
<> 156:95d6b41a828b 3690 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3691 }
<> 144:ef7eb2e8f9f7 3692
<> 156:95d6b41a828b 3693 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3694 /* Check if CRC error occurred */
<> 156:95d6b41a828b 3695 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 144:ef7eb2e8f9f7 3696 {
<> 144:ef7eb2e8f9f7 3697 hspi->State = HAL_SPI_STATE_READY;
<> 156:95d6b41a828b 3698 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 144:ef7eb2e8f9f7 3699 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 144:ef7eb2e8f9f7 3700 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 3701 }
<> 144:ef7eb2e8f9f7 3702 else
<> 144:ef7eb2e8f9f7 3703 {
<> 156:95d6b41a828b 3704 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 3705 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 3706 {
<> 156:95d6b41a828b 3707 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 3708 {
<> 144:ef7eb2e8f9f7 3709 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 3710 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 3711 }
<> 144:ef7eb2e8f9f7 3712 else
<> 144:ef7eb2e8f9f7 3713 {
<> 144:ef7eb2e8f9f7 3714 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 3715 HAL_SPI_TxRxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 3716 }
<> 144:ef7eb2e8f9f7 3717 }
<> 144:ef7eb2e8f9f7 3718 else
<> 144:ef7eb2e8f9f7 3719 {
<> 144:ef7eb2e8f9f7 3720 hspi->State = HAL_SPI_STATE_READY;
<> 144:ef7eb2e8f9f7 3721 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 3722 }
<> 156:95d6b41a828b 3723 #if (USE_SPI_CRC != 0U)
<> 144:ef7eb2e8f9f7 3724 }
<> 156:95d6b41a828b 3725 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3726 }
<> 144:ef7eb2e8f9f7 3727
<> 144:ef7eb2e8f9f7 3728 /**
<> 144:ef7eb2e8f9f7 3729 * @brief Handle the end of the RX transaction.
Anna Bridge 180:96ed750bd169 3730 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3731 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3732 * @retval None
<> 144:ef7eb2e8f9f7 3733 */
<> 144:ef7eb2e8f9f7 3734 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3735 {
<> 156:95d6b41a828b 3736 /* Disable RXNE and ERR interrupt */
<> 156:95d6b41a828b 3737 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
<> 156:95d6b41a828b 3738
<> 156:95d6b41a828b 3739 /* Check the end of the transaction */
<> 156:95d6b41a828b 3740 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 3741 {
<> 156:95d6b41a828b 3742 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 156:95d6b41a828b 3743 }
<> 156:95d6b41a828b 3744 hspi->State = HAL_SPI_STATE_READY;
<> 156:95d6b41a828b 3745
<> 156:95d6b41a828b 3746 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3747 /* Check if CRC error occurred */
<> 156:95d6b41a828b 3748 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
<> 156:95d6b41a828b 3749 {
<> 156:95d6b41a828b 3750 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
<> 156:95d6b41a828b 3751 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
<> 156:95d6b41a828b 3752 HAL_SPI_ErrorCallback(hspi);
<> 156:95d6b41a828b 3753 }
<> 156:95d6b41a828b 3754 else
<> 156:95d6b41a828b 3755 {
<> 156:95d6b41a828b 3756 #endif /* USE_SPI_CRC */
<> 156:95d6b41a828b 3757 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 3758 {
<> 156:95d6b41a828b 3759 HAL_SPI_RxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 3760 }
<> 144:ef7eb2e8f9f7 3761 else
<> 144:ef7eb2e8f9f7 3762 {
<> 156:95d6b41a828b 3763 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 3764 }
<> 156:95d6b41a828b 3765 #if (USE_SPI_CRC != 0U)
<> 156:95d6b41a828b 3766 }
<> 156:95d6b41a828b 3767 #endif /* USE_SPI_CRC */
<> 144:ef7eb2e8f9f7 3768 }
<> 144:ef7eb2e8f9f7 3769
<> 144:ef7eb2e8f9f7 3770 /**
<> 144:ef7eb2e8f9f7 3771 * @brief Handle the end of the TX transaction.
Anna Bridge 180:96ed750bd169 3772 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3773 * the configuration information for SPI module.
<> 144:ef7eb2e8f9f7 3774 * @retval None
<> 144:ef7eb2e8f9f7 3775 */
<> 144:ef7eb2e8f9f7 3776 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
<> 144:ef7eb2e8f9f7 3777 {
<> 156:95d6b41a828b 3778 uint32_t tickstart = 0U;
<> 156:95d6b41a828b 3779
<> 156:95d6b41a828b 3780 /* Init tickstart for timeout management*/
<> 156:95d6b41a828b 3781 tickstart = HAL_GetTick();
<> 156:95d6b41a828b 3782
<> 144:ef7eb2e8f9f7 3783 /* Disable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 3784 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
<> 144:ef7eb2e8f9f7 3785
<> 144:ef7eb2e8f9f7 3786 /* Check the end of the transaction */
<> 156:95d6b41a828b 3787 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3788 {
<> 156:95d6b41a828b 3789 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
<> 144:ef7eb2e8f9f7 3790 }
<> 144:ef7eb2e8f9f7 3791
<> 144:ef7eb2e8f9f7 3792 /* Clear overrun flag in 2 Lines communication mode because received is not read */
<> 156:95d6b41a828b 3793 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 3794 {
<> 144:ef7eb2e8f9f7 3795 __HAL_SPI_CLEAR_OVRFLAG(hspi);
<> 144:ef7eb2e8f9f7 3796 }
<> 144:ef7eb2e8f9f7 3797
<> 144:ef7eb2e8f9f7 3798 hspi->State = HAL_SPI_STATE_READY;
<> 156:95d6b41a828b 3799 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
<> 144:ef7eb2e8f9f7 3800 {
<> 144:ef7eb2e8f9f7 3801 HAL_SPI_ErrorCallback(hspi);
<> 144:ef7eb2e8f9f7 3802 }
<> 144:ef7eb2e8f9f7 3803 else
<> 144:ef7eb2e8f9f7 3804 {
<> 144:ef7eb2e8f9f7 3805 HAL_SPI_TxCpltCallback(hspi);
<> 144:ef7eb2e8f9f7 3806 }
<> 144:ef7eb2e8f9f7 3807 }
<> 144:ef7eb2e8f9f7 3808
<> 144:ef7eb2e8f9f7 3809 /**
<> 156:95d6b41a828b 3810 * @brief Handle abort a Rx transaction.
Anna Bridge 180:96ed750bd169 3811 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 156:95d6b41a828b 3812 * the configuration information for SPI module.
<> 156:95d6b41a828b 3813 * @retval None
<> 156:95d6b41a828b 3814 */
<> 156:95d6b41a828b 3815 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
<> 156:95d6b41a828b 3816 {
Anna Bridge 180:96ed750bd169 3817 __IO uint32_t count;
Anna Bridge 180:96ed750bd169 3818
<> 156:95d6b41a828b 3819 /* Disable SPI Peripheral */
<> 156:95d6b41a828b 3820 __HAL_SPI_DISABLE(hspi);
<> 156:95d6b41a828b 3821
Anna Bridge 180:96ed750bd169 3822 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
Anna Bridge 180:96ed750bd169 3823
<> 156:95d6b41a828b 3824 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
<> 156:95d6b41a828b 3825 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
<> 156:95d6b41a828b 3826
Anna Bridge 180:96ed750bd169 3827 /* Check RXNEIE is disabled */
Anna Bridge 180:96ed750bd169 3828 do
<> 156:95d6b41a828b 3829 {
Anna Bridge 180:96ed750bd169 3830 if (count-- == 0U)
Anna Bridge 180:96ed750bd169 3831 {
Anna Bridge 180:96ed750bd169 3832 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
Anna Bridge 180:96ed750bd169 3833 break;
Anna Bridge 180:96ed750bd169 3834 }
<> 156:95d6b41a828b 3835 }
Anna Bridge 180:96ed750bd169 3836 while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
<> 156:95d6b41a828b 3837
<> 156:95d6b41a828b 3838 /* Control the BSY flag */
<> 156:95d6b41a828b 3839 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 3840 {
<> 156:95d6b41a828b 3841 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 3842 }
<> 156:95d6b41a828b 3843
<> 156:95d6b41a828b 3844 /* Empty the FRLVL fifo */
<> 156:95d6b41a828b 3845 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 3846 {
<> 156:95d6b41a828b 3847 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 3848 }
<> 156:95d6b41a828b 3849
<> 156:95d6b41a828b 3850 hspi->State = HAL_SPI_STATE_ABORT;
<> 156:95d6b41a828b 3851 }
<> 156:95d6b41a828b 3852
<> 156:95d6b41a828b 3853 /**
<> 156:95d6b41a828b 3854 * @brief Handle abort a Tx or Rx/Tx transaction.
Anna Bridge 180:96ed750bd169 3855 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
<> 156:95d6b41a828b 3856 * the configuration information for SPI module.
<> 156:95d6b41a828b 3857 * @retval None
<> 156:95d6b41a828b 3858 */
<> 156:95d6b41a828b 3859 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
<> 156:95d6b41a828b 3860 {
Anna Bridge 180:96ed750bd169 3861 __IO uint32_t count;
Anna Bridge 180:96ed750bd169 3862
Anna Bridge 180:96ed750bd169 3863 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
Anna Bridge 180:96ed750bd169 3864
<> 156:95d6b41a828b 3865 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
<> 156:95d6b41a828b 3866 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
<> 156:95d6b41a828b 3867
Anna Bridge 180:96ed750bd169 3868 /* Check TXEIE is disabled */
Anna Bridge 180:96ed750bd169 3869 do
<> 156:95d6b41a828b 3870 {
Anna Bridge 180:96ed750bd169 3871 if (count-- == 0U)
Anna Bridge 180:96ed750bd169 3872 {
Anna Bridge 180:96ed750bd169 3873 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
Anna Bridge 180:96ed750bd169 3874 break;
Anna Bridge 180:96ed750bd169 3875 }
<> 156:95d6b41a828b 3876 }
Anna Bridge 180:96ed750bd169 3877 while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
<> 156:95d6b41a828b 3878
<> 156:95d6b41a828b 3879 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 3880 {
<> 156:95d6b41a828b 3881 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 3882 }
<> 156:95d6b41a828b 3883
<> 156:95d6b41a828b 3884 /* Disable SPI Peripheral */
<> 156:95d6b41a828b 3885 __HAL_SPI_DISABLE(hspi);
<> 156:95d6b41a828b 3886
<> 156:95d6b41a828b 3887 /* Empty the FRLVL fifo */
<> 156:95d6b41a828b 3888 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
<> 156:95d6b41a828b 3889 {
<> 156:95d6b41a828b 3890 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
<> 156:95d6b41a828b 3891 }
<> 156:95d6b41a828b 3892
<> 156:95d6b41a828b 3893 hspi->State = HAL_SPI_STATE_ABORT;
<> 156:95d6b41a828b 3894 }
<> 156:95d6b41a828b 3895
<> 156:95d6b41a828b 3896 /**
<> 144:ef7eb2e8f9f7 3897 * @}
<> 144:ef7eb2e8f9f7 3898 */
<> 144:ef7eb2e8f9f7 3899
<> 144:ef7eb2e8f9f7 3900 #endif /* HAL_SPI_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 3901
<> 144:ef7eb2e8f9f7 3902 /**
<> 144:ef7eb2e8f9f7 3903 * @}
<> 144:ef7eb2e8f9f7 3904 */
<> 144:ef7eb2e8f9f7 3905
<> 144:ef7eb2e8f9f7 3906 /**
<> 144:ef7eb2e8f9f7 3907 * @}
<> 144:ef7eb2e8f9f7 3908 */
<> 144:ef7eb2e8f9f7 3909
<> 144:ef7eb2e8f9f7 3910 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/