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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_rcc.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of RCC HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F0xx_HAL_RCC_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F0xx_HAL_RCC_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup RCC
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @addtogroup RCC_Private_Constants
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @defgroup RCC_Timeout RCC Timeout
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /* Disable Backup domain write protection state change timeout */
<> 156:95d6b41a828b 64 #define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
<> 144:ef7eb2e8f9f7 65 /* LSE state change timeout */
<> 144:ef7eb2e8f9f7 66 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
<> 156:95d6b41a828b 67 #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
<> 144:ef7eb2e8f9f7 68 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Anna Bridge 180:96ed750bd169 69 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
Anna Bridge 180:96ed750bd169 70 #define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
Anna Bridge 180:96ed750bd169 71 #define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
Anna Bridge 180:96ed750bd169 72 #define HSI14_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
<> 144:ef7eb2e8f9f7 73 #if defined(RCC_HSI48_SUPPORT)
Anna Bridge 180:96ed750bd169 74 #define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
<> 144:ef7eb2e8f9f7 75 #endif /* RCC_HSI48_SUPPORT */
<> 144:ef7eb2e8f9f7 76 /**
<> 144:ef7eb2e8f9f7 77 * @}
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /** @defgroup RCC_Register_Offset Register offsets
<> 144:ef7eb2e8f9f7 81 * @{
<> 144:ef7eb2e8f9f7 82 */
<> 144:ef7eb2e8f9f7 83 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Anna Bridge 180:96ed750bd169 84 #define RCC_CR_OFFSET 0x00
Anna Bridge 180:96ed750bd169 85 #define RCC_CFGR_OFFSET 0x04
Anna Bridge 180:96ed750bd169 86 #define RCC_CIR_OFFSET 0x08
Anna Bridge 180:96ed750bd169 87 #define RCC_BDCR_OFFSET 0x20
Anna Bridge 180:96ed750bd169 88 #define RCC_CSR_OFFSET 0x24
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /**
<> 144:ef7eb2e8f9f7 91 * @}
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /* CR register byte 2 (Bits[23:16]) base address */
<> 156:95d6b41a828b 96 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /* CIR register byte 1 (Bits[15:8]) base address */
<> 156:95d6b41a828b 99 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /* CIR register byte 2 (Bits[23:16]) base address */
<> 156:95d6b41a828b 102 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /* Defines used for Flags */
<> 156:95d6b41a828b 105 #define CR_REG_INDEX ((uint8_t)1U)
<> 156:95d6b41a828b 106 #define CR2_REG_INDEX ((uint8_t)2U)
<> 156:95d6b41a828b 107 #define BDCR_REG_INDEX ((uint8_t)3U)
<> 156:95d6b41a828b 108 #define CSR_REG_INDEX ((uint8_t)4U)
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /* Bits position in in the CFGR register */
<> 144:ef7eb2e8f9f7 111 #define RCC_CFGR_PLLMUL_BITNUMBER 18U
<> 144:ef7eb2e8f9f7 112 #define RCC_CFGR_HPRE_BITNUMBER 4U
<> 144:ef7eb2e8f9f7 113 #define RCC_CFGR_PPRE_BITNUMBER 8U
<> 144:ef7eb2e8f9f7 114 /* Flags in the CFGR2 register */
Anna Bridge 180:96ed750bd169 115 #define RCC_CFGR2_PREDIV_BITNUMBER 0
<> 144:ef7eb2e8f9f7 116 /* Flags in the CR register */
Anna Bridge 180:96ed750bd169 117 #define RCC_CR_HSIRDY_BitNumber 1
Anna Bridge 180:96ed750bd169 118 #define RCC_CR_HSERDY_BitNumber 17
Anna Bridge 180:96ed750bd169 119 #define RCC_CR_PLLRDY_BitNumber 25
<> 144:ef7eb2e8f9f7 120 /* Flags in the CR2 register */
Anna Bridge 180:96ed750bd169 121 #define RCC_CR2_HSI14RDY_BitNumber 1
Anna Bridge 180:96ed750bd169 122 #define RCC_CR2_HSI48RDY_BitNumber 16
<> 144:ef7eb2e8f9f7 123 /* Flags in the BDCR register */
Anna Bridge 180:96ed750bd169 124 #define RCC_BDCR_LSERDY_BitNumber 1
<> 144:ef7eb2e8f9f7 125 /* Flags in the CSR register */
Anna Bridge 180:96ed750bd169 126 #define RCC_CSR_LSIRDY_BitNumber 1
Anna Bridge 180:96ed750bd169 127 #define RCC_CSR_V18PWRRSTF_BitNumber 23
Anna Bridge 180:96ed750bd169 128 #define RCC_CSR_RMVF_BitNumber 24
Anna Bridge 180:96ed750bd169 129 #define RCC_CSR_OBLRSTF_BitNumber 25
Anna Bridge 180:96ed750bd169 130 #define RCC_CSR_PINRSTF_BitNumber 26
Anna Bridge 180:96ed750bd169 131 #define RCC_CSR_PORRSTF_BitNumber 27
Anna Bridge 180:96ed750bd169 132 #define RCC_CSR_SFTRSTF_BitNumber 28
Anna Bridge 180:96ed750bd169 133 #define RCC_CSR_IWDGRSTF_BitNumber 29
Anna Bridge 180:96ed750bd169 134 #define RCC_CSR_WWDGRSTF_BitNumber 30
Anna Bridge 180:96ed750bd169 135 #define RCC_CSR_LPWRRSTF_BitNumber 31
<> 144:ef7eb2e8f9f7 136 /* Flags in the HSITRIM register */
Anna Bridge 180:96ed750bd169 137 #define RCC_CR_HSITRIM_BitNumber 3
Anna Bridge 180:96ed750bd169 138 #define RCC_HSI14TRIM_BIT_NUMBER 3
<> 156:95d6b41a828b 139 #define RCC_FLAG_MASK ((uint8_t)0x1FU)
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /**
<> 144:ef7eb2e8f9f7 142 * @}
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /** @addtogroup RCC_Private_Macros
<> 144:ef7eb2e8f9f7 146 * @{
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
<> 144:ef7eb2e8f9f7 149 ((__HSE__) == RCC_HSE_BYPASS))
<> 144:ef7eb2e8f9f7 150 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
<> 144:ef7eb2e8f9f7 151 ((__LSE__) == RCC_LSE_BYPASS))
<> 144:ef7eb2e8f9f7 152 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
<> 144:ef7eb2e8f9f7 153 #define IS_RCC_HSI14(__HSI14__) (((__HSI14__) == RCC_HSI14_OFF) || ((__HSI14__) == RCC_HSI14_ON) || ((__HSI14__) == RCC_HSI14_ADC_CONTROL))
<> 156:95d6b41a828b 154 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
<> 144:ef7eb2e8f9f7 155 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
<> 144:ef7eb2e8f9f7 156 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
<> 144:ef7eb2e8f9f7 157 ((__PLL__) == RCC_PLL_ON))
<> 144:ef7eb2e8f9f7 158 #define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \
<> 144:ef7eb2e8f9f7 159 ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \
<> 144:ef7eb2e8f9f7 160 ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \
<> 144:ef7eb2e8f9f7 161 ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \
<> 144:ef7eb2e8f9f7 162 ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \
<> 144:ef7eb2e8f9f7 163 ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \
<> 144:ef7eb2e8f9f7 164 ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \
<> 144:ef7eb2e8f9f7 165 ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16))
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
<> 144:ef7eb2e8f9f7 168 ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
<> 144:ef7eb2e8f9f7 169 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
<> 144:ef7eb2e8f9f7 170 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
<> 144:ef7eb2e8f9f7 171 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
<> 144:ef7eb2e8f9f7 172 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
<> 144:ef7eb2e8f9f7 173 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
<> 144:ef7eb2e8f9f7 174 ((__MUL__) == RCC_PLL_MUL16))
<> 144:ef7eb2e8f9f7 175 #define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 176 (((__CLK__) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
<> 144:ef7eb2e8f9f7 177 (((__CLK__) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
<> 144:ef7eb2e8f9f7 178 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
<> 144:ef7eb2e8f9f7 179 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
<> 144:ef7eb2e8f9f7 180 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
<> 144:ef7eb2e8f9f7 181 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
<> 144:ef7eb2e8f9f7 182 ((__HCLK__) == RCC_SYSCLK_DIV512))
<> 144:ef7eb2e8f9f7 183 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
<> 144:ef7eb2e8f9f7 184 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
<> 144:ef7eb2e8f9f7 185 ((__PCLK__) == RCC_HCLK_DIV16))
<> 144:ef7eb2e8f9f7 186 #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
<> 144:ef7eb2e8f9f7 187 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
<> 144:ef7eb2e8f9f7 188 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 189 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
<> 144:ef7eb2e8f9f7 190 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
<> 144:ef7eb2e8f9f7 191 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \
<> 144:ef7eb2e8f9f7 192 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 193 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 194 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
<> 144:ef7eb2e8f9f7 195 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 196 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /**
<> 144:ef7eb2e8f9f7 199 * @}
<> 144:ef7eb2e8f9f7 200 */
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /** @defgroup RCC_Exported_Types RCC Exported Types
<> 144:ef7eb2e8f9f7 205 * @{
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /**
<> 144:ef7eb2e8f9f7 209 * @brief RCC PLL configuration structure definition
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211 typedef struct
<> 144:ef7eb2e8f9f7 212 {
<> 144:ef7eb2e8f9f7 213 uint32_t PLLState; /*!< PLLState: The new state of the PLL.
<> 144:ef7eb2e8f9f7 214 This parameter can be a value of @ref RCC_PLL_Config */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
<> 144:ef7eb2e8f9f7 217 This parameter must be a value of @ref RCC_PLL_Clock_Source */
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
<> 144:ef7eb2e8f9f7 220 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
<> 144:ef7eb2e8f9f7 223 This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 } RCC_PLLInitTypeDef;
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /**
<> 144:ef7eb2e8f9f7 228 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 typedef struct
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 uint32_t OscillatorType; /*!< The oscillators to be configured.
<> 144:ef7eb2e8f9f7 233 This parameter can be a value of @ref RCC_Oscillator_Type */
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 uint32_t HSEState; /*!< The new state of the HSE.
<> 144:ef7eb2e8f9f7 236 This parameter can be a value of @ref RCC_HSE_Config */
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 uint32_t LSEState; /*!< The new state of the LSE.
<> 144:ef7eb2e8f9f7 239 This parameter can be a value of @ref RCC_LSE_Config */
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 uint32_t HSIState; /*!< The new state of the HSI.
<> 144:ef7eb2e8f9f7 242 This parameter can be a value of @ref RCC_HSI_Config */
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
Anna Bridge 180:96ed750bd169 245 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 uint32_t HSI14State; /*!< The new state of the HSI14.
<> 144:ef7eb2e8f9f7 248 This parameter can be a value of @ref RCC_HSI14_Config */
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
Anna Bridge 180:96ed750bd169 251 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 uint32_t LSIState; /*!< The new state of the LSI.
<> 144:ef7eb2e8f9f7 254 This parameter can be a value of @ref RCC_LSI_Config */
<> 144:ef7eb2e8f9f7 255
Anna Bridge 180:96ed750bd169 256 #if defined(RCC_HSI48_SUPPORT)
<> 144:ef7eb2e8f9f7 257 uint32_t HSI48State; /*!< The new state of the HSI48.
<> 144:ef7eb2e8f9f7 258 This parameter can be a value of @ref RCC_HSI48_Config */
<> 144:ef7eb2e8f9f7 259
Anna Bridge 180:96ed750bd169 260 #endif /* RCC_HSI48_SUPPORT */
<> 144:ef7eb2e8f9f7 261 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 } RCC_OscInitTypeDef;
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /**
<> 144:ef7eb2e8f9f7 266 * @brief RCC System, AHB and APB busses clock configuration structure definition
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 typedef struct
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 uint32_t ClockType; /*!< The clock to be configured.
<> 144:ef7eb2e8f9f7 271 This parameter can be a value of @ref RCC_System_Clock_Type */
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
<> 144:ef7eb2e8f9f7 274 This parameter can be a value of @ref RCC_System_Clock_Source */
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
<> 144:ef7eb2e8f9f7 277 This parameter can be a value of @ref RCC_AHB_Clock_Source */
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
<> 144:ef7eb2e8f9f7 280 This parameter can be a value of @ref RCC_APB1_Clock_Source */
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 } RCC_ClkInitTypeDef;
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /**
<> 144:ef7eb2e8f9f7 285 * @}
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 289 /** @defgroup RCC_Exported_Constants RCC Exported Constants
<> 144:ef7eb2e8f9f7 290 * @{
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
<> 144:ef7eb2e8f9f7 294 * @{
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /**
<> 144:ef7eb2e8f9f7 300 * @}
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /** @defgroup RCC_Oscillator_Type Oscillator Type
<> 144:ef7eb2e8f9f7 304 * @{
<> 144:ef7eb2e8f9f7 305 */
<> 156:95d6b41a828b 306 #define RCC_OSCILLATORTYPE_NONE (0x00000000U)
<> 156:95d6b41a828b 307 #define RCC_OSCILLATORTYPE_HSE (0x00000001U)
<> 156:95d6b41a828b 308 #define RCC_OSCILLATORTYPE_HSI (0x00000002U)
<> 156:95d6b41a828b 309 #define RCC_OSCILLATORTYPE_LSE (0x00000004U)
<> 156:95d6b41a828b 310 #define RCC_OSCILLATORTYPE_LSI (0x00000008U)
<> 156:95d6b41a828b 311 #define RCC_OSCILLATORTYPE_HSI14 (0x00000010U)
<> 144:ef7eb2e8f9f7 312 #if defined(RCC_HSI48_SUPPORT)
<> 156:95d6b41a828b 313 #define RCC_OSCILLATORTYPE_HSI48 (0x00000020U)
<> 144:ef7eb2e8f9f7 314 #endif /* RCC_HSI48_SUPPORT */
<> 144:ef7eb2e8f9f7 315 /**
<> 144:ef7eb2e8f9f7 316 * @}
<> 144:ef7eb2e8f9f7 317 */
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /** @defgroup RCC_HSE_Config HSE Config
<> 144:ef7eb2e8f9f7 320 * @{
<> 144:ef7eb2e8f9f7 321 */
<> 156:95d6b41a828b 322 #define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */
<> 156:95d6b41a828b 323 #define RCC_HSE_ON (0x00000001U) /*!< HSE clock activation */
<> 156:95d6b41a828b 324 #define RCC_HSE_BYPASS (0x00000005U) /*!< External clock source for HSE clock */
<> 144:ef7eb2e8f9f7 325 /**
<> 144:ef7eb2e8f9f7 326 * @}
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /** @defgroup RCC_LSE_Config LSE Config
<> 144:ef7eb2e8f9f7 330 * @{
<> 144:ef7eb2e8f9f7 331 */
<> 156:95d6b41a828b 332 #define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */
<> 156:95d6b41a828b 333 #define RCC_LSE_ON (0x00000001U) /*!< LSE clock activation */
<> 156:95d6b41a828b 334 #define RCC_LSE_BYPASS (0x00000005U) /*!< External clock source for LSE clock */
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /**
<> 144:ef7eb2e8f9f7 337 * @}
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /** @defgroup RCC_HSI_Config HSI Config
<> 144:ef7eb2e8f9f7 341 * @{
<> 144:ef7eb2e8f9f7 342 */
<> 156:95d6b41a828b 343 #define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */
<> 144:ef7eb2e8f9f7 344 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
<> 144:ef7eb2e8f9f7 345
<> 156:95d6b41a828b 346 #define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /**
<> 144:ef7eb2e8f9f7 349 * @}
<> 144:ef7eb2e8f9f7 350 */
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /** @defgroup RCC_HSI14_Config RCC HSI14 Config
<> 144:ef7eb2e8f9f7 353 * @{
<> 144:ef7eb2e8f9f7 354 */
Anna Bridge 180:96ed750bd169 355 #define RCC_HSI14_OFF (0x00000000U)
<> 144:ef7eb2e8f9f7 356 #define RCC_HSI14_ON RCC_CR2_HSI14ON
<> 144:ef7eb2e8f9f7 357 #define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS)
<> 144:ef7eb2e8f9f7 358
<> 156:95d6b41a828b 359 #define RCC_HSI14CALIBRATION_DEFAULT (0x10U) /* Default HSI14 calibration trimming value */
<> 144:ef7eb2e8f9f7 360 /**
<> 144:ef7eb2e8f9f7 361 * @}
<> 144:ef7eb2e8f9f7 362 */
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /** @defgroup RCC_LSI_Config LSI Config
<> 144:ef7eb2e8f9f7 365 * @{
<> 144:ef7eb2e8f9f7 366 */
<> 156:95d6b41a828b 367 #define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */
<> 144:ef7eb2e8f9f7 368 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /**
<> 144:ef7eb2e8f9f7 371 * @}
<> 144:ef7eb2e8f9f7 372 */
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 #if defined(RCC_HSI48_SUPPORT)
<> 144:ef7eb2e8f9f7 375 /** @defgroup RCC_HSI48_Config HSI48 Config
<> 144:ef7eb2e8f9f7 376 * @{
<> 144:ef7eb2e8f9f7 377 */
<> 156:95d6b41a828b 378 #define RCC_HSI48_OFF ((uint8_t)0x00U)
<> 156:95d6b41a828b 379 #define RCC_HSI48_ON ((uint8_t)0x01U)
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /**
<> 144:ef7eb2e8f9f7 382 * @}
<> 144:ef7eb2e8f9f7 383 */
<> 144:ef7eb2e8f9f7 384 #endif /* RCC_HSI48_SUPPORT */
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /** @defgroup RCC_PLL_Config PLL Config
<> 144:ef7eb2e8f9f7 387 * @{
<> 144:ef7eb2e8f9f7 388 */
<> 156:95d6b41a828b 389 #define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */
<> 156:95d6b41a828b 390 #define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */
<> 156:95d6b41a828b 391 #define RCC_PLL_ON (0x00000002U) /*!< PLL activation */
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /**
<> 144:ef7eb2e8f9f7 394 * @}
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /** @defgroup RCC_System_Clock_Type System Clock Type
<> 144:ef7eb2e8f9f7 398 * @{
<> 144:ef7eb2e8f9f7 399 */
<> 156:95d6b41a828b 400 #define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */
<> 156:95d6b41a828b 401 #define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */
<> 156:95d6b41a828b 402 #define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /**
<> 144:ef7eb2e8f9f7 405 * @}
<> 144:ef7eb2e8f9f7 406 */
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /** @defgroup RCC_System_Clock_Source System Clock Source
<> 144:ef7eb2e8f9f7 409 * @{
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
<> 144:ef7eb2e8f9f7 412 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
<> 144:ef7eb2e8f9f7 413 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /**
<> 144:ef7eb2e8f9f7 416 * @}
<> 144:ef7eb2e8f9f7 417 */
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
<> 144:ef7eb2e8f9f7 420 * @{
<> 144:ef7eb2e8f9f7 421 */
<> 144:ef7eb2e8f9f7 422 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
<> 144:ef7eb2e8f9f7 423 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
<> 144:ef7eb2e8f9f7 424 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /**
<> 144:ef7eb2e8f9f7 427 * @}
<> 144:ef7eb2e8f9f7 428 */
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
<> 144:ef7eb2e8f9f7 431 * @{
<> 144:ef7eb2e8f9f7 432 */
<> 144:ef7eb2e8f9f7 433 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
<> 144:ef7eb2e8f9f7 434 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
<> 144:ef7eb2e8f9f7 435 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
<> 144:ef7eb2e8f9f7 436 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
<> 144:ef7eb2e8f9f7 437 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
<> 144:ef7eb2e8f9f7 438 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
<> 144:ef7eb2e8f9f7 439 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
<> 144:ef7eb2e8f9f7 440 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
<> 144:ef7eb2e8f9f7 441 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /**
<> 144:ef7eb2e8f9f7 444 * @}
<> 144:ef7eb2e8f9f7 445 */
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
<> 144:ef7eb2e8f9f7 448 * @{
<> 144:ef7eb2e8f9f7 449 */
<> 144:ef7eb2e8f9f7 450 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1 /*!< HCLK not divided */
<> 144:ef7eb2e8f9f7 451 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2 /*!< HCLK divided by 2 */
<> 144:ef7eb2e8f9f7 452 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4 /*!< HCLK divided by 4 */
<> 144:ef7eb2e8f9f7 453 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8 /*!< HCLK divided by 8 */
<> 144:ef7eb2e8f9f7 454 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /**
<> 144:ef7eb2e8f9f7 457 * @}
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
<> 144:ef7eb2e8f9f7 461 * @{
<> 144:ef7eb2e8f9f7 462 */
<> 156:95d6b41a828b 463 #define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock */
<> 144:ef7eb2e8f9f7 464 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
<> 144:ef7eb2e8f9f7 465 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
<> 144:ef7eb2e8f9f7 466 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */
<> 144:ef7eb2e8f9f7 467 /**
<> 144:ef7eb2e8f9f7 468 * @}
<> 144:ef7eb2e8f9f7 469 */
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
<> 144:ef7eb2e8f9f7 472 * @{
<> 144:ef7eb2e8f9f7 473 */
<> 144:ef7eb2e8f9f7 474 #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
<> 144:ef7eb2e8f9f7 475 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
<> 144:ef7eb2e8f9f7 476 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
<> 144:ef7eb2e8f9f7 477 #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
<> 144:ef7eb2e8f9f7 478 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
<> 144:ef7eb2e8f9f7 479 #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
<> 144:ef7eb2e8f9f7 480 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
<> 144:ef7eb2e8f9f7 481 #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
<> 144:ef7eb2e8f9f7 482 #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
<> 144:ef7eb2e8f9f7 483 #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
<> 144:ef7eb2e8f9f7 484 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
<> 144:ef7eb2e8f9f7 485 #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
<> 144:ef7eb2e8f9f7 486 #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
<> 144:ef7eb2e8f9f7 487 #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
<> 144:ef7eb2e8f9f7 488 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /**
<> 144:ef7eb2e8f9f7 491 * @}
<> 144:ef7eb2e8f9f7 492 */
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
<> 144:ef7eb2e8f9f7 495 * @{
<> 144:ef7eb2e8f9f7 496 */
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 #define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
<> 144:ef7eb2e8f9f7 499 #define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
<> 144:ef7eb2e8f9f7 500 #define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
<> 144:ef7eb2e8f9f7 501 #define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
<> 144:ef7eb2e8f9f7 502 #define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
<> 144:ef7eb2e8f9f7 503 #define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
<> 144:ef7eb2e8f9f7 504 #define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
<> 144:ef7eb2e8f9f7 505 #define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
<> 144:ef7eb2e8f9f7 506 #define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
<> 144:ef7eb2e8f9f7 507 #define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
<> 144:ef7eb2e8f9f7 508 #define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
<> 144:ef7eb2e8f9f7 509 #define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
<> 144:ef7eb2e8f9f7 510 #define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
<> 144:ef7eb2e8f9f7 511 #define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
<> 144:ef7eb2e8f9f7 512 #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
<> 144:ef7eb2e8f9f7 513 #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /**
<> 144:ef7eb2e8f9f7 516 * @}
<> 144:ef7eb2e8f9f7 517 */
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source
<> 144:ef7eb2e8f9f7 521 * @{
<> 144:ef7eb2e8f9f7 522 */
<> 144:ef7eb2e8f9f7 523 #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
<> 144:ef7eb2e8f9f7 524 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
<> 144:ef7eb2e8f9f7 525 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
<> 144:ef7eb2e8f9f7 526 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /**
<> 144:ef7eb2e8f9f7 529 * @}
<> 144:ef7eb2e8f9f7 530 */
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
<> 144:ef7eb2e8f9f7 533 * @{
<> 144:ef7eb2e8f9f7 534 */
<> 144:ef7eb2e8f9f7 535 #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
<> 144:ef7eb2e8f9f7 536 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /**
<> 144:ef7eb2e8f9f7 539 * @}
<> 144:ef7eb2e8f9f7 540 */
<> 144:ef7eb2e8f9f7 541 /** @defgroup RCC_MCO_Index MCO Index
<> 144:ef7eb2e8f9f7 542 * @{
<> 144:ef7eb2e8f9f7 543 */
<> 156:95d6b41a828b 544 #define RCC_MCO1 (0x00000000U)
<> 144:ef7eb2e8f9f7 545 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /**
<> 144:ef7eb2e8f9f7 548 * @}
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source
<> 144:ef7eb2e8f9f7 552 * @{
<> 144:ef7eb2e8f9f7 553 */
<> 144:ef7eb2e8f9f7 554 #define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
<> 144:ef7eb2e8f9f7 555 #define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
<> 144:ef7eb2e8f9f7 556 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
<> 144:ef7eb2e8f9f7 557 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
<> 144:ef7eb2e8f9f7 558 #define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
<> 144:ef7eb2e8f9f7 559 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
<> 144:ef7eb2e8f9f7 560 #define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
<> 144:ef7eb2e8f9f7 561 #define RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCO_HSI14
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /**
<> 144:ef7eb2e8f9f7 564 * @}
<> 144:ef7eb2e8f9f7 565 */
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /** @defgroup RCC_Interrupt Interrupts
<> 144:ef7eb2e8f9f7 568 * @{
<> 144:ef7eb2e8f9f7 569 */
<> 144:ef7eb2e8f9f7 570 #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 571 #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 572 #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 573 #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 574 #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 575 #define RCC_IT_HSI14RDY ((uint8_t)RCC_CIR_HSI14RDYF) /*!< HSI14 Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 576 #if defined(RCC_CIR_HSI48RDYF)
<> 144:ef7eb2e8f9f7 577 #define RCC_IT_HSI48RDY ((uint8_t)RCC_CIR_HSI48RDYF) /*!< HSI48 Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 578 #endif
<> 144:ef7eb2e8f9f7 579 #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
<> 144:ef7eb2e8f9f7 580 /**
<> 144:ef7eb2e8f9f7 581 * @}
<> 144:ef7eb2e8f9f7 582 */
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /** @defgroup RCC_Flag Flags
<> 144:ef7eb2e8f9f7 585 * Elements values convention: XXXYYYYYb
<> 144:ef7eb2e8f9f7 586 * - YYYYY : Flag position in the register
<> 144:ef7eb2e8f9f7 587 * - XXX : Register index
<> 144:ef7eb2e8f9f7 588 * - 001: CR register
<> 144:ef7eb2e8f9f7 589 * - 010: CR2 register
<> 144:ef7eb2e8f9f7 590 * - 011: BDCR register
<> 144:ef7eb2e8f9f7 591 * - 0100: CSR register
<> 144:ef7eb2e8f9f7 592 * @{
<> 144:ef7eb2e8f9f7 593 */
<> 144:ef7eb2e8f9f7 594 /* Flags in the CR register */
<> 156:95d6b41a828b 595 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_BitNumber))
<> 156:95d6b41a828b 596 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_BitNumber))
<> 156:95d6b41a828b 597 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_BitNumber))
<> 144:ef7eb2e8f9f7 598 /* Flags in the CR2 register */
<> 156:95d6b41a828b 599 #define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI14RDY_BitNumber))
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /* Flags in the CSR register */
<> 156:95d6b41a828b 602 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_BitNumber))
<> 144:ef7eb2e8f9f7 603 #if defined(RCC_CSR_V18PWRRSTF)
<> 156:95d6b41a828b 604 #define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_V18PWRRSTF_BitNumber))
<> 144:ef7eb2e8f9f7 605 #endif
<> 156:95d6b41a828b 606 #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_BitNumber))
<> 156:95d6b41a828b 607 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_BitNumber)) /*!< PIN reset flag */
<> 156:95d6b41a828b 608 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_BitNumber)) /*!< POR/PDR reset flag */
<> 156:95d6b41a828b 609 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_BitNumber)) /*!< Software Reset flag */
<> 156:95d6b41a828b 610 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_BitNumber)) /*!< Independent Watchdog reset flag */
<> 156:95d6b41a828b 611 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_BitNumber)) /*!< Window watchdog reset flag */
<> 156:95d6b41a828b 612 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_BitNumber)) /*!< Low-Power reset flag */
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 /* Flags in the BDCR register */
<> 156:95d6b41a828b 615 #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_BitNumber)) /*!< External Low Speed oscillator Ready */
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 /**
<> 144:ef7eb2e8f9f7 618 * @}
<> 144:ef7eb2e8f9f7 619 */
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /**
<> 144:ef7eb2e8f9f7 622 * @}
<> 144:ef7eb2e8f9f7 623 */
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 /** @defgroup RCC_Exported_Macros RCC Exported Macros
<> 144:ef7eb2e8f9f7 628 * @{
<> 144:ef7eb2e8f9f7 629 */
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
<> 144:ef7eb2e8f9f7 632 * @brief Enable or disable the AHB peripheral clock.
<> 144:ef7eb2e8f9f7 633 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 634 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 635 * using it.
<> 144:ef7eb2e8f9f7 636 * @{
<> 144:ef7eb2e8f9f7 637 */
<> 144:ef7eb2e8f9f7 638 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 639 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 640 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
<> 144:ef7eb2e8f9f7 641 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 642 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
<> 144:ef7eb2e8f9f7 643 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 644 } while(0U)
<> 144:ef7eb2e8f9f7 645 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 646 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 647 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
<> 144:ef7eb2e8f9f7 648 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 649 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
<> 144:ef7eb2e8f9f7 650 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 651 } while(0U)
<> 144:ef7eb2e8f9f7 652 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 653 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 654 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
<> 144:ef7eb2e8f9f7 655 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 656 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
<> 144:ef7eb2e8f9f7 657 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 658 } while(0U)
<> 144:ef7eb2e8f9f7 659 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 660 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 661 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
<> 144:ef7eb2e8f9f7 662 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 663 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
<> 144:ef7eb2e8f9f7 664 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 665 } while(0U)
<> 144:ef7eb2e8f9f7 666 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 667 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 668 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
<> 144:ef7eb2e8f9f7 669 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 670 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
<> 144:ef7eb2e8f9f7 671 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 672 } while(0U)
<> 144:ef7eb2e8f9f7 673 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 674 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 675 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
<> 144:ef7eb2e8f9f7 676 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 677 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
<> 144:ef7eb2e8f9f7 678 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 679 } while(0U)
<> 144:ef7eb2e8f9f7 680 #define __HAL_RCC_SRAM_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 681 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 682 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
<> 144:ef7eb2e8f9f7 683 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 684 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
<> 144:ef7eb2e8f9f7 685 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 686 } while(0U)
<> 144:ef7eb2e8f9f7 687 #define __HAL_RCC_FLITF_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 688 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 689 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
<> 144:ef7eb2e8f9f7 690 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 691 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
<> 144:ef7eb2e8f9f7 692 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 693 } while(0U)
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
<> 144:ef7eb2e8f9f7 696 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
<> 144:ef7eb2e8f9f7 697 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
<> 144:ef7eb2e8f9f7 698 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
<> 144:ef7eb2e8f9f7 699 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
<> 144:ef7eb2e8f9f7 700 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
<> 144:ef7eb2e8f9f7 701 #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
<> 144:ef7eb2e8f9f7 702 #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
<> 144:ef7eb2e8f9f7 703 /**
<> 144:ef7eb2e8f9f7 704 * @}
<> 144:ef7eb2e8f9f7 705 */
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
<> 144:ef7eb2e8f9f7 708 * @brief Get the enable or disable status of the AHB peripheral clock.
<> 144:ef7eb2e8f9f7 709 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 710 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 711 * using it.
<> 144:ef7eb2e8f9f7 712 * @{
<> 144:ef7eb2e8f9f7 713 */
<> 144:ef7eb2e8f9f7 714 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
<> 144:ef7eb2e8f9f7 715 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
<> 144:ef7eb2e8f9f7 716 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
<> 144:ef7eb2e8f9f7 717 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
<> 144:ef7eb2e8f9f7 718 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
<> 144:ef7eb2e8f9f7 719 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
<> 144:ef7eb2e8f9f7 720 #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
<> 144:ef7eb2e8f9f7 721 #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
<> 144:ef7eb2e8f9f7 722 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
<> 144:ef7eb2e8f9f7 723 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
<> 144:ef7eb2e8f9f7 724 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
<> 144:ef7eb2e8f9f7 725 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
<> 144:ef7eb2e8f9f7 726 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
<> 144:ef7eb2e8f9f7 727 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
<> 144:ef7eb2e8f9f7 728 #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
<> 144:ef7eb2e8f9f7 729 #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
<> 144:ef7eb2e8f9f7 730 /**
<> 144:ef7eb2e8f9f7 731 * @}
<> 144:ef7eb2e8f9f7 732 */
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
<> 144:ef7eb2e8f9f7 735 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
<> 144:ef7eb2e8f9f7 736 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 737 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 738 * using it.
<> 144:ef7eb2e8f9f7 739 * @{
<> 144:ef7eb2e8f9f7 740 */
<> 144:ef7eb2e8f9f7 741 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 742 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 743 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
<> 144:ef7eb2e8f9f7 744 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 745 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
<> 144:ef7eb2e8f9f7 746 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 747 } while(0U)
<> 144:ef7eb2e8f9f7 748 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 749 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 750 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
<> 144:ef7eb2e8f9f7 751 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 752 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
<> 144:ef7eb2e8f9f7 753 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 754 } while(0U)
<> 144:ef7eb2e8f9f7 755 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 756 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 757 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
<> 144:ef7eb2e8f9f7 758 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 759 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
<> 144:ef7eb2e8f9f7 760 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 761 } while(0U)
<> 144:ef7eb2e8f9f7 762 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 763 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 764 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
<> 144:ef7eb2e8f9f7 765 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 766 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
<> 144:ef7eb2e8f9f7 767 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 768 } while(0U)
<> 144:ef7eb2e8f9f7 769 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 770 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 771 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
<> 144:ef7eb2e8f9f7 772 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 773 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
<> 144:ef7eb2e8f9f7 774 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 775 } while(0U)
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
<> 144:ef7eb2e8f9f7 778 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
<> 144:ef7eb2e8f9f7 779 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
<> 144:ef7eb2e8f9f7 780 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
<> 144:ef7eb2e8f9f7 781 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
<> 144:ef7eb2e8f9f7 782 /**
<> 144:ef7eb2e8f9f7 783 * @}
<> 144:ef7eb2e8f9f7 784 */
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
<> 144:ef7eb2e8f9f7 787 * @brief Get the enable or disable status of the APB1 peripheral clock.
<> 144:ef7eb2e8f9f7 788 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 789 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 790 * using it.
<> 144:ef7eb2e8f9f7 791 * @{
<> 144:ef7eb2e8f9f7 792 */
<> 144:ef7eb2e8f9f7 793 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
<> 144:ef7eb2e8f9f7 794 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
<> 144:ef7eb2e8f9f7 795 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
<> 144:ef7eb2e8f9f7 796 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
<> 144:ef7eb2e8f9f7 797 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
<> 144:ef7eb2e8f9f7 798 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
<> 144:ef7eb2e8f9f7 799 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
<> 144:ef7eb2e8f9f7 800 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
<> 144:ef7eb2e8f9f7 801 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
<> 144:ef7eb2e8f9f7 802 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
<> 144:ef7eb2e8f9f7 803 /**
<> 144:ef7eb2e8f9f7 804 * @}
<> 144:ef7eb2e8f9f7 805 */
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
<> 144:ef7eb2e8f9f7 809 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
<> 144:ef7eb2e8f9f7 810 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 811 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 812 * using it.
<> 144:ef7eb2e8f9f7 813 * @{
<> 144:ef7eb2e8f9f7 814 */
<> 144:ef7eb2e8f9f7 815 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 816 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 817 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
<> 144:ef7eb2e8f9f7 818 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 819 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
<> 144:ef7eb2e8f9f7 820 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 821 } while(0U)
<> 144:ef7eb2e8f9f7 822 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 823 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 824 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
<> 144:ef7eb2e8f9f7 825 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 826 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
<> 144:ef7eb2e8f9f7 827 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 828 } while(0U)
<> 144:ef7eb2e8f9f7 829 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 830 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 831 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
<> 144:ef7eb2e8f9f7 832 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 833 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
<> 144:ef7eb2e8f9f7 834 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 835 } while(0U)
<> 144:ef7eb2e8f9f7 836 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 837 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 838 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
<> 144:ef7eb2e8f9f7 839 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 840 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
<> 144:ef7eb2e8f9f7 841 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 842 } while(0U)
<> 144:ef7eb2e8f9f7 843 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 844 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 845 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
<> 144:ef7eb2e8f9f7 846 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 847 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
<> 144:ef7eb2e8f9f7 848 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 849 } while(0U)
<> 144:ef7eb2e8f9f7 850 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 851 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 852 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
<> 144:ef7eb2e8f9f7 853 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 854 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
<> 144:ef7eb2e8f9f7 855 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 856 } while(0U)
<> 144:ef7eb2e8f9f7 857 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 858 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 859 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
<> 144:ef7eb2e8f9f7 860 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 861 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
<> 144:ef7eb2e8f9f7 862 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 863 } while(0U)
<> 144:ef7eb2e8f9f7 864 #define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 865 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 866 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
<> 144:ef7eb2e8f9f7 867 /* Delay after an RCC peripheral clock enabling */\
<> 144:ef7eb2e8f9f7 868 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
<> 144:ef7eb2e8f9f7 869 UNUSED(tmpreg); \
Anna Bridge 180:96ed750bd169 870 } while(0U)
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
<> 144:ef7eb2e8f9f7 873 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
<> 144:ef7eb2e8f9f7 874 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
<> 144:ef7eb2e8f9f7 875 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
<> 144:ef7eb2e8f9f7 876 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
<> 144:ef7eb2e8f9f7 877 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
<> 144:ef7eb2e8f9f7 878 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
<> 144:ef7eb2e8f9f7 879 #define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
<> 144:ef7eb2e8f9f7 880 /**
<> 144:ef7eb2e8f9f7 881 * @}
<> 144:ef7eb2e8f9f7 882 */
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
<> 144:ef7eb2e8f9f7 885 * @brief Get the enable or disable status of the APB2 peripheral clock.
<> 144:ef7eb2e8f9f7 886 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 887 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 888 * using it.
<> 144:ef7eb2e8f9f7 889 * @{
<> 144:ef7eb2e8f9f7 890 */
<> 144:ef7eb2e8f9f7 891 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
<> 144:ef7eb2e8f9f7 892 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
<> 144:ef7eb2e8f9f7 893 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
<> 144:ef7eb2e8f9f7 894 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
<> 144:ef7eb2e8f9f7 895 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
<> 144:ef7eb2e8f9f7 896 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
<> 144:ef7eb2e8f9f7 897 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
<> 144:ef7eb2e8f9f7 898 #define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) != RESET)
<> 144:ef7eb2e8f9f7 899 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
<> 144:ef7eb2e8f9f7 900 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
<> 144:ef7eb2e8f9f7 901 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
<> 144:ef7eb2e8f9f7 902 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
<> 144:ef7eb2e8f9f7 903 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
<> 144:ef7eb2e8f9f7 904 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
<> 144:ef7eb2e8f9f7 905 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
<> 144:ef7eb2e8f9f7 906 #define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) == RESET)
<> 144:ef7eb2e8f9f7 907 /**
<> 144:ef7eb2e8f9f7 908 * @}
<> 144:ef7eb2e8f9f7 909 */
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
<> 144:ef7eb2e8f9f7 912 * @brief Force or release AHB peripheral reset.
<> 144:ef7eb2e8f9f7 913 * @{
<> 144:ef7eb2e8f9f7 914 */
<> 144:ef7eb2e8f9f7 915 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 916 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
<> 144:ef7eb2e8f9f7 917 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
<> 144:ef7eb2e8f9f7 918 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
<> 144:ef7eb2e8f9f7 919 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
<> 144:ef7eb2e8f9f7 920
<> 156:95d6b41a828b 921 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
<> 144:ef7eb2e8f9f7 922 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
<> 144:ef7eb2e8f9f7 923 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
<> 144:ef7eb2e8f9f7 924 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
<> 144:ef7eb2e8f9f7 925 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
<> 144:ef7eb2e8f9f7 926 /**
<> 144:ef7eb2e8f9f7 927 * @}
<> 144:ef7eb2e8f9f7 928 */
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
<> 144:ef7eb2e8f9f7 931 * @brief Force or release APB1 peripheral reset.
<> 144:ef7eb2e8f9f7 932 * @{
<> 144:ef7eb2e8f9f7 933 */
<> 144:ef7eb2e8f9f7 934 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 935 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
<> 144:ef7eb2e8f9f7 936 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
<> 144:ef7eb2e8f9f7 937 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
<> 144:ef7eb2e8f9f7 938 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
<> 144:ef7eb2e8f9f7 939 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
<> 144:ef7eb2e8f9f7 940
<> 156:95d6b41a828b 941 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
<> 144:ef7eb2e8f9f7 942 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
<> 144:ef7eb2e8f9f7 943 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
<> 144:ef7eb2e8f9f7 944 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
<> 144:ef7eb2e8f9f7 945 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
<> 144:ef7eb2e8f9f7 946 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
<> 144:ef7eb2e8f9f7 947 /**
<> 144:ef7eb2e8f9f7 948 * @}
<> 144:ef7eb2e8f9f7 949 */
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
<> 144:ef7eb2e8f9f7 952 * @brief Force or release APB2 peripheral reset.
<> 144:ef7eb2e8f9f7 953 * @{
<> 144:ef7eb2e8f9f7 954 */
<> 144:ef7eb2e8f9f7 955 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 956 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
<> 144:ef7eb2e8f9f7 957 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
<> 144:ef7eb2e8f9f7 958 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
<> 144:ef7eb2e8f9f7 959 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
<> 144:ef7eb2e8f9f7 960 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
<> 144:ef7eb2e8f9f7 961 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
<> 144:ef7eb2e8f9f7 962 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
<> 144:ef7eb2e8f9f7 963 #define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST))
<> 144:ef7eb2e8f9f7 964
<> 156:95d6b41a828b 965 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
<> 144:ef7eb2e8f9f7 966 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
<> 144:ef7eb2e8f9f7 967 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
<> 144:ef7eb2e8f9f7 968 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
<> 144:ef7eb2e8f9f7 969 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
<> 144:ef7eb2e8f9f7 970 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
<> 144:ef7eb2e8f9f7 971 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
<> 144:ef7eb2e8f9f7 972 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
<> 144:ef7eb2e8f9f7 973 #define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
<> 144:ef7eb2e8f9f7 974 /**
<> 144:ef7eb2e8f9f7 975 * @}
<> 144:ef7eb2e8f9f7 976 */
<> 144:ef7eb2e8f9f7 977 /** @defgroup RCC_HSI_Configuration HSI Configuration
<> 144:ef7eb2e8f9f7 978 * @{
<> 144:ef7eb2e8f9f7 979 */
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
<> 144:ef7eb2e8f9f7 982 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
<> 144:ef7eb2e8f9f7 983 * @note HSI can not be stopped if it is used as system clock source. In this case,
<> 144:ef7eb2e8f9f7 984 * you have to select another source of the system clock then stop the HSI.
<> 144:ef7eb2e8f9f7 985 * @note After enabling the HSI, the application software should wait on HSIRDY
<> 144:ef7eb2e8f9f7 986 * flag to be set indicating that HSI clock is stable and can be used as
<> 144:ef7eb2e8f9f7 987 * system clock source.
<> 144:ef7eb2e8f9f7 988 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
<> 144:ef7eb2e8f9f7 989 * clock cycles.
<> 144:ef7eb2e8f9f7 990 */
<> 144:ef7eb2e8f9f7 991 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
<> 144:ef7eb2e8f9f7 992 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
<> 144:ef7eb2e8f9f7 993
<> 144:ef7eb2e8f9f7 994 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
<> 144:ef7eb2e8f9f7 995 * @note The calibration is used to compensate for the variations in voltage
<> 144:ef7eb2e8f9f7 996 * and temperature that influence the frequency of the internal HSI RC.
<> 144:ef7eb2e8f9f7 997 * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
<> 144:ef7eb2e8f9f7 998 * (default is RCC_HSICALIBRATION_DEFAULT).
<> 144:ef7eb2e8f9f7 999 * This parameter must be a number between 0 and 0x1F.
<> 144:ef7eb2e8f9f7 1000 */
<> 144:ef7eb2e8f9f7 1001 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
<> 144:ef7eb2e8f9f7 1002 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_BitNumber)
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 /**
<> 144:ef7eb2e8f9f7 1005 * @}
<> 144:ef7eb2e8f9f7 1006 */
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008 /** @defgroup RCC_LSI_Configuration LSI Configuration
<> 144:ef7eb2e8f9f7 1009 * @{
<> 144:ef7eb2e8f9f7 1010 */
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 /** @brief Macro to enable the Internal Low Speed oscillator (LSI).
<> 144:ef7eb2e8f9f7 1013 * @note After enabling the LSI, the application software should wait on
<> 144:ef7eb2e8f9f7 1014 * LSIRDY flag to be set indicating that LSI clock is stable and can
<> 144:ef7eb2e8f9f7 1015 * be used to clock the IWDG and/or the RTC.
<> 144:ef7eb2e8f9f7 1016 */
<> 144:ef7eb2e8f9f7 1017 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 /** @brief Macro to disable the Internal Low Speed oscillator (LSI).
<> 144:ef7eb2e8f9f7 1020 * @note LSI can not be disabled if the IWDG is running.
<> 144:ef7eb2e8f9f7 1021 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
<> 144:ef7eb2e8f9f7 1022 * clock cycles.
<> 144:ef7eb2e8f9f7 1023 */
<> 144:ef7eb2e8f9f7 1024 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /**
<> 144:ef7eb2e8f9f7 1027 * @}
<> 144:ef7eb2e8f9f7 1028 */
<> 144:ef7eb2e8f9f7 1029
<> 144:ef7eb2e8f9f7 1030 /** @defgroup RCC_HSE_Configuration HSE Configuration
<> 144:ef7eb2e8f9f7 1031 * @{
<> 144:ef7eb2e8f9f7 1032 */
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 /**
<> 144:ef7eb2e8f9f7 1035 * @brief Macro to configure the External High Speed oscillator (HSE).
<> 144:ef7eb2e8f9f7 1036 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
<> 144:ef7eb2e8f9f7 1037 * supported by this macro. User should request a transition to HSE Off
<> 144:ef7eb2e8f9f7 1038 * first and then HSE On or HSE Bypass.
<> 144:ef7eb2e8f9f7 1039 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
<> 144:ef7eb2e8f9f7 1040 * software should wait on HSERDY flag to be set indicating that HSE clock
<> 144:ef7eb2e8f9f7 1041 * is stable and can be used to clock the PLL and/or system clock.
<> 144:ef7eb2e8f9f7 1042 * @note HSE state can not be changed if it is used directly or through the
<> 144:ef7eb2e8f9f7 1043 * PLL as system clock. In this case, you have to select another source
<> 144:ef7eb2e8f9f7 1044 * of the system clock then change the HSE state (ex. disable it).
<> 144:ef7eb2e8f9f7 1045 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
<> 144:ef7eb2e8f9f7 1046 * @note This function reset the CSSON bit, so if the clock security system(CSS)
<> 144:ef7eb2e8f9f7 1047 * was previously enabled you have to enable it again after calling this
<> 144:ef7eb2e8f9f7 1048 * function.
<> 144:ef7eb2e8f9f7 1049 * @param __STATE__ specifies the new state of the HSE.
<> 144:ef7eb2e8f9f7 1050 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1051 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
<> 144:ef7eb2e8f9f7 1052 * 6 HSE oscillator clock cycles.
<> 144:ef7eb2e8f9f7 1053 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator
<> 144:ef7eb2e8f9f7 1054 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
<> 144:ef7eb2e8f9f7 1055 */
<> 144:ef7eb2e8f9f7 1056 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
<> 144:ef7eb2e8f9f7 1057 do{ \
<> 144:ef7eb2e8f9f7 1058 if ((__STATE__) == RCC_HSE_ON) \
<> 144:ef7eb2e8f9f7 1059 { \
<> 144:ef7eb2e8f9f7 1060 SET_BIT(RCC->CR, RCC_CR_HSEON); \
<> 144:ef7eb2e8f9f7 1061 } \
<> 144:ef7eb2e8f9f7 1062 else if ((__STATE__) == RCC_HSE_OFF) \
<> 144:ef7eb2e8f9f7 1063 { \
<> 144:ef7eb2e8f9f7 1064 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
<> 144:ef7eb2e8f9f7 1065 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
<> 144:ef7eb2e8f9f7 1066 } \
<> 144:ef7eb2e8f9f7 1067 else if ((__STATE__) == RCC_HSE_BYPASS) \
<> 144:ef7eb2e8f9f7 1068 { \
<> 144:ef7eb2e8f9f7 1069 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
<> 144:ef7eb2e8f9f7 1070 SET_BIT(RCC->CR, RCC_CR_HSEON); \
<> 144:ef7eb2e8f9f7 1071 } \
<> 144:ef7eb2e8f9f7 1072 else \
<> 144:ef7eb2e8f9f7 1073 { \
<> 144:ef7eb2e8f9f7 1074 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
<> 144:ef7eb2e8f9f7 1075 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
<> 144:ef7eb2e8f9f7 1076 } \
Anna Bridge 180:96ed750bd169 1077 }while(0U)
<> 144:ef7eb2e8f9f7 1078
<> 144:ef7eb2e8f9f7 1079 /**
<> 144:ef7eb2e8f9f7 1080 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
<> 144:ef7eb2e8f9f7 1081 * @note Predivision factor can not be changed if PLL is used as system clock
<> 144:ef7eb2e8f9f7 1082 * In this case, you have to select another source of the system clock, disable the PLL and
<> 144:ef7eb2e8f9f7 1083 * then change the HSE predivision factor.
<> 144:ef7eb2e8f9f7 1084 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
<> 144:ef7eb2e8f9f7 1085 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
<> 144:ef7eb2e8f9f7 1086 */
<> 144:ef7eb2e8f9f7 1087 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
<> 144:ef7eb2e8f9f7 1088 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090 /**
<> 144:ef7eb2e8f9f7 1091 * @}
<> 144:ef7eb2e8f9f7 1092 */
<> 144:ef7eb2e8f9f7 1093
<> 144:ef7eb2e8f9f7 1094 /** @defgroup RCC_LSE_Configuration LSE Configuration
<> 144:ef7eb2e8f9f7 1095 * @{
<> 144:ef7eb2e8f9f7 1096 */
<> 144:ef7eb2e8f9f7 1097
<> 144:ef7eb2e8f9f7 1098 /**
<> 144:ef7eb2e8f9f7 1099 * @brief Macro to configure the External Low Speed oscillator (LSE).
<> 144:ef7eb2e8f9f7 1100 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
<> 144:ef7eb2e8f9f7 1101 * @note As the LSE is in the Backup domain and write access is denied to
<> 144:ef7eb2e8f9f7 1102 * this domain after reset, you have to enable write access using
<> 144:ef7eb2e8f9f7 1103 * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
<> 144:ef7eb2e8f9f7 1104 * (to be done once after reset).
<> 144:ef7eb2e8f9f7 1105 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
<> 144:ef7eb2e8f9f7 1106 * software should wait on LSERDY flag to be set indicating that LSE clock
<> 144:ef7eb2e8f9f7 1107 * is stable and can be used to clock the RTC.
<> 144:ef7eb2e8f9f7 1108 * @param __STATE__ specifies the new state of the LSE.
<> 144:ef7eb2e8f9f7 1109 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1110 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
<> 144:ef7eb2e8f9f7 1111 * 6 LSE oscillator clock cycles.
<> 144:ef7eb2e8f9f7 1112 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
<> 144:ef7eb2e8f9f7 1113 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
<> 144:ef7eb2e8f9f7 1114 */
<> 144:ef7eb2e8f9f7 1115 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
<> 144:ef7eb2e8f9f7 1116 do{ \
<> 144:ef7eb2e8f9f7 1117 if ((__STATE__) == RCC_LSE_ON) \
<> 144:ef7eb2e8f9f7 1118 { \
<> 144:ef7eb2e8f9f7 1119 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
<> 144:ef7eb2e8f9f7 1120 } \
<> 144:ef7eb2e8f9f7 1121 else if ((__STATE__) == RCC_LSE_OFF) \
<> 144:ef7eb2e8f9f7 1122 { \
<> 144:ef7eb2e8f9f7 1123 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
<> 144:ef7eb2e8f9f7 1124 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
<> 144:ef7eb2e8f9f7 1125 } \
<> 144:ef7eb2e8f9f7 1126 else if ((__STATE__) == RCC_LSE_BYPASS) \
<> 144:ef7eb2e8f9f7 1127 { \
<> 144:ef7eb2e8f9f7 1128 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
<> 144:ef7eb2e8f9f7 1129 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
<> 144:ef7eb2e8f9f7 1130 } \
<> 144:ef7eb2e8f9f7 1131 else \
<> 144:ef7eb2e8f9f7 1132 { \
<> 144:ef7eb2e8f9f7 1133 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
<> 144:ef7eb2e8f9f7 1134 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
<> 144:ef7eb2e8f9f7 1135 } \
Anna Bridge 180:96ed750bd169 1136 }while(0U)
<> 144:ef7eb2e8f9f7 1137
<> 144:ef7eb2e8f9f7 1138 /**
<> 144:ef7eb2e8f9f7 1139 * @}
<> 144:ef7eb2e8f9f7 1140 */
<> 144:ef7eb2e8f9f7 1141
<> 144:ef7eb2e8f9f7 1142 /** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration
<> 144:ef7eb2e8f9f7 1143 * @{
<> 144:ef7eb2e8f9f7 1144 */
<> 144:ef7eb2e8f9f7 1145
<> 144:ef7eb2e8f9f7 1146 /** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14).
<> 144:ef7eb2e8f9f7 1147 * @note After enabling the HSI14 with @ref __HAL_RCC_HSI14_ENABLE(), the application software
<> 144:ef7eb2e8f9f7 1148 * should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be
<> 144:ef7eb2e8f9f7 1149 * used as system clock source. This is not necessary if @ref HAL_RCC_OscConfig() is used.
<> 144:ef7eb2e8f9f7 1150 * clock cycles.
<> 144:ef7eb2e8f9f7 1151 */
<> 144:ef7eb2e8f9f7 1152 #define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON)
<> 144:ef7eb2e8f9f7 1153
<> 144:ef7eb2e8f9f7 1154 /** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14).
<> 144:ef7eb2e8f9f7 1155 * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
<> 144:ef7eb2e8f9f7 1156 * @note HSI14 can not be stopped if it is used as system clock source. In this case,
<> 144:ef7eb2e8f9f7 1157 * you have to select another source of the system clock then stop the HSI14.
<> 144:ef7eb2e8f9f7 1158 * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
<> 144:ef7eb2e8f9f7 1159 * clock cycles.
<> 144:ef7eb2e8f9f7 1160 */
<> 144:ef7eb2e8f9f7 1161 #define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON)
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 /** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC.
<> 144:ef7eb2e8f9f7 1164 */
<> 144:ef7eb2e8f9f7 1165 #define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 /** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC.
<> 144:ef7eb2e8f9f7 1168 */
<> 144:ef7eb2e8f9f7 1169 #define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 /** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value.
<> 144:ef7eb2e8f9f7 1172 * @note The calibration is used to compensate for the variations in voltage
<> 144:ef7eb2e8f9f7 1173 * and temperature that influence the frequency of the internal HSI14 RC.
<> 144:ef7eb2e8f9f7 1174 * @param __HSI14CALIBRATIONVALUE__ specifies the calibration trimming value
<> 144:ef7eb2e8f9f7 1175 * (default is RCC_HSI14CALIBRATION_DEFAULT).
<> 144:ef7eb2e8f9f7 1176 * This parameter must be a number between 0 and 0x1F.
<> 144:ef7eb2e8f9f7 1177 */
<> 144:ef7eb2e8f9f7 1178 #define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CALIBRATIONVALUE__) \
<> 144:ef7eb2e8f9f7 1179 MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CALIBRATIONVALUE__) << RCC_HSI14TRIM_BIT_NUMBER)
<> 144:ef7eb2e8f9f7 1180 /**
<> 144:ef7eb2e8f9f7 1181 * @}
<> 144:ef7eb2e8f9f7 1182 */
<> 144:ef7eb2e8f9f7 1183
<> 144:ef7eb2e8f9f7 1184 /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
<> 144:ef7eb2e8f9f7 1185 * @{
<> 144:ef7eb2e8f9f7 1186 */
<> 144:ef7eb2e8f9f7 1187
<> 144:ef7eb2e8f9f7 1188 /** @brief Macro to configure the USART1 clock (USART1CLK).
<> 144:ef7eb2e8f9f7 1189 * @param __USART1CLKSOURCE__ specifies the USART1 clock source.
<> 144:ef7eb2e8f9f7 1190 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1191 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
<> 144:ef7eb2e8f9f7 1192 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
<> 144:ef7eb2e8f9f7 1193 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
<> 144:ef7eb2e8f9f7 1194 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
<> 144:ef7eb2e8f9f7 1195 */
<> 144:ef7eb2e8f9f7 1196 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 1197 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__))
<> 144:ef7eb2e8f9f7 1198
<> 144:ef7eb2e8f9f7 1199 /** @brief Macro to get the USART1 clock source.
<> 144:ef7eb2e8f9f7 1200 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 1201 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
<> 144:ef7eb2e8f9f7 1202 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
<> 144:ef7eb2e8f9f7 1203 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
<> 144:ef7eb2e8f9f7 1204 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
<> 144:ef7eb2e8f9f7 1205 */
<> 144:ef7eb2e8f9f7 1206 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
<> 144:ef7eb2e8f9f7 1207
<> 144:ef7eb2e8f9f7 1208 /**
<> 144:ef7eb2e8f9f7 1209 * @}
<> 144:ef7eb2e8f9f7 1210 */
<> 144:ef7eb2e8f9f7 1211
<> 144:ef7eb2e8f9f7 1212 /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
<> 144:ef7eb2e8f9f7 1213 * @{
<> 144:ef7eb2e8f9f7 1214 */
<> 144:ef7eb2e8f9f7 1215
<> 144:ef7eb2e8f9f7 1216 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
<> 144:ef7eb2e8f9f7 1217 * @param __I2C1CLKSOURCE__ specifies the I2C1 clock source.
<> 144:ef7eb2e8f9f7 1218 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1219 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
<> 144:ef7eb2e8f9f7 1220 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
<> 144:ef7eb2e8f9f7 1221 */
<> 144:ef7eb2e8f9f7 1222 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 1223 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__))
<> 144:ef7eb2e8f9f7 1224
<> 144:ef7eb2e8f9f7 1225 /** @brief Macro to get the I2C1 clock source.
<> 144:ef7eb2e8f9f7 1226 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 1227 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
<> 144:ef7eb2e8f9f7 1228 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
<> 144:ef7eb2e8f9f7 1229 */
<> 144:ef7eb2e8f9f7 1230 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
<> 144:ef7eb2e8f9f7 1231 /**
<> 144:ef7eb2e8f9f7 1232 * @}
<> 144:ef7eb2e8f9f7 1233 */
<> 144:ef7eb2e8f9f7 1234
<> 144:ef7eb2e8f9f7 1235 /** @defgroup RCC_PLL_Configuration PLL Configuration
<> 144:ef7eb2e8f9f7 1236 * @{
<> 144:ef7eb2e8f9f7 1237 */
<> 144:ef7eb2e8f9f7 1238
<> 144:ef7eb2e8f9f7 1239 /** @brief Macro to enable the main PLL.
<> 144:ef7eb2e8f9f7 1240 * @note After enabling the main PLL, the application software should wait on
<> 144:ef7eb2e8f9f7 1241 * PLLRDY flag to be set indicating that PLL clock is stable and can
<> 144:ef7eb2e8f9f7 1242 * be used as system clock source.
<> 144:ef7eb2e8f9f7 1243 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
<> 144:ef7eb2e8f9f7 1244 */
<> 144:ef7eb2e8f9f7 1245 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
<> 144:ef7eb2e8f9f7 1246
<> 144:ef7eb2e8f9f7 1247 /** @brief Macro to disable the main PLL.
<> 144:ef7eb2e8f9f7 1248 * @note The main PLL can not be disabled if it is used as system clock source
<> 144:ef7eb2e8f9f7 1249 */
<> 144:ef7eb2e8f9f7 1250 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
<> 144:ef7eb2e8f9f7 1251
<> 144:ef7eb2e8f9f7 1252 /** @brief Macro to configure the PLL clock source, multiplication and division factors.
<> 144:ef7eb2e8f9f7 1253 * @note This function must be used only when the main PLL is disabled.
<> 144:ef7eb2e8f9f7 1254 *
<> 144:ef7eb2e8f9f7 1255 * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
<> 144:ef7eb2e8f9f7 1256 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1257 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
<> 144:ef7eb2e8f9f7 1258 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
<> 144:ef7eb2e8f9f7 1259 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
<> 144:ef7eb2e8f9f7 1260 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1261 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
<> 144:ef7eb2e8f9f7 1262 * @param __PREDIV__ specifies the predivider factor for PLL VCO input clock
<> 144:ef7eb2e8f9f7 1263 * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
<> 144:ef7eb2e8f9f7 1264 *
<> 144:ef7eb2e8f9f7 1265 */
<> 144:ef7eb2e8f9f7 1266 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PREDIV__, __PLLMUL__) \
<> 144:ef7eb2e8f9f7 1267 do { \
<> 144:ef7eb2e8f9f7 1268 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
<> 144:ef7eb2e8f9f7 1269 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSOURCE__))); \
Anna Bridge 180:96ed750bd169 1270 } while(0U)
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272
<> 144:ef7eb2e8f9f7 1273 /** @brief Get oscillator clock selected as PLL input clock
<> 144:ef7eb2e8f9f7 1274 * @retval The clock source used for PLL entry. The returned value can be one
<> 144:ef7eb2e8f9f7 1275 * of the following:
<> 144:ef7eb2e8f9f7 1276 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
<> 144:ef7eb2e8f9f7 1277 */
<> 144:ef7eb2e8f9f7 1278 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 /**
<> 144:ef7eb2e8f9f7 1281 * @}
<> 144:ef7eb2e8f9f7 1282 */
<> 144:ef7eb2e8f9f7 1283
<> 144:ef7eb2e8f9f7 1284 /** @defgroup RCC_Get_Clock_source Get Clock source
<> 144:ef7eb2e8f9f7 1285 * @{
<> 144:ef7eb2e8f9f7 1286 */
<> 144:ef7eb2e8f9f7 1287
<> 144:ef7eb2e8f9f7 1288 /**
<> 144:ef7eb2e8f9f7 1289 * @brief Macro to configure the system clock source.
<> 144:ef7eb2e8f9f7 1290 * @param __SYSCLKSOURCE__ specifies the system clock source.
<> 144:ef7eb2e8f9f7 1291 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1292 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
<> 144:ef7eb2e8f9f7 1293 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
<> 144:ef7eb2e8f9f7 1294 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
<> 144:ef7eb2e8f9f7 1295 */
<> 144:ef7eb2e8f9f7 1296 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
<> 144:ef7eb2e8f9f7 1297 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
<> 144:ef7eb2e8f9f7 1298
<> 144:ef7eb2e8f9f7 1299 /** @brief Macro to get the clock source used as system clock.
<> 144:ef7eb2e8f9f7 1300 * @retval The clock source used as system clock. The returned value can be one
<> 144:ef7eb2e8f9f7 1301 * of the following:
<> 144:ef7eb2e8f9f7 1302 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
<> 144:ef7eb2e8f9f7 1303 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
<> 144:ef7eb2e8f9f7 1304 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
<> 144:ef7eb2e8f9f7 1305 */
<> 144:ef7eb2e8f9f7 1306 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
<> 144:ef7eb2e8f9f7 1307
<> 144:ef7eb2e8f9f7 1308 /**
<> 144:ef7eb2e8f9f7 1309 * @}
<> 144:ef7eb2e8f9f7 1310 */
<> 144:ef7eb2e8f9f7 1311
<> 144:ef7eb2e8f9f7 1312 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
<> 144:ef7eb2e8f9f7 1313 * @{
<> 144:ef7eb2e8f9f7 1314 */
<> 144:ef7eb2e8f9f7 1315
<> 144:ef7eb2e8f9f7 1316 #if defined(RCC_CFGR_MCOPRE)
<> 144:ef7eb2e8f9f7 1317 /** @brief Macro to configure the MCO clock.
<> 144:ef7eb2e8f9f7 1318 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
<> 144:ef7eb2e8f9f7 1319 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1320 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
<> 144:ef7eb2e8f9f7 1321 * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
<> 144:ef7eb2e8f9f7 1322 * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock
<> 144:ef7eb2e8f9f7 1323 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
<> 144:ef7eb2e8f9f7 1324 * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
<> 144:ef7eb2e8f9f7 1325 * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
<> 144:ef7eb2e8f9f7 1326 * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock
<> 144:ef7eb2e8f9f7 1327 @if STM32F042x6
<> 144:ef7eb2e8f9f7 1328 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
<> 144:ef7eb2e8f9f7 1329 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 1330 @elseif STM32F048xx
<> 144:ef7eb2e8f9f7 1331 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
<> 144:ef7eb2e8f9f7 1332 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 1333 @elseif STM32F071xB
<> 144:ef7eb2e8f9f7 1334 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
<> 144:ef7eb2e8f9f7 1335 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 1336 @elseif STM32F072xB
<> 144:ef7eb2e8f9f7 1337 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
<> 144:ef7eb2e8f9f7 1338 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 1339 @elseif STM32F078xx
<> 144:ef7eb2e8f9f7 1340 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
<> 144:ef7eb2e8f9f7 1341 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 1342 @elseif STM32F091xC
<> 144:ef7eb2e8f9f7 1343 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
<> 144:ef7eb2e8f9f7 1344 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 1345 @elseif STM32F098xx
<> 144:ef7eb2e8f9f7 1346 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
<> 144:ef7eb2e8f9f7 1347 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 1348 @elseif STM32F030x6
<> 144:ef7eb2e8f9f7 1349 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 1350 @elseif STM32F030xC
<> 144:ef7eb2e8f9f7 1351 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 1352 @elseif STM32F031x6
<> 144:ef7eb2e8f9f7 1353 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 1354 @elseif STM32F038xx
<> 144:ef7eb2e8f9f7 1355 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 1356 @elseif STM32F070x6
<> 144:ef7eb2e8f9f7 1357 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 1358 @elseif STM32F070xB
<> 144:ef7eb2e8f9f7 1359 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 1360 @endif
<> 144:ef7eb2e8f9f7 1361 * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
<> 144:ef7eb2e8f9f7 1362 * @param __MCODIV__ specifies the MCO clock prescaler.
<> 144:ef7eb2e8f9f7 1363 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1364 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
<> 144:ef7eb2e8f9f7 1365 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
<> 144:ef7eb2e8f9f7 1366 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
<> 144:ef7eb2e8f9f7 1367 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
<> 144:ef7eb2e8f9f7 1368 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
<> 144:ef7eb2e8f9f7 1369 * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32
<> 144:ef7eb2e8f9f7 1370 * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64
<> 144:ef7eb2e8f9f7 1371 * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128
<> 144:ef7eb2e8f9f7 1372 */
<> 144:ef7eb2e8f9f7 1373 #else
<> 144:ef7eb2e8f9f7 1374 /** @brief Macro to configure the MCO clock.
<> 144:ef7eb2e8f9f7 1375 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
<> 144:ef7eb2e8f9f7 1376 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1377 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
<> 144:ef7eb2e8f9f7 1378 * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
<> 144:ef7eb2e8f9f7 1379 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
<> 144:ef7eb2e8f9f7 1380 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
<> 144:ef7eb2e8f9f7 1381 * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
<> 144:ef7eb2e8f9f7 1382 * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
<> 144:ef7eb2e8f9f7 1383 * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock
<> 144:ef7eb2e8f9f7 1384 * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
<> 144:ef7eb2e8f9f7 1385 * @param __MCODIV__ specifies the MCO clock prescaler.
<> 144:ef7eb2e8f9f7 1386 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1387 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
<> 144:ef7eb2e8f9f7 1388 */
<> 144:ef7eb2e8f9f7 1389 #endif
<> 144:ef7eb2e8f9f7 1390 #if defined(RCC_CFGR_MCOPRE)
<> 144:ef7eb2e8f9f7 1391 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
<> 144:ef7eb2e8f9f7 1392 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
<> 144:ef7eb2e8f9f7 1393 #else
<> 144:ef7eb2e8f9f7 1394
<> 144:ef7eb2e8f9f7 1395 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
<> 144:ef7eb2e8f9f7 1396 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
<> 144:ef7eb2e8f9f7 1397
<> 144:ef7eb2e8f9f7 1398 #endif
<> 144:ef7eb2e8f9f7 1399
<> 144:ef7eb2e8f9f7 1400 /**
<> 144:ef7eb2e8f9f7 1401 * @}
<> 144:ef7eb2e8f9f7 1402 */
<> 144:ef7eb2e8f9f7 1403
<> 144:ef7eb2e8f9f7 1404 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
<> 144:ef7eb2e8f9f7 1405 * @{
<> 144:ef7eb2e8f9f7 1406 */
<> 144:ef7eb2e8f9f7 1407
<> 144:ef7eb2e8f9f7 1408 /** @brief Macro to configure the RTC clock (RTCCLK).
<> 144:ef7eb2e8f9f7 1409 * @note As the RTC clock configuration bits are in the Backup domain and write
<> 144:ef7eb2e8f9f7 1410 * access is denied to this domain after reset, you have to enable write
<> 144:ef7eb2e8f9f7 1411 * access using the Power Backup Access macro before to configure
<> 144:ef7eb2e8f9f7 1412 * the RTC clock source (to be done once after reset).
<> 156:95d6b41a828b 1413 * @note Once the RTC clock is configured it cannot be changed unless the
<> 144:ef7eb2e8f9f7 1414 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
<> 144:ef7eb2e8f9f7 1415 * a Power On Reset (POR).
<> 144:ef7eb2e8f9f7 1416 *
<> 144:ef7eb2e8f9f7 1417 * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
<> 144:ef7eb2e8f9f7 1418 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1419 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
<> 144:ef7eb2e8f9f7 1420 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
<> 144:ef7eb2e8f9f7 1421 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
<> 144:ef7eb2e8f9f7 1422 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
<> 144:ef7eb2e8f9f7 1423 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
<> 144:ef7eb2e8f9f7 1424 * work in STOP and STANDBY modes, and can be used as wakeup source.
<> 144:ef7eb2e8f9f7 1425 * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
<> 144:ef7eb2e8f9f7 1426 * the RTC cannot be used in STOP and STANDBY modes.
<> 144:ef7eb2e8f9f7 1427 * @note The system must always be configured so as to get a PCLK frequency greater than or
<> 144:ef7eb2e8f9f7 1428 * equal to the RTCCLK frequency for a proper operation of the RTC.
<> 144:ef7eb2e8f9f7 1429 */
<> 144:ef7eb2e8f9f7 1430 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
<> 144:ef7eb2e8f9f7 1431
<> 144:ef7eb2e8f9f7 1432 /** @brief Macro to get the RTC clock source.
<> 144:ef7eb2e8f9f7 1433 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 1434 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
<> 144:ef7eb2e8f9f7 1435 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
<> 144:ef7eb2e8f9f7 1436 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
<> 144:ef7eb2e8f9f7 1437 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
<> 144:ef7eb2e8f9f7 1438 */
<> 144:ef7eb2e8f9f7 1439 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
<> 144:ef7eb2e8f9f7 1440
<> 144:ef7eb2e8f9f7 1441 /** @brief Macro to enable the the RTC clock.
<> 144:ef7eb2e8f9f7 1442 * @note These macros must be used only after the RTC clock source was selected.
<> 144:ef7eb2e8f9f7 1443 */
<> 144:ef7eb2e8f9f7 1444 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
<> 144:ef7eb2e8f9f7 1445
<> 144:ef7eb2e8f9f7 1446 /** @brief Macro to disable the the RTC clock.
<> 144:ef7eb2e8f9f7 1447 * @note These macros must be used only after the RTC clock source was selected.
<> 144:ef7eb2e8f9f7 1448 */
<> 144:ef7eb2e8f9f7 1449 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
<> 144:ef7eb2e8f9f7 1450
<> 144:ef7eb2e8f9f7 1451 /** @brief Macro to force the Backup domain reset.
<> 144:ef7eb2e8f9f7 1452 * @note This function resets the RTC peripheral (including the backup registers)
<> 144:ef7eb2e8f9f7 1453 * and the RTC clock source selection in RCC_BDCR register.
<> 144:ef7eb2e8f9f7 1454 */
<> 144:ef7eb2e8f9f7 1455 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
<> 144:ef7eb2e8f9f7 1456
<> 144:ef7eb2e8f9f7 1457 /** @brief Macros to release the Backup domain reset.
<> 144:ef7eb2e8f9f7 1458 */
<> 144:ef7eb2e8f9f7 1459 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
<> 144:ef7eb2e8f9f7 1460
<> 144:ef7eb2e8f9f7 1461 /**
<> 144:ef7eb2e8f9f7 1462 * @}
<> 144:ef7eb2e8f9f7 1463 */
<> 144:ef7eb2e8f9f7 1464
<> 144:ef7eb2e8f9f7 1465 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
<> 144:ef7eb2e8f9f7 1466 * @brief macros to manage the specified RCC Flags and interrupts.
<> 144:ef7eb2e8f9f7 1467 * @{
<> 144:ef7eb2e8f9f7 1468 */
<> 144:ef7eb2e8f9f7 1469
<> 144:ef7eb2e8f9f7 1470 /** @brief Enable RCC interrupt.
<> 144:ef7eb2e8f9f7 1471 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
<> 144:ef7eb2e8f9f7 1472 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1473 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
<> 144:ef7eb2e8f9f7 1474 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
<> 144:ef7eb2e8f9f7 1475 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
<> 144:ef7eb2e8f9f7 1476 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
<> 144:ef7eb2e8f9f7 1477 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
<> 144:ef7eb2e8f9f7 1478 * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt
<> 144:ef7eb2e8f9f7 1479 @if STM32F042x6
<> 144:ef7eb2e8f9f7 1480 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1481 @elseif STM32F048xx
<> 144:ef7eb2e8f9f7 1482 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1483 @elseif STM32F071xB
<> 144:ef7eb2e8f9f7 1484 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1485 @elseif STM32F072xB
<> 144:ef7eb2e8f9f7 1486 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1487 @elseif STM32F078xx
<> 144:ef7eb2e8f9f7 1488 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1489 @elseif STM32F091xC
<> 144:ef7eb2e8f9f7 1490 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1491 @elseif STM32F098xx
<> 144:ef7eb2e8f9f7 1492 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1493 @endif
<> 144:ef7eb2e8f9f7 1494 */
<> 144:ef7eb2e8f9f7 1495 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1496
<> 144:ef7eb2e8f9f7 1497 /** @brief Disable RCC interrupt.
<> 144:ef7eb2e8f9f7 1498 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
<> 144:ef7eb2e8f9f7 1499 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1500 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
<> 144:ef7eb2e8f9f7 1501 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
<> 144:ef7eb2e8f9f7 1502 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
<> 144:ef7eb2e8f9f7 1503 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
<> 144:ef7eb2e8f9f7 1504 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
<> 144:ef7eb2e8f9f7 1505 * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt
<> 144:ef7eb2e8f9f7 1506 @if STM32F042x6
<> 144:ef7eb2e8f9f7 1507 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1508 @elseif STM32F048xx
<> 144:ef7eb2e8f9f7 1509 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1510 @elseif STM32F071xB
<> 144:ef7eb2e8f9f7 1511 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1512 @elseif STM32F072xB
<> 144:ef7eb2e8f9f7 1513 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1514 @elseif STM32F078xx
<> 144:ef7eb2e8f9f7 1515 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1516 @elseif STM32F091xC
<> 144:ef7eb2e8f9f7 1517 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1518 @elseif STM32F098xx
<> 144:ef7eb2e8f9f7 1519 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1520 @endif
<> 144:ef7eb2e8f9f7 1521 */
<> 144:ef7eb2e8f9f7 1522 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 1523
<> 144:ef7eb2e8f9f7 1524 /** @brief Clear the RCC's interrupt pending bits.
<> 144:ef7eb2e8f9f7 1525 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
<> 144:ef7eb2e8f9f7 1526 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1527 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
<> 144:ef7eb2e8f9f7 1528 * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
<> 144:ef7eb2e8f9f7 1529 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
<> 144:ef7eb2e8f9f7 1530 * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
<> 144:ef7eb2e8f9f7 1531 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
<> 144:ef7eb2e8f9f7 1532 * @arg @ref RCC_IT_CSS Clock Security System interrupt
<> 144:ef7eb2e8f9f7 1533 * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt
<> 144:ef7eb2e8f9f7 1534 @if STM32F042x6
<> 144:ef7eb2e8f9f7 1535 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1536 @elseif STM32F048xx
<> 144:ef7eb2e8f9f7 1537 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1538 @elseif STM32F071xB
<> 144:ef7eb2e8f9f7 1539 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1540 @elseif STM32F072xB
<> 144:ef7eb2e8f9f7 1541 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1542 @elseif STM32F078xx
<> 144:ef7eb2e8f9f7 1543 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1544 @elseif STM32F091xC
<> 144:ef7eb2e8f9f7 1545 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1546 @elseif STM32F098xx
<> 144:ef7eb2e8f9f7 1547 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1548 @endif
<> 144:ef7eb2e8f9f7 1549 */
<> 144:ef7eb2e8f9f7 1550 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1551
<> 144:ef7eb2e8f9f7 1552 /** @brief Check the RCC's interrupt has occurred or not.
<> 144:ef7eb2e8f9f7 1553 * @param __INTERRUPT__ specifies the RCC interrupt source to check.
<> 144:ef7eb2e8f9f7 1554 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1555 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
<> 144:ef7eb2e8f9f7 1556 * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
<> 144:ef7eb2e8f9f7 1557 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
<> 144:ef7eb2e8f9f7 1558 * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
<> 144:ef7eb2e8f9f7 1559 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
<> 144:ef7eb2e8f9f7 1560 * @arg @ref RCC_IT_CSS Clock Security System interrupt
<> 144:ef7eb2e8f9f7 1561 * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt enable
<> 144:ef7eb2e8f9f7 1562 @if STM32F042x6
<> 144:ef7eb2e8f9f7 1563 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1564 @elseif STM32F048xx
<> 144:ef7eb2e8f9f7 1565 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1566 @elseif STM32F071xB
<> 144:ef7eb2e8f9f7 1567 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1568 @elseif STM32F072xB
<> 144:ef7eb2e8f9f7 1569 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1570 @elseif STM32F078xx
<> 144:ef7eb2e8f9f7 1571 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1572 @elseif STM32F091xC
<> 144:ef7eb2e8f9f7 1573 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1574 @elseif STM32F098xx
<> 144:ef7eb2e8f9f7 1575 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
<> 144:ef7eb2e8f9f7 1576 @endif
<> 144:ef7eb2e8f9f7 1577 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 1578 */
<> 144:ef7eb2e8f9f7 1579 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1580
<> 144:ef7eb2e8f9f7 1581 /** @brief Set RMVF bit to clear the reset flags.
<> 144:ef7eb2e8f9f7 1582 * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
<> 144:ef7eb2e8f9f7 1583 * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
<> 144:ef7eb2e8f9f7 1584 */
<> 144:ef7eb2e8f9f7 1585 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
<> 144:ef7eb2e8f9f7 1586
<> 144:ef7eb2e8f9f7 1587 /** @brief Check RCC flag is set or not.
<> 144:ef7eb2e8f9f7 1588 * @param __FLAG__ specifies the flag to check.
<> 144:ef7eb2e8f9f7 1589 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1590 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
<> 144:ef7eb2e8f9f7 1591 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
<> 144:ef7eb2e8f9f7 1592 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
<> 144:ef7eb2e8f9f7 1593 * @arg @ref RCC_FLAG_HSI14RDY HSI14 oscillator clock ready
<> 144:ef7eb2e8f9f7 1594 @if STM32F038xx
<> 144:ef7eb2e8f9f7 1595 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
<> 144:ef7eb2e8f9f7 1596 @elseif STM32F042x6
<> 144:ef7eb2e8f9f7 1597 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
<> 144:ef7eb2e8f9f7 1598 @elseif STM32F048xx
<> 144:ef7eb2e8f9f7 1599 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
<> 144:ef7eb2e8f9f7 1600 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
<> 144:ef7eb2e8f9f7 1601 @elseif STM32F058xx
<> 144:ef7eb2e8f9f7 1602 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
<> 144:ef7eb2e8f9f7 1603 @elseif STM32F071xB
<> 144:ef7eb2e8f9f7 1604 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
<> 144:ef7eb2e8f9f7 1605 @elseif STM32F072xB
<> 144:ef7eb2e8f9f7 1606 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
<> 144:ef7eb2e8f9f7 1607 @elseif STM32F078xx
<> 144:ef7eb2e8f9f7 1608 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
<> 144:ef7eb2e8f9f7 1609 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
<> 144:ef7eb2e8f9f7 1610 @elseif STM32F091xC
<> 144:ef7eb2e8f9f7 1611 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
<> 144:ef7eb2e8f9f7 1612 @elseif STM32F098xx
<> 144:ef7eb2e8f9f7 1613 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
<> 144:ef7eb2e8f9f7 1614 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
<> 144:ef7eb2e8f9f7 1615 @endif
<> 144:ef7eb2e8f9f7 1616 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
<> 144:ef7eb2e8f9f7 1617 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
<> 144:ef7eb2e8f9f7 1618 * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
<> 144:ef7eb2e8f9f7 1619 * @arg @ref RCC_FLAG_PINRST Pin reset.
<> 144:ef7eb2e8f9f7 1620 * @arg @ref RCC_FLAG_PORRST POR/PDR reset.
<> 144:ef7eb2e8f9f7 1621 * @arg @ref RCC_FLAG_SFTRST Software reset.
<> 144:ef7eb2e8f9f7 1622 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
<> 144:ef7eb2e8f9f7 1623 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
<> 144:ef7eb2e8f9f7 1624 * @arg @ref RCC_FLAG_LPWRRST Low Power reset.
<> 144:ef7eb2e8f9f7 1625 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 1626 */
<> 156:95d6b41a828b 1627 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \
<> 156:95d6b41a828b 1628 (((__FLAG__) >> 5U) == CR2_REG_INDEX)? RCC->CR2 : \
<> 156:95d6b41a828b 1629 (((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
<> 156:95d6b41a828b 1630 RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
<> 144:ef7eb2e8f9f7 1631
<> 144:ef7eb2e8f9f7 1632 /**
<> 144:ef7eb2e8f9f7 1633 * @}
<> 144:ef7eb2e8f9f7 1634 */
<> 144:ef7eb2e8f9f7 1635
<> 144:ef7eb2e8f9f7 1636 /**
<> 144:ef7eb2e8f9f7 1637 * @}
<> 144:ef7eb2e8f9f7 1638 */
<> 144:ef7eb2e8f9f7 1639
<> 144:ef7eb2e8f9f7 1640 /* Include RCC HAL Extension module */
<> 144:ef7eb2e8f9f7 1641 #include "stm32f0xx_hal_rcc_ex.h"
<> 144:ef7eb2e8f9f7 1642
<> 144:ef7eb2e8f9f7 1643 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1644 /** @addtogroup RCC_Exported_Functions
<> 144:ef7eb2e8f9f7 1645 * @{
<> 144:ef7eb2e8f9f7 1646 */
<> 144:ef7eb2e8f9f7 1647
<> 144:ef7eb2e8f9f7 1648 /** @addtogroup RCC_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 1649 * @{
<> 144:ef7eb2e8f9f7 1650 */
<> 144:ef7eb2e8f9f7 1651
<> 144:ef7eb2e8f9f7 1652 /* Initialization and de-initialization functions ******************************/
<> 144:ef7eb2e8f9f7 1653 void HAL_RCC_DeInit(void);
<> 144:ef7eb2e8f9f7 1654 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
<> 144:ef7eb2e8f9f7 1655 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
<> 144:ef7eb2e8f9f7 1656
<> 144:ef7eb2e8f9f7 1657 /**
<> 144:ef7eb2e8f9f7 1658 * @}
<> 144:ef7eb2e8f9f7 1659 */
<> 144:ef7eb2e8f9f7 1660
<> 144:ef7eb2e8f9f7 1661 /** @addtogroup RCC_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 1662 * @{
<> 144:ef7eb2e8f9f7 1663 */
<> 144:ef7eb2e8f9f7 1664
<> 144:ef7eb2e8f9f7 1665 /* Peripheral Control functions ************************************************/
<> 144:ef7eb2e8f9f7 1666 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
<> 144:ef7eb2e8f9f7 1667 void HAL_RCC_EnableCSS(void);
<> 156:95d6b41a828b 1668 /* CSS NMI IRQ handler */
<> 156:95d6b41a828b 1669 void HAL_RCC_NMI_IRQHandler(void);
<> 156:95d6b41a828b 1670 /* User Callbacks in non blocking mode (IT mode) */
<> 156:95d6b41a828b 1671 void HAL_RCC_CSSCallback(void);
<> 144:ef7eb2e8f9f7 1672 void HAL_RCC_DisableCSS(void);
<> 144:ef7eb2e8f9f7 1673 uint32_t HAL_RCC_GetSysClockFreq(void);
<> 144:ef7eb2e8f9f7 1674 uint32_t HAL_RCC_GetHCLKFreq(void);
<> 144:ef7eb2e8f9f7 1675 uint32_t HAL_RCC_GetPCLK1Freq(void);
<> 144:ef7eb2e8f9f7 1676 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
<> 144:ef7eb2e8f9f7 1677 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
<> 144:ef7eb2e8f9f7 1678
<> 144:ef7eb2e8f9f7 1679 /**
<> 144:ef7eb2e8f9f7 1680 * @}
<> 144:ef7eb2e8f9f7 1681 */
<> 144:ef7eb2e8f9f7 1682
<> 144:ef7eb2e8f9f7 1683 /**
<> 144:ef7eb2e8f9f7 1684 * @}
<> 144:ef7eb2e8f9f7 1685 */
<> 144:ef7eb2e8f9f7 1686
<> 144:ef7eb2e8f9f7 1687 /**
<> 144:ef7eb2e8f9f7 1688 * @}
<> 144:ef7eb2e8f9f7 1689 */
<> 144:ef7eb2e8f9f7 1690
<> 144:ef7eb2e8f9f7 1691 /**
<> 144:ef7eb2e8f9f7 1692 * @}
<> 144:ef7eb2e8f9f7 1693 */
<> 144:ef7eb2e8f9f7 1694
<> 144:ef7eb2e8f9f7 1695 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1696 }
<> 144:ef7eb2e8f9f7 1697 #endif
<> 144:ef7eb2e8f9f7 1698
<> 144:ef7eb2e8f9f7 1699 #endif /* __STM32F0xx_HAL_RCC_H */
<> 144:ef7eb2e8f9f7 1700
<> 144:ef7eb2e8f9f7 1701 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 1702