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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_pwr_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of PWR HAL Extension module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F0xx_HAL_PWR_EX_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F0xx_HAL_PWR_EX_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup PWREx
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /** @defgroup PWREx_Exported_Types PWREx Exported Types
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
<> 144:ef7eb2e8f9f7 62 defined (STM32F071xB) || defined (STM32F072xB) || \
<> 144:ef7eb2e8f9f7 63 defined (STM32F091xC)
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /**
<> 144:ef7eb2e8f9f7 66 * @brief PWR PVD configuration structure definition
<> 144:ef7eb2e8f9f7 67 */
<> 144:ef7eb2e8f9f7 68 typedef struct
<> 144:ef7eb2e8f9f7 69 {
<> 144:ef7eb2e8f9f7 70 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level
<> 144:ef7eb2e8f9f7 71 This parameter can be a value of @ref PWREx_PVD_detection_level */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
<> 144:ef7eb2e8f9f7 74 This parameter can be a value of @ref PWREx_PVD_Mode */
<> 144:ef7eb2e8f9f7 75 }PWR_PVDTypeDef;
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
<> 144:ef7eb2e8f9f7 78 /* defined (STM32F071xB) || defined (STM32F072xB) || */
<> 144:ef7eb2e8f9f7 79 /* defined (STM32F091xC) */
<> 144:ef7eb2e8f9f7 80 /**
<> 144:ef7eb2e8f9f7 81 * @}
<> 144:ef7eb2e8f9f7 82 */
<> 144:ef7eb2e8f9f7 83 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
<> 144:ef7eb2e8f9f7 86 * @{
<> 144:ef7eb2e8f9f7 87 */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins
<> 144:ef7eb2e8f9f7 91 * @{
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 94 defined (STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 95 #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
<> 144:ef7eb2e8f9f7 96 #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
<> 144:ef7eb2e8f9f7 97 #define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3)
<> 144:ef7eb2e8f9f7 98 #define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
<> 144:ef7eb2e8f9f7 99 #define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5)
<> 144:ef7eb2e8f9f7 100 #define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
<> 144:ef7eb2e8f9f7 101 #define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
<> 144:ef7eb2e8f9f7 102 #define PWR_WAKEUP_PIN8 ((uint32_t)PWR_CSR_EWUP8)
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
<> 144:ef7eb2e8f9f7 105 ((PIN) == PWR_WAKEUP_PIN2) || \
<> 144:ef7eb2e8f9f7 106 ((PIN) == PWR_WAKEUP_PIN3) || \
<> 144:ef7eb2e8f9f7 107 ((PIN) == PWR_WAKEUP_PIN4) || \
<> 144:ef7eb2e8f9f7 108 ((PIN) == PWR_WAKEUP_PIN5) || \
<> 144:ef7eb2e8f9f7 109 ((PIN) == PWR_WAKEUP_PIN6) || \
<> 144:ef7eb2e8f9f7 110 ((PIN) == PWR_WAKEUP_PIN7) || \
<> 144:ef7eb2e8f9f7 111 ((PIN) == PWR_WAKEUP_PIN8))
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 #elif defined(STM32F030xC) || defined (STM32F070xB)
<> 144:ef7eb2e8f9f7 114 #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
<> 144:ef7eb2e8f9f7 115 #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
<> 144:ef7eb2e8f9f7 116 #define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
<> 144:ef7eb2e8f9f7 117 #define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5)
<> 144:ef7eb2e8f9f7 118 #define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
<> 144:ef7eb2e8f9f7 119 #define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
<> 144:ef7eb2e8f9f7 122 ((PIN) == PWR_WAKEUP_PIN2) || \
<> 144:ef7eb2e8f9f7 123 ((PIN) == PWR_WAKEUP_PIN4) || \
<> 144:ef7eb2e8f9f7 124 ((PIN) == PWR_WAKEUP_PIN5) || \
<> 144:ef7eb2e8f9f7 125 ((PIN) == PWR_WAKEUP_PIN6) || \
<> 144:ef7eb2e8f9f7 126 ((PIN) == PWR_WAKEUP_PIN7))
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 #elif defined(STM32F042x6) || defined (STM32F048xx)
<> 144:ef7eb2e8f9f7 129 #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
<> 144:ef7eb2e8f9f7 130 #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
<> 144:ef7eb2e8f9f7 131 #define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
<> 144:ef7eb2e8f9f7 132 #define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
<> 144:ef7eb2e8f9f7 133 #define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
<> 144:ef7eb2e8f9f7 136 ((PIN) == PWR_WAKEUP_PIN2) || \
<> 144:ef7eb2e8f9f7 137 ((PIN) == PWR_WAKEUP_PIN4) || \
<> 144:ef7eb2e8f9f7 138 ((PIN) == PWR_WAKEUP_PIN6) || \
<> 144:ef7eb2e8f9f7 139 ((PIN) == PWR_WAKEUP_PIN7))
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 #else
<> 144:ef7eb2e8f9f7 142 #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
<> 144:ef7eb2e8f9f7 143 #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
<> 144:ef7eb2e8f9f7 147 ((PIN) == PWR_WAKEUP_PIN2))
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 #endif
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /**
<> 144:ef7eb2e8f9f7 152 * @}
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /** @defgroup PWREx_EXTI_Line PWREx EXTI Line
<> 144:ef7eb2e8f9f7 156 * @{
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
<> 144:ef7eb2e8f9f7 159 defined (STM32F071xB) || defined (STM32F072xB) || \
<> 144:ef7eb2e8f9f7 160 defined (STM32F091xC)
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 #define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
<> 144:ef7eb2e8f9f7 165 /* defined (STM32F071xB) || defined (STM32F072xB) || */
<> 144:ef7eb2e8f9f7 166 /* defined (STM32F091xC) */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 #if defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 169 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 170 defined (STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 #define PWR_EXTI_LINE_VDDIO2 ((uint32_t)EXTI_IMR_MR31) /*!< External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 #endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\
<> 144:ef7eb2e8f9f7 175 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 176 defined (STM32F091xC) || defined (STM32F098xx) ||*/
<> 144:ef7eb2e8f9f7 177 /**
<> 144:ef7eb2e8f9f7 178 * @}
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
<> 144:ef7eb2e8f9f7 182 defined (STM32F071xB) || defined (STM32F072xB) || \
<> 144:ef7eb2e8f9f7 183 defined (STM32F091xC)
<> 144:ef7eb2e8f9f7 184 /** @defgroup PWREx_PVD_detection_level PWREx PVD detection level
<> 144:ef7eb2e8f9f7 185 * @{
<> 144:ef7eb2e8f9f7 186 */
<> 144:ef7eb2e8f9f7 187 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
<> 144:ef7eb2e8f9f7 188 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
<> 144:ef7eb2e8f9f7 189 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
<> 144:ef7eb2e8f9f7 190 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
<> 144:ef7eb2e8f9f7 191 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
<> 144:ef7eb2e8f9f7 192 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
<> 144:ef7eb2e8f9f7 193 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
<> 144:ef7eb2e8f9f7 194 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7
<> 144:ef7eb2e8f9f7 195 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
<> 144:ef7eb2e8f9f7 196 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
<> 144:ef7eb2e8f9f7 197 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
<> 144:ef7eb2e8f9f7 198 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
<> 144:ef7eb2e8f9f7 199 /**
<> 144:ef7eb2e8f9f7 200 * @}
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /** @defgroup PWREx_PVD_Mode PWREx PVD Mode
<> 144:ef7eb2e8f9f7 204 * @{
<> 144:ef7eb2e8f9f7 205 */
<> 156:95d6b41a828b 206 #define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< basic mode is used */
<> 156:95d6b41a828b 207 #define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
<> 156:95d6b41a828b 208 #define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
<> 156:95d6b41a828b 209 #define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
<> 156:95d6b41a828b 210 #define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */
<> 156:95d6b41a828b 211 #define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */
<> 156:95d6b41a828b 212 #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
<> 144:ef7eb2e8f9f7 215 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
<> 144:ef7eb2e8f9f7 216 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
<> 144:ef7eb2e8f9f7 217 ((MODE) == PWR_PVD_MODE_NORMAL))
<> 144:ef7eb2e8f9f7 218 /**
<> 144:ef7eb2e8f9f7 219 * @}
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
<> 144:ef7eb2e8f9f7 222 /* defined (STM32F071xB) || defined (STM32F072xB) || */
<> 144:ef7eb2e8f9f7 223 /* defined (STM32F091xC) */
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /** @defgroup PWREx_Flag PWREx Flag
<> 144:ef7eb2e8f9f7 226 * @{
<> 144:ef7eb2e8f9f7 227 */
<> 144:ef7eb2e8f9f7 228 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
<> 144:ef7eb2e8f9f7 229 defined (STM32F071xB) || defined (STM32F072xB) || \
<> 144:ef7eb2e8f9f7 230 defined (STM32F091xC)
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 #define PWR_FLAG_WU PWR_CSR_WUF
<> 144:ef7eb2e8f9f7 233 #define PWR_FLAG_SB PWR_CSR_SBF
<> 144:ef7eb2e8f9f7 234 #define PWR_FLAG_PVDO PWR_CSR_PVDO
<> 144:ef7eb2e8f9f7 235 #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
<> 144:ef7eb2e8f9f7 236 #elif defined (STM32F070x6) || defined (STM32F070xB) || defined (STM32F030xC)
<> 144:ef7eb2e8f9f7 237 #define PWR_FLAG_WU PWR_CSR_WUF
<> 144:ef7eb2e8f9f7 238 #define PWR_FLAG_SB PWR_CSR_SBF
<> 144:ef7eb2e8f9f7 239 #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
<> 144:ef7eb2e8f9f7 240 #else
<> 144:ef7eb2e8f9f7 241 #define PWR_FLAG_WU PWR_CSR_WUF
<> 144:ef7eb2e8f9f7 242 #define PWR_FLAG_SB PWR_CSR_SBF
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
<> 144:ef7eb2e8f9f7 245 /* defined (STM32F071xB) || defined (STM32F072xB) || */
<> 144:ef7eb2e8f9f7 246 /* defined (STM32F091xC) */
<> 144:ef7eb2e8f9f7 247 /**
<> 144:ef7eb2e8f9f7 248 * @}
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /**
<> 144:ef7eb2e8f9f7 252 * @}
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 256 /** @defgroup PWREx_Exported_Macros PWREx Exported Macros
<> 144:ef7eb2e8f9f7 257 * @{
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
<> 144:ef7eb2e8f9f7 260 defined (STM32F071xB) || defined (STM32F072xB) || \
<> 144:ef7eb2e8f9f7 261 defined (STM32F091xC)
<> 144:ef7eb2e8f9f7 262 /**
<> 144:ef7eb2e8f9f7 263 * @brief Enable interrupt on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 264 * @retval None.
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /**
<> 144:ef7eb2e8f9f7 269 * @brief Disable interrupt on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 270 * @retval None.
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @brief Enable event on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 276 * @retval None.
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /**
<> 144:ef7eb2e8f9f7 281 * @brief Disable event on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 282 * @retval None.
<> 144:ef7eb2e8f9f7 283 */
<> 144:ef7eb2e8f9f7 284 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /**
<> 144:ef7eb2e8f9f7 287 * @brief Disable the PVD Extended Interrupt Rising Trigger.
<> 144:ef7eb2e8f9f7 288 * @retval None.
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /**
<> 144:ef7eb2e8f9f7 293 * @brief Disable the PVD Extended Interrupt Falling Trigger.
<> 144:ef7eb2e8f9f7 294 * @retval None.
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /**
<> 144:ef7eb2e8f9f7 299 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
<> 144:ef7eb2e8f9f7 300 * @retval None
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /**
<> 144:ef7eb2e8f9f7 306 * @brief PVD EXTI line configuration: set falling edge trigger.
<> 144:ef7eb2e8f9f7 307 * @retval None.
<> 144:ef7eb2e8f9f7 308 */
<> 144:ef7eb2e8f9f7 309 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /**
<> 144:ef7eb2e8f9f7 312 * @brief PVD EXTI line configuration: set rising edge trigger.
<> 144:ef7eb2e8f9f7 313 * @retval None.
<> 144:ef7eb2e8f9f7 314 */
<> 144:ef7eb2e8f9f7 315 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /**
<> 144:ef7eb2e8f9f7 318 * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
<> 144:ef7eb2e8f9f7 319 * @retval None
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /**
<> 144:ef7eb2e8f9f7 324 * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
<> 144:ef7eb2e8f9f7 325 * @retval EXTI PVD Line Status.
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /**
<> 144:ef7eb2e8f9f7 330 * @brief Clear the PVD EXTI flag.
<> 144:ef7eb2e8f9f7 331 * @retval None.
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /**
<> 144:ef7eb2e8f9f7 336 * @brief Generate a Software interrupt on selected EXTI line.
<> 144:ef7eb2e8f9f7 337 * @retval None.
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
<> 144:ef7eb2e8f9f7 342 /* defined (STM32F071xB) || defined (STM32F072xB) || */
<> 144:ef7eb2e8f9f7 343 /* defined (STM32F091xC) */
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 #if defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 347 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 348 defined (STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 349 /**
<> 144:ef7eb2e8f9f7 350 * @brief Enable interrupt on Vddio2 Monitor Exti Line 31.
<> 144:ef7eb2e8f9f7 351 * @retval None.
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353 #define __HAL_PWR_VDDIO2_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_VDDIO2))
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /**
<> 144:ef7eb2e8f9f7 356 * @brief Disable interrupt on Vddio2 Monitor Exti Line 31.
<> 144:ef7eb2e8f9f7 357 * @retval None.
<> 144:ef7eb2e8f9f7 358 */
<> 144:ef7eb2e8f9f7 359 #define __HAL_PWR_VDDIO2_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_VDDIO2))
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /**
<> 144:ef7eb2e8f9f7 362 * @brief Vddio2 Monitor EXTI line configuration: clear falling edge and rising edge trigger.
<> 144:ef7eb2e8f9f7 363 * @retval None.
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365 #define __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() \
<> 144:ef7eb2e8f9f7 366 do{ \
<> 144:ef7eb2e8f9f7 367 EXTI->FTSR &= ~(PWR_EXTI_LINE_VDDIO2); \
<> 144:ef7eb2e8f9f7 368 EXTI->RTSR &= ~(PWR_EXTI_LINE_VDDIO2); \
<> 144:ef7eb2e8f9f7 369 } while(0)
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /**
<> 144:ef7eb2e8f9f7 372 * @brief Vddio2 Monitor EXTI line configuration: set falling edge trigger.
<> 144:ef7eb2e8f9f7 373 * @retval None.
<> 144:ef7eb2e8f9f7 374 */
<> 144:ef7eb2e8f9f7 375 #define __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_VDDIO2)
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /**
<> 144:ef7eb2e8f9f7 378 * @brief Check whether the specified VDDIO2 monitor EXTI interrupt flag is set or not.
<> 144:ef7eb2e8f9f7 379 * @retval EXTI VDDIO2 Monitor Line Status.
<> 144:ef7eb2e8f9f7 380 */
<> 144:ef7eb2e8f9f7 381 #define __HAL_PWR_VDDIO2_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_VDDIO2))
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /**
<> 144:ef7eb2e8f9f7 384 * @brief Clear the VDDIO2 Monitor EXTI flag.
<> 144:ef7eb2e8f9f7 385 * @retval None.
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_VDDIO2))
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /**
<> 144:ef7eb2e8f9f7 390 * @brief Generate a Software interrupt on selected EXTI line.
<> 144:ef7eb2e8f9f7 391 * @retval None.
<> 144:ef7eb2e8f9f7 392 */
<> 144:ef7eb2e8f9f7 393 #define __HAL_PWR_VDDIO2_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_VDDIO2))
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 #endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\
<> 144:ef7eb2e8f9f7 397 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 398 defined (STM32F091xC) || defined (STM32F098xx) */
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /**
<> 144:ef7eb2e8f9f7 401 * @}
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
<> 144:ef7eb2e8f9f7 407 * @{
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /** @addtogroup PWREx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 411 * @{
<> 144:ef7eb2e8f9f7 412 */
<> 144:ef7eb2e8f9f7 413 /* I/O operation functions ***************************************************/
<> 144:ef7eb2e8f9f7 414 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
<> 144:ef7eb2e8f9f7 415 defined (STM32F071xB) || defined (STM32F072xB) || \
<> 144:ef7eb2e8f9f7 416 defined (STM32F091xC)
<> 144:ef7eb2e8f9f7 417 void HAL_PWR_PVD_IRQHandler(void);
<> 144:ef7eb2e8f9f7 418 void HAL_PWR_PVDCallback(void);
<> 144:ef7eb2e8f9f7 419 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
<> 144:ef7eb2e8f9f7 420 /* defined (STM32F071xB) || defined (STM32F072xB) || */
<> 144:ef7eb2e8f9f7 421 /* defined (STM32F091xC) */
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 #if defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 424 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 425 defined (STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 426 void HAL_PWREx_Vddio2Monitor_IRQHandler(void);
<> 144:ef7eb2e8f9f7 427 void HAL_PWREx_Vddio2MonitorCallback(void);
<> 144:ef7eb2e8f9f7 428 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 429 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 430 defined (STM32F091xC) || defined (STM32F098xx) */
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /* Peripheral Control functions **********************************************/
<> 144:ef7eb2e8f9f7 433 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
<> 144:ef7eb2e8f9f7 434 defined (STM32F071xB) || defined (STM32F072xB) || \
<> 144:ef7eb2e8f9f7 435 defined (STM32F091xC)
<> 144:ef7eb2e8f9f7 436 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
<> 144:ef7eb2e8f9f7 437 void HAL_PWR_EnablePVD(void);
<> 144:ef7eb2e8f9f7 438 void HAL_PWR_DisablePVD(void);
<> 144:ef7eb2e8f9f7 439 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
<> 144:ef7eb2e8f9f7 440 /* defined (STM32F071xB) || defined (STM32F072xB) || */
<> 144:ef7eb2e8f9f7 441 /* defined (STM32F091xC) */
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 #if defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 444 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 445 defined (STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 446 void HAL_PWREx_EnableVddio2Monitor(void);
<> 144:ef7eb2e8f9f7 447 void HAL_PWREx_DisableVddio2Monitor(void);
<> 144:ef7eb2e8f9f7 448 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 449 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
<> 144:ef7eb2e8f9f7 450 defined (STM32F091xC) || defined (STM32F098xx) */
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /**
<> 144:ef7eb2e8f9f7 453 * @}
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /**
<> 144:ef7eb2e8f9f7 457 * @}
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /**
<> 144:ef7eb2e8f9f7 461 * @}
<> 144:ef7eb2e8f9f7 462 */
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /**
<> 144:ef7eb2e8f9f7 465 * @}
<> 144:ef7eb2e8f9f7 466 */
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 469 }
<> 144:ef7eb2e8f9f7 470 #endif
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 #endif /* __STM32F0xx_HAL_PWR_EX_H */
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 475