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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_iwdg.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of IWDG HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F0xx_HAL_IWDG_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F0xx_HAL_IWDG_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 156:95d6b41a828b 51 /** @defgroup IWDG IWDG
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56 /** @defgroup IWDG_Exported_Types IWDG Exported Types
<> 144:ef7eb2e8f9f7 57 * @{
<> 144:ef7eb2e8f9f7 58 */
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /**
<> 144:ef7eb2e8f9f7 61 * @brief IWDG Init structure definition
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63 typedef struct
<> 144:ef7eb2e8f9f7 64 {
<> 144:ef7eb2e8f9f7 65 uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
<> 144:ef7eb2e8f9f7 66 This parameter can be a value of @ref IWDG_Prescaler */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
<> 144:ef7eb2e8f9f7 69 This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
<> 144:ef7eb2e8f9f7 72 This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 } IWDG_InitTypeDef;
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /**
<> 144:ef7eb2e8f9f7 77 * @brief IWDG Handle Structure definition
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79 typedef struct
<> 144:ef7eb2e8f9f7 80 {
<> 144:ef7eb2e8f9f7 81 IWDG_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 IWDG_InitTypeDef Init; /*!< IWDG required parameters */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 }IWDG_HandleTypeDef;
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /**
<> 144:ef7eb2e8f9f7 88 * @}
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 92 /** @defgroup IWDG_Exported_Constants IWDG Exported Constants
<> 144:ef7eb2e8f9f7 93 * @{
<> 144:ef7eb2e8f9f7 94 */
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /** @defgroup IWDG_Prescaler IWDG Prescaler
<> 144:ef7eb2e8f9f7 97 * @{
<> 144:ef7eb2e8f9f7 98 */
<> 156:95d6b41a828b 99 #define IWDG_PRESCALER_4 0x00000000U /*!< IWDG prescaler set to 4 */
<> 156:95d6b41a828b 100 #define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
<> 156:95d6b41a828b 101 #define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
<> 156:95d6b41a828b 102 #define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
<> 156:95d6b41a828b 103 #define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
<> 156:95d6b41a828b 104 #define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
<> 156:95d6b41a828b 105 #define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
<> 144:ef7eb2e8f9f7 106 /**
<> 144:ef7eb2e8f9f7 107 * @}
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 156:95d6b41a828b 110 /** @defgroup IWDG_Window_option IWDG Window option
<> 144:ef7eb2e8f9f7 111 * @{
<> 144:ef7eb2e8f9f7 112 */
<> 156:95d6b41a828b 113 #define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
<> 144:ef7eb2e8f9f7 114 /**
<> 144:ef7eb2e8f9f7 115 * @}
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /**
<> 144:ef7eb2e8f9f7 119 * @}
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 123 /** @defgroup IWDG_Exported_Macros IWDG Exported Macros
<> 144:ef7eb2e8f9f7 124 * @{
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /**
<> 144:ef7eb2e8f9f7 128 * @brief Enable the IWDG peripheral.
<> 156:95d6b41a828b 129 * @param __HANDLE__ IWDG handle
<> 144:ef7eb2e8f9f7 130 * @retval None
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132 #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /**
<> 156:95d6b41a828b 135 * @brief Reload IWDG counter with value defined in the reload register
<> 156:95d6b41a828b 136 * (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
<> 156:95d6b41a828b 137 * @param __HANDLE__ IWDG handle
<> 144:ef7eb2e8f9f7 138 * @retval None
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /**
<> 144:ef7eb2e8f9f7 143 * @}
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /* Exported functions --------------------------------------------------------*/
<> 156:95d6b41a828b 147 /** @defgroup IWDG_Exported_Functions IWDG Exported Functions
<> 144:ef7eb2e8f9f7 148 * @{
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150
<> 156:95d6b41a828b 151 /** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
<> 144:ef7eb2e8f9f7 152 * @{
<> 144:ef7eb2e8f9f7 153 */
<> 156:95d6b41a828b 154 /* Initialization/Start functions ********************************************/
<> 144:ef7eb2e8f9f7 155 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
<> 144:ef7eb2e8f9f7 156 /**
<> 144:ef7eb2e8f9f7 157 * @}
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159
<> 156:95d6b41a828b 160 /** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 161 * @{
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163 /* I/O operation functions ****************************************************/
<> 144:ef7eb2e8f9f7 164 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
<> 144:ef7eb2e8f9f7 165 /**
<> 144:ef7eb2e8f9f7 166 * @}
<> 144:ef7eb2e8f9f7 167 */
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /**
<> 144:ef7eb2e8f9f7 170 * @}
<> 144:ef7eb2e8f9f7 171 */
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /* Private constants ---------------------------------------------------------*/
<> 156:95d6b41a828b 174 /** @defgroup IWDG_Private_Constants IWDG Private Constants
<> 144:ef7eb2e8f9f7 175 * @{
<> 144:ef7eb2e8f9f7 176 */
<> 156:95d6b41a828b 177
<> 144:ef7eb2e8f9f7 178 /**
<> 144:ef7eb2e8f9f7 179 * @brief IWDG Key Register BitMask
<> 144:ef7eb2e8f9f7 180 */
<> 156:95d6b41a828b 181 #define IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
<> 156:95d6b41a828b 182 #define IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
<> 156:95d6b41a828b 183 #define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
<> 156:95d6b41a828b 184 #define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /**
<> 144:ef7eb2e8f9f7 187 * @}
<> 144:ef7eb2e8f9f7 188 */
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 191 /** @defgroup IWDG_Private_Macros IWDG Private Macros
<> 144:ef7eb2e8f9f7 192 * @{
<> 144:ef7eb2e8f9f7 193 */
<> 156:95d6b41a828b 194
<> 144:ef7eb2e8f9f7 195 /**
<> 156:95d6b41a828b 196 * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
<> 156:95d6b41a828b 197 * @param __HANDLE__ IWDG handle
<> 144:ef7eb2e8f9f7 198 * @retval None
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /**
<> 156:95d6b41a828b 203 * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
<> 156:95d6b41a828b 204 * @param __HANDLE__ IWDG handle
<> 144:ef7eb2e8f9f7 205 * @retval None
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /**
<> 144:ef7eb2e8f9f7 210 * @brief Check IWDG prescaler value.
<> 156:95d6b41a828b 211 * @param __PRESCALER__ IWDG prescaler value
<> 144:ef7eb2e8f9f7 212 * @retval None
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214 #define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
<> 144:ef7eb2e8f9f7 215 ((__PRESCALER__) == IWDG_PRESCALER_8) || \
<> 144:ef7eb2e8f9f7 216 ((__PRESCALER__) == IWDG_PRESCALER_16) || \
<> 144:ef7eb2e8f9f7 217 ((__PRESCALER__) == IWDG_PRESCALER_32) || \
<> 144:ef7eb2e8f9f7 218 ((__PRESCALER__) == IWDG_PRESCALER_64) || \
<> 144:ef7eb2e8f9f7 219 ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
<> 144:ef7eb2e8f9f7 220 ((__PRESCALER__) == IWDG_PRESCALER_256))
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /**
<> 144:ef7eb2e8f9f7 223 * @brief Check IWDG reload value.
<> 156:95d6b41a828b 224 * @param __RELOAD__ IWDG reload value
<> 144:ef7eb2e8f9f7 225 * @retval None
<> 144:ef7eb2e8f9f7 226 */
<> 156:95d6b41a828b 227 #define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /**
<> 144:ef7eb2e8f9f7 230 * @brief Check IWDG window value.
<> 156:95d6b41a828b 231 * @param __WINDOW__ IWDG window value
<> 144:ef7eb2e8f9f7 232 * @retval None
<> 144:ef7eb2e8f9f7 233 */
<> 156:95d6b41a828b 234 #define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /**
<> 144:ef7eb2e8f9f7 237 * @}
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /**
<> 144:ef7eb2e8f9f7 241 * @}
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /**
<> 144:ef7eb2e8f9f7 245 * @}
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 250 }
<> 144:ef7eb2e8f9f7 251 #endif
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 #endif /* __STM32F0xx_HAL_IWDG_H */
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 256