mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_irda.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 180:96ed750bd169
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f0xx_hal_irda.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @brief IRDA HAL module driver. |
<> | 144:ef7eb2e8f9f7 | 6 | * This file provides firmware functions to manage the following |
<> | 144:ef7eb2e8f9f7 | 7 | * functionalities of the IrDA (Infrared Data Association) Peripheral |
<> | 144:ef7eb2e8f9f7 | 8 | * (IRDA) |
<> | 144:ef7eb2e8f9f7 | 9 | * + Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 10 | * + IO operation functions |
<> | 144:ef7eb2e8f9f7 | 11 | * + Peripheral State and Errors functions |
<> | 144:ef7eb2e8f9f7 | 12 | * + Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 13 | * |
<> | 144:ef7eb2e8f9f7 | 14 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 15 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 16 | ##### How to use this driver ##### |
<> | 144:ef7eb2e8f9f7 | 17 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 18 | [..] |
<> | 144:ef7eb2e8f9f7 | 19 | The IRDA HAL driver can be used as follows: |
<> | 144:ef7eb2e8f9f7 | 20 | |
<> | 144:ef7eb2e8f9f7 | 21 | (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda). |
<> | 144:ef7eb2e8f9f7 | 22 | (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API |
<> | 144:ef7eb2e8f9f7 | 23 | in setting the associated USART or UART in IRDA mode: |
<> | 144:ef7eb2e8f9f7 | 24 | (++) Enable the USARTx/UARTx interface clock. |
<> | 144:ef7eb2e8f9f7 | 25 | (++) USARTx/UARTx pins configuration: |
<> | 144:ef7eb2e8f9f7 | 26 | (+++) Enable the clock for the USARTx/UARTx GPIOs. |
<> | 144:ef7eb2e8f9f7 | 27 | (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input). |
<> | 144:ef7eb2e8f9f7 | 28 | (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT() |
<> | 144:ef7eb2e8f9f7 | 29 | and HAL_IRDA_Receive_IT() APIs): |
<> | 144:ef7eb2e8f9f7 | 30 | (+++) Configure the USARTx/UARTx interrupt priority. |
<> | 144:ef7eb2e8f9f7 | 31 | (+++) Enable the NVIC USARTx/UARTx IRQ handle. |
<> | 144:ef7eb2e8f9f7 | 32 | (+++) The specific IRDA interrupts (Transmission complete interrupt, |
<> | 144:ef7eb2e8f9f7 | 33 | RXNE interrupt and Error Interrupts) will be managed using the macros |
<> | 144:ef7eb2e8f9f7 | 34 | __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. |
<> | 144:ef7eb2e8f9f7 | 35 | |
<> | 144:ef7eb2e8f9f7 | 36 | (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA() |
<> | 144:ef7eb2e8f9f7 | 37 | and HAL_IRDA_Receive_DMA() APIs): |
<> | 144:ef7eb2e8f9f7 | 38 | (+++) Declare a DMA handle structure for the Tx/Rx channel. |
<> | 144:ef7eb2e8f9f7 | 39 | (+++) Enable the DMAx interface clock. |
<> | 144:ef7eb2e8f9f7 | 40 | (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. |
<> | 144:ef7eb2e8f9f7 | 41 | (+++) Configure the DMA Tx/Rx channel. |
<> | 144:ef7eb2e8f9f7 | 42 | (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle. |
<> | 144:ef7eb2e8f9f7 | 43 | (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. |
<> | 144:ef7eb2e8f9f7 | 44 | |
<> | 144:ef7eb2e8f9f7 | 45 | (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter), |
<> | 144:ef7eb2e8f9f7 | 46 | the normal or low power mode and the clock prescaler in the hirda handle Init structure. |
<> | 144:ef7eb2e8f9f7 | 47 | |
<> | 144:ef7eb2e8f9f7 | 48 | (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API: |
<> | 144:ef7eb2e8f9f7 | 49 | (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) |
<> | 144:ef7eb2e8f9f7 | 50 | by calling the customized HAL_IRDA_MspInit() API. |
<> | 144:ef7eb2e8f9f7 | 51 | |
<> | 144:ef7eb2e8f9f7 | 52 | -@@- The specific IRDA interrupts (Transmission complete interrupt, |
<> | 144:ef7eb2e8f9f7 | 53 | RXNE interrupt and Error Interrupts) will be managed using the macros |
<> | 144:ef7eb2e8f9f7 | 54 | __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. |
<> | 144:ef7eb2e8f9f7 | 55 | |
<> | 144:ef7eb2e8f9f7 | 56 | (#) Three operation modes are available within this driver : |
<> | 144:ef7eb2e8f9f7 | 57 | |
<> | 144:ef7eb2e8f9f7 | 58 | *** Polling mode IO operation *** |
<> | 144:ef7eb2e8f9f7 | 59 | ================================= |
<> | 144:ef7eb2e8f9f7 | 60 | [..] |
<> | 144:ef7eb2e8f9f7 | 61 | (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit() |
<> | 144:ef7eb2e8f9f7 | 62 | (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive() |
<> | 144:ef7eb2e8f9f7 | 63 | |
<> | 144:ef7eb2e8f9f7 | 64 | *** Interrupt mode IO operation *** |
<> | 144:ef7eb2e8f9f7 | 65 | =================================== |
<> | 144:ef7eb2e8f9f7 | 66 | [..] |
<> | 144:ef7eb2e8f9f7 | 67 | (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT() |
<> | 144:ef7eb2e8f9f7 | 68 | (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 69 | add his own code by customization of function pointer HAL_IRDA_TxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 70 | (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT() |
<> | 144:ef7eb2e8f9f7 | 71 | (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 72 | add his own code by customization of function pointer HAL_IRDA_RxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 73 | (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can |
<> | 144:ef7eb2e8f9f7 | 74 | add his own code by customization of function pointer HAL_IRDA_ErrorCallback() |
<> | 144:ef7eb2e8f9f7 | 75 | |
<> | 144:ef7eb2e8f9f7 | 76 | *** DMA mode IO operation *** |
<> | 144:ef7eb2e8f9f7 | 77 | ============================== |
<> | 144:ef7eb2e8f9f7 | 78 | [..] |
<> | 144:ef7eb2e8f9f7 | 79 | (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA() |
<> | 144:ef7eb2e8f9f7 | 80 | (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 81 | add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 82 | (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 83 | add his own code by customization of function pointer HAL_IRDA_TxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 84 | (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA() |
<> | 144:ef7eb2e8f9f7 | 85 | (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 86 | add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 87 | (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 88 | add his own code by customization of function pointer HAL_IRDA_RxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 89 | (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can |
<> | 144:ef7eb2e8f9f7 | 90 | add his own code by customization of function pointer HAL_IRDA_ErrorCallback() |
<> | 144:ef7eb2e8f9f7 | 91 | |
<> | 144:ef7eb2e8f9f7 | 92 | *** IRDA HAL driver macros list *** |
<> | 144:ef7eb2e8f9f7 | 93 | ==================================== |
<> | 144:ef7eb2e8f9f7 | 94 | [..] |
<> | 144:ef7eb2e8f9f7 | 95 | Below the list of most used macros in IRDA HAL driver. |
<> | 144:ef7eb2e8f9f7 | 96 | |
<> | 144:ef7eb2e8f9f7 | 97 | (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral |
<> | 144:ef7eb2e8f9f7 | 98 | (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral |
<> | 144:ef7eb2e8f9f7 | 99 | (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not |
<> | 144:ef7eb2e8f9f7 | 100 | (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag |
<> | 144:ef7eb2e8f9f7 | 101 | (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt |
<> | 144:ef7eb2e8f9f7 | 102 | (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt |
<> | 144:ef7eb2e8f9f7 | 103 | (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled |
<> | 144:ef7eb2e8f9f7 | 104 | |
<> | 144:ef7eb2e8f9f7 | 105 | [..] |
<> | 144:ef7eb2e8f9f7 | 106 | (@) You can refer to the IRDA HAL driver header file for more useful macros |
<> | 144:ef7eb2e8f9f7 | 107 | |
<> | 144:ef7eb2e8f9f7 | 108 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 109 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 110 | * @attention |
<> | 144:ef7eb2e8f9f7 | 111 | * |
<> | 144:ef7eb2e8f9f7 | 112 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 113 | * |
<> | 144:ef7eb2e8f9f7 | 114 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 115 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 116 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 117 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 118 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 119 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 120 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 121 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 122 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 123 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 124 | * |
<> | 144:ef7eb2e8f9f7 | 125 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 126 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 127 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 128 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 129 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 130 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 131 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 132 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 133 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 134 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 135 | * |
<> | 144:ef7eb2e8f9f7 | 136 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 137 | */ |
<> | 144:ef7eb2e8f9f7 | 138 | |
<> | 144:ef7eb2e8f9f7 | 139 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 140 | #include "stm32f0xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 141 | |
<> | 144:ef7eb2e8f9f7 | 142 | #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) |
<> | 144:ef7eb2e8f9f7 | 143 | |
<> | 144:ef7eb2e8f9f7 | 144 | /** @addtogroup STM32F0xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 145 | * @{ |
<> | 144:ef7eb2e8f9f7 | 146 | */ |
<> | 144:ef7eb2e8f9f7 | 147 | |
<> | 144:ef7eb2e8f9f7 | 148 | /** @defgroup IRDA IRDA |
<> | 144:ef7eb2e8f9f7 | 149 | * @brief HAL IRDA module driver |
<> | 144:ef7eb2e8f9f7 | 150 | * @{ |
<> | 144:ef7eb2e8f9f7 | 151 | */ |
<> | 144:ef7eb2e8f9f7 | 152 | |
<> | 156:95d6b41a828b | 153 | #ifdef HAL_IRDA_MODULE_ENABLED |
<> | 156:95d6b41a828b | 154 | |
<> | 144:ef7eb2e8f9f7 | 155 | /* Private typedef -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 156 | /* Private define ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 157 | /** @defgroup IRDA_Private_Constants IRDA Private Constants |
<> | 144:ef7eb2e8f9f7 | 158 | * @{ |
<> | 144:ef7eb2e8f9f7 | 159 | */ |
<> | 156:95d6b41a828b | 160 | #define IRDA_TEACK_REACK_TIMEOUT 1000U /*!< IRDA TX or RX enable acknowledge time-out value */ |
<> | 144:ef7eb2e8f9f7 | 161 | #define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \ |
<> | 144:ef7eb2e8f9f7 | 162 | | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */ |
<> | 144:ef7eb2e8f9f7 | 163 | /** |
<> | 144:ef7eb2e8f9f7 | 164 | * @} |
<> | 144:ef7eb2e8f9f7 | 165 | */ |
<> | 144:ef7eb2e8f9f7 | 166 | |
<> | 144:ef7eb2e8f9f7 | 167 | /* Private macros ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 168 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 169 | /* Private function prototypes -----------------------------------------------*/ |
<> | 156:95d6b41a828b | 170 | /** @addtogroup IRDA_Private_Functions |
<> | 144:ef7eb2e8f9f7 | 171 | * @{ |
<> | 144:ef7eb2e8f9f7 | 172 | */ |
<> | 144:ef7eb2e8f9f7 | 173 | static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda); |
<> | 144:ef7eb2e8f9f7 | 174 | static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda); |
<> | 156:95d6b41a828b | 175 | static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); |
<> | 156:95d6b41a828b | 176 | static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda); |
<> | 156:95d6b41a828b | 177 | static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda); |
<> | 144:ef7eb2e8f9f7 | 178 | static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 179 | static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 180 | static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 181 | static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 182 | static void IRDA_DMAError(DMA_HandleTypeDef *hdma); |
<> | 156:95d6b41a828b | 183 | static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma); |
<> | 156:95d6b41a828b | 184 | static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma); |
<> | 156:95d6b41a828b | 185 | static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma); |
<> | 156:95d6b41a828b | 186 | static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); |
<> | 156:95d6b41a828b | 187 | static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); |
<> | 156:95d6b41a828b | 188 | static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); |
<> | 156:95d6b41a828b | 189 | static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); |
<> | 156:95d6b41a828b | 190 | static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); |
<> | 144:ef7eb2e8f9f7 | 191 | /** |
<> | 144:ef7eb2e8f9f7 | 192 | * @} |
<> | 144:ef7eb2e8f9f7 | 193 | */ |
<> | 144:ef7eb2e8f9f7 | 194 | |
<> | 144:ef7eb2e8f9f7 | 195 | /* Exported functions --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 196 | |
<> | 144:ef7eb2e8f9f7 | 197 | /** @defgroup IRDA_Exported_Functions IRDA Exported Functions |
<> | 144:ef7eb2e8f9f7 | 198 | * @{ |
<> | 144:ef7eb2e8f9f7 | 199 | */ |
<> | 144:ef7eb2e8f9f7 | 200 | |
<> | 144:ef7eb2e8f9f7 | 201 | /** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 202 | * @brief Initialization and Configuration functions |
<> | 144:ef7eb2e8f9f7 | 203 | * |
<> | 144:ef7eb2e8f9f7 | 204 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 205 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 206 | ##### Initialization and Configuration functions ##### |
<> | 144:ef7eb2e8f9f7 | 207 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 208 | [..] |
<> | 144:ef7eb2e8f9f7 | 209 | This subsection provides a set of functions allowing to initialize the USARTx |
<> | 144:ef7eb2e8f9f7 | 210 | in asynchronous IRDA mode. |
<> | 144:ef7eb2e8f9f7 | 211 | (+) For the asynchronous mode only these parameters can be configured: |
<> | 144:ef7eb2e8f9f7 | 212 | (++) Baud Rate |
<> | 144:ef7eb2e8f9f7 | 213 | (++) Word Length |
<> | 144:ef7eb2e8f9f7 | 214 | (++) Parity |
<> | 144:ef7eb2e8f9f7 | 215 | (++) Power mode |
<> | 144:ef7eb2e8f9f7 | 216 | (++) Prescaler setting |
<> | 144:ef7eb2e8f9f7 | 217 | (++) Receiver/transmitter modes |
<> | 144:ef7eb2e8f9f7 | 218 | |
<> | 144:ef7eb2e8f9f7 | 219 | [..] |
<> | 144:ef7eb2e8f9f7 | 220 | The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures |
<> | 144:ef7eb2e8f9f7 | 221 | (details for the procedures are available in reference manual). |
<> | 144:ef7eb2e8f9f7 | 222 | |
<> | 144:ef7eb2e8f9f7 | 223 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 224 | * @{ |
<> | 144:ef7eb2e8f9f7 | 225 | */ |
<> | 144:ef7eb2e8f9f7 | 226 | |
<> | 144:ef7eb2e8f9f7 | 227 | /* |
<> | 144:ef7eb2e8f9f7 | 228 | Additional Table: If the parity is enabled, then the MSB bit of the data written |
<> | 144:ef7eb2e8f9f7 | 229 | in the data register is transmitted but is changed by the parity bit. |
<> | 144:ef7eb2e8f9f7 | 230 | According to device capability (support or not of 7-bit word length), |
<> | 144:ef7eb2e8f9f7 | 231 | frame length is either defined by the M bit (8-bits or 9-bits) |
<> | 144:ef7eb2e8f9f7 | 232 | or by the M1 and M0 bits (7-bit, 8-bit or 9-bit). |
<> | 144:ef7eb2e8f9f7 | 233 | Possible IRDA frame formats are as listed in the following table: |
<> | 144:ef7eb2e8f9f7 | 234 | |
<> | 144:ef7eb2e8f9f7 | 235 | Table 1. IRDA frame format. |
<> | 144:ef7eb2e8f9f7 | 236 | +-----------------------------------------------------------------------+ |
<> | 144:ef7eb2e8f9f7 | 237 | | M bit | PCE bit | IRDA frame | |
<> | 144:ef7eb2e8f9f7 | 238 | |-------------------|-----------|---------------------------------------| |
<> | 144:ef7eb2e8f9f7 | 239 | | 0 | 0 | | SB | 8-bit data | STB | | |
<> | 144:ef7eb2e8f9f7 | 240 | |-------------------|-----------|---------------------------------------| |
<> | 144:ef7eb2e8f9f7 | 241 | | 0 | 1 | | SB | 7-bit data | PB | STB | | |
<> | 144:ef7eb2e8f9f7 | 242 | |-------------------|-----------|---------------------------------------| |
<> | 144:ef7eb2e8f9f7 | 243 | | 1 | 0 | | SB | 9-bit data | STB | | |
<> | 144:ef7eb2e8f9f7 | 244 | |-------------------|-----------|---------------------------------------| |
<> | 144:ef7eb2e8f9f7 | 245 | | 1 | 1 | | SB | 8-bit data | PB | STB | | |
<> | 144:ef7eb2e8f9f7 | 246 | +-----------------------------------------------------------------------+ |
<> | 144:ef7eb2e8f9f7 | 247 | | M1 bit | M0 bit | PCE bit | IRDA frame | |
<> | 144:ef7eb2e8f9f7 | 248 | |---------|---------|-----------|---------------------------------------| |
<> | 144:ef7eb2e8f9f7 | 249 | | 0 | 0 | 0 | | SB | 8 bit data | STB | | |
<> | 144:ef7eb2e8f9f7 | 250 | |---------|---------|-----------|---------------------------------------| |
<> | 144:ef7eb2e8f9f7 | 251 | | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |
<> | 144:ef7eb2e8f9f7 | 252 | |---------|---------|-----------|---------------------------------------| |
<> | 144:ef7eb2e8f9f7 | 253 | | 0 | 1 | 0 | | SB | 9 bit data | STB | | |
<> | 144:ef7eb2e8f9f7 | 254 | |---------|---------|-----------|---------------------------------------| |
<> | 144:ef7eb2e8f9f7 | 255 | | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |
<> | 144:ef7eb2e8f9f7 | 256 | |---------|---------|-----------|---------------------------------------| |
<> | 144:ef7eb2e8f9f7 | 257 | | 1 | 0 | 0 | | SB | 7 bit data | STB | | |
<> | 144:ef7eb2e8f9f7 | 258 | |---------|---------|-----------|---------------------------------------| |
<> | 144:ef7eb2e8f9f7 | 259 | | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | |
<> | 144:ef7eb2e8f9f7 | 260 | +-----------------------------------------------------------------------+ |
<> | 144:ef7eb2e8f9f7 | 261 | |
<> | 144:ef7eb2e8f9f7 | 262 | */ |
<> | 144:ef7eb2e8f9f7 | 263 | |
<> | 144:ef7eb2e8f9f7 | 264 | /** |
<> | 144:ef7eb2e8f9f7 | 265 | * @brief Initialize the IRDA mode according to the specified |
<> | 144:ef7eb2e8f9f7 | 266 | * parameters in the IRDA_InitTypeDef and initialize the associated handle. |
Anna Bridge |
180:96ed750bd169 | 267 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 268 | * the configuration information for the specified IRDA module. |
<> | 144:ef7eb2e8f9f7 | 269 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 270 | */ |
<> | 144:ef7eb2e8f9f7 | 271 | HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 272 | { |
<> | 144:ef7eb2e8f9f7 | 273 | /* Check the IRDA handle allocation */ |
<> | 144:ef7eb2e8f9f7 | 274 | if(hirda == NULL) |
<> | 144:ef7eb2e8f9f7 | 275 | { |
<> | 144:ef7eb2e8f9f7 | 276 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 277 | } |
<> | 144:ef7eb2e8f9f7 | 278 | |
<> | 144:ef7eb2e8f9f7 | 279 | /* Check the USART/UART associated to the IRDA handle */ |
<> | 144:ef7eb2e8f9f7 | 280 | assert_param(IS_IRDA_INSTANCE(hirda->Instance)); |
<> | 144:ef7eb2e8f9f7 | 281 | |
<> | 144:ef7eb2e8f9f7 | 282 | if(hirda->gState == HAL_IRDA_STATE_RESET) |
<> | 144:ef7eb2e8f9f7 | 283 | { |
<> | 144:ef7eb2e8f9f7 | 284 | /* Allocate lock resource and initialize it */ |
<> | 144:ef7eb2e8f9f7 | 285 | hirda->Lock = HAL_UNLOCKED; |
<> | 144:ef7eb2e8f9f7 | 286 | |
<> | 144:ef7eb2e8f9f7 | 287 | /* Init the low level hardware : GPIO, CLOCK */ |
<> | 144:ef7eb2e8f9f7 | 288 | HAL_IRDA_MspInit(hirda); |
<> | 144:ef7eb2e8f9f7 | 289 | } |
<> | 144:ef7eb2e8f9f7 | 290 | |
<> | 144:ef7eb2e8f9f7 | 291 | hirda->gState = HAL_IRDA_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 292 | |
<> | 144:ef7eb2e8f9f7 | 293 | /* Disable the Peripheral to update the configuration registers */ |
<> | 144:ef7eb2e8f9f7 | 294 | __HAL_IRDA_DISABLE(hirda); |
<> | 144:ef7eb2e8f9f7 | 295 | |
<> | 144:ef7eb2e8f9f7 | 296 | /* Set the IRDA Communication parameters */ |
<> | 144:ef7eb2e8f9f7 | 297 | if (IRDA_SetConfig(hirda) == HAL_ERROR) |
<> | 144:ef7eb2e8f9f7 | 298 | { |
<> | 144:ef7eb2e8f9f7 | 299 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 300 | } |
<> | 144:ef7eb2e8f9f7 | 301 | |
<> | 144:ef7eb2e8f9f7 | 302 | /* In IRDA mode, the following bits must be kept cleared: |
<> | 144:ef7eb2e8f9f7 | 303 | - LINEN, STOP and CLKEN bits in the USART_CR2 register, |
<> | 144:ef7eb2e8f9f7 | 304 | - SCEN and HDSEL bits in the USART_CR3 register.*/ |
<> | 156:95d6b41a828b | 305 | CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); |
<> | 156:95d6b41a828b | 306 | CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); |
<> | 144:ef7eb2e8f9f7 | 307 | |
<> | 144:ef7eb2e8f9f7 | 308 | /* set the UART/USART in IRDA mode */ |
<> | 144:ef7eb2e8f9f7 | 309 | hirda->Instance->CR3 |= USART_CR3_IREN; |
<> | 144:ef7eb2e8f9f7 | 310 | |
<> | 144:ef7eb2e8f9f7 | 311 | /* Enable the Peripheral */ |
<> | 144:ef7eb2e8f9f7 | 312 | __HAL_IRDA_ENABLE(hirda); |
<> | 144:ef7eb2e8f9f7 | 313 | |
<> | 144:ef7eb2e8f9f7 | 314 | /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */ |
<> | 144:ef7eb2e8f9f7 | 315 | return (IRDA_CheckIdleState(hirda)); |
<> | 144:ef7eb2e8f9f7 | 316 | } |
<> | 144:ef7eb2e8f9f7 | 317 | |
<> | 144:ef7eb2e8f9f7 | 318 | /** |
<> | 144:ef7eb2e8f9f7 | 319 | * @brief DeInitialize the IRDA peripheral. |
Anna Bridge |
180:96ed750bd169 | 320 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 321 | * the configuration information for the specified IRDA module. |
<> | 144:ef7eb2e8f9f7 | 322 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 323 | */ |
<> | 144:ef7eb2e8f9f7 | 324 | HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 325 | { |
<> | 144:ef7eb2e8f9f7 | 326 | /* Check the IRDA handle allocation */ |
<> | 144:ef7eb2e8f9f7 | 327 | if(hirda == NULL) |
<> | 144:ef7eb2e8f9f7 | 328 | { |
<> | 144:ef7eb2e8f9f7 | 329 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 330 | } |
<> | 144:ef7eb2e8f9f7 | 331 | |
<> | 144:ef7eb2e8f9f7 | 332 | /* Check the USART/UART associated to the IRDA handle */ |
<> | 144:ef7eb2e8f9f7 | 333 | assert_param(IS_IRDA_INSTANCE(hirda->Instance)); |
<> | 144:ef7eb2e8f9f7 | 334 | |
<> | 144:ef7eb2e8f9f7 | 335 | hirda->gState = HAL_IRDA_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 336 | |
<> | 144:ef7eb2e8f9f7 | 337 | /* DeInit the low level hardware */ |
<> | 144:ef7eb2e8f9f7 | 338 | HAL_IRDA_MspDeInit(hirda); |
<> | 144:ef7eb2e8f9f7 | 339 | /* Disable the Peripheral */ |
<> | 144:ef7eb2e8f9f7 | 340 | __HAL_IRDA_DISABLE(hirda); |
<> | 144:ef7eb2e8f9f7 | 341 | |
<> | 156:95d6b41a828b | 342 | hirda->ErrorCode = HAL_IRDA_ERROR_NONE; |
<> | 156:95d6b41a828b | 343 | hirda->gState = HAL_IRDA_STATE_RESET; |
<> | 156:95d6b41a828b | 344 | hirda->RxState = HAL_IRDA_STATE_RESET; |
<> | 144:ef7eb2e8f9f7 | 345 | |
<> | 144:ef7eb2e8f9f7 | 346 | /* Process Unlock */ |
<> | 144:ef7eb2e8f9f7 | 347 | __HAL_UNLOCK(hirda); |
<> | 144:ef7eb2e8f9f7 | 348 | |
<> | 144:ef7eb2e8f9f7 | 349 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 350 | } |
<> | 144:ef7eb2e8f9f7 | 351 | |
<> | 144:ef7eb2e8f9f7 | 352 | /** |
<> | 144:ef7eb2e8f9f7 | 353 | * @brief Initialize the IRDA MSP. |
Anna Bridge |
180:96ed750bd169 | 354 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 355 | * the configuration information for the specified IRDA module. |
<> | 144:ef7eb2e8f9f7 | 356 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 357 | */ |
<> | 156:95d6b41a828b | 358 | __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 359 | { |
<> | 144:ef7eb2e8f9f7 | 360 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 361 | UNUSED(hirda); |
<> | 144:ef7eb2e8f9f7 | 362 | |
<> | 144:ef7eb2e8f9f7 | 363 | /* NOTE: This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 364 | the HAL_IRDA_MspInit can be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 365 | */ |
<> | 144:ef7eb2e8f9f7 | 366 | } |
<> | 144:ef7eb2e8f9f7 | 367 | |
<> | 144:ef7eb2e8f9f7 | 368 | /** |
<> | 144:ef7eb2e8f9f7 | 369 | * @brief DeInitialize the IRDA MSP. |
Anna Bridge |
180:96ed750bd169 | 370 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 371 | * the configuration information for the specified IRDA module. |
<> | 144:ef7eb2e8f9f7 | 372 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 373 | */ |
<> | 156:95d6b41a828b | 374 | __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 375 | { |
<> | 144:ef7eb2e8f9f7 | 376 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 377 | UNUSED(hirda); |
<> | 144:ef7eb2e8f9f7 | 378 | |
<> | 144:ef7eb2e8f9f7 | 379 | /* NOTE: This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 380 | the HAL_IRDA_MspDeInit can be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 381 | */ |
<> | 144:ef7eb2e8f9f7 | 382 | } |
<> | 144:ef7eb2e8f9f7 | 383 | |
<> | 144:ef7eb2e8f9f7 | 384 | /** |
<> | 144:ef7eb2e8f9f7 | 385 | * @} |
<> | 144:ef7eb2e8f9f7 | 386 | */ |
<> | 144:ef7eb2e8f9f7 | 387 | |
<> | 144:ef7eb2e8f9f7 | 388 | /** @defgroup IRDA_Exported_Functions_Group2 IO operation functions |
<> | 144:ef7eb2e8f9f7 | 389 | * @brief IRDA Transmit and Receive functions |
<> | 144:ef7eb2e8f9f7 | 390 | * |
<> | 144:ef7eb2e8f9f7 | 391 | @verbatim |
<> | 156:95d6b41a828b | 392 | =============================================================================== |
<> | 156:95d6b41a828b | 393 | ##### IO operation functions ##### |
<> | 156:95d6b41a828b | 394 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 395 | [..] |
<> | 144:ef7eb2e8f9f7 | 396 | This subsection provides a set of functions allowing to manage the IRDA data transfers. |
<> | 144:ef7eb2e8f9f7 | 397 | |
<> | 144:ef7eb2e8f9f7 | 398 | [..] |
<> | 144:ef7eb2e8f9f7 | 399 | IrDA is a half duplex communication protocol. If the Transmitter is busy, any data |
<> | 144:ef7eb2e8f9f7 | 400 | on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver |
<> | 144:ef7eb2e8f9f7 | 401 | is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. |
<> | 144:ef7eb2e8f9f7 | 402 | While receiving data, transmission should be avoided as the data to be transmitted |
<> | 144:ef7eb2e8f9f7 | 403 | could be corrupted. |
<> | 144:ef7eb2e8f9f7 | 404 | |
<> | 156:95d6b41a828b | 405 | (#) There are two mode of transfer: |
<> | 144:ef7eb2e8f9f7 | 406 | (++) Blocking mode: the communication is performed in polling mode. |
<> | 144:ef7eb2e8f9f7 | 407 | The HAL status of all data processing is returned by the same function |
<> | 144:ef7eb2e8f9f7 | 408 | after finishing transfer. |
<> | 156:95d6b41a828b | 409 | (++) Non-Blocking mode: the communication is performed using Interrupts |
<> | 144:ef7eb2e8f9f7 | 410 | or DMA, these API's return the HAL status. |
<> | 144:ef7eb2e8f9f7 | 411 | The end of the data processing will be indicated through the |
<> | 144:ef7eb2e8f9f7 | 412 | dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when |
<> | 144:ef7eb2e8f9f7 | 413 | using DMA mode. |
<> | 144:ef7eb2e8f9f7 | 414 | The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks |
<> | 144:ef7eb2e8f9f7 | 415 | will be executed respectively at the end of the Transmit or Receive process |
<> | 144:ef7eb2e8f9f7 | 416 | The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected |
<> | 144:ef7eb2e8f9f7 | 417 | |
<> | 144:ef7eb2e8f9f7 | 418 | (#) Blocking mode APIs are : |
<> | 144:ef7eb2e8f9f7 | 419 | (++) HAL_IRDA_Transmit() |
<> | 144:ef7eb2e8f9f7 | 420 | (++) HAL_IRDA_Receive() |
<> | 144:ef7eb2e8f9f7 | 421 | |
<> | 144:ef7eb2e8f9f7 | 422 | (#) Non Blocking mode APIs with Interrupt are : |
<> | 144:ef7eb2e8f9f7 | 423 | (++) HAL_IRDA_Transmit_IT() |
<> | 144:ef7eb2e8f9f7 | 424 | (++) HAL_IRDA_Receive_IT() |
<> | 144:ef7eb2e8f9f7 | 425 | (++) HAL_IRDA_IRQHandler() |
<> | 144:ef7eb2e8f9f7 | 426 | |
<> | 144:ef7eb2e8f9f7 | 427 | (#) Non Blocking mode functions with DMA are : |
<> | 144:ef7eb2e8f9f7 | 428 | (++) HAL_IRDA_Transmit_DMA() |
<> | 144:ef7eb2e8f9f7 | 429 | (++) HAL_IRDA_Receive_DMA() |
<> | 144:ef7eb2e8f9f7 | 430 | (++) HAL_IRDA_DMAPause() |
<> | 144:ef7eb2e8f9f7 | 431 | (++) HAL_IRDA_DMAResume() |
<> | 144:ef7eb2e8f9f7 | 432 | (++) HAL_IRDA_DMAStop() |
<> | 144:ef7eb2e8f9f7 | 433 | |
<> | 144:ef7eb2e8f9f7 | 434 | (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode: |
<> | 144:ef7eb2e8f9f7 | 435 | (++) HAL_IRDA_TxHalfCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 436 | (++) HAL_IRDA_TxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 437 | (++) HAL_IRDA_RxHalfCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 438 | (++) HAL_IRDA_RxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 439 | (++) HAL_IRDA_ErrorCallback() |
<> | 144:ef7eb2e8f9f7 | 440 | |
<> | 156:95d6b41a828b | 441 | (#) Non-Blocking mode transfers could be aborted using Abort API's : |
<> | 156:95d6b41a828b | 442 | (++) HAL_IRDA_Abort() |
<> | 156:95d6b41a828b | 443 | (++) HAL_IRDA_AbortTransmit() |
<> | 156:95d6b41a828b | 444 | (++) HAL_IRDA_AbortReceive() |
<> | 156:95d6b41a828b | 445 | (++) HAL_IRDA_Abort_IT() |
<> | 156:95d6b41a828b | 446 | (++) HAL_IRDA_AbortTransmit_IT() |
<> | 156:95d6b41a828b | 447 | (++) HAL_IRDA_AbortReceive_IT() |
<> | 156:95d6b41a828b | 448 | |
<> | 156:95d6b41a828b | 449 | (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided: |
<> | 156:95d6b41a828b | 450 | (++) HAL_IRDA_AbortCpltCallback() |
<> | 156:95d6b41a828b | 451 | (++) HAL_IRDA_AbortTransmitCpltCallback() |
<> | 156:95d6b41a828b | 452 | (++) HAL_IRDA_AbortReceiveCpltCallback() |
<> | 156:95d6b41a828b | 453 | |
<> | 156:95d6b41a828b | 454 | (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. |
<> | 156:95d6b41a828b | 455 | Errors are handled as follows : |
<> | 156:95d6b41a828b | 456 | (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is |
<> | 156:95d6b41a828b | 457 | to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . |
<> | 156:95d6b41a828b | 458 | Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, |
<> | 156:95d6b41a828b | 459 | and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. |
<> | 156:95d6b41a828b | 460 | If user wants to abort it, Abort services should be called by user. |
<> | 156:95d6b41a828b | 461 | (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. |
<> | 156:95d6b41a828b | 462 | This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. |
<> | 156:95d6b41a828b | 463 | Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. |
<> | 156:95d6b41a828b | 464 | |
<> | 144:ef7eb2e8f9f7 | 465 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 466 | * @{ |
<> | 144:ef7eb2e8f9f7 | 467 | */ |
<> | 144:ef7eb2e8f9f7 | 468 | |
<> | 144:ef7eb2e8f9f7 | 469 | /** |
<> | 156:95d6b41a828b | 470 | * @brief Send an amount of data in blocking mode. |
<> | 156:95d6b41a828b | 471 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 472 | * the configuration information for the specified IRDA module. |
<> | 156:95d6b41a828b | 473 | * @param pData Pointer to data buffer. |
<> | 156:95d6b41a828b | 474 | * @param Size Amount of data to be sent. |
<> | 156:95d6b41a828b | 475 | * @param Timeout Specify timeout value. |
<> | 144:ef7eb2e8f9f7 | 476 | * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), |
<> | 144:ef7eb2e8f9f7 | 477 | * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) |
<> | 144:ef7eb2e8f9f7 | 478 | * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, |
<> | 144:ef7eb2e8f9f7 | 479 | * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. |
<> | 144:ef7eb2e8f9f7 | 480 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 481 | */ |
<> | 144:ef7eb2e8f9f7 | 482 | HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 483 | { |
<> | 144:ef7eb2e8f9f7 | 484 | uint16_t* tmp; |
<> | 156:95d6b41a828b | 485 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 486 | |
<> | 144:ef7eb2e8f9f7 | 487 | /* Check that a Tx process is not already ongoing */ |
<> | 144:ef7eb2e8f9f7 | 488 | if(hirda->gState == HAL_IRDA_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 489 | { |
<> | 156:95d6b41a828b | 490 | if((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 491 | { |
<> | 144:ef7eb2e8f9f7 | 492 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 493 | } |
<> | 144:ef7eb2e8f9f7 | 494 | |
<> | 144:ef7eb2e8f9f7 | 495 | /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter |
<> | 144:ef7eb2e8f9f7 | 496 | should be aligned on a u16 frontier, as data to be filled into TDR will be |
<> | 144:ef7eb2e8f9f7 | 497 | handled through a u16 cast. */ |
<> | 144:ef7eb2e8f9f7 | 498 | if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE)) |
<> | 144:ef7eb2e8f9f7 | 499 | { |
<> | 156:95d6b41a828b | 500 | if((((uint32_t)pData)&1U) != 0U) |
<> | 144:ef7eb2e8f9f7 | 501 | { |
<> | 144:ef7eb2e8f9f7 | 502 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 503 | } |
<> | 144:ef7eb2e8f9f7 | 504 | } |
<> | 144:ef7eb2e8f9f7 | 505 | |
<> | 144:ef7eb2e8f9f7 | 506 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 507 | __HAL_LOCK(hirda); |
<> | 144:ef7eb2e8f9f7 | 508 | |
<> | 144:ef7eb2e8f9f7 | 509 | hirda->ErrorCode = HAL_IRDA_ERROR_NONE; |
<> | 156:95d6b41a828b | 510 | hirda->gState = HAL_IRDA_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 511 | |
<> | 156:95d6b41a828b | 512 | /* Init tickstart for timeout managment*/ |
<> | 156:95d6b41a828b | 513 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 514 | |
<> | 144:ef7eb2e8f9f7 | 515 | hirda->TxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 516 | hirda->TxXferCount = Size; |
<> | 156:95d6b41a828b | 517 | while(hirda->TxXferCount > 0U) |
<> | 144:ef7eb2e8f9f7 | 518 | { |
<> | 144:ef7eb2e8f9f7 | 519 | hirda->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 520 | |
<> | 156:95d6b41a828b | 521 | if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 522 | { |
<> | 144:ef7eb2e8f9f7 | 523 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 524 | } |
<> | 144:ef7eb2e8f9f7 | 525 | if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) |
<> | 144:ef7eb2e8f9f7 | 526 | { |
<> | 144:ef7eb2e8f9f7 | 527 | tmp = (uint16_t*) pData; |
<> | 156:95d6b41a828b | 528 | hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU); |
<> | 156:95d6b41a828b | 529 | pData += 2; |
<> | 144:ef7eb2e8f9f7 | 530 | } |
<> | 144:ef7eb2e8f9f7 | 531 | else |
<> | 144:ef7eb2e8f9f7 | 532 | { |
<> | 156:95d6b41a828b | 533 | hirda->Instance->TDR = (*pData++ & (uint8_t)0xFFU); |
<> | 144:ef7eb2e8f9f7 | 534 | } |
<> | 144:ef7eb2e8f9f7 | 535 | } |
<> | 144:ef7eb2e8f9f7 | 536 | |
<> | 156:95d6b41a828b | 537 | if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 538 | { |
<> | 144:ef7eb2e8f9f7 | 539 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 540 | } |
<> | 144:ef7eb2e8f9f7 | 541 | |
<> | 144:ef7eb2e8f9f7 | 542 | /* At end of Tx process, restore hirda->gState to Ready */ |
<> | 144:ef7eb2e8f9f7 | 543 | hirda->gState = HAL_IRDA_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 544 | |
<> | 144:ef7eb2e8f9f7 | 545 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 546 | __HAL_UNLOCK(hirda); |
<> | 144:ef7eb2e8f9f7 | 547 | |
<> | 144:ef7eb2e8f9f7 | 548 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 549 | } |
<> | 144:ef7eb2e8f9f7 | 550 | else |
<> | 144:ef7eb2e8f9f7 | 551 | { |
<> | 144:ef7eb2e8f9f7 | 552 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 553 | } |
<> | 144:ef7eb2e8f9f7 | 554 | } |
<> | 144:ef7eb2e8f9f7 | 555 | |
<> | 144:ef7eb2e8f9f7 | 556 | /** |
<> | 156:95d6b41a828b | 557 | * @brief Receive an amount of data in blocking mode. |
<> | 156:95d6b41a828b | 558 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 559 | * the configuration information for the specified IRDA module. |
<> | 156:95d6b41a828b | 560 | * @param pData Pointer to data buffer. |
<> | 156:95d6b41a828b | 561 | * @param Size Amount of data to be received. |
<> | 156:95d6b41a828b | 562 | * @param Timeout Specify timeout value. |
<> | 144:ef7eb2e8f9f7 | 563 | * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), |
<> | 144:ef7eb2e8f9f7 | 564 | * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) |
<> | 144:ef7eb2e8f9f7 | 565 | * (as received data will be handled using u16 pointer cast). Depending on compilation chain, |
<> | 144:ef7eb2e8f9f7 | 566 | * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. |
<> | 144:ef7eb2e8f9f7 | 567 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 568 | */ |
<> | 144:ef7eb2e8f9f7 | 569 | HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 570 | { |
<> | 144:ef7eb2e8f9f7 | 571 | uint16_t* tmp; |
<> | 144:ef7eb2e8f9f7 | 572 | uint16_t uhMask; |
<> | 156:95d6b41a828b | 573 | uint32_t tickstart = 0; |
<> | 144:ef7eb2e8f9f7 | 574 | |
<> | 144:ef7eb2e8f9f7 | 575 | /* Check that a Rx process is not already ongoing */ |
<> | 144:ef7eb2e8f9f7 | 576 | if(hirda->RxState == HAL_IRDA_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 577 | { |
<> | 156:95d6b41a828b | 578 | if((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 579 | { |
<> | 144:ef7eb2e8f9f7 | 580 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 581 | } |
<> | 144:ef7eb2e8f9f7 | 582 | |
<> | 144:ef7eb2e8f9f7 | 583 | /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter |
<> | 144:ef7eb2e8f9f7 | 584 | should be aligned on a u16 frontier, as data to be received from RDR will be |
<> | 144:ef7eb2e8f9f7 | 585 | handled through a u16 cast. */ |
<> | 144:ef7eb2e8f9f7 | 586 | if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE)) |
<> | 144:ef7eb2e8f9f7 | 587 | { |
<> | 156:95d6b41a828b | 588 | if((((uint32_t)pData)&1U) != 0U) |
<> | 144:ef7eb2e8f9f7 | 589 | { |
<> | 144:ef7eb2e8f9f7 | 590 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 591 | } |
<> | 144:ef7eb2e8f9f7 | 592 | } |
<> | 144:ef7eb2e8f9f7 | 593 | |
<> | 144:ef7eb2e8f9f7 | 594 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 595 | __HAL_LOCK(hirda); |
<> | 144:ef7eb2e8f9f7 | 596 | |
<> | 144:ef7eb2e8f9f7 | 597 | hirda->ErrorCode = HAL_IRDA_ERROR_NONE; |
<> | 156:95d6b41a828b | 598 | hirda->RxState = HAL_IRDA_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 599 | |
<> | 156:95d6b41a828b | 600 | /* Init tickstart for timeout managment*/ |
<> | 156:95d6b41a828b | 601 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 602 | |
<> | 144:ef7eb2e8f9f7 | 603 | hirda->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 604 | hirda->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 605 | |
<> | 156:95d6b41a828b | 606 | /* Computation of the mask to apply to RDR register |
<> | 144:ef7eb2e8f9f7 | 607 | of the UART associated to the IRDA */ |
<> | 144:ef7eb2e8f9f7 | 608 | IRDA_MASK_COMPUTATION(hirda); |
<> | 144:ef7eb2e8f9f7 | 609 | uhMask = hirda->Mask; |
<> | 144:ef7eb2e8f9f7 | 610 | |
<> | 144:ef7eb2e8f9f7 | 611 | /* Check data remaining to be received */ |
<> | 156:95d6b41a828b | 612 | while(hirda->RxXferCount > 0U) |
<> | 144:ef7eb2e8f9f7 | 613 | { |
<> | 144:ef7eb2e8f9f7 | 614 | hirda->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 615 | |
<> | 156:95d6b41a828b | 616 | if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 617 | { |
<> | 144:ef7eb2e8f9f7 | 618 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 619 | } |
<> | 144:ef7eb2e8f9f7 | 620 | if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) |
<> | 144:ef7eb2e8f9f7 | 621 | { |
<> | 144:ef7eb2e8f9f7 | 622 | tmp = (uint16_t*) pData ; |
<> | 144:ef7eb2e8f9f7 | 623 | *tmp = (uint16_t)(hirda->Instance->RDR & uhMask); |
<> | 144:ef7eb2e8f9f7 | 624 | pData +=2; |
<> | 144:ef7eb2e8f9f7 | 625 | } |
<> | 144:ef7eb2e8f9f7 | 626 | else |
<> | 144:ef7eb2e8f9f7 | 627 | { |
<> | 144:ef7eb2e8f9f7 | 628 | *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); |
<> | 144:ef7eb2e8f9f7 | 629 | } |
<> | 144:ef7eb2e8f9f7 | 630 | } |
<> | 144:ef7eb2e8f9f7 | 631 | |
<> | 144:ef7eb2e8f9f7 | 632 | /* At end of Rx process, restore hirda->RxState to Ready */ |
<> | 144:ef7eb2e8f9f7 | 633 | hirda->RxState = HAL_IRDA_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 634 | |
<> | 144:ef7eb2e8f9f7 | 635 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 636 | __HAL_UNLOCK(hirda); |
<> | 144:ef7eb2e8f9f7 | 637 | |
<> | 144:ef7eb2e8f9f7 | 638 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 639 | } |
<> | 144:ef7eb2e8f9f7 | 640 | else |
<> | 144:ef7eb2e8f9f7 | 641 | { |
<> | 144:ef7eb2e8f9f7 | 642 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 643 | } |
<> | 144:ef7eb2e8f9f7 | 644 | } |
<> | 144:ef7eb2e8f9f7 | 645 | |
<> | 144:ef7eb2e8f9f7 | 646 | /** |
<> | 156:95d6b41a828b | 647 | * @brief Send an amount of data in interrupt mode. |
<> | 156:95d6b41a828b | 648 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 649 | * the configuration information for the specified IRDA module. |
<> | 156:95d6b41a828b | 650 | * @param pData Pointer to data buffer. |
<> | 156:95d6b41a828b | 651 | * @param Size Amount of data to be sent. |
<> | 144:ef7eb2e8f9f7 | 652 | * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), |
<> | 144:ef7eb2e8f9f7 | 653 | * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) |
<> | 144:ef7eb2e8f9f7 | 654 | * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, |
<> | 144:ef7eb2e8f9f7 | 655 | * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. |
<> | 144:ef7eb2e8f9f7 | 656 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 657 | */ |
<> | 144:ef7eb2e8f9f7 | 658 | HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 659 | { |
<> | 144:ef7eb2e8f9f7 | 660 | /* Check that a Tx process is not already ongoing */ |
<> | 144:ef7eb2e8f9f7 | 661 | if(hirda->gState == HAL_IRDA_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 662 | { |
<> | 156:95d6b41a828b | 663 | if((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 664 | { |
<> | 144:ef7eb2e8f9f7 | 665 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 666 | } |
<> | 144:ef7eb2e8f9f7 | 667 | |
<> | 144:ef7eb2e8f9f7 | 668 | /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter |
<> | 144:ef7eb2e8f9f7 | 669 | should be aligned on a u16 frontier, as data to be filled into TDR will be |
<> | 144:ef7eb2e8f9f7 | 670 | handled through a u16 cast. */ |
<> | 144:ef7eb2e8f9f7 | 671 | if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE)) |
<> | 144:ef7eb2e8f9f7 | 672 | { |
<> | 156:95d6b41a828b | 673 | if((((uint32_t)pData)&1U) != 0U) |
<> | 144:ef7eb2e8f9f7 | 674 | { |
<> | 144:ef7eb2e8f9f7 | 675 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 676 | } |
<> | 144:ef7eb2e8f9f7 | 677 | } |
<> | 144:ef7eb2e8f9f7 | 678 | |
<> | 144:ef7eb2e8f9f7 | 679 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 680 | __HAL_LOCK(hirda); |
<> | 144:ef7eb2e8f9f7 | 681 | |
<> | 144:ef7eb2e8f9f7 | 682 | hirda->pTxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 683 | hirda->TxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 684 | hirda->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 685 | |
<> | 144:ef7eb2e8f9f7 | 686 | hirda->ErrorCode = HAL_IRDA_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 687 | hirda->gState = HAL_IRDA_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 688 | |
<> | 144:ef7eb2e8f9f7 | 689 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 690 | __HAL_UNLOCK(hirda); |
<> | 144:ef7eb2e8f9f7 | 691 | |
<> | 144:ef7eb2e8f9f7 | 692 | /* Enable the IRDA Transmit Data Register Empty Interrupt */ |
<> | 156:95d6b41a828b | 693 | SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE); |
<> | 144:ef7eb2e8f9f7 | 694 | |
<> | 144:ef7eb2e8f9f7 | 695 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 696 | } |
<> | 144:ef7eb2e8f9f7 | 697 | else |
<> | 144:ef7eb2e8f9f7 | 698 | { |
<> | 144:ef7eb2e8f9f7 | 699 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 700 | } |
<> | 144:ef7eb2e8f9f7 | 701 | } |
<> | 144:ef7eb2e8f9f7 | 702 | |
<> | 144:ef7eb2e8f9f7 | 703 | /** |
<> | 156:95d6b41a828b | 704 | * @brief Receive an amount of data in interrupt mode. |
<> | 156:95d6b41a828b | 705 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 706 | * the configuration information for the specified IRDA module. |
<> | 156:95d6b41a828b | 707 | * @param pData Pointer to data buffer. |
<> | 156:95d6b41a828b | 708 | * @param Size Amount of data to be received. |
<> | 144:ef7eb2e8f9f7 | 709 | * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), |
<> | 144:ef7eb2e8f9f7 | 710 | * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) |
<> | 144:ef7eb2e8f9f7 | 711 | * (as received data will be handled using u16 pointer cast). Depending on compilation chain, |
<> | 144:ef7eb2e8f9f7 | 712 | * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. |
<> | 144:ef7eb2e8f9f7 | 713 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 714 | */ |
<> | 144:ef7eb2e8f9f7 | 715 | HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 716 | { |
<> | 144:ef7eb2e8f9f7 | 717 | /* Check that a Rx process is not already ongoing */ |
<> | 144:ef7eb2e8f9f7 | 718 | if(hirda->RxState == HAL_IRDA_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 719 | { |
<> | 156:95d6b41a828b | 720 | if((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 721 | { |
<> | 144:ef7eb2e8f9f7 | 722 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 723 | } |
<> | 144:ef7eb2e8f9f7 | 724 | |
<> | 144:ef7eb2e8f9f7 | 725 | /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter |
<> | 144:ef7eb2e8f9f7 | 726 | should be aligned on a u16 frontier, as data to be received from RDR will be |
<> | 144:ef7eb2e8f9f7 | 727 | handled through a u16 cast. */ |
<> | 144:ef7eb2e8f9f7 | 728 | if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE)) |
<> | 144:ef7eb2e8f9f7 | 729 | { |
<> | 156:95d6b41a828b | 730 | if((((uint32_t)pData)&1U) != 0U) |
<> | 144:ef7eb2e8f9f7 | 731 | { |
<> | 144:ef7eb2e8f9f7 | 732 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 733 | } |
<> | 144:ef7eb2e8f9f7 | 734 | } |
<> | 144:ef7eb2e8f9f7 | 735 | |
<> | 144:ef7eb2e8f9f7 | 736 | /* Process Locked */ |
<> | 156:95d6b41a828b | 737 | __HAL_LOCK(hirda); |
<> | 144:ef7eb2e8f9f7 | 738 | |
<> | 144:ef7eb2e8f9f7 | 739 | hirda->pRxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 740 | hirda->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 741 | hirda->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 742 | |
<> | 144:ef7eb2e8f9f7 | 743 | /* Computation of the mask to apply to the RDR register |
<> | 144:ef7eb2e8f9f7 | 744 | of the UART associated to the IRDA */ |
<> | 144:ef7eb2e8f9f7 | 745 | IRDA_MASK_COMPUTATION(hirda); |
<> | 144:ef7eb2e8f9f7 | 746 | |
<> | 144:ef7eb2e8f9f7 | 747 | hirda->ErrorCode = HAL_IRDA_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 748 | hirda->RxState = HAL_IRDA_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 749 | |
<> | 144:ef7eb2e8f9f7 | 750 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 751 | __HAL_UNLOCK(hirda); |
<> | 144:ef7eb2e8f9f7 | 752 | |
<> | 156:95d6b41a828b | 753 | /* Enable the IRDA Parity Error and Data Register not empty Interrupts */ |
<> | 156:95d6b41a828b | 754 | SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE); |
<> | 144:ef7eb2e8f9f7 | 755 | |
<> | 144:ef7eb2e8f9f7 | 756 | /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ |
<> | 156:95d6b41a828b | 757 | SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); |
<> | 144:ef7eb2e8f9f7 | 758 | |
<> | 144:ef7eb2e8f9f7 | 759 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 760 | } |
<> | 144:ef7eb2e8f9f7 | 761 | else |
<> | 144:ef7eb2e8f9f7 | 762 | { |
<> | 144:ef7eb2e8f9f7 | 763 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 764 | } |
<> | 144:ef7eb2e8f9f7 | 765 | } |
<> | 144:ef7eb2e8f9f7 | 766 | |
<> | 144:ef7eb2e8f9f7 | 767 | /** |
<> | 156:95d6b41a828b | 768 | * @brief Send an amount of data in DMA mode. |
<> | 156:95d6b41a828b | 769 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 770 | * the configuration information for the specified IRDA module. |
<> | 156:95d6b41a828b | 771 | * @param pData pointer to data buffer. |
<> | 156:95d6b41a828b | 772 | * @param Size amount of data to be sent. |
<> | 144:ef7eb2e8f9f7 | 773 | * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), |
<> | 144:ef7eb2e8f9f7 | 774 | * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) |
<> | 144:ef7eb2e8f9f7 | 775 | * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain, |
<> | 144:ef7eb2e8f9f7 | 776 | * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. |
<> | 144:ef7eb2e8f9f7 | 777 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 778 | */ |
<> | 144:ef7eb2e8f9f7 | 779 | HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 780 | { |
<> | 144:ef7eb2e8f9f7 | 781 | /* Check that a Tx process is not already ongoing */ |
<> | 144:ef7eb2e8f9f7 | 782 | if(hirda->gState == HAL_IRDA_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 783 | { |
<> | 156:95d6b41a828b | 784 | if((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 785 | { |
<> | 144:ef7eb2e8f9f7 | 786 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 787 | } |
<> | 144:ef7eb2e8f9f7 | 788 | |
<> | 144:ef7eb2e8f9f7 | 789 | /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter |
<> | 144:ef7eb2e8f9f7 | 790 | should be aligned on a u16 frontier, as data copy into TDR will be |
<> | 144:ef7eb2e8f9f7 | 791 | handled by DMA from a u16 frontier. */ |
<> | 144:ef7eb2e8f9f7 | 792 | if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE)) |
<> | 144:ef7eb2e8f9f7 | 793 | { |
<> | 156:95d6b41a828b | 794 | if((((uint32_t)pData)&1U) != 0U) |
<> | 144:ef7eb2e8f9f7 | 795 | { |
<> | 144:ef7eb2e8f9f7 | 796 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 797 | } |
<> | 144:ef7eb2e8f9f7 | 798 | } |
<> | 144:ef7eb2e8f9f7 | 799 | |
<> | 144:ef7eb2e8f9f7 | 800 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 801 | __HAL_LOCK(hirda); |
<> | 144:ef7eb2e8f9f7 | 802 | |
<> | 144:ef7eb2e8f9f7 | 803 | hirda->pTxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 804 | hirda->TxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 805 | hirda->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 806 | |
<> | 144:ef7eb2e8f9f7 | 807 | hirda->ErrorCode = HAL_IRDA_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 808 | hirda->gState = HAL_IRDA_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 809 | |
<> | 144:ef7eb2e8f9f7 | 810 | /* Set the IRDA DMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 811 | hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt; |
<> | 144:ef7eb2e8f9f7 | 812 | |
<> | 144:ef7eb2e8f9f7 | 813 | /* Set the IRDA DMA half transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 814 | hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt; |
<> | 144:ef7eb2e8f9f7 | 815 | |
<> | 144:ef7eb2e8f9f7 | 816 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 817 | hirda->hdmatx->XferErrorCallback = IRDA_DMAError; |
<> | 144:ef7eb2e8f9f7 | 818 | |
<> | 156:95d6b41a828b | 819 | /* Set the DMA abort callback */ |
<> | 156:95d6b41a828b | 820 | hirda->hdmatx->XferAbortCallback = NULL; |
<> | 156:95d6b41a828b | 821 | |
<> | 144:ef7eb2e8f9f7 | 822 | /* Enable the IRDA transmit DMA channel */ |
<> | 156:95d6b41a828b | 823 | HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size); |
<> | 144:ef7eb2e8f9f7 | 824 | |
<> | 144:ef7eb2e8f9f7 | 825 | /* Clear the TC flag in the ICR register */ |
<> | 144:ef7eb2e8f9f7 | 826 | __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF); |
<> | 144:ef7eb2e8f9f7 | 827 | |
<> | 156:95d6b41a828b | 828 | /* Process Unlocked */ |
<> | 156:95d6b41a828b | 829 | __HAL_UNLOCK(hirda); |
<> | 156:95d6b41a828b | 830 | |
<> | 144:ef7eb2e8f9f7 | 831 | /* Enable the DMA transfer for transmit request by setting the DMAT bit |
<> | 144:ef7eb2e8f9f7 | 832 | in the USART CR3 register */ |
<> | 156:95d6b41a828b | 833 | SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); |
<> | 144:ef7eb2e8f9f7 | 834 | |
<> | 144:ef7eb2e8f9f7 | 835 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 836 | } |
<> | 144:ef7eb2e8f9f7 | 837 | else |
<> | 144:ef7eb2e8f9f7 | 838 | { |
<> | 144:ef7eb2e8f9f7 | 839 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 840 | } |
<> | 144:ef7eb2e8f9f7 | 841 | } |
<> | 144:ef7eb2e8f9f7 | 842 | |
<> | 144:ef7eb2e8f9f7 | 843 | /** |
<> | 156:95d6b41a828b | 844 | * @brief Receive an amount of data in DMA mode. |
<> | 156:95d6b41a828b | 845 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 846 | * the configuration information for the specified IRDA module. |
<> | 156:95d6b41a828b | 847 | * @param pData Pointer to data buffer. |
<> | 156:95d6b41a828b | 848 | * @param Size Amount of data to be received. |
<> | 144:ef7eb2e8f9f7 | 849 | * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), |
<> | 144:ef7eb2e8f9f7 | 850 | * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) |
<> | 144:ef7eb2e8f9f7 | 851 | * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, |
<> | 144:ef7eb2e8f9f7 | 852 | * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. |
<> | 144:ef7eb2e8f9f7 | 853 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 854 | */ |
<> | 144:ef7eb2e8f9f7 | 855 | HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 856 | { |
<> | 144:ef7eb2e8f9f7 | 857 | /* Check that a Rx process is not already ongoing */ |
<> | 144:ef7eb2e8f9f7 | 858 | if(hirda->RxState == HAL_IRDA_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 859 | { |
<> | 156:95d6b41a828b | 860 | if((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 861 | { |
<> | 144:ef7eb2e8f9f7 | 862 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 863 | } |
<> | 144:ef7eb2e8f9f7 | 864 | |
<> | 144:ef7eb2e8f9f7 | 865 | /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter |
<> | 144:ef7eb2e8f9f7 | 866 | should be aligned on a u16 frontier, as data copy from RDR will be |
<> | 144:ef7eb2e8f9f7 | 867 | handled by DMA from a u16 frontier. */ |
<> | 144:ef7eb2e8f9f7 | 868 | if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE)) |
<> | 144:ef7eb2e8f9f7 | 869 | { |
<> | 156:95d6b41a828b | 870 | if((((uint32_t)pData)&1U) != 0U) |
<> | 144:ef7eb2e8f9f7 | 871 | { |
<> | 144:ef7eb2e8f9f7 | 872 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 873 | } |
<> | 144:ef7eb2e8f9f7 | 874 | } |
<> | 144:ef7eb2e8f9f7 | 875 | |
<> | 144:ef7eb2e8f9f7 | 876 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 877 | __HAL_LOCK(hirda); |
<> | 144:ef7eb2e8f9f7 | 878 | |
<> | 144:ef7eb2e8f9f7 | 879 | hirda->pRxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 880 | hirda->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 881 | |
<> | 144:ef7eb2e8f9f7 | 882 | hirda->ErrorCode = HAL_IRDA_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 883 | hirda->RxState = HAL_IRDA_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 884 | |
<> | 144:ef7eb2e8f9f7 | 885 | /* Set the IRDA DMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 886 | hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt; |
<> | 144:ef7eb2e8f9f7 | 887 | |
<> | 144:ef7eb2e8f9f7 | 888 | /* Set the IRDA DMA half transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 889 | hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt; |
<> | 144:ef7eb2e8f9f7 | 890 | |
<> | 144:ef7eb2e8f9f7 | 891 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 892 | hirda->hdmarx->XferErrorCallback = IRDA_DMAError; |
<> | 144:ef7eb2e8f9f7 | 893 | |
<> | 156:95d6b41a828b | 894 | /* Set the DMA abort callback */ |
<> | 156:95d6b41a828b | 895 | hirda->hdmarx->XferAbortCallback = NULL; |
<> | 156:95d6b41a828b | 896 | |
<> | 144:ef7eb2e8f9f7 | 897 | /* Enable the DMA channel */ |
<> | 156:95d6b41a828b | 898 | HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size); |
<> | 156:95d6b41a828b | 899 | |
<> | 156:95d6b41a828b | 900 | /* Process Unlocked */ |
<> | 156:95d6b41a828b | 901 | __HAL_UNLOCK(hirda); |
<> | 156:95d6b41a828b | 902 | |
<> | 156:95d6b41a828b | 903 | /* Enable the UART Parity Error Interrupt */ |
<> | 156:95d6b41a828b | 904 | SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); |
<> | 156:95d6b41a828b | 905 | |
<> | 156:95d6b41a828b | 906 | /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ |
<> | 156:95d6b41a828b | 907 | SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); |
<> | 144:ef7eb2e8f9f7 | 908 | |
<> | 144:ef7eb2e8f9f7 | 909 | /* Enable the DMA transfer for the receiver request by setting the DMAR bit |
<> | 144:ef7eb2e8f9f7 | 910 | in the USART CR3 register */ |
<> | 156:95d6b41a828b | 911 | SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); |
<> | 144:ef7eb2e8f9f7 | 912 | |
<> | 144:ef7eb2e8f9f7 | 913 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 914 | } |
<> | 144:ef7eb2e8f9f7 | 915 | else |
<> | 144:ef7eb2e8f9f7 | 916 | { |
<> | 144:ef7eb2e8f9f7 | 917 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 918 | } |
<> | 144:ef7eb2e8f9f7 | 919 | } |
<> | 144:ef7eb2e8f9f7 | 920 | |
<> | 144:ef7eb2e8f9f7 | 921 | |
<> | 144:ef7eb2e8f9f7 | 922 | /** |
<> | 156:95d6b41a828b | 923 | * @brief Pause the DMA Transfer. |
<> | 156:95d6b41a828b | 924 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 925 | * the configuration information for the specified IRDA module. |
<> | 144:ef7eb2e8f9f7 | 926 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 927 | */ |
<> | 144:ef7eb2e8f9f7 | 928 | HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 929 | { |
<> | 144:ef7eb2e8f9f7 | 930 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 931 | __HAL_LOCK(hirda); |
<> | 156:95d6b41a828b | 932 | |
<> | 156:95d6b41a828b | 933 | if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && |
<> | 156:95d6b41a828b | 934 | (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))) |
<> | 144:ef7eb2e8f9f7 | 935 | { |
<> | 144:ef7eb2e8f9f7 | 936 | /* Disable the IRDA DMA Tx request */ |
<> | 144:ef7eb2e8f9f7 | 937 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); |
<> | 144:ef7eb2e8f9f7 | 938 | } |
<> | 156:95d6b41a828b | 939 | if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && |
<> | 156:95d6b41a828b | 940 | (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) |
<> | 144:ef7eb2e8f9f7 | 941 | { |
<> | 156:95d6b41a828b | 942 | /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ |
<> | 156:95d6b41a828b | 943 | CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); |
<> | 156:95d6b41a828b | 944 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); |
<> | 156:95d6b41a828b | 945 | |
<> | 144:ef7eb2e8f9f7 | 946 | /* Disable the IRDA DMA Rx request */ |
<> | 144:ef7eb2e8f9f7 | 947 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); |
<> | 144:ef7eb2e8f9f7 | 948 | } |
<> | 144:ef7eb2e8f9f7 | 949 | |
<> | 144:ef7eb2e8f9f7 | 950 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 951 | __HAL_UNLOCK(hirda); |
<> | 156:95d6b41a828b | 952 | |
<> | 156:95d6b41a828b | 953 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 954 | } |
<> | 144:ef7eb2e8f9f7 | 955 | |
<> | 144:ef7eb2e8f9f7 | 956 | /** |
<> | 156:95d6b41a828b | 957 | * @brief Resume the DMA Transfer. |
<> | 156:95d6b41a828b | 958 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 959 | * the configuration information for the specified UART module. |
<> | 144:ef7eb2e8f9f7 | 960 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 961 | */ |
<> | 144:ef7eb2e8f9f7 | 962 | HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 963 | { |
<> | 144:ef7eb2e8f9f7 | 964 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 965 | __HAL_LOCK(hirda); |
<> | 156:95d6b41a828b | 966 | |
<> | 144:ef7eb2e8f9f7 | 967 | if(hirda->gState == HAL_IRDA_STATE_BUSY_TX) |
<> | 144:ef7eb2e8f9f7 | 968 | { |
<> | 144:ef7eb2e8f9f7 | 969 | /* Enable the IRDA DMA Tx request */ |
<> | 144:ef7eb2e8f9f7 | 970 | SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); |
<> | 144:ef7eb2e8f9f7 | 971 | } |
<> | 144:ef7eb2e8f9f7 | 972 | if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX) |
<> | 144:ef7eb2e8f9f7 | 973 | { |
<> | 144:ef7eb2e8f9f7 | 974 | /* Clear the Overrun flag before resuming the Rx transfer*/ |
<> | 144:ef7eb2e8f9f7 | 975 | __HAL_IRDA_CLEAR_OREFLAG(hirda); |
<> | 156:95d6b41a828b | 976 | |
<> | 156:95d6b41a828b | 977 | /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ |
<> | 156:95d6b41a828b | 978 | SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); |
<> | 156:95d6b41a828b | 979 | SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); |
<> | 156:95d6b41a828b | 980 | |
<> | 144:ef7eb2e8f9f7 | 981 | /* Enable the IRDA DMA Rx request */ |
<> | 144:ef7eb2e8f9f7 | 982 | SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); |
<> | 144:ef7eb2e8f9f7 | 983 | } |
<> | 156:95d6b41a828b | 984 | |
<> | 144:ef7eb2e8f9f7 | 985 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 986 | __HAL_UNLOCK(hirda); |
<> | 156:95d6b41a828b | 987 | |
<> | 144:ef7eb2e8f9f7 | 988 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 989 | } |
<> | 144:ef7eb2e8f9f7 | 990 | |
<> | 144:ef7eb2e8f9f7 | 991 | /** |
<> | 156:95d6b41a828b | 992 | * @brief Stop the DMA Transfer. |
<> | 156:95d6b41a828b | 993 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 994 | * the configuration information for the specified UART module. |
<> | 144:ef7eb2e8f9f7 | 995 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 996 | */ |
<> | 144:ef7eb2e8f9f7 | 997 | HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 998 | { |
<> | 144:ef7eb2e8f9f7 | 999 | /* The Lock is not implemented on this API to allow the user application |
<> | 144:ef7eb2e8f9f7 | 1000 | to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() / |
<> | 156:95d6b41a828b | 1001 | HAL_IRDA_TxHalfCpltCallback() / HAL_IRDA_RxHalfCpltCallback(): |
<> | 156:95d6b41a828b | 1002 | indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete |
<> | 156:95d6b41a828b | 1003 | interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of |
<> | 156:95d6b41a828b | 1004 | the stream and the corresponding call back is executed. */ |
<> | 156:95d6b41a828b | 1005 | |
<> | 156:95d6b41a828b | 1006 | /* Stop IRDA DMA Tx request if ongoing */ |
<> | 156:95d6b41a828b | 1007 | if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && |
<> | 156:95d6b41a828b | 1008 | (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))) |
<> | 156:95d6b41a828b | 1009 | { |
<> | 156:95d6b41a828b | 1010 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); |
<> | 156:95d6b41a828b | 1011 | |
<> | 156:95d6b41a828b | 1012 | /* Abort the IRDA DMA Tx channel */ |
<> | 156:95d6b41a828b | 1013 | if(hirda->hdmatx != NULL) |
<> | 156:95d6b41a828b | 1014 | { |
<> | 156:95d6b41a828b | 1015 | HAL_DMA_Abort(hirda->hdmatx); |
<> | 156:95d6b41a828b | 1016 | } |
<> | 156:95d6b41a828b | 1017 | |
<> | 156:95d6b41a828b | 1018 | IRDA_EndTxTransfer(hirda); |
<> | 156:95d6b41a828b | 1019 | } |
<> | 156:95d6b41a828b | 1020 | |
<> | 156:95d6b41a828b | 1021 | /* Stop IRDA DMA Rx request if ongoing */ |
<> | 156:95d6b41a828b | 1022 | if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && |
<> | 156:95d6b41a828b | 1023 | (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) |
<> | 156:95d6b41a828b | 1024 | { |
<> | 156:95d6b41a828b | 1025 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); |
<> | 156:95d6b41a828b | 1026 | |
<> | 156:95d6b41a828b | 1027 | /* Abort the IRDA DMA Rx channel */ |
<> | 156:95d6b41a828b | 1028 | if(hirda->hdmarx != NULL) |
<> | 156:95d6b41a828b | 1029 | { |
<> | 156:95d6b41a828b | 1030 | HAL_DMA_Abort(hirda->hdmarx); |
<> | 156:95d6b41a828b | 1031 | } |
<> | 156:95d6b41a828b | 1032 | |
<> | 156:95d6b41a828b | 1033 | IRDA_EndRxTransfer(hirda); |
<> | 156:95d6b41a828b | 1034 | } |
<> | 156:95d6b41a828b | 1035 | |
<> | 156:95d6b41a828b | 1036 | return HAL_OK; |
<> | 156:95d6b41a828b | 1037 | } |
<> | 156:95d6b41a828b | 1038 | |
<> | 156:95d6b41a828b | 1039 | /** |
<> | 156:95d6b41a828b | 1040 | * @brief Abort ongoing transfers (blocking mode). |
<> | 156:95d6b41a828b | 1041 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 1042 | * the configuration information for the specified UART module. |
<> | 156:95d6b41a828b | 1043 | * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. |
<> | 156:95d6b41a828b | 1044 | * This procedure performs following operations : |
<> | 156:95d6b41a828b | 1045 | * - Disable IRDA Interrupts (Tx and Rx) |
<> | 156:95d6b41a828b | 1046 | * - Disable the DMA transfer in the peripheral register (if enabled) |
<> | 156:95d6b41a828b | 1047 | * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) |
<> | 156:95d6b41a828b | 1048 | * - Set handle State to READY |
<> | 156:95d6b41a828b | 1049 | * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. |
<> | 156:95d6b41a828b | 1050 | * @retval HAL status |
<> | 156:95d6b41a828b | 1051 | */ |
<> | 156:95d6b41a828b | 1052 | HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) |
<> | 156:95d6b41a828b | 1053 | { |
<> | 156:95d6b41a828b | 1054 | /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ |
<> | 156:95d6b41a828b | 1055 | CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); |
<> | 156:95d6b41a828b | 1056 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); |
<> | 156:95d6b41a828b | 1057 | |
<> | 156:95d6b41a828b | 1058 | /* Disable the IRDA DMA Tx request if enabled */ |
<> | 156:95d6b41a828b | 1059 | if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) |
<> | 156:95d6b41a828b | 1060 | { |
<> | 156:95d6b41a828b | 1061 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); |
<> | 156:95d6b41a828b | 1062 | |
<> | 156:95d6b41a828b | 1063 | /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */ |
<> | 156:95d6b41a828b | 1064 | if(hirda->hdmatx != NULL) |
<> | 156:95d6b41a828b | 1065 | { |
<> | 156:95d6b41a828b | 1066 | /* Set the IRDA DMA Abort callback to Null. |
<> | 156:95d6b41a828b | 1067 | No call back execution at end of DMA abort procedure */ |
<> | 156:95d6b41a828b | 1068 | hirda->hdmatx->XferAbortCallback = NULL; |
<> | 156:95d6b41a828b | 1069 | |
<> | 156:95d6b41a828b | 1070 | HAL_DMA_Abort(hirda->hdmatx); |
<> | 156:95d6b41a828b | 1071 | } |
<> | 156:95d6b41a828b | 1072 | } |
<> | 156:95d6b41a828b | 1073 | |
<> | 156:95d6b41a828b | 1074 | /* Disable the IRDA DMA Rx request if enabled */ |
<> | 156:95d6b41a828b | 1075 | if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) |
<> | 156:95d6b41a828b | 1076 | { |
<> | 156:95d6b41a828b | 1077 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); |
<> | 156:95d6b41a828b | 1078 | |
<> | 156:95d6b41a828b | 1079 | /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */ |
<> | 156:95d6b41a828b | 1080 | if(hirda->hdmarx != NULL) |
<> | 156:95d6b41a828b | 1081 | { |
<> | 156:95d6b41a828b | 1082 | /* Set the IRDA DMA Abort callback to Null. |
<> | 156:95d6b41a828b | 1083 | No call back execution at end of DMA abort procedure */ |
<> | 156:95d6b41a828b | 1084 | hirda->hdmarx->XferAbortCallback = NULL; |
<> | 156:95d6b41a828b | 1085 | |
<> | 156:95d6b41a828b | 1086 | HAL_DMA_Abort(hirda->hdmarx); |
<> | 156:95d6b41a828b | 1087 | } |
<> | 156:95d6b41a828b | 1088 | } |
<> | 156:95d6b41a828b | 1089 | |
<> | 156:95d6b41a828b | 1090 | /* Reset Tx and Rx transfer counters */ |
<> | 156:95d6b41a828b | 1091 | hirda->TxXferCount = 0U; |
<> | 156:95d6b41a828b | 1092 | hirda->RxXferCount = 0U; |
<> | 156:95d6b41a828b | 1093 | |
<> | 156:95d6b41a828b | 1094 | /* Clear the Error flags in the ICR register */ |
<> | 156:95d6b41a828b | 1095 | __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); |
<> | 144:ef7eb2e8f9f7 | 1096 | |
<> | 156:95d6b41a828b | 1097 | /* Restore hirda->gState and hirda->RxState to Ready */ |
<> | 156:95d6b41a828b | 1098 | hirda->gState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 1099 | hirda->RxState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 1100 | |
<> | 156:95d6b41a828b | 1101 | /* Reset Handle ErrorCode to No Error */ |
<> | 156:95d6b41a828b | 1102 | hirda->ErrorCode = HAL_IRDA_ERROR_NONE; |
<> | 156:95d6b41a828b | 1103 | |
<> | 156:95d6b41a828b | 1104 | return HAL_OK; |
<> | 156:95d6b41a828b | 1105 | } |
<> | 156:95d6b41a828b | 1106 | |
<> | 156:95d6b41a828b | 1107 | /** |
<> | 156:95d6b41a828b | 1108 | * @brief Abort ongoing Transmit transfer (blocking mode). |
<> | 156:95d6b41a828b | 1109 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 1110 | * the configuration information for the specified UART module. |
<> | 156:95d6b41a828b | 1111 | * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. |
<> | 156:95d6b41a828b | 1112 | * This procedure performs following operations : |
<> | 156:95d6b41a828b | 1113 | * - Disable IRDA Interrupts (Tx) |
<> | 156:95d6b41a828b | 1114 | * - Disable the DMA transfer in the peripheral register (if enabled) |
<> | 156:95d6b41a828b | 1115 | * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) |
<> | 156:95d6b41a828b | 1116 | * - Set handle State to READY |
<> | 156:95d6b41a828b | 1117 | * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. |
<> | 156:95d6b41a828b | 1118 | * @retval HAL status |
<> | 156:95d6b41a828b | 1119 | */ |
<> | 156:95d6b41a828b | 1120 | HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) |
<> | 156:95d6b41a828b | 1121 | { |
<> | 156:95d6b41a828b | 1122 | /* Disable TXEIE and TCIE interrupts */ |
<> | 156:95d6b41a828b | 1123 | CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); |
<> | 156:95d6b41a828b | 1124 | |
<> | 156:95d6b41a828b | 1125 | /* Disable the IRDA DMA Tx request if enabled */ |
<> | 156:95d6b41a828b | 1126 | if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) |
<> | 144:ef7eb2e8f9f7 | 1127 | { |
<> | 156:95d6b41a828b | 1128 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); |
<> | 156:95d6b41a828b | 1129 | |
<> | 156:95d6b41a828b | 1130 | /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */ |
<> | 156:95d6b41a828b | 1131 | if(hirda->hdmatx != NULL) |
<> | 156:95d6b41a828b | 1132 | { |
<> | 156:95d6b41a828b | 1133 | /* Set the IRDA DMA Abort callback to Null. |
<> | 156:95d6b41a828b | 1134 | No call back execution at end of DMA abort procedure */ |
<> | 156:95d6b41a828b | 1135 | hirda->hdmatx->XferAbortCallback = NULL; |
<> | 156:95d6b41a828b | 1136 | |
<> | 156:95d6b41a828b | 1137 | HAL_DMA_Abort(hirda->hdmatx); |
<> | 156:95d6b41a828b | 1138 | } |
<> | 144:ef7eb2e8f9f7 | 1139 | } |
<> | 156:95d6b41a828b | 1140 | |
<> | 156:95d6b41a828b | 1141 | /* Reset Tx transfer counter */ |
<> | 156:95d6b41a828b | 1142 | hirda->TxXferCount = 0U; |
<> | 156:95d6b41a828b | 1143 | |
<> | 156:95d6b41a828b | 1144 | /* Restore hirda->gState to Ready */ |
<> | 156:95d6b41a828b | 1145 | hirda->gState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 1146 | |
<> | 156:95d6b41a828b | 1147 | return HAL_OK; |
<> | 156:95d6b41a828b | 1148 | } |
<> | 156:95d6b41a828b | 1149 | |
<> | 156:95d6b41a828b | 1150 | /** |
<> | 156:95d6b41a828b | 1151 | * @brief Abort ongoing Receive transfer (blocking mode). |
<> | 156:95d6b41a828b | 1152 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 1153 | * the configuration information for the specified UART module. |
<> | 156:95d6b41a828b | 1154 | * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. |
<> | 156:95d6b41a828b | 1155 | * This procedure performs following operations : |
<> | 156:95d6b41a828b | 1156 | * - Disable IRDA Interrupts (Rx) |
<> | 156:95d6b41a828b | 1157 | * - Disable the DMA transfer in the peripheral register (if enabled) |
<> | 156:95d6b41a828b | 1158 | * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) |
<> | 156:95d6b41a828b | 1159 | * - Set handle State to READY |
<> | 156:95d6b41a828b | 1160 | * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. |
<> | 156:95d6b41a828b | 1161 | * @retval HAL status |
<> | 156:95d6b41a828b | 1162 | */ |
<> | 156:95d6b41a828b | 1163 | HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) |
<> | 156:95d6b41a828b | 1164 | { |
<> | 156:95d6b41a828b | 1165 | /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ |
<> | 156:95d6b41a828b | 1166 | CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); |
<> | 156:95d6b41a828b | 1167 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); |
<> | 156:95d6b41a828b | 1168 | |
<> | 156:95d6b41a828b | 1169 | /* Disable the IRDA DMA Rx request if enabled */ |
<> | 156:95d6b41a828b | 1170 | if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) |
<> | 144:ef7eb2e8f9f7 | 1171 | { |
<> | 156:95d6b41a828b | 1172 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); |
<> | 156:95d6b41a828b | 1173 | |
<> | 156:95d6b41a828b | 1174 | /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */ |
<> | 156:95d6b41a828b | 1175 | if(hirda->hdmarx != NULL) |
<> | 156:95d6b41a828b | 1176 | { |
<> | 156:95d6b41a828b | 1177 | /* Set the IRDA DMA Abort callback to Null. |
<> | 156:95d6b41a828b | 1178 | No call back execution at end of DMA abort procedure */ |
<> | 156:95d6b41a828b | 1179 | hirda->hdmarx->XferAbortCallback = NULL; |
<> | 156:95d6b41a828b | 1180 | |
<> | 156:95d6b41a828b | 1181 | HAL_DMA_Abort(hirda->hdmarx); |
<> | 156:95d6b41a828b | 1182 | } |
<> | 144:ef7eb2e8f9f7 | 1183 | } |
<> | 156:95d6b41a828b | 1184 | |
<> | 156:95d6b41a828b | 1185 | /* Reset Rx transfer counter */ |
<> | 156:95d6b41a828b | 1186 | hirda->RxXferCount = 0U; |
<> | 156:95d6b41a828b | 1187 | |
<> | 156:95d6b41a828b | 1188 | /* Clear the Error flags in the ICR register */ |
<> | 156:95d6b41a828b | 1189 | __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); |
<> | 156:95d6b41a828b | 1190 | |
<> | 156:95d6b41a828b | 1191 | /* Restore hirda->RxState to Ready */ |
<> | 144:ef7eb2e8f9f7 | 1192 | hirda->RxState = HAL_IRDA_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1193 | |
<> | 144:ef7eb2e8f9f7 | 1194 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1195 | } |
<> | 144:ef7eb2e8f9f7 | 1196 | |
<> | 156:95d6b41a828b | 1197 | /** |
<> | 156:95d6b41a828b | 1198 | * @brief Abort ongoing transfers (Interrupt mode). |
<> | 156:95d6b41a828b | 1199 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 1200 | * the configuration information for the specified UART module. |
<> | 156:95d6b41a828b | 1201 | * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. |
<> | 156:95d6b41a828b | 1202 | * This procedure performs following operations : |
<> | 156:95d6b41a828b | 1203 | * - Disable IRDA Interrupts (Tx and Rx) |
<> | 156:95d6b41a828b | 1204 | * - Disable the DMA transfer in the peripheral register (if enabled) |
<> | 156:95d6b41a828b | 1205 | * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) |
<> | 156:95d6b41a828b | 1206 | * - Set handle State to READY |
<> | 156:95d6b41a828b | 1207 | * - At abort completion, call user abort complete callback |
<> | 156:95d6b41a828b | 1208 | * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be |
<> | 156:95d6b41a828b | 1209 | * considered as completed only when user abort complete callback is executed (not when exiting function). |
<> | 156:95d6b41a828b | 1210 | * @retval HAL status |
<> | 156:95d6b41a828b | 1211 | */ |
<> | 156:95d6b41a828b | 1212 | HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) |
<> | 156:95d6b41a828b | 1213 | { |
<> | 156:95d6b41a828b | 1214 | uint32_t abortcplt = 1U; |
<> | 156:95d6b41a828b | 1215 | |
<> | 156:95d6b41a828b | 1216 | /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ |
<> | 156:95d6b41a828b | 1217 | CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); |
<> | 156:95d6b41a828b | 1218 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); |
<> | 156:95d6b41a828b | 1219 | |
<> | 156:95d6b41a828b | 1220 | /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised |
<> | 156:95d6b41a828b | 1221 | before any call to DMA Abort functions */ |
<> | 156:95d6b41a828b | 1222 | /* DMA Tx Handle is valid */ |
<> | 156:95d6b41a828b | 1223 | if(hirda->hdmatx != NULL) |
<> | 156:95d6b41a828b | 1224 | { |
<> | 156:95d6b41a828b | 1225 | /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled. |
<> | 156:95d6b41a828b | 1226 | Otherwise, set it to NULL */ |
<> | 156:95d6b41a828b | 1227 | if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) |
<> | 156:95d6b41a828b | 1228 | { |
<> | 156:95d6b41a828b | 1229 | hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback; |
<> | 156:95d6b41a828b | 1230 | } |
<> | 156:95d6b41a828b | 1231 | else |
<> | 156:95d6b41a828b | 1232 | { |
<> | 156:95d6b41a828b | 1233 | hirda->hdmatx->XferAbortCallback = NULL; |
<> | 156:95d6b41a828b | 1234 | } |
<> | 156:95d6b41a828b | 1235 | } |
<> | 156:95d6b41a828b | 1236 | /* DMA Rx Handle is valid */ |
<> | 156:95d6b41a828b | 1237 | if(hirda->hdmarx != NULL) |
<> | 156:95d6b41a828b | 1238 | { |
<> | 156:95d6b41a828b | 1239 | /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled. |
<> | 156:95d6b41a828b | 1240 | Otherwise, set it to NULL */ |
<> | 156:95d6b41a828b | 1241 | if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) |
<> | 156:95d6b41a828b | 1242 | { |
<> | 156:95d6b41a828b | 1243 | hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback; |
<> | 156:95d6b41a828b | 1244 | } |
<> | 156:95d6b41a828b | 1245 | else |
<> | 156:95d6b41a828b | 1246 | { |
<> | 156:95d6b41a828b | 1247 | hirda->hdmarx->XferAbortCallback = NULL; |
<> | 156:95d6b41a828b | 1248 | } |
<> | 156:95d6b41a828b | 1249 | } |
<> | 156:95d6b41a828b | 1250 | |
<> | 156:95d6b41a828b | 1251 | /* Disable the IRDA DMA Tx request if enabled */ |
<> | 156:95d6b41a828b | 1252 | if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) |
<> | 156:95d6b41a828b | 1253 | { |
<> | 156:95d6b41a828b | 1254 | /* Disable DMA Tx at UART level */ |
<> | 156:95d6b41a828b | 1255 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); |
<> | 156:95d6b41a828b | 1256 | |
<> | 156:95d6b41a828b | 1257 | /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */ |
<> | 156:95d6b41a828b | 1258 | if(hirda->hdmatx != NULL) |
<> | 156:95d6b41a828b | 1259 | { |
<> | 156:95d6b41a828b | 1260 | /* IRDA Tx DMA Abort callback has already been initialised : |
<> | 156:95d6b41a828b | 1261 | will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ |
<> | 156:95d6b41a828b | 1262 | |
<> | 156:95d6b41a828b | 1263 | /* Abort DMA TX */ |
<> | 156:95d6b41a828b | 1264 | if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) |
<> | 156:95d6b41a828b | 1265 | { |
<> | 156:95d6b41a828b | 1266 | hirda->hdmatx->XferAbortCallback = NULL; |
<> | 156:95d6b41a828b | 1267 | } |
<> | 156:95d6b41a828b | 1268 | else |
<> | 156:95d6b41a828b | 1269 | { |
<> | 156:95d6b41a828b | 1270 | abortcplt = 0U; |
<> | 156:95d6b41a828b | 1271 | } |
<> | 156:95d6b41a828b | 1272 | } |
<> | 156:95d6b41a828b | 1273 | } |
<> | 156:95d6b41a828b | 1274 | |
<> | 156:95d6b41a828b | 1275 | /* Disable the IRDA DMA Rx request if enabled */ |
<> | 156:95d6b41a828b | 1276 | if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) |
<> | 156:95d6b41a828b | 1277 | { |
<> | 156:95d6b41a828b | 1278 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); |
<> | 156:95d6b41a828b | 1279 | |
<> | 156:95d6b41a828b | 1280 | /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */ |
<> | 156:95d6b41a828b | 1281 | if(hirda->hdmarx != NULL) |
<> | 156:95d6b41a828b | 1282 | { |
<> | 156:95d6b41a828b | 1283 | /* IRDA Rx DMA Abort callback has already been initialised : |
<> | 156:95d6b41a828b | 1284 | will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ |
<> | 156:95d6b41a828b | 1285 | |
<> | 156:95d6b41a828b | 1286 | /* Abort DMA RX */ |
<> | 156:95d6b41a828b | 1287 | if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) |
<> | 156:95d6b41a828b | 1288 | { |
<> | 156:95d6b41a828b | 1289 | hirda->hdmarx->XferAbortCallback = NULL; |
<> | 156:95d6b41a828b | 1290 | abortcplt = 1; |
<> | 156:95d6b41a828b | 1291 | } |
<> | 156:95d6b41a828b | 1292 | else |
<> | 156:95d6b41a828b | 1293 | { |
<> | 156:95d6b41a828b | 1294 | abortcplt = 0; |
<> | 156:95d6b41a828b | 1295 | } |
<> | 156:95d6b41a828b | 1296 | } |
<> | 156:95d6b41a828b | 1297 | } |
<> | 156:95d6b41a828b | 1298 | |
<> | 156:95d6b41a828b | 1299 | /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ |
<> | 156:95d6b41a828b | 1300 | if (abortcplt == 1U) |
<> | 156:95d6b41a828b | 1301 | { |
<> | 156:95d6b41a828b | 1302 | /* Reset Tx and Rx transfer counters */ |
<> | 156:95d6b41a828b | 1303 | hirda->TxXferCount = 0U; |
<> | 156:95d6b41a828b | 1304 | hirda->RxXferCount = 0U; |
<> | 156:95d6b41a828b | 1305 | |
<> | 156:95d6b41a828b | 1306 | /* Reset errorCode */ |
<> | 156:95d6b41a828b | 1307 | hirda->ErrorCode = HAL_IRDA_ERROR_NONE; |
<> | 156:95d6b41a828b | 1308 | |
<> | 156:95d6b41a828b | 1309 | /* Clear the Error flags in the ICR register */ |
<> | 156:95d6b41a828b | 1310 | __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); |
<> | 156:95d6b41a828b | 1311 | |
<> | 156:95d6b41a828b | 1312 | /* Restore hirda->gState and hirda->RxState to Ready */ |
<> | 156:95d6b41a828b | 1313 | hirda->gState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 1314 | hirda->RxState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 1315 | |
<> | 156:95d6b41a828b | 1316 | /* As no DMA to be aborted, call directly user Abort complete callback */ |
<> | 156:95d6b41a828b | 1317 | HAL_IRDA_AbortCpltCallback(hirda); |
<> | 156:95d6b41a828b | 1318 | } |
<> | 156:95d6b41a828b | 1319 | |
<> | 156:95d6b41a828b | 1320 | return HAL_OK; |
<> | 156:95d6b41a828b | 1321 | } |
<> | 144:ef7eb2e8f9f7 | 1322 | |
<> | 144:ef7eb2e8f9f7 | 1323 | /** |
<> | 156:95d6b41a828b | 1324 | * @brief Abort ongoing Transmit transfer (Interrupt mode). |
<> | 156:95d6b41a828b | 1325 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 1326 | * the configuration information for the specified UART module. |
<> | 156:95d6b41a828b | 1327 | * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. |
<> | 156:95d6b41a828b | 1328 | * This procedure performs following operations : |
<> | 156:95d6b41a828b | 1329 | * - Disable IRDA Interrupts (Tx) |
<> | 156:95d6b41a828b | 1330 | * - Disable the DMA transfer in the peripheral register (if enabled) |
<> | 156:95d6b41a828b | 1331 | * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) |
<> | 156:95d6b41a828b | 1332 | * - Set handle State to READY |
<> | 156:95d6b41a828b | 1333 | * - At abort completion, call user abort complete callback |
<> | 156:95d6b41a828b | 1334 | * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be |
<> | 156:95d6b41a828b | 1335 | * considered as completed only when user abort complete callback is executed (not when exiting function). |
<> | 156:95d6b41a828b | 1336 | * @retval HAL status |
<> | 156:95d6b41a828b | 1337 | */ |
<> | 156:95d6b41a828b | 1338 | HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) |
<> | 156:95d6b41a828b | 1339 | { |
<> | 156:95d6b41a828b | 1340 | /* Disable TXEIE and TCIE interrupts */ |
<> | 156:95d6b41a828b | 1341 | CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); |
<> | 156:95d6b41a828b | 1342 | |
<> | 156:95d6b41a828b | 1343 | /* Disable the IRDA DMA Tx request if enabled */ |
<> | 156:95d6b41a828b | 1344 | if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) |
<> | 156:95d6b41a828b | 1345 | { |
<> | 156:95d6b41a828b | 1346 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); |
<> | 156:95d6b41a828b | 1347 | |
<> | 156:95d6b41a828b | 1348 | /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */ |
<> | 156:95d6b41a828b | 1349 | if(hirda->hdmatx != NULL) |
<> | 156:95d6b41a828b | 1350 | { |
<> | 156:95d6b41a828b | 1351 | /* Set the IRDA DMA Abort callback : |
<> | 156:95d6b41a828b | 1352 | will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ |
<> | 156:95d6b41a828b | 1353 | hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback; |
<> | 156:95d6b41a828b | 1354 | |
<> | 156:95d6b41a828b | 1355 | /* Abort DMA TX */ |
<> | 156:95d6b41a828b | 1356 | if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) |
<> | 156:95d6b41a828b | 1357 | { |
<> | 156:95d6b41a828b | 1358 | /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */ |
<> | 156:95d6b41a828b | 1359 | hirda->hdmatx->XferAbortCallback(hirda->hdmatx); |
<> | 156:95d6b41a828b | 1360 | } |
<> | 156:95d6b41a828b | 1361 | } |
<> | 156:95d6b41a828b | 1362 | else |
<> | 156:95d6b41a828b | 1363 | { |
<> | 156:95d6b41a828b | 1364 | /* Reset Tx transfer counter */ |
<> | 156:95d6b41a828b | 1365 | hirda->TxXferCount = 0U; |
<> | 156:95d6b41a828b | 1366 | |
<> | 156:95d6b41a828b | 1367 | /* Restore hirda->gState to Ready */ |
<> | 156:95d6b41a828b | 1368 | hirda->gState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 1369 | |
<> | 156:95d6b41a828b | 1370 | /* As no DMA to be aborted, call directly user Abort complete callback */ |
<> | 156:95d6b41a828b | 1371 | HAL_IRDA_AbortTransmitCpltCallback(hirda); |
<> | 156:95d6b41a828b | 1372 | } |
<> | 156:95d6b41a828b | 1373 | } |
<> | 156:95d6b41a828b | 1374 | else |
<> | 156:95d6b41a828b | 1375 | { |
<> | 156:95d6b41a828b | 1376 | /* Reset Tx transfer counter */ |
<> | 156:95d6b41a828b | 1377 | hirda->TxXferCount = 0U; |
<> | 156:95d6b41a828b | 1378 | |
<> | 156:95d6b41a828b | 1379 | /* Restore hirda->gState to Ready */ |
<> | 156:95d6b41a828b | 1380 | hirda->gState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 1381 | |
<> | 156:95d6b41a828b | 1382 | /* As no DMA to be aborted, call directly user Abort complete callback */ |
<> | 156:95d6b41a828b | 1383 | HAL_IRDA_AbortTransmitCpltCallback(hirda); |
<> | 156:95d6b41a828b | 1384 | } |
<> | 156:95d6b41a828b | 1385 | |
<> | 156:95d6b41a828b | 1386 | return HAL_OK; |
<> | 156:95d6b41a828b | 1387 | } |
<> | 156:95d6b41a828b | 1388 | |
<> | 156:95d6b41a828b | 1389 | /** |
<> | 156:95d6b41a828b | 1390 | * @brief Abort ongoing Receive transfer (Interrupt mode). |
<> | 156:95d6b41a828b | 1391 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 1392 | * the configuration information for the specified UART module. |
<> | 156:95d6b41a828b | 1393 | * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. |
<> | 156:95d6b41a828b | 1394 | * This procedure performs following operations : |
<> | 156:95d6b41a828b | 1395 | * - Disable IRDA Interrupts (Rx) |
<> | 156:95d6b41a828b | 1396 | * - Disable the DMA transfer in the peripheral register (if enabled) |
<> | 156:95d6b41a828b | 1397 | * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) |
<> | 156:95d6b41a828b | 1398 | * - Set handle State to READY |
<> | 156:95d6b41a828b | 1399 | * - At abort completion, call user abort complete callback |
<> | 156:95d6b41a828b | 1400 | * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be |
<> | 156:95d6b41a828b | 1401 | * considered as completed only when user abort complete callback is executed (not when exiting function). |
<> | 156:95d6b41a828b | 1402 | * @retval HAL status |
<> | 156:95d6b41a828b | 1403 | */ |
<> | 156:95d6b41a828b | 1404 | HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) |
<> | 156:95d6b41a828b | 1405 | { |
<> | 156:95d6b41a828b | 1406 | /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ |
<> | 156:95d6b41a828b | 1407 | CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); |
<> | 156:95d6b41a828b | 1408 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); |
<> | 156:95d6b41a828b | 1409 | |
<> | 156:95d6b41a828b | 1410 | /* Disable the IRDA DMA Rx request if enabled */ |
<> | 156:95d6b41a828b | 1411 | if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) |
<> | 156:95d6b41a828b | 1412 | { |
<> | 156:95d6b41a828b | 1413 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); |
<> | 156:95d6b41a828b | 1414 | |
<> | 156:95d6b41a828b | 1415 | /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */ |
<> | 156:95d6b41a828b | 1416 | if(hirda->hdmarx != NULL) |
<> | 156:95d6b41a828b | 1417 | { |
<> | 156:95d6b41a828b | 1418 | /* Set the IRDA DMA Abort callback : |
<> | 156:95d6b41a828b | 1419 | will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ |
<> | 156:95d6b41a828b | 1420 | hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback; |
<> | 156:95d6b41a828b | 1421 | |
<> | 156:95d6b41a828b | 1422 | /* Abort DMA RX */ |
<> | 156:95d6b41a828b | 1423 | if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) |
<> | 156:95d6b41a828b | 1424 | { |
<> | 156:95d6b41a828b | 1425 | /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */ |
<> | 156:95d6b41a828b | 1426 | hirda->hdmarx->XferAbortCallback(hirda->hdmarx); |
<> | 156:95d6b41a828b | 1427 | } |
<> | 156:95d6b41a828b | 1428 | } |
<> | 156:95d6b41a828b | 1429 | else |
<> | 156:95d6b41a828b | 1430 | { |
<> | 156:95d6b41a828b | 1431 | /* Reset Rx transfer counter */ |
<> | 156:95d6b41a828b | 1432 | hirda->RxXferCount = 0U; |
<> | 156:95d6b41a828b | 1433 | |
<> | 156:95d6b41a828b | 1434 | /* Clear the Error flags in the ICR register */ |
<> | 156:95d6b41a828b | 1435 | __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); |
<> | 156:95d6b41a828b | 1436 | |
<> | 156:95d6b41a828b | 1437 | /* Restore hirda->RxState to Ready */ |
<> | 156:95d6b41a828b | 1438 | hirda->RxState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 1439 | |
<> | 156:95d6b41a828b | 1440 | /* As no DMA to be aborted, call directly user Abort complete callback */ |
<> | 156:95d6b41a828b | 1441 | HAL_IRDA_AbortReceiveCpltCallback(hirda); |
<> | 156:95d6b41a828b | 1442 | } |
<> | 156:95d6b41a828b | 1443 | } |
<> | 156:95d6b41a828b | 1444 | else |
<> | 156:95d6b41a828b | 1445 | { |
<> | 156:95d6b41a828b | 1446 | /* Reset Rx transfer counter */ |
<> | 156:95d6b41a828b | 1447 | hirda->RxXferCount = 0U; |
<> | 156:95d6b41a828b | 1448 | |
<> | 156:95d6b41a828b | 1449 | /* Clear the Error flags in the ICR register */ |
<> | 156:95d6b41a828b | 1450 | __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); |
<> | 156:95d6b41a828b | 1451 | |
<> | 156:95d6b41a828b | 1452 | /* Restore hirda->RxState to Ready */ |
<> | 156:95d6b41a828b | 1453 | hirda->RxState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 1454 | |
<> | 156:95d6b41a828b | 1455 | /* As no DMA to be aborted, call directly user Abort complete callback */ |
<> | 156:95d6b41a828b | 1456 | HAL_IRDA_AbortReceiveCpltCallback(hirda); |
<> | 156:95d6b41a828b | 1457 | } |
<> | 156:95d6b41a828b | 1458 | |
<> | 156:95d6b41a828b | 1459 | return HAL_OK; |
<> | 156:95d6b41a828b | 1460 | } |
<> | 156:95d6b41a828b | 1461 | |
<> | 156:95d6b41a828b | 1462 | /** |
<> | 156:95d6b41a828b | 1463 | * @brief Handle IRDA interrupt request. |
<> | 156:95d6b41a828b | 1464 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1465 | * the configuration information for the specified IRDA module. |
<> | 144:ef7eb2e8f9f7 | 1466 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1467 | */ |
<> | 144:ef7eb2e8f9f7 | 1468 | void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 1469 | { |
<> | 156:95d6b41a828b | 1470 | uint32_t isrflags = READ_REG(hirda->Instance->ISR); |
<> | 156:95d6b41a828b | 1471 | uint32_t cr1its = READ_REG(hirda->Instance->CR1); |
<> | 156:95d6b41a828b | 1472 | uint32_t cr3its; |
<> | 156:95d6b41a828b | 1473 | uint32_t errorflags; |
<> | 144:ef7eb2e8f9f7 | 1474 | |
<> | 156:95d6b41a828b | 1475 | /* If no error occurs */ |
<> | 156:95d6b41a828b | 1476 | errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); |
<> | 156:95d6b41a828b | 1477 | if (errorflags == RESET) |
<> | 156:95d6b41a828b | 1478 | { |
<> | 156:95d6b41a828b | 1479 | /* IRDA in mode Receiver ---------------------------------------------------*/ |
<> | 156:95d6b41a828b | 1480 | if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) |
<> | 156:95d6b41a828b | 1481 | { |
<> | 156:95d6b41a828b | 1482 | IRDA_Receive_IT(hirda); |
<> | 156:95d6b41a828b | 1483 | return; |
<> | 156:95d6b41a828b | 1484 | } |
<> | 156:95d6b41a828b | 1485 | } |
<> | 156:95d6b41a828b | 1486 | |
<> | 156:95d6b41a828b | 1487 | /* If some errors occur */ |
<> | 156:95d6b41a828b | 1488 | cr3its = READ_REG(hirda->Instance->CR3); |
<> | 156:95d6b41a828b | 1489 | if( (errorflags != RESET) |
<> | 156:95d6b41a828b | 1490 | && ( ((cr3its & USART_CR3_EIE) != RESET) |
<> | 156:95d6b41a828b | 1491 | || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) |
<> | 156:95d6b41a828b | 1492 | { |
<> | 156:95d6b41a828b | 1493 | /* IRDA parity error interrupt occurred -------------------------------------*/ |
<> | 156:95d6b41a828b | 1494 | if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) |
<> | 156:95d6b41a828b | 1495 | { |
<> | 156:95d6b41a828b | 1496 | __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF); |
<> | 144:ef7eb2e8f9f7 | 1497 | |
<> | 156:95d6b41a828b | 1498 | hirda->ErrorCode |= HAL_IRDA_ERROR_PE; |
<> | 156:95d6b41a828b | 1499 | } |
<> | 156:95d6b41a828b | 1500 | |
<> | 156:95d6b41a828b | 1501 | /* IRDA frame error interrupt occurred --------------------------------------*/ |
<> | 156:95d6b41a828b | 1502 | if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) |
<> | 156:95d6b41a828b | 1503 | { |
<> | 156:95d6b41a828b | 1504 | __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF); |
<> | 156:95d6b41a828b | 1505 | |
<> | 156:95d6b41a828b | 1506 | hirda->ErrorCode |= HAL_IRDA_ERROR_FE; |
<> | 156:95d6b41a828b | 1507 | } |
<> | 144:ef7eb2e8f9f7 | 1508 | |
<> | 156:95d6b41a828b | 1509 | /* IRDA noise error interrupt occurred --------------------------------------*/ |
<> | 156:95d6b41a828b | 1510 | if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) |
<> | 156:95d6b41a828b | 1511 | { |
<> | 156:95d6b41a828b | 1512 | __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF); |
<> | 156:95d6b41a828b | 1513 | |
<> | 156:95d6b41a828b | 1514 | hirda->ErrorCode |= HAL_IRDA_ERROR_NE; |
<> | 156:95d6b41a828b | 1515 | } |
<> | 144:ef7eb2e8f9f7 | 1516 | |
<> | 156:95d6b41a828b | 1517 | /* IRDA Over-Run interrupt occurred -----------------------------------------*/ |
<> | 156:95d6b41a828b | 1518 | if(((isrflags & USART_ISR_ORE) != RESET) && |
<> | 156:95d6b41a828b | 1519 | (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) |
<> | 156:95d6b41a828b | 1520 | { |
<> | 156:95d6b41a828b | 1521 | __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); |
<> | 156:95d6b41a828b | 1522 | |
<> | 156:95d6b41a828b | 1523 | hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; |
<> | 156:95d6b41a828b | 1524 | } |
<> | 144:ef7eb2e8f9f7 | 1525 | |
<> | 156:95d6b41a828b | 1526 | /* Call IRDA Error Call back function if need be --------------------------*/ |
<> | 156:95d6b41a828b | 1527 | if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE) |
<> | 156:95d6b41a828b | 1528 | { |
<> | 156:95d6b41a828b | 1529 | /* IRDA in mode Receiver ---------------------------------------------------*/ |
<> | 156:95d6b41a828b | 1530 | if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) |
<> | 156:95d6b41a828b | 1531 | { |
<> | 156:95d6b41a828b | 1532 | IRDA_Receive_IT(hirda); |
<> | 156:95d6b41a828b | 1533 | } |
<> | 144:ef7eb2e8f9f7 | 1534 | |
<> | 156:95d6b41a828b | 1535 | /* If Overrun error occurs, or if any error occurs in DMA mode reception, |
<> | 156:95d6b41a828b | 1536 | consider error as blocking */ |
<> | 156:95d6b41a828b | 1537 | if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) || |
<> | 156:95d6b41a828b | 1538 | (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))) |
<> | 156:95d6b41a828b | 1539 | { |
<> | 156:95d6b41a828b | 1540 | /* Blocking error : transfer is aborted |
<> | 156:95d6b41a828b | 1541 | Set the IRDA state ready to be able to start again the process, |
<> | 156:95d6b41a828b | 1542 | Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ |
<> | 156:95d6b41a828b | 1543 | IRDA_EndRxTransfer(hirda); |
<> | 156:95d6b41a828b | 1544 | |
<> | 156:95d6b41a828b | 1545 | /* Disable the IRDA DMA Rx request if enabled */ |
<> | 156:95d6b41a828b | 1546 | if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) |
<> | 156:95d6b41a828b | 1547 | { |
<> | 156:95d6b41a828b | 1548 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); |
<> | 156:95d6b41a828b | 1549 | |
<> | 156:95d6b41a828b | 1550 | /* Abort the IRDA DMA Rx channel */ |
<> | 156:95d6b41a828b | 1551 | if(hirda->hdmarx != NULL) |
<> | 156:95d6b41a828b | 1552 | { |
<> | 156:95d6b41a828b | 1553 | /* Set the IRDA DMA Abort callback : |
<> | 156:95d6b41a828b | 1554 | will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */ |
<> | 156:95d6b41a828b | 1555 | hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError; |
<> | 144:ef7eb2e8f9f7 | 1556 | |
<> | 156:95d6b41a828b | 1557 | /* Abort DMA RX */ |
<> | 156:95d6b41a828b | 1558 | if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) |
<> | 156:95d6b41a828b | 1559 | { |
<> | 156:95d6b41a828b | 1560 | /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */ |
<> | 156:95d6b41a828b | 1561 | hirda->hdmarx->XferAbortCallback(hirda->hdmarx); |
<> | 156:95d6b41a828b | 1562 | } |
<> | 156:95d6b41a828b | 1563 | } |
<> | 156:95d6b41a828b | 1564 | else |
<> | 156:95d6b41a828b | 1565 | { |
<> | 156:95d6b41a828b | 1566 | /* Call user error callback */ |
<> | 156:95d6b41a828b | 1567 | HAL_IRDA_ErrorCallback(hirda); |
<> | 156:95d6b41a828b | 1568 | } |
<> | 156:95d6b41a828b | 1569 | } |
<> | 156:95d6b41a828b | 1570 | else |
<> | 156:95d6b41a828b | 1571 | { |
<> | 156:95d6b41a828b | 1572 | /* Call user error callback */ |
<> | 156:95d6b41a828b | 1573 | HAL_IRDA_ErrorCallback(hirda); |
<> | 156:95d6b41a828b | 1574 | } |
<> | 156:95d6b41a828b | 1575 | } |
<> | 156:95d6b41a828b | 1576 | else |
<> | 156:95d6b41a828b | 1577 | { |
<> | 156:95d6b41a828b | 1578 | /* Non Blocking error : transfer could go on. |
<> | 156:95d6b41a828b | 1579 | Error is notified to user through user error callback */ |
<> | 156:95d6b41a828b | 1580 | HAL_IRDA_ErrorCallback(hirda); |
<> | 156:95d6b41a828b | 1581 | hirda->ErrorCode = HAL_IRDA_ERROR_NONE; |
<> | 156:95d6b41a828b | 1582 | } |
<> | 156:95d6b41a828b | 1583 | } |
<> | 156:95d6b41a828b | 1584 | return; |
<> | 144:ef7eb2e8f9f7 | 1585 | |
<> | 156:95d6b41a828b | 1586 | } /* End if some error occurs */ |
<> | 144:ef7eb2e8f9f7 | 1587 | |
<> | 144:ef7eb2e8f9f7 | 1588 | /* IRDA in mode Transmitter ------------------------------------------------*/ |
<> | 156:95d6b41a828b | 1589 | if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 1590 | { |
<> | 144:ef7eb2e8f9f7 | 1591 | IRDA_Transmit_IT(hirda); |
<> | 156:95d6b41a828b | 1592 | return; |
<> | 144:ef7eb2e8f9f7 | 1593 | } |
<> | 144:ef7eb2e8f9f7 | 1594 | |
<> | 144:ef7eb2e8f9f7 | 1595 | /* IRDA in mode Transmitter (transmission end) -----------------------------*/ |
<> | 156:95d6b41a828b | 1596 | if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 1597 | { |
<> | 144:ef7eb2e8f9f7 | 1598 | IRDA_EndTransmit_IT(hirda); |
<> | 156:95d6b41a828b | 1599 | return; |
<> | 144:ef7eb2e8f9f7 | 1600 | } |
<> | 144:ef7eb2e8f9f7 | 1601 | |
<> | 144:ef7eb2e8f9f7 | 1602 | } |
<> | 144:ef7eb2e8f9f7 | 1603 | |
<> | 144:ef7eb2e8f9f7 | 1604 | /** |
<> | 144:ef7eb2e8f9f7 | 1605 | * @brief Tx Transfer completed callback. |
<> | 156:95d6b41a828b | 1606 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 1607 | * the configuration information for the specified IRDA module. |
<> | 144:ef7eb2e8f9f7 | 1608 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1609 | */ |
<> | 156:95d6b41a828b | 1610 | __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 1611 | { |
<> | 144:ef7eb2e8f9f7 | 1612 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1613 | UNUSED(hirda); |
<> | 144:ef7eb2e8f9f7 | 1614 | |
<> | 156:95d6b41a828b | 1615 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 156:95d6b41a828b | 1616 | the HAL_IRDA_TxCpltCallback can be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 1617 | */ |
<> | 144:ef7eb2e8f9f7 | 1618 | } |
<> | 144:ef7eb2e8f9f7 | 1619 | |
<> | 144:ef7eb2e8f9f7 | 1620 | /** |
<> | 144:ef7eb2e8f9f7 | 1621 | * @brief Tx Half Transfer completed callback. |
<> | 156:95d6b41a828b | 1622 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 1623 | * the configuration information for the specified USART module. |
<> | 144:ef7eb2e8f9f7 | 1624 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1625 | */ |
<> | 156:95d6b41a828b | 1626 | __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 1627 | { |
<> | 144:ef7eb2e8f9f7 | 1628 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1629 | UNUSED(hirda); |
<> | 144:ef7eb2e8f9f7 | 1630 | |
<> | 156:95d6b41a828b | 1631 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 156:95d6b41a828b | 1632 | the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 1633 | */ |
<> | 144:ef7eb2e8f9f7 | 1634 | } |
<> | 144:ef7eb2e8f9f7 | 1635 | |
<> | 144:ef7eb2e8f9f7 | 1636 | /** |
<> | 144:ef7eb2e8f9f7 | 1637 | * @brief Rx Transfer completed callback. |
<> | 156:95d6b41a828b | 1638 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 1639 | * the configuration information for the specified IRDA module. |
<> | 144:ef7eb2e8f9f7 | 1640 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1641 | */ |
<> | 144:ef7eb2e8f9f7 | 1642 | __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 1643 | { |
<> | 144:ef7eb2e8f9f7 | 1644 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1645 | UNUSED(hirda); |
<> | 144:ef7eb2e8f9f7 | 1646 | |
<> | 156:95d6b41a828b | 1647 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 156:95d6b41a828b | 1648 | the HAL_IRDA_RxCpltCallback can be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 1649 | */ |
<> | 144:ef7eb2e8f9f7 | 1650 | } |
<> | 144:ef7eb2e8f9f7 | 1651 | |
<> | 144:ef7eb2e8f9f7 | 1652 | /** |
<> | 144:ef7eb2e8f9f7 | 1653 | * @brief Rx Half Transfer complete callback. |
Anna Bridge |
180:96ed750bd169 | 1654 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1655 | * the configuration information for the specified IRDA module. |
<> | 144:ef7eb2e8f9f7 | 1656 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1657 | */ |
<> | 144:ef7eb2e8f9f7 | 1658 | __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 1659 | { |
<> | 144:ef7eb2e8f9f7 | 1660 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1661 | UNUSED(hirda); |
<> | 144:ef7eb2e8f9f7 | 1662 | |
<> | 144:ef7eb2e8f9f7 | 1663 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1664 | the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 1665 | */ |
<> | 144:ef7eb2e8f9f7 | 1666 | } |
<> | 144:ef7eb2e8f9f7 | 1667 | |
<> | 144:ef7eb2e8f9f7 | 1668 | /** |
<> | 144:ef7eb2e8f9f7 | 1669 | * @brief IRDA error callback. |
<> | 156:95d6b41a828b | 1670 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 1671 | * the configuration information for the specified IRDA module. |
<> | 144:ef7eb2e8f9f7 | 1672 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1673 | */ |
<> | 156:95d6b41a828b | 1674 | __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) |
<> | 156:95d6b41a828b | 1675 | { |
<> | 156:95d6b41a828b | 1676 | /* Prevent unused argument(s) compilation warning */ |
<> | 156:95d6b41a828b | 1677 | UNUSED(hirda); |
<> | 156:95d6b41a828b | 1678 | |
<> | 156:95d6b41a828b | 1679 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 156:95d6b41a828b | 1680 | the HAL_IRDA_ErrorCallback can be implemented in the user file. |
<> | 156:95d6b41a828b | 1681 | */ |
<> | 156:95d6b41a828b | 1682 | } |
<> | 156:95d6b41a828b | 1683 | |
<> | 156:95d6b41a828b | 1684 | /** |
<> | 156:95d6b41a828b | 1685 | * @brief IRDA Abort Complete callback. |
<> | 156:95d6b41a828b | 1686 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 1687 | * the configuration information for the specified IRDA module. |
<> | 156:95d6b41a828b | 1688 | * @retval None |
<> | 156:95d6b41a828b | 1689 | */ |
<> | 156:95d6b41a828b | 1690 | __weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 1691 | { |
<> | 144:ef7eb2e8f9f7 | 1692 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1693 | UNUSED(hirda); |
<> | 144:ef7eb2e8f9f7 | 1694 | |
<> | 156:95d6b41a828b | 1695 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 156:95d6b41a828b | 1696 | the HAL_IRDA_AbortCpltCallback can be implemented in the user file. |
<> | 156:95d6b41a828b | 1697 | */ |
<> | 156:95d6b41a828b | 1698 | } |
<> | 156:95d6b41a828b | 1699 | |
<> | 156:95d6b41a828b | 1700 | /** |
<> | 156:95d6b41a828b | 1701 | * @brief IRDA Abort Complete callback. |
<> | 156:95d6b41a828b | 1702 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 1703 | * the configuration information for the specified IRDA module. |
<> | 156:95d6b41a828b | 1704 | * @retval None |
<> | 156:95d6b41a828b | 1705 | */ |
<> | 156:95d6b41a828b | 1706 | __weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda) |
<> | 156:95d6b41a828b | 1707 | { |
<> | 156:95d6b41a828b | 1708 | /* Prevent unused argument(s) compilation warning */ |
<> | 156:95d6b41a828b | 1709 | UNUSED(hirda); |
<> | 156:95d6b41a828b | 1710 | |
<> | 156:95d6b41a828b | 1711 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 156:95d6b41a828b | 1712 | the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file. |
<> | 156:95d6b41a828b | 1713 | */ |
<> | 156:95d6b41a828b | 1714 | } |
<> | 156:95d6b41a828b | 1715 | |
<> | 156:95d6b41a828b | 1716 | /** |
<> | 156:95d6b41a828b | 1717 | * @brief IRDA Abort Receive Complete callback. |
<> | 156:95d6b41a828b | 1718 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 1719 | * the configuration information for the specified IRDA module. |
<> | 156:95d6b41a828b | 1720 | * @retval None |
<> | 156:95d6b41a828b | 1721 | */ |
<> | 156:95d6b41a828b | 1722 | __weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda) |
<> | 156:95d6b41a828b | 1723 | { |
<> | 156:95d6b41a828b | 1724 | /* Prevent unused argument(s) compilation warning */ |
<> | 156:95d6b41a828b | 1725 | UNUSED(hirda); |
<> | 156:95d6b41a828b | 1726 | |
<> | 156:95d6b41a828b | 1727 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 156:95d6b41a828b | 1728 | the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 1729 | */ |
<> | 144:ef7eb2e8f9f7 | 1730 | } |
<> | 144:ef7eb2e8f9f7 | 1731 | |
<> | 144:ef7eb2e8f9f7 | 1732 | /** |
<> | 144:ef7eb2e8f9f7 | 1733 | * @} |
<> | 144:ef7eb2e8f9f7 | 1734 | */ |
<> | 144:ef7eb2e8f9f7 | 1735 | |
<> | 144:ef7eb2e8f9f7 | 1736 | /** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions |
<> | 144:ef7eb2e8f9f7 | 1737 | * @brief IRDA State and Errors functions |
<> | 144:ef7eb2e8f9f7 | 1738 | * |
<> | 144:ef7eb2e8f9f7 | 1739 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 1740 | ============================================================================== |
<> | 156:95d6b41a828b | 1741 | ##### Peripheral State and Error functions ##### |
<> | 144:ef7eb2e8f9f7 | 1742 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1743 | [..] |
<> | 144:ef7eb2e8f9f7 | 1744 | This subsection provides a set of functions allowing to return the State of IrDA |
<> | 144:ef7eb2e8f9f7 | 1745 | communication process and also return Peripheral Errors occurred during communication process |
<> | 144:ef7eb2e8f9f7 | 1746 | (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state |
<> | 144:ef7eb2e8f9f7 | 1747 | of the IRDA peripheral handle. |
<> | 144:ef7eb2e8f9f7 | 1748 | (+) HAL_IRDA_GetError() checks in run-time errors that could occur during |
<> | 144:ef7eb2e8f9f7 | 1749 | communication. |
<> | 144:ef7eb2e8f9f7 | 1750 | |
<> | 144:ef7eb2e8f9f7 | 1751 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 1752 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1753 | */ |
<> | 144:ef7eb2e8f9f7 | 1754 | |
<> | 144:ef7eb2e8f9f7 | 1755 | /** |
<> | 144:ef7eb2e8f9f7 | 1756 | * @brief Return the IRDA handle state. |
<> | 144:ef7eb2e8f9f7 | 1757 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1758 | * the configuration information for the specified IRDA module. |
<> | 144:ef7eb2e8f9f7 | 1759 | * @retval HAL state |
<> | 144:ef7eb2e8f9f7 | 1760 | */ |
<> | 144:ef7eb2e8f9f7 | 1761 | HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 1762 | { |
<> | 144:ef7eb2e8f9f7 | 1763 | /* Return IRDA handle state */ |
<> | 156:95d6b41a828b | 1764 | uint32_t temp1= 0x00U, temp2 = 0x00U; |
<> | 144:ef7eb2e8f9f7 | 1765 | temp1 = hirda->gState; |
<> | 144:ef7eb2e8f9f7 | 1766 | temp2 = hirda->RxState; |
<> | 156:95d6b41a828b | 1767 | |
<> | 144:ef7eb2e8f9f7 | 1768 | return (HAL_IRDA_StateTypeDef)(temp1 | temp2); |
<> | 144:ef7eb2e8f9f7 | 1769 | } |
<> | 144:ef7eb2e8f9f7 | 1770 | |
<> | 144:ef7eb2e8f9f7 | 1771 | /** |
<> | 144:ef7eb2e8f9f7 | 1772 | * @brief Return the IRDA handle error code. |
<> | 144:ef7eb2e8f9f7 | 1773 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1774 | * the configuration information for the specified IRDA module. |
<> | 144:ef7eb2e8f9f7 | 1775 | * @retval IRDA Error Code |
<> | 144:ef7eb2e8f9f7 | 1776 | */ |
<> | 144:ef7eb2e8f9f7 | 1777 | uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 1778 | { |
<> | 144:ef7eb2e8f9f7 | 1779 | return hirda->ErrorCode; |
<> | 144:ef7eb2e8f9f7 | 1780 | } |
<> | 144:ef7eb2e8f9f7 | 1781 | |
<> | 144:ef7eb2e8f9f7 | 1782 | /** |
<> | 144:ef7eb2e8f9f7 | 1783 | * @} |
<> | 144:ef7eb2e8f9f7 | 1784 | */ |
<> | 144:ef7eb2e8f9f7 | 1785 | |
<> | 144:ef7eb2e8f9f7 | 1786 | /** |
<> | 144:ef7eb2e8f9f7 | 1787 | * @} |
<> | 144:ef7eb2e8f9f7 | 1788 | */ |
<> | 144:ef7eb2e8f9f7 | 1789 | |
<> | 156:95d6b41a828b | 1790 | /** @defgroup IRDA_Private_Functions IRDA Private Functions |
<> | 144:ef7eb2e8f9f7 | 1791 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1792 | */ |
<> | 144:ef7eb2e8f9f7 | 1793 | |
<> | 144:ef7eb2e8f9f7 | 1794 | /** |
<> | 156:95d6b41a828b | 1795 | * @brief Configure the IRDA peripheral. |
<> | 156:95d6b41a828b | 1796 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1797 | * the configuration information for the specified IRDA module. |
<> | 144:ef7eb2e8f9f7 | 1798 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1799 | */ |
<> | 144:ef7eb2e8f9f7 | 1800 | static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 1801 | { |
<> | 156:95d6b41a828b | 1802 | uint32_t tmpreg = 0x00000000U; |
<> | 144:ef7eb2e8f9f7 | 1803 | IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED; |
<> | 144:ef7eb2e8f9f7 | 1804 | HAL_StatusTypeDef ret = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1805 | |
<> | 144:ef7eb2e8f9f7 | 1806 | /* Check the communication parameters */ |
<> | 144:ef7eb2e8f9f7 | 1807 | assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); |
<> | 144:ef7eb2e8f9f7 | 1808 | assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength)); |
<> | 144:ef7eb2e8f9f7 | 1809 | assert_param(IS_IRDA_PARITY(hirda->Init.Parity)); |
<> | 144:ef7eb2e8f9f7 | 1810 | assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode)); |
<> | 144:ef7eb2e8f9f7 | 1811 | assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler)); |
<> | 144:ef7eb2e8f9f7 | 1812 | assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode)); |
<> | 144:ef7eb2e8f9f7 | 1813 | |
<> | 144:ef7eb2e8f9f7 | 1814 | /*-------------------------- USART CR1 Configuration -----------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1815 | /* Configure the IRDA Word Length, Parity and transfer Mode: |
<> | 144:ef7eb2e8f9f7 | 1816 | Set the M bits according to hirda->Init.WordLength value |
<> | 144:ef7eb2e8f9f7 | 1817 | Set PCE and PS bits according to hirda->Init.Parity value |
<> | 144:ef7eb2e8f9f7 | 1818 | Set TE and RE bits according to hirda->Init.Mode value */ |
<> | 144:ef7eb2e8f9f7 | 1819 | tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ; |
<> | 144:ef7eb2e8f9f7 | 1820 | |
<> | 144:ef7eb2e8f9f7 | 1821 | MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg); |
<> | 144:ef7eb2e8f9f7 | 1822 | |
<> | 144:ef7eb2e8f9f7 | 1823 | /*-------------------------- USART CR3 Configuration -----------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1824 | MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode); |
<> | 144:ef7eb2e8f9f7 | 1825 | |
<> | 144:ef7eb2e8f9f7 | 1826 | /*-------------------------- USART GTPR Configuration ----------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1827 | MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler); |
<> | 144:ef7eb2e8f9f7 | 1828 | |
<> | 144:ef7eb2e8f9f7 | 1829 | /*-------------------------- USART BRR Configuration -----------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1830 | IRDA_GETCLOCKSOURCE(hirda, clocksource); |
<> | 144:ef7eb2e8f9f7 | 1831 | switch (clocksource) |
<> | 144:ef7eb2e8f9f7 | 1832 | { |
<> | 144:ef7eb2e8f9f7 | 1833 | case IRDA_CLOCKSOURCE_PCLK1: |
<> | 144:ef7eb2e8f9f7 | 1834 | hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); |
<> | 144:ef7eb2e8f9f7 | 1835 | break; |
<> | 144:ef7eb2e8f9f7 | 1836 | case IRDA_CLOCKSOURCE_HSI: |
<> | 144:ef7eb2e8f9f7 | 1837 | hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); |
<> | 144:ef7eb2e8f9f7 | 1838 | break; |
<> | 144:ef7eb2e8f9f7 | 1839 | case IRDA_CLOCKSOURCE_SYSCLK: |
<> | 144:ef7eb2e8f9f7 | 1840 | hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); |
<> | 144:ef7eb2e8f9f7 | 1841 | break; |
<> | 144:ef7eb2e8f9f7 | 1842 | case IRDA_CLOCKSOURCE_LSE: |
<> | 144:ef7eb2e8f9f7 | 1843 | hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate); |
<> | 144:ef7eb2e8f9f7 | 1844 | break; |
<> | 144:ef7eb2e8f9f7 | 1845 | case IRDA_CLOCKSOURCE_UNDEFINED: |
<> | 144:ef7eb2e8f9f7 | 1846 | default: |
<> | 144:ef7eb2e8f9f7 | 1847 | ret = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1848 | break; |
<> | 144:ef7eb2e8f9f7 | 1849 | } |
<> | 144:ef7eb2e8f9f7 | 1850 | |
<> | 144:ef7eb2e8f9f7 | 1851 | return ret; |
<> | 144:ef7eb2e8f9f7 | 1852 | } |
<> | 144:ef7eb2e8f9f7 | 1853 | |
<> | 144:ef7eb2e8f9f7 | 1854 | /** |
<> | 156:95d6b41a828b | 1855 | * @brief Check the IRDA Idle State. |
<> | 156:95d6b41a828b | 1856 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1857 | * the configuration information for the specified IRDA module. |
<> | 144:ef7eb2e8f9f7 | 1858 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1859 | */ |
<> | 144:ef7eb2e8f9f7 | 1860 | static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 1861 | { |
<> | 156:95d6b41a828b | 1862 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 1863 | |
<> | 144:ef7eb2e8f9f7 | 1864 | /* Initialize the IRDA ErrorCode */ |
<> | 144:ef7eb2e8f9f7 | 1865 | hirda->ErrorCode = HAL_IRDA_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1866 | |
<> | 156:95d6b41a828b | 1867 | /* Init tickstart for timeout managment*/ |
<> | 156:95d6b41a828b | 1868 | tickstart = HAL_GetTick(); |
<> | 156:95d6b41a828b | 1869 | |
<> | 144:ef7eb2e8f9f7 | 1870 | /* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices). |
<> | 144:ef7eb2e8f9f7 | 1871 | Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature. |
<> | 144:ef7eb2e8f9f7 | 1872 | */ |
<> | 144:ef7eb2e8f9f7 | 1873 | #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) |
<> | 144:ef7eb2e8f9f7 | 1874 | if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(hirda->Instance)) |
<> | 144:ef7eb2e8f9f7 | 1875 | { |
<> | 144:ef7eb2e8f9f7 | 1876 | /* Check if the Transmitter is enabled */ |
<> | 144:ef7eb2e8f9f7 | 1877 | if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) |
<> | 144:ef7eb2e8f9f7 | 1878 | { |
<> | 144:ef7eb2e8f9f7 | 1879 | /* Wait until TEACK flag is set */ |
<> | 156:95d6b41a828b | 1880 | if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1881 | { |
<> | 144:ef7eb2e8f9f7 | 1882 | /* Timeout occurred */ |
<> | 144:ef7eb2e8f9f7 | 1883 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1884 | } |
<> | 144:ef7eb2e8f9f7 | 1885 | } |
<> | 144:ef7eb2e8f9f7 | 1886 | |
<> | 144:ef7eb2e8f9f7 | 1887 | /* Check if the Receiver is enabled */ |
<> | 144:ef7eb2e8f9f7 | 1888 | if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) |
<> | 144:ef7eb2e8f9f7 | 1889 | { |
<> | 144:ef7eb2e8f9f7 | 1890 | /* Wait until REACK flag is set */ |
<> | 156:95d6b41a828b | 1891 | if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1892 | { |
<> | 144:ef7eb2e8f9f7 | 1893 | /* Timeout occurred */ |
<> | 144:ef7eb2e8f9f7 | 1894 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1895 | } |
<> | 144:ef7eb2e8f9f7 | 1896 | } |
<> | 144:ef7eb2e8f9f7 | 1897 | } |
<> | 144:ef7eb2e8f9f7 | 1898 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 1899 | |
<> | 144:ef7eb2e8f9f7 | 1900 | /* Initialize the IRDA state*/ |
<> | 156:95d6b41a828b | 1901 | hirda->gState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 1902 | hirda->RxState = HAL_IRDA_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1903 | |
<> | 144:ef7eb2e8f9f7 | 1904 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1905 | __HAL_UNLOCK(hirda); |
<> | 144:ef7eb2e8f9f7 | 1906 | |
<> | 144:ef7eb2e8f9f7 | 1907 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1908 | } |
<> | 144:ef7eb2e8f9f7 | 1909 | |
<> | 144:ef7eb2e8f9f7 | 1910 | /** |
<> | 144:ef7eb2e8f9f7 | 1911 | * @brief Handle IRDA Communication Timeout. |
<> | 156:95d6b41a828b | 1912 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 1913 | * the configuration information for the specified IRDA module. |
<> | 156:95d6b41a828b | 1914 | * @param Flag Specifies the IRDA flag to check. |
<> | 156:95d6b41a828b | 1915 | * @param Status the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status. |
<> | 156:95d6b41a828b | 1916 | * @param Tickstart Tick start value |
<> | 156:95d6b41a828b | 1917 | * @param Timeout Timeout duration |
<> | 144:ef7eb2e8f9f7 | 1918 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1919 | */ |
<> | 156:95d6b41a828b | 1920 | static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 1921 | { |
<> | 144:ef7eb2e8f9f7 | 1922 | /* Wait until flag is set */ |
<> | 156:95d6b41a828b | 1923 | while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status) |
<> | 144:ef7eb2e8f9f7 | 1924 | { |
<> | 156:95d6b41a828b | 1925 | /* Check for the Timeout */ |
<> | 156:95d6b41a828b | 1926 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 1927 | { |
<> | 156:95d6b41a828b | 1928 | if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 1929 | { |
<> | 156:95d6b41a828b | 1930 | /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ |
<> | 156:95d6b41a828b | 1931 | CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); |
<> | 156:95d6b41a828b | 1932 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); |
<> | 144:ef7eb2e8f9f7 | 1933 | |
<> | 156:95d6b41a828b | 1934 | hirda->gState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 1935 | hirda->RxState = HAL_IRDA_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1936 | |
<> | 156:95d6b41a828b | 1937 | /* Process Unlocked */ |
<> | 156:95d6b41a828b | 1938 | __HAL_UNLOCK(hirda); |
<> | 144:ef7eb2e8f9f7 | 1939 | |
<> | 156:95d6b41a828b | 1940 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1941 | } |
<> | 144:ef7eb2e8f9f7 | 1942 | } |
<> | 144:ef7eb2e8f9f7 | 1943 | } |
<> | 144:ef7eb2e8f9f7 | 1944 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1945 | } |
<> | 144:ef7eb2e8f9f7 | 1946 | |
<> | 156:95d6b41a828b | 1947 | |
<> | 156:95d6b41a828b | 1948 | /** |
<> | 156:95d6b41a828b | 1949 | * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion). |
<> | 156:95d6b41a828b | 1950 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 1951 | * the configuration information for the specified IRDA module. |
<> | 156:95d6b41a828b | 1952 | * @retval None |
<> | 156:95d6b41a828b | 1953 | */ |
<> | 156:95d6b41a828b | 1954 | static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda) |
<> | 156:95d6b41a828b | 1955 | { |
<> | 156:95d6b41a828b | 1956 | /* Disable TXEIE and TCIE interrupts */ |
<> | 156:95d6b41a828b | 1957 | CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); |
<> | 156:95d6b41a828b | 1958 | |
<> | 156:95d6b41a828b | 1959 | /* At end of Tx process, restore hirda->gState to Ready */ |
<> | 156:95d6b41a828b | 1960 | hirda->gState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 1961 | } |
<> | 156:95d6b41a828b | 1962 | |
<> | 156:95d6b41a828b | 1963 | |
<> | 156:95d6b41a828b | 1964 | /** |
<> | 156:95d6b41a828b | 1965 | * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). |
<> | 156:95d6b41a828b | 1966 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 1967 | * the configuration information for the specified IRDA module. |
<> | 156:95d6b41a828b | 1968 | * @retval None |
<> | 156:95d6b41a828b | 1969 | */ |
<> | 156:95d6b41a828b | 1970 | static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda) |
<> | 156:95d6b41a828b | 1971 | { |
<> | 156:95d6b41a828b | 1972 | /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ |
<> | 156:95d6b41a828b | 1973 | CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); |
<> | 156:95d6b41a828b | 1974 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); |
<> | 156:95d6b41a828b | 1975 | |
<> | 156:95d6b41a828b | 1976 | /* At end of Rx process, restore hirda->RxState to Ready */ |
<> | 156:95d6b41a828b | 1977 | hirda->RxState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 1978 | } |
<> | 156:95d6b41a828b | 1979 | |
<> | 156:95d6b41a828b | 1980 | |
<> | 144:ef7eb2e8f9f7 | 1981 | /** |
<> | 144:ef7eb2e8f9f7 | 1982 | * @brief DMA IRDA transmit process complete callback. |
<> | 156:95d6b41a828b | 1983 | * @param hdma Pointer to a DMA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 1984 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 1985 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1986 | */ |
<> | 144:ef7eb2e8f9f7 | 1987 | static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 1988 | { |
<> | 156:95d6b41a828b | 1989 | IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); |
<> | 144:ef7eb2e8f9f7 | 1990 | |
<> | 144:ef7eb2e8f9f7 | 1991 | /* DMA Normal mode */ |
<> | 144:ef7eb2e8f9f7 | 1992 | if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) |
<> | 144:ef7eb2e8f9f7 | 1993 | { |
<> | 156:95d6b41a828b | 1994 | hirda->TxXferCount = 0U; |
<> | 144:ef7eb2e8f9f7 | 1995 | |
<> | 144:ef7eb2e8f9f7 | 1996 | /* Disable the DMA transfer for transmit request by resetting the DMAT bit |
<> | 144:ef7eb2e8f9f7 | 1997 | in the IRDA CR3 register */ |
<> | 156:95d6b41a828b | 1998 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); |
<> | 144:ef7eb2e8f9f7 | 1999 | |
<> | 144:ef7eb2e8f9f7 | 2000 | /* Enable the IRDA Transmit Complete Interrupt */ |
<> | 156:95d6b41a828b | 2001 | SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); |
<> | 144:ef7eb2e8f9f7 | 2002 | } |
<> | 144:ef7eb2e8f9f7 | 2003 | /* DMA Circular mode */ |
<> | 144:ef7eb2e8f9f7 | 2004 | else |
<> | 144:ef7eb2e8f9f7 | 2005 | { |
<> | 144:ef7eb2e8f9f7 | 2006 | HAL_IRDA_TxCpltCallback(hirda); |
<> | 144:ef7eb2e8f9f7 | 2007 | } |
<> | 156:95d6b41a828b | 2008 | |
<> | 144:ef7eb2e8f9f7 | 2009 | } |
<> | 144:ef7eb2e8f9f7 | 2010 | |
<> | 144:ef7eb2e8f9f7 | 2011 | /** |
<> | 156:95d6b41a828b | 2012 | * @brief DMA IRDA transmit process half complete callback. |
<> | 156:95d6b41a828b | 2013 | * @param hdma Pointer to a DMA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 2014 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 2015 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2016 | */ |
<> | 144:ef7eb2e8f9f7 | 2017 | static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2018 | { |
<> | 156:95d6b41a828b | 2019 | IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); |
<> | 144:ef7eb2e8f9f7 | 2020 | |
<> | 144:ef7eb2e8f9f7 | 2021 | HAL_IRDA_TxHalfCpltCallback(hirda); |
<> | 144:ef7eb2e8f9f7 | 2022 | } |
<> | 144:ef7eb2e8f9f7 | 2023 | |
<> | 144:ef7eb2e8f9f7 | 2024 | /** |
<> | 144:ef7eb2e8f9f7 | 2025 | * @brief DMA IRDA receive process complete callback. |
Anna Bridge |
180:96ed750bd169 | 2026 | * @param hdma Pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2027 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 2028 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2029 | */ |
<> | 144:ef7eb2e8f9f7 | 2030 | static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2031 | { |
<> | 156:95d6b41a828b | 2032 | IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); |
<> | 144:ef7eb2e8f9f7 | 2033 | |
<> | 144:ef7eb2e8f9f7 | 2034 | /* DMA Normal mode */ |
<> | 144:ef7eb2e8f9f7 | 2035 | if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) |
<> | 144:ef7eb2e8f9f7 | 2036 | { |
<> | 156:95d6b41a828b | 2037 | hirda->RxXferCount = 0U; |
<> | 156:95d6b41a828b | 2038 | |
<> | 156:95d6b41a828b | 2039 | /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ |
<> | 156:95d6b41a828b | 2040 | CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); |
<> | 156:95d6b41a828b | 2041 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); |
<> | 144:ef7eb2e8f9f7 | 2042 | |
<> | 144:ef7eb2e8f9f7 | 2043 | /* Disable the DMA transfer for the receiver request by resetting the DMAR bit |
<> | 144:ef7eb2e8f9f7 | 2044 | in the IRDA CR3 register */ |
<> | 156:95d6b41a828b | 2045 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); |
<> | 144:ef7eb2e8f9f7 | 2046 | |
<> | 144:ef7eb2e8f9f7 | 2047 | /* At end of Rx process, restore hirda->RxState to Ready */ |
<> | 144:ef7eb2e8f9f7 | 2048 | hirda->RxState = HAL_IRDA_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2049 | } |
<> | 144:ef7eb2e8f9f7 | 2050 | |
<> | 144:ef7eb2e8f9f7 | 2051 | HAL_IRDA_RxCpltCallback(hirda); |
<> | 144:ef7eb2e8f9f7 | 2052 | } |
<> | 144:ef7eb2e8f9f7 | 2053 | |
<> | 144:ef7eb2e8f9f7 | 2054 | /** |
<> | 144:ef7eb2e8f9f7 | 2055 | * @brief DMA IRDA receive process half complete callback. |
Anna Bridge |
180:96ed750bd169 | 2056 | * @param hdma Pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2057 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 2058 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2059 | */ |
<> | 144:ef7eb2e8f9f7 | 2060 | static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2061 | { |
<> | 156:95d6b41a828b | 2062 | IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); |
<> | 144:ef7eb2e8f9f7 | 2063 | |
<> | 144:ef7eb2e8f9f7 | 2064 | HAL_IRDA_RxHalfCpltCallback(hirda); |
<> | 144:ef7eb2e8f9f7 | 2065 | } |
<> | 144:ef7eb2e8f9f7 | 2066 | |
<> | 144:ef7eb2e8f9f7 | 2067 | /** |
<> | 156:95d6b41a828b | 2068 | * @brief DMA IRDA communication error callback. |
<> | 156:95d6b41a828b | 2069 | * @param hdma Pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2070 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 2071 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2072 | */ |
<> | 144:ef7eb2e8f9f7 | 2073 | static void IRDA_DMAError(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2074 | { |
<> | 156:95d6b41a828b | 2075 | IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); |
<> | 156:95d6b41a828b | 2076 | |
<> | 156:95d6b41a828b | 2077 | /* Stop IRDA DMA Tx request if ongoing */ |
<> | 156:95d6b41a828b | 2078 | if ( (hirda->gState == HAL_IRDA_STATE_BUSY_TX) |
<> | 156:95d6b41a828b | 2079 | &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) ) |
<> | 156:95d6b41a828b | 2080 | { |
<> | 156:95d6b41a828b | 2081 | hirda->TxXferCount = 0U; |
<> | 156:95d6b41a828b | 2082 | IRDA_EndTxTransfer(hirda); |
<> | 156:95d6b41a828b | 2083 | } |
<> | 144:ef7eb2e8f9f7 | 2084 | |
<> | 156:95d6b41a828b | 2085 | /* Stop IRDA DMA Rx request if ongoing */ |
<> | 156:95d6b41a828b | 2086 | if ( (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) |
<> | 156:95d6b41a828b | 2087 | &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) ) |
<> | 156:95d6b41a828b | 2088 | { |
<> | 156:95d6b41a828b | 2089 | hirda->RxXferCount = 0; |
<> | 156:95d6b41a828b | 2090 | IRDA_EndRxTransfer(hirda); |
<> | 156:95d6b41a828b | 2091 | } |
<> | 156:95d6b41a828b | 2092 | |
<> | 144:ef7eb2e8f9f7 | 2093 | hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; |
<> | 156:95d6b41a828b | 2094 | HAL_IRDA_ErrorCallback(hirda); |
<> | 156:95d6b41a828b | 2095 | } |
<> | 156:95d6b41a828b | 2096 | |
<> | 156:95d6b41a828b | 2097 | /** |
<> | 156:95d6b41a828b | 2098 | * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error |
<> | 156:95d6b41a828b | 2099 | * (To be called at end of DMA Abort procedure following error occurrence). |
<> | 156:95d6b41a828b | 2100 | * @param hdma DMA handle. |
<> | 156:95d6b41a828b | 2101 | * @retval None |
<> | 156:95d6b41a828b | 2102 | */ |
<> | 156:95d6b41a828b | 2103 | static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma) |
<> | 156:95d6b41a828b | 2104 | { |
<> | 156:95d6b41a828b | 2105 | IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); |
<> | 156:95d6b41a828b | 2106 | hirda->RxXferCount = 0U; |
<> | 156:95d6b41a828b | 2107 | hirda->TxXferCount = 0U; |
<> | 144:ef7eb2e8f9f7 | 2108 | |
<> | 144:ef7eb2e8f9f7 | 2109 | HAL_IRDA_ErrorCallback(hirda); |
<> | 144:ef7eb2e8f9f7 | 2110 | } |
<> | 144:ef7eb2e8f9f7 | 2111 | |
<> | 156:95d6b41a828b | 2112 | /** |
<> | 156:95d6b41a828b | 2113 | * @brief DMA IRDA Tx communication abort callback, when initiated by user |
<> | 156:95d6b41a828b | 2114 | * (To be called at end of DMA Tx Abort procedure following user abort request). |
<> | 156:95d6b41a828b | 2115 | * @note When this callback is executed, User Abort complete call back is called only if no |
<> | 156:95d6b41a828b | 2116 | * Abort still ongoing for Rx DMA Handle. |
<> | 156:95d6b41a828b | 2117 | * @param hdma DMA handle. |
<> | 156:95d6b41a828b | 2118 | * @retval None |
<> | 156:95d6b41a828b | 2119 | */ |
<> | 156:95d6b41a828b | 2120 | static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma) |
<> | 156:95d6b41a828b | 2121 | { |
<> | 156:95d6b41a828b | 2122 | IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent); |
<> | 156:95d6b41a828b | 2123 | |
<> | 156:95d6b41a828b | 2124 | hirda->hdmatx->XferAbortCallback = NULL; |
<> | 156:95d6b41a828b | 2125 | |
<> | 156:95d6b41a828b | 2126 | /* Check if an Abort process is still ongoing */ |
<> | 156:95d6b41a828b | 2127 | if(hirda->hdmarx != NULL) |
<> | 156:95d6b41a828b | 2128 | { |
<> | 156:95d6b41a828b | 2129 | if(hirda->hdmarx->XferAbortCallback != NULL) |
<> | 156:95d6b41a828b | 2130 | { |
<> | 156:95d6b41a828b | 2131 | return; |
<> | 156:95d6b41a828b | 2132 | } |
<> | 156:95d6b41a828b | 2133 | } |
<> | 156:95d6b41a828b | 2134 | |
<> | 156:95d6b41a828b | 2135 | /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ |
<> | 156:95d6b41a828b | 2136 | hirda->TxXferCount = 0U; |
<> | 156:95d6b41a828b | 2137 | hirda->RxXferCount = 0U; |
<> | 156:95d6b41a828b | 2138 | |
<> | 156:95d6b41a828b | 2139 | /* Reset errorCode */ |
<> | 156:95d6b41a828b | 2140 | hirda->ErrorCode = HAL_IRDA_ERROR_NONE; |
<> | 156:95d6b41a828b | 2141 | |
<> | 156:95d6b41a828b | 2142 | /* Clear the Error flags in the ICR register */ |
<> | 156:95d6b41a828b | 2143 | __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); |
<> | 156:95d6b41a828b | 2144 | |
<> | 156:95d6b41a828b | 2145 | /* Restore hirda->gState and hirda->RxState to Ready */ |
<> | 156:95d6b41a828b | 2146 | hirda->gState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 2147 | hirda->RxState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 2148 | |
<> | 156:95d6b41a828b | 2149 | /* Call user Abort complete callback */ |
<> | 156:95d6b41a828b | 2150 | HAL_IRDA_AbortCpltCallback(hirda); |
<> | 156:95d6b41a828b | 2151 | } |
<> | 156:95d6b41a828b | 2152 | |
<> | 144:ef7eb2e8f9f7 | 2153 | |
<> | 144:ef7eb2e8f9f7 | 2154 | /** |
<> | 156:95d6b41a828b | 2155 | * @brief DMA IRDA Rx communication abort callback, when initiated by user |
<> | 156:95d6b41a828b | 2156 | * (To be called at end of DMA Rx Abort procedure following user abort request). |
<> | 156:95d6b41a828b | 2157 | * @note When this callback is executed, User Abort complete call back is called only if no |
<> | 156:95d6b41a828b | 2158 | * Abort still ongoing for Tx DMA Handle. |
<> | 156:95d6b41a828b | 2159 | * @param hdma DMA handle. |
<> | 156:95d6b41a828b | 2160 | * @retval None |
<> | 156:95d6b41a828b | 2161 | */ |
<> | 156:95d6b41a828b | 2162 | static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma) |
<> | 156:95d6b41a828b | 2163 | { |
<> | 156:95d6b41a828b | 2164 | IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent); |
<> | 156:95d6b41a828b | 2165 | |
<> | 156:95d6b41a828b | 2166 | hirda->hdmarx->XferAbortCallback = NULL; |
<> | 156:95d6b41a828b | 2167 | |
<> | 156:95d6b41a828b | 2168 | /* Check if an Abort process is still ongoing */ |
<> | 156:95d6b41a828b | 2169 | if(hirda->hdmatx != NULL) |
<> | 156:95d6b41a828b | 2170 | { |
<> | 156:95d6b41a828b | 2171 | if(hirda->hdmatx->XferAbortCallback != NULL) |
<> | 156:95d6b41a828b | 2172 | { |
<> | 156:95d6b41a828b | 2173 | return; |
<> | 156:95d6b41a828b | 2174 | } |
<> | 156:95d6b41a828b | 2175 | } |
<> | 156:95d6b41a828b | 2176 | |
<> | 156:95d6b41a828b | 2177 | /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ |
<> | 156:95d6b41a828b | 2178 | hirda->TxXferCount = 0U; |
<> | 156:95d6b41a828b | 2179 | hirda->RxXferCount = 0U; |
<> | 156:95d6b41a828b | 2180 | |
<> | 156:95d6b41a828b | 2181 | /* Reset errorCode */ |
<> | 156:95d6b41a828b | 2182 | hirda->ErrorCode = HAL_IRDA_ERROR_NONE; |
<> | 156:95d6b41a828b | 2183 | |
<> | 156:95d6b41a828b | 2184 | /* Clear the Error flags in the ICR register */ |
<> | 156:95d6b41a828b | 2185 | __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); |
<> | 156:95d6b41a828b | 2186 | |
<> | 156:95d6b41a828b | 2187 | /* Restore hirda->gState and hirda->RxState to Ready */ |
<> | 156:95d6b41a828b | 2188 | hirda->gState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 2189 | hirda->RxState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 2190 | |
<> | 156:95d6b41a828b | 2191 | /* Call user Abort complete callback */ |
<> | 156:95d6b41a828b | 2192 | HAL_IRDA_AbortCpltCallback(hirda); |
<> | 156:95d6b41a828b | 2193 | } |
<> | 156:95d6b41a828b | 2194 | |
<> | 156:95d6b41a828b | 2195 | |
<> | 156:95d6b41a828b | 2196 | /** |
<> | 156:95d6b41a828b | 2197 | * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to |
<> | 156:95d6b41a828b | 2198 | * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) |
<> | 156:95d6b41a828b | 2199 | * (This callback is executed at end of DMA Tx Abort procedure following user abort request, |
<> | 156:95d6b41a828b | 2200 | * and leads to user Tx Abort Complete callback execution). |
<> | 156:95d6b41a828b | 2201 | * @param hdma DMA handle. |
<> | 156:95d6b41a828b | 2202 | * @retval None |
<> | 156:95d6b41a828b | 2203 | */ |
<> | 156:95d6b41a828b | 2204 | static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) |
<> | 156:95d6b41a828b | 2205 | { |
<> | 156:95d6b41a828b | 2206 | IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent); |
<> | 156:95d6b41a828b | 2207 | |
<> | 156:95d6b41a828b | 2208 | hirda->TxXferCount = 0U; |
<> | 156:95d6b41a828b | 2209 | |
<> | 156:95d6b41a828b | 2210 | /* Restore hirda->gState to Ready */ |
<> | 156:95d6b41a828b | 2211 | hirda->gState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 2212 | |
<> | 156:95d6b41a828b | 2213 | /* Call user Abort complete callback */ |
<> | 156:95d6b41a828b | 2214 | HAL_IRDA_AbortTransmitCpltCallback(hirda); |
<> | 156:95d6b41a828b | 2215 | } |
<> | 156:95d6b41a828b | 2216 | |
<> | 156:95d6b41a828b | 2217 | /** |
<> | 156:95d6b41a828b | 2218 | * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to |
<> | 156:95d6b41a828b | 2219 | * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) |
<> | 156:95d6b41a828b | 2220 | * (This callback is executed at end of DMA Rx Abort procedure following user abort request, |
<> | 156:95d6b41a828b | 2221 | * and leads to user Rx Abort Complete callback execution). |
<> | 156:95d6b41a828b | 2222 | * @param hdma DMA handle. |
<> | 156:95d6b41a828b | 2223 | * @retval None |
<> | 156:95d6b41a828b | 2224 | */ |
<> | 156:95d6b41a828b | 2225 | static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) |
<> | 156:95d6b41a828b | 2226 | { |
<> | 156:95d6b41a828b | 2227 | IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 156:95d6b41a828b | 2228 | |
<> | 156:95d6b41a828b | 2229 | hirda->RxXferCount = 0U; |
<> | 156:95d6b41a828b | 2230 | |
<> | 156:95d6b41a828b | 2231 | /* Clear the Error flags in the ICR register */ |
<> | 156:95d6b41a828b | 2232 | __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); |
<> | 156:95d6b41a828b | 2233 | |
<> | 156:95d6b41a828b | 2234 | /* Restore hirda->RxState to Ready */ |
<> | 156:95d6b41a828b | 2235 | hirda->RxState = HAL_IRDA_STATE_READY; |
<> | 156:95d6b41a828b | 2236 | |
<> | 156:95d6b41a828b | 2237 | /* Call user Abort complete callback */ |
<> | 156:95d6b41a828b | 2238 | HAL_IRDA_AbortReceiveCpltCallback(hirda); |
<> | 156:95d6b41a828b | 2239 | } |
<> | 156:95d6b41a828b | 2240 | |
<> | 156:95d6b41a828b | 2241 | /** |
<> | 156:95d6b41a828b | 2242 | * @brief Send an amount of data in interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 2243 | * @note Function is called under interruption only, once |
<> | 144:ef7eb2e8f9f7 | 2244 | * interruptions have been enabled by HAL_IRDA_Transmit_IT(). |
<> | 156:95d6b41a828b | 2245 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 2246 | * the configuration information for the specified IRDA module. |
<> | 144:ef7eb2e8f9f7 | 2247 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2248 | */ |
<> | 144:ef7eb2e8f9f7 | 2249 | static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 2250 | { |
<> | 144:ef7eb2e8f9f7 | 2251 | uint16_t* tmp; |
<> | 144:ef7eb2e8f9f7 | 2252 | |
<> | 144:ef7eb2e8f9f7 | 2253 | /* Check that a Tx process is ongoing */ |
<> | 144:ef7eb2e8f9f7 | 2254 | if(hirda->gState == HAL_IRDA_STATE_BUSY_TX) |
<> | 144:ef7eb2e8f9f7 | 2255 | { |
<> | 156:95d6b41a828b | 2256 | if(hirda->TxXferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 2257 | { |
<> | 144:ef7eb2e8f9f7 | 2258 | /* Disable the IRDA Transmit Data Register Empty Interrupt */ |
<> | 156:95d6b41a828b | 2259 | CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE); |
<> | 144:ef7eb2e8f9f7 | 2260 | |
<> | 144:ef7eb2e8f9f7 | 2261 | /* Enable the IRDA Transmit Complete Interrupt */ |
<> | 156:95d6b41a828b | 2262 | SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); |
<> | 144:ef7eb2e8f9f7 | 2263 | |
<> | 144:ef7eb2e8f9f7 | 2264 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2265 | } |
<> | 144:ef7eb2e8f9f7 | 2266 | else |
<> | 144:ef7eb2e8f9f7 | 2267 | { |
<> | 144:ef7eb2e8f9f7 | 2268 | if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) |
<> | 144:ef7eb2e8f9f7 | 2269 | { |
<> | 144:ef7eb2e8f9f7 | 2270 | tmp = (uint16_t*) hirda->pTxBuffPtr; |
<> | 156:95d6b41a828b | 2271 | hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU); |
<> | 156:95d6b41a828b | 2272 | hirda->pTxBuffPtr += 2U; |
<> | 144:ef7eb2e8f9f7 | 2273 | } |
<> | 144:ef7eb2e8f9f7 | 2274 | else |
<> | 144:ef7eb2e8f9f7 | 2275 | { |
<> | 156:95d6b41a828b | 2276 | hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFFU); |
<> | 144:ef7eb2e8f9f7 | 2277 | } |
<> | 144:ef7eb2e8f9f7 | 2278 | hirda->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 2279 | |
<> | 144:ef7eb2e8f9f7 | 2280 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2281 | } |
<> | 144:ef7eb2e8f9f7 | 2282 | } |
<> | 144:ef7eb2e8f9f7 | 2283 | else |
<> | 144:ef7eb2e8f9f7 | 2284 | { |
<> | 144:ef7eb2e8f9f7 | 2285 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 2286 | } |
<> | 144:ef7eb2e8f9f7 | 2287 | } |
<> | 144:ef7eb2e8f9f7 | 2288 | |
<> | 144:ef7eb2e8f9f7 | 2289 | /** |
<> | 144:ef7eb2e8f9f7 | 2290 | * @brief Wrap up transmission in non-blocking mode. |
<> | 156:95d6b41a828b | 2291 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2292 | * the configuration information for the specified IRDA module. |
<> | 144:ef7eb2e8f9f7 | 2293 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2294 | */ |
<> | 144:ef7eb2e8f9f7 | 2295 | static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 2296 | { |
<> | 144:ef7eb2e8f9f7 | 2297 | /* Disable the IRDA Transmit Complete Interrupt */ |
<> | 156:95d6b41a828b | 2298 | CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE); |
<> | 144:ef7eb2e8f9f7 | 2299 | |
<> | 144:ef7eb2e8f9f7 | 2300 | /* Tx process is ended, restore hirda->gState to Ready */ |
<> | 144:ef7eb2e8f9f7 | 2301 | hirda->gState = HAL_IRDA_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2302 | |
<> | 144:ef7eb2e8f9f7 | 2303 | HAL_IRDA_TxCpltCallback(hirda); |
<> | 144:ef7eb2e8f9f7 | 2304 | |
<> | 144:ef7eb2e8f9f7 | 2305 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2306 | } |
<> | 144:ef7eb2e8f9f7 | 2307 | |
<> | 144:ef7eb2e8f9f7 | 2308 | /** |
<> | 156:95d6b41a828b | 2309 | * @brief Receive an amount of data in interrupt mode. |
<> | 156:95d6b41a828b | 2310 | * @note Function is called under interruption only, once |
<> | 156:95d6b41a828b | 2311 | * interruptions have been enabled by HAL_IRDA_Receive_IT() |
<> | 144:ef7eb2e8f9f7 | 2312 | * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains |
<> | 156:95d6b41a828b | 2313 | * the configuration information for the specified IRDA module. |
<> | 144:ef7eb2e8f9f7 | 2314 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2315 | */ |
<> | 144:ef7eb2e8f9f7 | 2316 | static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) |
<> | 144:ef7eb2e8f9f7 | 2317 | { |
<> | 144:ef7eb2e8f9f7 | 2318 | uint16_t* tmp; |
<> | 156:95d6b41a828b | 2319 | uint16_t uhMask = hirda->Mask; |
<> | 156:95d6b41a828b | 2320 | uint16_t uhdata; |
<> | 144:ef7eb2e8f9f7 | 2321 | |
<> | 144:ef7eb2e8f9f7 | 2322 | /* Check that a Rx process is ongoing */ |
<> | 144:ef7eb2e8f9f7 | 2323 | if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) |
<> | 144:ef7eb2e8f9f7 | 2324 | { |
<> | 156:95d6b41a828b | 2325 | uhdata = (uint16_t) READ_REG(hirda->Instance->RDR); |
<> | 144:ef7eb2e8f9f7 | 2326 | if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) |
<> | 144:ef7eb2e8f9f7 | 2327 | { |
<> | 144:ef7eb2e8f9f7 | 2328 | tmp = (uint16_t*) hirda->pRxBuffPtr ; |
<> | 156:95d6b41a828b | 2329 | *tmp = (uint16_t)(uhdata & uhMask); |
<> | 156:95d6b41a828b | 2330 | hirda->pRxBuffPtr +=2U; |
<> | 144:ef7eb2e8f9f7 | 2331 | } |
<> | 144:ef7eb2e8f9f7 | 2332 | else |
<> | 144:ef7eb2e8f9f7 | 2333 | { |
<> | 156:95d6b41a828b | 2334 | *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); |
<> | 144:ef7eb2e8f9f7 | 2335 | } |
<> | 144:ef7eb2e8f9f7 | 2336 | |
<> | 156:95d6b41a828b | 2337 | if(--hirda->RxXferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 2338 | { |
<> | 156:95d6b41a828b | 2339 | /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */ |
<> | 156:95d6b41a828b | 2340 | CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); |
<> | 144:ef7eb2e8f9f7 | 2341 | |
<> | 144:ef7eb2e8f9f7 | 2342 | /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ |
<> | 156:95d6b41a828b | 2343 | CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); |
<> | 144:ef7eb2e8f9f7 | 2344 | |
<> | 144:ef7eb2e8f9f7 | 2345 | /* Rx process is completed, restore hirda->RxState to Ready */ |
<> | 144:ef7eb2e8f9f7 | 2346 | hirda->RxState = HAL_IRDA_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2347 | |
<> | 144:ef7eb2e8f9f7 | 2348 | HAL_IRDA_RxCpltCallback(hirda); |
<> | 144:ef7eb2e8f9f7 | 2349 | |
<> | 144:ef7eb2e8f9f7 | 2350 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2351 | } |
<> | 144:ef7eb2e8f9f7 | 2352 | |
<> | 144:ef7eb2e8f9f7 | 2353 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2354 | } |
<> | 144:ef7eb2e8f9f7 | 2355 | else |
<> | 144:ef7eb2e8f9f7 | 2356 | { |
<> | 144:ef7eb2e8f9f7 | 2357 | /* Clear RXNE interrupt flag */ |
<> | 144:ef7eb2e8f9f7 | 2358 | __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST); |
<> | 144:ef7eb2e8f9f7 | 2359 | |
<> | 144:ef7eb2e8f9f7 | 2360 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 2361 | } |
<> | 144:ef7eb2e8f9f7 | 2362 | } |
<> | 144:ef7eb2e8f9f7 | 2363 | |
<> | 144:ef7eb2e8f9f7 | 2364 | /** |
<> | 144:ef7eb2e8f9f7 | 2365 | * @} |
<> | 144:ef7eb2e8f9f7 | 2366 | */ |
<> | 144:ef7eb2e8f9f7 | 2367 | |
<> | 156:95d6b41a828b | 2368 | #endif /* HAL_IRDA_MODULE_ENABLED */ |
<> | 144:ef7eb2e8f9f7 | 2369 | /** |
<> | 144:ef7eb2e8f9f7 | 2370 | * @} |
<> | 144:ef7eb2e8f9f7 | 2371 | */ |
<> | 144:ef7eb2e8f9f7 | 2372 | |
<> | 144:ef7eb2e8f9f7 | 2373 | /** |
<> | 144:ef7eb2e8f9f7 | 2374 | * @} |
<> | 144:ef7eb2e8f9f7 | 2375 | */ |
<> | 144:ef7eb2e8f9f7 | 2376 | |
<> | 144:ef7eb2e8f9f7 | 2377 | #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ |
<> | 144:ef7eb2e8f9f7 | 2378 | |
<> | 144:ef7eb2e8f9f7 | 2379 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |