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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_i2s.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of I2S HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F0xx_HAL_I2S_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F0xx_HAL_I2S_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #if defined(STM32F031x6) || defined(STM32F038xx) || \
<> 144:ef7eb2e8f9f7 45 defined(STM32F051x8) || defined(STM32F058xx) || \
<> 144:ef7eb2e8f9f7 46 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 47 defined(STM32F042x6) || defined(STM32F048xx) || \
<> 144:ef7eb2e8f9f7 48 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 51 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /** @addtogroup I2S
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 62 /** @defgroup I2S_Exported_Types I2S Exported Types
<> 144:ef7eb2e8f9f7 63 * @{
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /**
<> 144:ef7eb2e8f9f7 67 * @brief I2S Init structure definition
<> 144:ef7eb2e8f9f7 68 */
<> 144:ef7eb2e8f9f7 69 typedef struct
<> 144:ef7eb2e8f9f7 70 {
<> 144:ef7eb2e8f9f7 71 uint32_t Mode; /*!< Specifies the I2S operating mode.
<> 144:ef7eb2e8f9f7 72 This parameter can be a value of @ref I2S_Mode */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
<> 144:ef7eb2e8f9f7 75 This parameter can be a value of @ref I2S_Standard */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
<> 144:ef7eb2e8f9f7 78 This parameter can be a value of @ref I2S_Data_Format */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
<> 144:ef7eb2e8f9f7 81 This parameter can be a value of @ref I2S_MCLK_Output */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
<> 144:ef7eb2e8f9f7 84 This parameter can be a value of @ref I2S_Audio_Frequency */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
<> 144:ef7eb2e8f9f7 87 This parameter can be a value of @ref I2S_Clock_Polarity */
<> 144:ef7eb2e8f9f7 88 }I2S_InitTypeDef;
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /**
<> 144:ef7eb2e8f9f7 91 * @brief HAL State structures definition
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93 typedef enum
<> 144:ef7eb2e8f9f7 94 {
<> 156:95d6b41a828b 95 HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
<> 156:95d6b41a828b 96 HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
<> 156:95d6b41a828b 97 HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
<> 156:95d6b41a828b 98 HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
<> 156:95d6b41a828b 99 HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
<> 156:95d6b41a828b 100 HAL_I2S_STATE_PAUSE = 0x06U, /*!< I2S pause state: used in case of DMA */
<> 156:95d6b41a828b 101 HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
<> 144:ef7eb2e8f9f7 102 }HAL_I2S_StateTypeDef;
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /**
<> 144:ef7eb2e8f9f7 105 * @brief I2S handle Structure definition
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107 typedef struct
<> 144:ef7eb2e8f9f7 108 {
<> 144:ef7eb2e8f9f7 109 SPI_TypeDef *Instance; /*!< I2S registers base address */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 I2S_InitTypeDef Init; /*!< I2S communication parameters */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
<> 144:ef7eb2e8f9f7 124 (This field is initialized at the
<> 144:ef7eb2e8f9f7 125 same value as transfer size at the
<> 144:ef7eb2e8f9f7 126 beginning of the transfer and
<> 144:ef7eb2e8f9f7 127 decremented when a sample is received.
<> 144:ef7eb2e8f9f7 128 NbSamplesReceived = RxBufferSize-RxBufferCount) */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 __IO uint32_t ErrorCode; /*!< I2S Error code
<> 144:ef7eb2e8f9f7 139 This parameter can be a value of @ref I2S_Error */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 }I2S_HandleTypeDef;
<> 144:ef7eb2e8f9f7 142 /**
<> 144:ef7eb2e8f9f7 143 * @}
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 147 /** @defgroup I2S_Exported_Constants I2S Exported Constants
<> 144:ef7eb2e8f9f7 148 * @{
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150 /** @defgroup I2S_Error I2S Error
<> 144:ef7eb2e8f9f7 151 * @{
<> 144:ef7eb2e8f9f7 152 */
<> 156:95d6b41a828b 153 #define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
<> 156:95d6b41a828b 154 #define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
<> 156:95d6b41a828b 155 #define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
<> 156:95d6b41a828b 156 #define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
<> 156:95d6b41a828b 157 #define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
<> 156:95d6b41a828b 158 #define HAL_I2S_ERROR_UNKNOW (0x00000010U) /*!< Unknow Error error */
<> 144:ef7eb2e8f9f7 159 /**
<> 144:ef7eb2e8f9f7 160 * @}
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /** @defgroup I2S_Mode I2S Mode
<> 144:ef7eb2e8f9f7 164 * @{
<> 144:ef7eb2e8f9f7 165 */
<> 156:95d6b41a828b 166 #define I2S_MODE_SLAVE_TX (0x00000000U)
<> 156:95d6b41a828b 167 #define I2S_MODE_SLAVE_RX (0x00000100U)
<> 156:95d6b41a828b 168 #define I2S_MODE_MASTER_TX (0x00000200U)
<> 156:95d6b41a828b 169 #define I2S_MODE_MASTER_RX (0x00000300U)
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
<> 144:ef7eb2e8f9f7 172 ((MODE) == I2S_MODE_SLAVE_RX) || \
<> 144:ef7eb2e8f9f7 173 ((MODE) == I2S_MODE_MASTER_TX)|| \
<> 144:ef7eb2e8f9f7 174 ((MODE) == I2S_MODE_MASTER_RX))
<> 144:ef7eb2e8f9f7 175 /**
<> 144:ef7eb2e8f9f7 176 * @}
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /** @defgroup I2S_Standard I2S Standard
<> 144:ef7eb2e8f9f7 180 * @{
<> 144:ef7eb2e8f9f7 181 */
<> 156:95d6b41a828b 182 #define I2S_STANDARD_PHILIPS (0x00000000U)
<> 156:95d6b41a828b 183 #define I2S_STANDARD_MSB (0x00000010U)
<> 156:95d6b41a828b 184 #define I2S_STANDARD_LSB (0x00000020U)
<> 156:95d6b41a828b 185 #define I2S_STANDARD_PCM_SHORT (0x00000030U)
<> 156:95d6b41a828b 186 #define I2S_STANDARD_PCM_LONG (0x000000B0U)
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
<> 144:ef7eb2e8f9f7 189 ((STANDARD) == I2S_STANDARD_MSB) || \
<> 144:ef7eb2e8f9f7 190 ((STANDARD) == I2S_STANDARD_LSB) || \
<> 144:ef7eb2e8f9f7 191 ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
<> 144:ef7eb2e8f9f7 192 ((STANDARD) == I2S_STANDARD_PCM_LONG))
<> 144:ef7eb2e8f9f7 193 /**
<> 144:ef7eb2e8f9f7 194 * @}
<> 144:ef7eb2e8f9f7 195 */
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /** @defgroup I2S_Data_Format I2S Data Format
<> 144:ef7eb2e8f9f7 198 * @{
<> 144:ef7eb2e8f9f7 199 */
<> 156:95d6b41a828b 200 #define I2S_DATAFORMAT_16B (0x00000000U)
<> 156:95d6b41a828b 201 #define I2S_DATAFORMAT_16B_EXTENDED (0x00000001U)
<> 156:95d6b41a828b 202 #define I2S_DATAFORMAT_24B (0x00000003U)
<> 156:95d6b41a828b 203 #define I2S_DATAFORMAT_32B (0x00000005U)
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
<> 144:ef7eb2e8f9f7 206 ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
<> 144:ef7eb2e8f9f7 207 ((FORMAT) == I2S_DATAFORMAT_24B) || \
<> 144:ef7eb2e8f9f7 208 ((FORMAT) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 209 /**
<> 144:ef7eb2e8f9f7 210 * @}
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /** @defgroup I2S_MCLK_Output I2S MCLK Output
<> 144:ef7eb2e8f9f7 214 * @{
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216 #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
<> 156:95d6b41a828b 217 #define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
<> 144:ef7eb2e8f9f7 220 ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
<> 144:ef7eb2e8f9f7 221 /**
<> 144:ef7eb2e8f9f7 222 * @}
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
<> 144:ef7eb2e8f9f7 226 * @{
<> 144:ef7eb2e8f9f7 227 */
<> 156:95d6b41a828b 228 #define I2S_AUDIOFREQ_192K (192000U)
<> 156:95d6b41a828b 229 #define I2S_AUDIOFREQ_96K (96000U)
<> 156:95d6b41a828b 230 #define I2S_AUDIOFREQ_48K (48000U)
<> 156:95d6b41a828b 231 #define I2S_AUDIOFREQ_44K (44100U)
<> 156:95d6b41a828b 232 #define I2S_AUDIOFREQ_32K (32000U)
<> 156:95d6b41a828b 233 #define I2S_AUDIOFREQ_22K (22050U)
<> 156:95d6b41a828b 234 #define I2S_AUDIOFREQ_16K (16000U)
<> 156:95d6b41a828b 235 #define I2S_AUDIOFREQ_11K (11025U)
<> 156:95d6b41a828b 236 #define I2S_AUDIOFREQ_8K (8000U)
<> 156:95d6b41a828b 237 #define I2S_AUDIOFREQ_DEFAULT (2U)
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
<> 144:ef7eb2e8f9f7 240 ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
<> 144:ef7eb2e8f9f7 241 ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
<> 144:ef7eb2e8f9f7 242 /**
<> 144:ef7eb2e8f9f7 243 * @}
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity
<> 144:ef7eb2e8f9f7 247 * @{
<> 144:ef7eb2e8f9f7 248 */
<> 156:95d6b41a828b 249 #define I2S_CPOL_LOW (0x00000000U)
<> 144:ef7eb2e8f9f7 250 #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
<> 144:ef7eb2e8f9f7 253 ((CPOL) == I2S_CPOL_HIGH))
<> 144:ef7eb2e8f9f7 254 /**
<> 144:ef7eb2e8f9f7 255 * @}
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition
<> 144:ef7eb2e8f9f7 259 * @{
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261 #define I2S_IT_TXE SPI_CR2_TXEIE
<> 144:ef7eb2e8f9f7 262 #define I2S_IT_RXNE SPI_CR2_RXNEIE
<> 144:ef7eb2e8f9f7 263 #define I2S_IT_ERR SPI_CR2_ERRIE
<> 144:ef7eb2e8f9f7 264 /**
<> 144:ef7eb2e8f9f7 265 * @}
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /** @defgroup I2S_Flag_definition I2S Flag definition
<> 144:ef7eb2e8f9f7 269 * @{
<> 144:ef7eb2e8f9f7 270 */
<> 144:ef7eb2e8f9f7 271 #define I2S_FLAG_TXE SPI_SR_TXE
<> 144:ef7eb2e8f9f7 272 #define I2S_FLAG_RXNE SPI_SR_RXNE
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 #define I2S_FLAG_UDR SPI_SR_UDR
<> 144:ef7eb2e8f9f7 275 #define I2S_FLAG_OVR SPI_SR_OVR
<> 144:ef7eb2e8f9f7 276 #define I2S_FLAG_FRE SPI_SR_FRE
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
<> 144:ef7eb2e8f9f7 279 #define I2S_FLAG_BSY SPI_SR_BSY
<> 144:ef7eb2e8f9f7 280 /**
<> 144:ef7eb2e8f9f7 281 * @}
<> 144:ef7eb2e8f9f7 282 */
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /**
<> 144:ef7eb2e8f9f7 285 * @}
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 289 /** @defgroup I2S_Exported_macros I2S Exported Macros
<> 144:ef7eb2e8f9f7 290 * @{
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /** @brief Reset I2S handle state
Anna Bridge 180:96ed750bd169 294 * @param __HANDLE__ I2S handle.
<> 144:ef7eb2e8f9f7 295 * @retval None
<> 144:ef7eb2e8f9f7 296 */
<> 144:ef7eb2e8f9f7 297 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /** @brief Enable or disable the specified SPI peripheral (in I2S mode).
Anna Bridge 180:96ed750bd169 300 * @param __HANDLE__ specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 301 * @retval None
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303 #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 304 #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SE))
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /** @brief Enable or disable the specified I2S interrupts.
Anna Bridge 180:96ed750bd169 307 * @param __HANDLE__ specifies the I2S Handle.
Anna Bridge 180:96ed750bd169 308 * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
<> 144:ef7eb2e8f9f7 309 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 310 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 311 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 312 * @arg I2S_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 313 * @retval None
<> 144:ef7eb2e8f9f7 314 */
<> 144:ef7eb2e8f9f7 315 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 316 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /** @brief Checks if the specified I2S interrupt source is enabled or disabled.
Anna Bridge 180:96ed750bd169 319 * @param __HANDLE__ specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 320 * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
Anna Bridge 180:96ed750bd169 321 * @param __INTERRUPT__ specifies the I2S interrupt source to check.
<> 144:ef7eb2e8f9f7 322 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 323 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 324 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 325 * @arg I2S_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 326 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /** @brief Checks whether the specified I2S flag is set or not.
Anna Bridge 180:96ed750bd169 331 * @param __HANDLE__ specifies the I2S Handle.
Anna Bridge 180:96ed750bd169 332 * @param __FLAG__ specifies the flag to check.
<> 144:ef7eb2e8f9f7 333 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 334 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
<> 144:ef7eb2e8f9f7 335 * @arg I2S_FLAG_TXE: Transmit buffer empty flag
<> 144:ef7eb2e8f9f7 336 * @arg I2S_FLAG_UDR: Underrun flag
<> 144:ef7eb2e8f9f7 337 * @arg I2S_FLAG_OVR: Overrun flag
<> 144:ef7eb2e8f9f7 338 * @arg I2S_FLAG_FRE: Frame error flag
<> 144:ef7eb2e8f9f7 339 * @arg I2S_FLAG_CHSIDE: Channel Side flag
<> 144:ef7eb2e8f9f7 340 * @arg I2S_FLAG_BSY: Busy flag
<> 144:ef7eb2e8f9f7 341 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 342 */
<> 144:ef7eb2e8f9f7 343 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /** @brief Clears the I2S OVR pending flag.
Anna Bridge 180:96ed750bd169 346 * @param __HANDLE__ specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 347 * @retval None
<> 144:ef7eb2e8f9f7 348 */
<> 144:ef7eb2e8f9f7 349 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
<> 144:ef7eb2e8f9f7 350 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 351 tmpreg = (__HANDLE__)->Instance->DR; \
<> 144:ef7eb2e8f9f7 352 tmpreg = (__HANDLE__)->Instance->SR; \
<> 144:ef7eb2e8f9f7 353 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 354 }while(0)
<> 144:ef7eb2e8f9f7 355 /** @brief Clears the I2S UDR pending flag.
Anna Bridge 180:96ed750bd169 356 * @param __HANDLE__ specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 357 * @retval None
<> 144:ef7eb2e8f9f7 358 */
<> 144:ef7eb2e8f9f7 359 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
<> 144:ef7eb2e8f9f7 360 __IO uint32_t tmpreg;\
<> 144:ef7eb2e8f9f7 361 tmpreg = ((__HANDLE__)->Instance->SR);\
<> 144:ef7eb2e8f9f7 362 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 363 }while(0)
<> 144:ef7eb2e8f9f7 364 /**
<> 144:ef7eb2e8f9f7 365 * @}
<> 144:ef7eb2e8f9f7 366 */
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 369 /** @addtogroup I2S_Exported_Functions
<> 144:ef7eb2e8f9f7 370 * @{
<> 144:ef7eb2e8f9f7 371 */
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /** @addtogroup I2S_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 374 * @{
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376 /* Initialization/de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 377 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 378 HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 379 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 380 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 381 /**
<> 144:ef7eb2e8f9f7 382 * @}
<> 144:ef7eb2e8f9f7 383 */
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /** @addtogroup I2S_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 386 * @{
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388 /* I/O operation functions ***************************************************/
<> 144:ef7eb2e8f9f7 389 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 390 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 391 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 394 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 395 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 396 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 399 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 400 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 403 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 404 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
<> 144:ef7eb2e8f9f7 407 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 408 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 409 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 410 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 411 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 412 /**
<> 144:ef7eb2e8f9f7 413 * @}
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /** @addtogroup I2S_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 417 * @{
<> 144:ef7eb2e8f9f7 418 */
<> 144:ef7eb2e8f9f7 419 /* Peripheral Control and State functions ************************************/
<> 144:ef7eb2e8f9f7 420 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 421 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 422 /**
<> 144:ef7eb2e8f9f7 423 * @}
<> 144:ef7eb2e8f9f7 424 */
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /**
<> 144:ef7eb2e8f9f7 427 * @}
<> 144:ef7eb2e8f9f7 428 */
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /**
<> 144:ef7eb2e8f9f7 432 * @}
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /**
<> 144:ef7eb2e8f9f7 436 * @}
<> 144:ef7eb2e8f9f7 437 */
<> 144:ef7eb2e8f9f7 438 #endif /* defined(STM32F031x6) || defined(STM32F038xx) || */
<> 144:ef7eb2e8f9f7 439 /* defined(STM32F051x8) || defined(STM32F058xx) || */
<> 144:ef7eb2e8f9f7 440 /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||*/
<> 144:ef7eb2e8f9f7 441 /* defined(STM32F042x6) || defined(STM32F048xx) || */
<> 144:ef7eb2e8f9f7 442 /* defined(STM32F091xC) || defined(STM32F098xx) */
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 445 }
<> 144:ef7eb2e8f9f7 446 #endif
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 #endif /* __STM32F0xx_HAL_I2S_H */
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/