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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_i2s.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief I2S HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
<> 144:ef7eb2e8f9f7 8 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 9 * + IO operation functions
<> 144:ef7eb2e8f9f7 10 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ===============================================================================
<> 144:ef7eb2e8f9f7 13 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 14 ===============================================================================
<> 144:ef7eb2e8f9f7 15 [..]
<> 144:ef7eb2e8f9f7 16 The I2S HAL driver can be used as follow:
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18 (#) Declare a I2S_HandleTypeDef handle structure.
<> 144:ef7eb2e8f9f7 19 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
<> 144:ef7eb2e8f9f7 20 (##) Enable the SPIx interface clock.
<> 144:ef7eb2e8f9f7 21 (##) I2S pins configuration:
<> 144:ef7eb2e8f9f7 22 (+++) Enable the clock for the I2S GPIOs.
<> 144:ef7eb2e8f9f7 23 (+++) Configure these I2S pins as alternate function pull-up.
<> 144:ef7eb2e8f9f7 24 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 25 and HAL_I2S_Receive_IT() APIs).
<> 144:ef7eb2e8f9f7 26 (+++) Configure the I2Sx interrupt priority.
<> 144:ef7eb2e8f9f7 27 (+++) Enable the NVIC I2S IRQ handle.
<> 144:ef7eb2e8f9f7 28 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 29 and HAL_I2S_Receive_DMA() APIs:
<> 144:ef7eb2e8f9f7 30 (+++) Declare a DMA handle structure for the Tx/Rx Channel.
<> 144:ef7eb2e8f9f7 31 (+++) Enable the DMAx interface clock.
<> 144:ef7eb2e8f9f7 32 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<> 144:ef7eb2e8f9f7 33 (+++) Configure the DMA Tx/Rx Channel.
<> 144:ef7eb2e8f9f7 34 (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
<> 144:ef7eb2e8f9f7 35 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
<> 144:ef7eb2e8f9f7 36 DMA Tx/Rx Channel.
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
<> 144:ef7eb2e8f9f7 39 using HAL_I2S_Init() function.
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 -@- The specific I2S interrupts (Transmission complete interrupt,
<> 144:ef7eb2e8f9f7 42 RXNE interrupt and Error Interrupts) will be managed using the macros
<> 144:ef7eb2e8f9f7 43 __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
<> 144:ef7eb2e8f9f7 44 -@- Make sure that either:
<> 144:ef7eb2e8f9f7 45 (+@) External clock source is configured after setting correctly
<> 144:ef7eb2e8f9f7 46 the define constant EXTERNAL_CLOCK_VALUE in the stm32f0xx_hal_conf.h file.
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 (#) Three mode of operations are available within this driver :
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 51 =================================
<> 144:ef7eb2e8f9f7 52 [..]
<> 144:ef7eb2e8f9f7 53 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
<> 144:ef7eb2e8f9f7 54 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 57 ===================================
<> 144:ef7eb2e8f9f7 58 [..]
<> 144:ef7eb2e8f9f7 59 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 60 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 61 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
<> 144:ef7eb2e8f9f7 62 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 63 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
<> 144:ef7eb2e8f9f7 64 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
<> 144:ef7eb2e8f9f7 65 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 66 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
<> 144:ef7eb2e8f9f7 67 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 68 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
<> 144:ef7eb2e8f9f7 69 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 70 add his own code by customization of function pointer HAL_I2S_ErrorCallback
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 73 ==============================
<> 144:ef7eb2e8f9f7 74 [..]
<> 144:ef7eb2e8f9f7 75 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 76 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 77 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
<> 144:ef7eb2e8f9f7 78 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 79 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
<> 144:ef7eb2e8f9f7 80 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
<> 144:ef7eb2e8f9f7 81 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 82 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
<> 144:ef7eb2e8f9f7 83 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 84 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
<> 144:ef7eb2e8f9f7 85 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 86 add his own code by customization of function pointer HAL_I2S_ErrorCallback
<> 144:ef7eb2e8f9f7 87 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
<> 144:ef7eb2e8f9f7 88 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
<> 144:ef7eb2e8f9f7 89 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 *** I2S HAL driver macros list ***
<> 144:ef7eb2e8f9f7 92 =============================================
<> 144:ef7eb2e8f9f7 93 [..]
<> 144:ef7eb2e8f9f7 94 Below the list of most used macros in I2S HAL driver.
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
<> 144:ef7eb2e8f9f7 97 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
<> 144:ef7eb2e8f9f7 98 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
<> 144:ef7eb2e8f9f7 99 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
<> 144:ef7eb2e8f9f7 100 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 [..]
<> 144:ef7eb2e8f9f7 103 (@) You can refer to the I2S HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 @endverbatim
<> 144:ef7eb2e8f9f7 106 ******************************************************************************
<> 144:ef7eb2e8f9f7 107 * @attention
<> 144:ef7eb2e8f9f7 108 *
<> 144:ef7eb2e8f9f7 109 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 110 *
<> 144:ef7eb2e8f9f7 111 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 112 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 113 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 114 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 115 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 116 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 117 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 118 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 119 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 120 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 121 *
<> 144:ef7eb2e8f9f7 122 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 123 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 124 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 125 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 126 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 127 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 128 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 129 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 130 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 131 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 132 *
<> 144:ef7eb2e8f9f7 133 ******************************************************************************
<> 144:ef7eb2e8f9f7 134 */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 137 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 #ifdef HAL_I2S_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 #if defined(STM32F031x6) || defined(STM32F038xx) || \
<> 144:ef7eb2e8f9f7 142 defined(STM32F051x8) || defined(STM32F058xx) || \
<> 144:ef7eb2e8f9f7 143 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 144 defined(STM32F042x6) || defined(STM32F048xx) || \
<> 144:ef7eb2e8f9f7 145 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 148 * @{
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /** @defgroup I2S I2S
<> 144:ef7eb2e8f9f7 152 * @brief I2S HAL module driver
<> 144:ef7eb2e8f9f7 153 * @{
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 157 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 158 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 159 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 160 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 161 /** @defgroup I2S_Private_Functions I2S Private Functions
<> 144:ef7eb2e8f9f7 162 * @{
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 165 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 166 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 167 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 168 static void I2S_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 169 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 170 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 171 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 172 /**
<> 144:ef7eb2e8f9f7 173 * @}
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /** @defgroup I2S_Exported_Functions I2S Exported Functions
<> 144:ef7eb2e8f9f7 179 * @{
<> 144:ef7eb2e8f9f7 180 */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 183 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 184 *
<> 144:ef7eb2e8f9f7 185 @verbatim
<> 144:ef7eb2e8f9f7 186 ===============================================================================
<> 144:ef7eb2e8f9f7 187 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 188 ===============================================================================
<> 144:ef7eb2e8f9f7 189 [..] This subsection provides a set of functions allowing to initialize and
<> 144:ef7eb2e8f9f7 190 de-initialiaze the I2Sx peripheral in simplex mode:
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 (+) User must Implement HAL_I2S_MspInit() function in which he configures
<> 144:ef7eb2e8f9f7 193 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 (+) Call the function HAL_I2S_Init() to configure the selected device with
<> 144:ef7eb2e8f9f7 196 the selected configuration:
<> 144:ef7eb2e8f9f7 197 (++) Mode
<> 144:ef7eb2e8f9f7 198 (++) Standard
<> 144:ef7eb2e8f9f7 199 (++) Data Format
<> 144:ef7eb2e8f9f7 200 (++) MCLK Output
<> 144:ef7eb2e8f9f7 201 (++) Audio frequency
<> 144:ef7eb2e8f9f7 202 (++) Polarity
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
<> 144:ef7eb2e8f9f7 205 of the selected I2Sx periperal.
<> 144:ef7eb2e8f9f7 206 @endverbatim
<> 144:ef7eb2e8f9f7 207 * @{
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /**
<> 144:ef7eb2e8f9f7 211 * @brief Initializes the I2S according to the specified parameters
<> 144:ef7eb2e8f9f7 212 * in the I2S_InitTypeDef and create the associated handle.
Anna Bridge 180:96ed750bd169 213 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 214 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 215 * @retval HAL status
<> 144:ef7eb2e8f9f7 216 */
<> 144:ef7eb2e8f9f7 217 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 218 {
<> 156:95d6b41a828b 219 uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
<> 156:95d6b41a828b 220 uint32_t tmp = 0U, i2sclk = 0U;
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /* Check the I2S handle allocation */
<> 144:ef7eb2e8f9f7 223 if(hi2s == NULL)
<> 144:ef7eb2e8f9f7 224 {
<> 144:ef7eb2e8f9f7 225 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /* Check the I2S parameters */
<> 144:ef7eb2e8f9f7 229 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
<> 144:ef7eb2e8f9f7 230 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
<> 144:ef7eb2e8f9f7 231 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
<> 144:ef7eb2e8f9f7 232 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
<> 144:ef7eb2e8f9f7 233 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
<> 144:ef7eb2e8f9f7 234 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
<> 144:ef7eb2e8f9f7 235 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 if(hi2s->State == HAL_I2S_STATE_RESET)
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 240 hi2s->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
<> 144:ef7eb2e8f9f7 243 HAL_I2S_MspInit(hi2s);
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 hi2s->State = HAL_I2S_STATE_BUSY;
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
<> 144:ef7eb2e8f9f7 249 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
<> 144:ef7eb2e8f9f7 250 hi2s->Instance->I2SCFGR &= (uint16_t)(~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
<> 144:ef7eb2e8f9f7 251 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
<> 144:ef7eb2e8f9f7 252 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
<> 156:95d6b41a828b 253 hi2s->Instance->I2SPR = 0x0002U;
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* Get the I2SCFGR register value */
<> 144:ef7eb2e8f9f7 256 tmpreg = hi2s->Instance->I2SCFGR;
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
<> 144:ef7eb2e8f9f7 259 if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
<> 144:ef7eb2e8f9f7 260 {
<> 156:95d6b41a828b 261 i2sodd = (uint16_t)0U;
<> 156:95d6b41a828b 262 i2sdiv = (uint16_t)2U;
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264 /* If the requested audio frequency is not the default, compute the prescaler */
<> 144:ef7eb2e8f9f7 265 else
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 /* Check the frame length (For the Prescaler computing) *******************/
<> 144:ef7eb2e8f9f7 268 if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 /* Packet length is 16 bits */
<> 156:95d6b41a828b 271 packetlength = 1U;
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273 else
<> 144:ef7eb2e8f9f7 274 {
<> 144:ef7eb2e8f9f7 275 /* Packet length is 32 bits */
<> 156:95d6b41a828b 276 packetlength = 2U;
<> 144:ef7eb2e8f9f7 277 }
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* Get I2S source Clock frequency ****************************************/
<> 144:ef7eb2e8f9f7 280 i2sclk = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* Compute the Real divider depending on the MCLK output state, with a floating point */
<> 144:ef7eb2e8f9f7 283 if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
<> 144:ef7eb2e8f9f7 284 {
<> 144:ef7eb2e8f9f7 285 /* MCLK output is enabled */
<> 156:95d6b41a828b 286 tmp = (uint32_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U);
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288 else
<> 144:ef7eb2e8f9f7 289 {
<> 144:ef7eb2e8f9f7 290 /* MCLK output is disabled */
<> 156:95d6b41a828b 291 tmp = (uint32_t)(((((i2sclk / (32U * packetlength)) *10U ) / hi2s->Init.AudioFreq)) + 5U);
<> 144:ef7eb2e8f9f7 292 }
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /* Remove the flatting point */
<> 156:95d6b41a828b 295 tmp = tmp / 10U;
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /* Check the parity of the divider */
<> 156:95d6b41a828b 298 i2sodd = (uint32_t)(tmp & 1U);
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Compute the i2sdiv prescaler */
<> 156:95d6b41a828b 301 i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
<> 156:95d6b41a828b 304 i2sodd = (uint32_t) (i2sodd << 8U);
<> 144:ef7eb2e8f9f7 305 }
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /* Test if the divider is 1 or 0 or greater than 0xFF */
<> 156:95d6b41a828b 308 if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
<> 144:ef7eb2e8f9f7 309 {
<> 144:ef7eb2e8f9f7 310 /* Set the default values */
<> 156:95d6b41a828b 311 i2sdiv = 2U;
<> 156:95d6b41a828b 312 i2sodd = 0U;
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /* Write to SPIx I2SPR register the computed value */
<> 144:ef7eb2e8f9f7 316 hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /* Configure the I2S with the I2S_InitStruct values */
<> 144:ef7eb2e8f9f7 319 tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /* Write to SPIx I2SCFGR */
<> 144:ef7eb2e8f9f7 322 hi2s->Instance->I2SCFGR = tmpreg;
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 325 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 return HAL_OK;
<> 144:ef7eb2e8f9f7 328 }
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /**
<> 144:ef7eb2e8f9f7 331 * @brief DeInitializes the I2S peripheral
Anna Bridge 180:96ed750bd169 332 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 333 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 334 * @retval HAL status
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 337 {
<> 144:ef7eb2e8f9f7 338 /* Check the I2S handle allocation */
<> 144:ef7eb2e8f9f7 339 if(hi2s == NULL)
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /* Check the parameters */
<> 144:ef7eb2e8f9f7 345 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 hi2s->State = HAL_I2S_STATE_BUSY;
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Disable the I2S Peripheral Clock */
<> 144:ef7eb2e8f9f7 350 __HAL_I2S_DISABLE(hi2s);
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 353 HAL_I2S_MspDeInit(hi2s);
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 356 hi2s->State = HAL_I2S_STATE_RESET;
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* Release Lock */
<> 144:ef7eb2e8f9f7 359 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 return HAL_OK;
<> 144:ef7eb2e8f9f7 362 }
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /**
<> 144:ef7eb2e8f9f7 365 * @brief I2S MSP Init
Anna Bridge 180:96ed750bd169 366 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 367 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 368 * @retval None
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 371 {
<> 144:ef7eb2e8f9f7 372 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 373 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 376 the HAL_I2S_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 377 */
<> 144:ef7eb2e8f9f7 378 }
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /**
<> 144:ef7eb2e8f9f7 381 * @brief I2S MSP DeInit
Anna Bridge 180:96ed750bd169 382 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 383 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 384 * @retval None
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 387 {
<> 144:ef7eb2e8f9f7 388 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 389 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 392 the HAL_I2S_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394 }
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /**
<> 144:ef7eb2e8f9f7 397 * @}
<> 144:ef7eb2e8f9f7 398 */
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 401 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 402 *
<> 144:ef7eb2e8f9f7 403 @verbatim
<> 144:ef7eb2e8f9f7 404 ===============================================================================
<> 144:ef7eb2e8f9f7 405 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 406 ===============================================================================
<> 144:ef7eb2e8f9f7 407 [..]
<> 144:ef7eb2e8f9f7 408 This subsection provides a set of functions allowing to manage the I2S data
<> 144:ef7eb2e8f9f7 409 transfers.
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 412 (++) Blocking mode : The communication is performed in the polling mode.
<> 144:ef7eb2e8f9f7 413 The status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 414 after finishing transfer.
<> 144:ef7eb2e8f9f7 415 (++) No-Blocking mode : The communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 416 or DMA. These functions return the status of the transfer startup.
<> 144:ef7eb2e8f9f7 417 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 418 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 419 using DMA mode.
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 (#) Blocking mode functions are :
<> 144:ef7eb2e8f9f7 422 (++) HAL_I2S_Transmit()
<> 144:ef7eb2e8f9f7 423 (++) HAL_I2S_Receive()
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 (#) No-Blocking mode functions with Interrupt are :
<> 144:ef7eb2e8f9f7 426 (++) HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 427 (++) HAL_I2S_Receive_IT()
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 (#) No-Blocking mode functions with DMA are :
<> 144:ef7eb2e8f9f7 430 (++) HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 431 (++) HAL_I2S_Receive_DMA()
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<> 144:ef7eb2e8f9f7 434 (++) HAL_I2S_TxCpltCallback()
<> 144:ef7eb2e8f9f7 435 (++) HAL_I2S_RxCpltCallback()
<> 144:ef7eb2e8f9f7 436 (++) HAL_I2S_ErrorCallback()
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 @endverbatim
<> 144:ef7eb2e8f9f7 439 * @{
<> 144:ef7eb2e8f9f7 440 */
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /**
<> 144:ef7eb2e8f9f7 443 * @brief Transmit an amount of data in blocking mode
Anna Bridge 180:96ed750bd169 444 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 445 * the configuration information for I2S module
Anna Bridge 180:96ed750bd169 446 * @param pData a 16-bit pointer to data buffer.
Anna Bridge 180:96ed750bd169 447 * @param Size number of data sample to be sent:
<> 144:ef7eb2e8f9f7 448 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 449 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 450 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 451 * the Size parameter means the number of 16-bit data length.
Anna Bridge 180:96ed750bd169 452 * @param Timeout Timeout duration
<> 144:ef7eb2e8f9f7 453 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 454 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 455 * @retval HAL status
<> 144:ef7eb2e8f9f7 456 */
<> 144:ef7eb2e8f9f7 457 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 458 {
<> 156:95d6b41a828b 459 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /* Process Locked */
<> 144:ef7eb2e8f9f7 465 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 468 {
<> 144:ef7eb2e8f9f7 469 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 470 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 471 {
<> 156:95d6b41a828b 472 hi2s->TxXferSize = (Size << 1U);
<> 156:95d6b41a828b 473 hi2s->TxXferCount = (Size << 1U);
<> 144:ef7eb2e8f9f7 474 }
<> 144:ef7eb2e8f9f7 475 else
<> 144:ef7eb2e8f9f7 476 {
<> 144:ef7eb2e8f9f7 477 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 478 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 479 }
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /* Set state and reset error code */
<> 144:ef7eb2e8f9f7 482 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 483 hi2s->State = HAL_I2S_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 484 hi2s->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 487 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 488 {
<> 144:ef7eb2e8f9f7 489 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 490 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 491 }
<> 144:ef7eb2e8f9f7 492
<> 156:95d6b41a828b 493 while(hi2s->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 494 {
<> 144:ef7eb2e8f9f7 495 /* Wait until TXE flag is set */
<> 144:ef7eb2e8f9f7 496 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 497 {
<> 144:ef7eb2e8f9f7 498 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 499 }
<> 144:ef7eb2e8f9f7 500 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 501 hi2s->TxXferCount--;
<> 144:ef7eb2e8f9f7 502 }
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /* Wait until TXE flag is set, to confirm the end of the transcation */
<> 144:ef7eb2e8f9f7 505 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 506 {
<> 144:ef7eb2e8f9f7 507 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509 /* Wait until Busy flag is reset */
<> 144:ef7eb2e8f9f7 510 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 511 {
<> 144:ef7eb2e8f9f7 512 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 513 }
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 518 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 return HAL_OK;
<> 144:ef7eb2e8f9f7 521 }
<> 144:ef7eb2e8f9f7 522 else
<> 144:ef7eb2e8f9f7 523 {
<> 144:ef7eb2e8f9f7 524 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 525 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 526 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 527 }
<> 144:ef7eb2e8f9f7 528 }
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /**
<> 144:ef7eb2e8f9f7 531 * @brief Receive an amount of data in blocking mode
Anna Bridge 180:96ed750bd169 532 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 533 * the configuration information for I2S module
Anna Bridge 180:96ed750bd169 534 * @param pData a 16-bit pointer to data buffer.
Anna Bridge 180:96ed750bd169 535 * @param Size number of data sample to be sent:
<> 144:ef7eb2e8f9f7 536 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 537 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 538 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 539 * the Size parameter means the number of 16-bit data length.
Anna Bridge 180:96ed750bd169 540 * @param Timeout Timeout duration
<> 144:ef7eb2e8f9f7 541 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 542 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 543 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
<> 144:ef7eb2e8f9f7 544 * in continouse way and as the I2S is not disabled at the end of the I2S transaction.
<> 144:ef7eb2e8f9f7 545 * @retval HAL status
<> 144:ef7eb2e8f9f7 546 */
<> 144:ef7eb2e8f9f7 547 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 548 {
<> 156:95d6b41a828b 549 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 550 {
<> 144:ef7eb2e8f9f7 551 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 552 }
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /* Process Locked */
<> 144:ef7eb2e8f9f7 555 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 558 {
<> 144:ef7eb2e8f9f7 559 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 560 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 561 {
<> 156:95d6b41a828b 562 hi2s->RxXferSize = (Size << 1U);
<> 156:95d6b41a828b 563 hi2s->RxXferCount = (Size << 1U);
<> 144:ef7eb2e8f9f7 564 }
<> 144:ef7eb2e8f9f7 565 else
<> 144:ef7eb2e8f9f7 566 {
<> 144:ef7eb2e8f9f7 567 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 568 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 569 }
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /* Set state and reset error code */
<> 144:ef7eb2e8f9f7 572 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 573 hi2s->State = HAL_I2S_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 574 hi2s->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 577 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 578 {
<> 144:ef7eb2e8f9f7 579 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 580 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 581 }
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 /* Receive data */
<> 156:95d6b41a828b 584 while(hi2s->RxXferCount > 0U)
<> 144:ef7eb2e8f9f7 585 {
<> 144:ef7eb2e8f9f7 586 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 587 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 588 {
<> 144:ef7eb2e8f9f7 589 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 590 }
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
<> 144:ef7eb2e8f9f7 593 hi2s->RxXferCount--;
<> 144:ef7eb2e8f9f7 594 }
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 599 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 return HAL_OK;
<> 144:ef7eb2e8f9f7 602 }
<> 144:ef7eb2e8f9f7 603 else
<> 144:ef7eb2e8f9f7 604 {
<> 144:ef7eb2e8f9f7 605 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 606 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 607 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 608 }
<> 144:ef7eb2e8f9f7 609 }
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /**
<> 144:ef7eb2e8f9f7 612 * @brief Transmit an amount of data in non-blocking mode with Interrupt
Anna Bridge 180:96ed750bd169 613 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 614 * the configuration information for I2S module
Anna Bridge 180:96ed750bd169 615 * @param pData a 16-bit pointer to data buffer.
Anna Bridge 180:96ed750bd169 616 * @param Size number of data sample to be sent:
<> 144:ef7eb2e8f9f7 617 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 618 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 619 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 620 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 621 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 622 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 623 * @retval HAL status
<> 144:ef7eb2e8f9f7 624 */
<> 144:ef7eb2e8f9f7 625 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 626 {
<> 156:95d6b41a828b 627 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 628 {
<> 144:ef7eb2e8f9f7 629 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 630 }
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /* Process Locked */
<> 144:ef7eb2e8f9f7 633 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 636 {
<> 144:ef7eb2e8f9f7 637 hi2s->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 638 hi2s->State = HAL_I2S_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 639 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 642 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 643 {
<> 156:95d6b41a828b 644 hi2s->TxXferSize = (Size << 1U);
<> 156:95d6b41a828b 645 hi2s->TxXferCount = (Size << 1U);
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647 else
<> 144:ef7eb2e8f9f7 648 {
<> 144:ef7eb2e8f9f7 649 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 650 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 651 }
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 654 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 657 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 658 {
<> 144:ef7eb2e8f9f7 659 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 660 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 661 }
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 664 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 return HAL_OK;
<> 144:ef7eb2e8f9f7 667 }
<> 144:ef7eb2e8f9f7 668 else
<> 144:ef7eb2e8f9f7 669 {
<> 144:ef7eb2e8f9f7 670 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 671 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 672 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 673 }
<> 144:ef7eb2e8f9f7 674 }
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /**
<> 144:ef7eb2e8f9f7 677 * @brief Receive an amount of data in non-blocking mode with Interrupt
Anna Bridge 180:96ed750bd169 678 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 679 * the configuration information for I2S module
Anna Bridge 180:96ed750bd169 680 * @param pData a 16-bit pointer to the Receive data buffer.
Anna Bridge 180:96ed750bd169 681 * @param Size number of data sample to be sent:
<> 144:ef7eb2e8f9f7 682 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 683 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 684 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 685 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 686 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 687 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 688 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
<> 144:ef7eb2e8f9f7 689 * between Master and Slave otherwise the I2S interrupt should be optimized.
<> 144:ef7eb2e8f9f7 690 * @retval HAL status
<> 144:ef7eb2e8f9f7 691 */
<> 144:ef7eb2e8f9f7 692 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 693 {
<> 156:95d6b41a828b 694 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 695 {
<> 144:ef7eb2e8f9f7 696 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 697 }
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /* Process Locked */
<> 144:ef7eb2e8f9f7 700 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 703 {
<> 144:ef7eb2e8f9f7 704 hi2s->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 705 hi2s->State = HAL_I2S_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 706 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 709 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 710 {
<> 156:95d6b41a828b 711 hi2s->RxXferSize = (Size << 1U);
<> 156:95d6b41a828b 712 hi2s->RxXferCount = (Size << 1U);
<> 144:ef7eb2e8f9f7 713 }
<> 144:ef7eb2e8f9f7 714 else
<> 144:ef7eb2e8f9f7 715 {
<> 144:ef7eb2e8f9f7 716 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 717 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 718 }
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 721 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 724 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 725 {
<> 144:ef7eb2e8f9f7 726 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 727 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 728 }
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 731 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 return HAL_OK;
<> 144:ef7eb2e8f9f7 734 }
<> 144:ef7eb2e8f9f7 735 else
<> 144:ef7eb2e8f9f7 736 {
<> 144:ef7eb2e8f9f7 737 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 738 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 739 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 740 }
<> 144:ef7eb2e8f9f7 741 }
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 /**
<> 144:ef7eb2e8f9f7 744 * @brief Transmit an amount of data in non-blocking mode with DMA
Anna Bridge 180:96ed750bd169 745 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 746 * the configuration information for I2S module
Anna Bridge 180:96ed750bd169 747 * @param pData a 16-bit pointer to the Transmit data buffer.
Anna Bridge 180:96ed750bd169 748 * @param Size number of data sample to be sent:
<> 144:ef7eb2e8f9f7 749 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 750 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 751 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 752 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 753 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 754 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 755 * @retval HAL status
<> 144:ef7eb2e8f9f7 756 */
<> 144:ef7eb2e8f9f7 757 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 758 {
<> 156:95d6b41a828b 759 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 760 {
<> 144:ef7eb2e8f9f7 761 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 762 }
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /* Process Locked */
<> 144:ef7eb2e8f9f7 765 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 768 {
<> 144:ef7eb2e8f9f7 769 hi2s->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 770 hi2s->State = HAL_I2S_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 771 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 774 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 775 {
<> 156:95d6b41a828b 776 hi2s->TxXferSize = (Size << 1U);
<> 156:95d6b41a828b 777 hi2s->TxXferCount = (Size << 1U);
<> 144:ef7eb2e8f9f7 778 }
<> 144:ef7eb2e8f9f7 779 else
<> 144:ef7eb2e8f9f7 780 {
<> 144:ef7eb2e8f9f7 781 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 782 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 783 }
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 /* Set the I2S Tx DMA Half transfert complete callback */
<> 144:ef7eb2e8f9f7 786 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 /* Set the I2S Tx DMA transfert complete callback */
<> 144:ef7eb2e8f9f7 789 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 792 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794 /* Enable the Tx DMA Channel */
<> 144:ef7eb2e8f9f7 795 HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 798 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 799 {
<> 144:ef7eb2e8f9f7 800 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 801 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 802 }
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /* Check if the I2S Tx request is already enabled */
<> 144:ef7eb2e8f9f7 805 if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
<> 144:ef7eb2e8f9f7 806 {
<> 144:ef7eb2e8f9f7 807 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 808 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
<> 144:ef7eb2e8f9f7 809 }
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 812 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 return HAL_OK;
<> 144:ef7eb2e8f9f7 815 }
<> 144:ef7eb2e8f9f7 816 else
<> 144:ef7eb2e8f9f7 817 {
<> 144:ef7eb2e8f9f7 818 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 819 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 820 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 821 }
<> 144:ef7eb2e8f9f7 822 }
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 /**
<> 144:ef7eb2e8f9f7 825 * @brief Receive an amount of data in non-blocking mode with DMA
Anna Bridge 180:96ed750bd169 826 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 827 * the configuration information for I2S module
Anna Bridge 180:96ed750bd169 828 * @param pData a 16-bit pointer to the Receive data buffer.
Anna Bridge 180:96ed750bd169 829 * @param Size number of data sample to be sent:
<> 144:ef7eb2e8f9f7 830 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 831 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 832 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 833 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 834 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 835 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 836 * @retval HAL status
<> 144:ef7eb2e8f9f7 837 */
<> 144:ef7eb2e8f9f7 838 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 839 {
<> 156:95d6b41a828b 840 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 841 {
<> 144:ef7eb2e8f9f7 842 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 843 }
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /* Process Locked */
<> 144:ef7eb2e8f9f7 846 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 849 {
<> 144:ef7eb2e8f9f7 850 hi2s->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 851 hi2s->State = HAL_I2S_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 852 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 855 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 856 {
<> 156:95d6b41a828b 857 hi2s->RxXferSize = (Size << 1U);
<> 156:95d6b41a828b 858 hi2s->RxXferCount = (Size << 1U);
<> 144:ef7eb2e8f9f7 859 }
<> 144:ef7eb2e8f9f7 860 else
<> 144:ef7eb2e8f9f7 861 {
<> 144:ef7eb2e8f9f7 862 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 863 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 864 }
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 /* Set the I2S Rx DMA Half transfert complete callback */
<> 144:ef7eb2e8f9f7 868 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 /* Set the I2S Rx DMA transfert complete callback */
<> 144:ef7eb2e8f9f7 871 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 874 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 /* Check if Master Receiver mode is selected */
<> 144:ef7eb2e8f9f7 877 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
<> 144:ef7eb2e8f9f7 878 {
<> 144:ef7eb2e8f9f7 879 /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
<> 144:ef7eb2e8f9f7 880 access to the SPI_SR register. */
<> 144:ef7eb2e8f9f7 881 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
<> 144:ef7eb2e8f9f7 882 }
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 /* Enable the Rx DMA Channel */
<> 144:ef7eb2e8f9f7 885 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 888 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 889 {
<> 144:ef7eb2e8f9f7 890 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 891 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 892 }
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 /* Check if the I2S Rx request is already enabled */
<> 144:ef7eb2e8f9f7 895 if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
<> 144:ef7eb2e8f9f7 896 {
<> 144:ef7eb2e8f9f7 897 /* Enable Rx DMA Request */
<> 144:ef7eb2e8f9f7 898 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
<> 144:ef7eb2e8f9f7 899 }
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 902 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 return HAL_OK;
<> 144:ef7eb2e8f9f7 905 }
<> 144:ef7eb2e8f9f7 906 else
<> 144:ef7eb2e8f9f7 907 {
<> 144:ef7eb2e8f9f7 908 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 909 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 910 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 911 }
<> 144:ef7eb2e8f9f7 912 }
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914 /**
<> 144:ef7eb2e8f9f7 915 * @brief Pauses the audio stream playing from the Media.
Anna Bridge 180:96ed750bd169 916 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 917 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 918 * @retval HAL status
<> 144:ef7eb2e8f9f7 919 */
<> 144:ef7eb2e8f9f7 920 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 921 {
<> 144:ef7eb2e8f9f7 922 /* Process Locked */
<> 144:ef7eb2e8f9f7 923 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 926 {
<> 144:ef7eb2e8f9f7 927 /* Disable the I2S DMA Tx request */
<> 144:ef7eb2e8f9f7 928 hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 929 }
<> 144:ef7eb2e8f9f7 930 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 931 {
<> 144:ef7eb2e8f9f7 932 /* Disable the I2S DMA Rx request */
<> 144:ef7eb2e8f9f7 933 hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 934 }
<> 144:ef7eb2e8f9f7 935
<> 144:ef7eb2e8f9f7 936 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 937 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 return HAL_OK;
<> 144:ef7eb2e8f9f7 940 }
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 /**
<> 144:ef7eb2e8f9f7 943 * @brief Resumes the audio stream playing from the Media.
Anna Bridge 180:96ed750bd169 944 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 945 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 946 * @retval HAL status
<> 144:ef7eb2e8f9f7 947 */
<> 144:ef7eb2e8f9f7 948 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 949 {
<> 144:ef7eb2e8f9f7 950 /* Process Locked */
<> 144:ef7eb2e8f9f7 951 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 954 {
<> 144:ef7eb2e8f9f7 955 /* Enable the I2S DMA Tx request */
<> 144:ef7eb2e8f9f7 956 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
<> 144:ef7eb2e8f9f7 957 }
<> 144:ef7eb2e8f9f7 958 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 959 {
<> 144:ef7eb2e8f9f7 960 /* Enable the I2S DMA Rx request */
<> 144:ef7eb2e8f9f7 961 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
<> 144:ef7eb2e8f9f7 962 }
<> 144:ef7eb2e8f9f7 963
<> 144:ef7eb2e8f9f7 964 /* If the I2S peripheral is still not enabled, enable it */
<> 156:95d6b41a828b 965 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
<> 144:ef7eb2e8f9f7 966 {
<> 144:ef7eb2e8f9f7 967 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 968 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 969 }
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 972 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 973
<> 144:ef7eb2e8f9f7 974 return HAL_OK;
<> 144:ef7eb2e8f9f7 975 }
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 /**
<> 144:ef7eb2e8f9f7 978 * @brief Resumes the audio stream playing from the Media.
Anna Bridge 180:96ed750bd169 979 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 980 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 981 * @retval HAL status
<> 144:ef7eb2e8f9f7 982 */
<> 144:ef7eb2e8f9f7 983 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 984 {
<> 144:ef7eb2e8f9f7 985 /* Process Locked */
<> 144:ef7eb2e8f9f7 986 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 /* Disable the I2S Tx/Rx DMA requests */
<> 144:ef7eb2e8f9f7 989 hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 990 hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992 /* Abort the I2S DMA tx channel */
<> 144:ef7eb2e8f9f7 993 if(hi2s->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 994 {
<> 144:ef7eb2e8f9f7 995 /* Disable the I2S DMA channel */
<> 144:ef7eb2e8f9f7 996 __HAL_DMA_DISABLE(hi2s->hdmatx);
<> 144:ef7eb2e8f9f7 997 HAL_DMA_Abort(hi2s->hdmatx);
<> 144:ef7eb2e8f9f7 998 }
<> 144:ef7eb2e8f9f7 999 /* Abort the I2S DMA rx channel */
<> 144:ef7eb2e8f9f7 1000 if(hi2s->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 1001 {
<> 144:ef7eb2e8f9f7 1002 /* Disable the I2S DMA channel */
<> 144:ef7eb2e8f9f7 1003 __HAL_DMA_DISABLE(hi2s->hdmarx);
<> 144:ef7eb2e8f9f7 1004 HAL_DMA_Abort(hi2s->hdmarx);
<> 144:ef7eb2e8f9f7 1005 }
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /* Disable I2S peripheral */
<> 144:ef7eb2e8f9f7 1008 __HAL_I2S_DISABLE(hi2s);
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1013 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 return HAL_OK;
<> 144:ef7eb2e8f9f7 1016 }
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 /**
<> 144:ef7eb2e8f9f7 1019 * @brief This function handles I2S interrupt request.
Anna Bridge 180:96ed750bd169 1020 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1021 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1022 * @retval None
<> 144:ef7eb2e8f9f7 1023 */
<> 144:ef7eb2e8f9f7 1024 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1025 {
<> 144:ef7eb2e8f9f7 1026 uint32_t i2ssr = hi2s->Instance->SR;
<> 144:ef7eb2e8f9f7 1027
<> 144:ef7eb2e8f9f7 1028 /* I2S in mode Receiver ------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1029 if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) &&
<> 144:ef7eb2e8f9f7 1030 ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
<> 144:ef7eb2e8f9f7 1031 {
<> 144:ef7eb2e8f9f7 1032 I2S_Receive_IT(hi2s);
<> 144:ef7eb2e8f9f7 1033 return;
<> 144:ef7eb2e8f9f7 1034 }
<> 144:ef7eb2e8f9f7 1035
<> 144:ef7eb2e8f9f7 1036 /* I2S in mode Tramitter -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1037 if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
<> 144:ef7eb2e8f9f7 1038 {
<> 144:ef7eb2e8f9f7 1039 I2S_Transmit_IT(hi2s);
<> 144:ef7eb2e8f9f7 1040 return;
<> 144:ef7eb2e8f9f7 1041 }
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 /* I2S Overrun error interrupt occured ---------------------------------*/
<> 144:ef7eb2e8f9f7 1044 if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
<> 144:ef7eb2e8f9f7 1045 {
<> 144:ef7eb2e8f9f7 1046 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1047 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1048
<> 144:ef7eb2e8f9f7 1049 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 1050 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 1053 hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
<> 144:ef7eb2e8f9f7 1054 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 1055 }
<> 144:ef7eb2e8f9f7 1056
<> 144:ef7eb2e8f9f7 1057 /* I2S Underrun error interrupt occured --------------------------------*/
<> 144:ef7eb2e8f9f7 1058 if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
<> 144:ef7eb2e8f9f7 1059 {
<> 144:ef7eb2e8f9f7 1060 /* Disable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1061 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1062
<> 144:ef7eb2e8f9f7 1063 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 1064 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1065
<> 144:ef7eb2e8f9f7 1066 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 1067 hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
<> 144:ef7eb2e8f9f7 1068 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 1069 }
<> 144:ef7eb2e8f9f7 1070 }
<> 144:ef7eb2e8f9f7 1071
<> 144:ef7eb2e8f9f7 1072 /**
<> 144:ef7eb2e8f9f7 1073 * @brief Tx Transfer Half completed callbacks
Anna Bridge 180:96ed750bd169 1074 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1075 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1076 * @retval None
<> 144:ef7eb2e8f9f7 1077 */
<> 144:ef7eb2e8f9f7 1078 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1079 {
<> 144:ef7eb2e8f9f7 1080 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1081 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1082
<> 144:ef7eb2e8f9f7 1083 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1084 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1085 */
<> 144:ef7eb2e8f9f7 1086 }
<> 144:ef7eb2e8f9f7 1087
<> 144:ef7eb2e8f9f7 1088 /**
<> 144:ef7eb2e8f9f7 1089 * @brief Tx Transfer completed callbacks
Anna Bridge 180:96ed750bd169 1090 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1091 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1092 * @retval None
<> 144:ef7eb2e8f9f7 1093 */
<> 144:ef7eb2e8f9f7 1094 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1095 {
<> 144:ef7eb2e8f9f7 1096 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1097 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1098
<> 144:ef7eb2e8f9f7 1099 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1100 the HAL_I2S_TxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1101 */
<> 144:ef7eb2e8f9f7 1102 }
<> 144:ef7eb2e8f9f7 1103
<> 144:ef7eb2e8f9f7 1104 /**
<> 144:ef7eb2e8f9f7 1105 * @brief Rx Transfer half completed callbacks
Anna Bridge 180:96ed750bd169 1106 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1107 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1108 * @retval None
<> 144:ef7eb2e8f9f7 1109 */
<> 144:ef7eb2e8f9f7 1110 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1111 {
<> 144:ef7eb2e8f9f7 1112 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1113 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1114
<> 144:ef7eb2e8f9f7 1115 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1116 the HAL_I2S_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1117 */
<> 144:ef7eb2e8f9f7 1118 }
<> 144:ef7eb2e8f9f7 1119
<> 144:ef7eb2e8f9f7 1120 /**
<> 144:ef7eb2e8f9f7 1121 * @brief Rx Transfer completed callbacks
Anna Bridge 180:96ed750bd169 1122 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1123 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1124 * @retval None
<> 144:ef7eb2e8f9f7 1125 */
<> 144:ef7eb2e8f9f7 1126 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1127 {
<> 144:ef7eb2e8f9f7 1128 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1129 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1132 the HAL_I2S_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1133 */
<> 144:ef7eb2e8f9f7 1134 }
<> 144:ef7eb2e8f9f7 1135
<> 144:ef7eb2e8f9f7 1136 /**
<> 144:ef7eb2e8f9f7 1137 * @brief I2S error callbacks
Anna Bridge 180:96ed750bd169 1138 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1139 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1140 * @retval None
<> 144:ef7eb2e8f9f7 1141 */
<> 144:ef7eb2e8f9f7 1142 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1143 {
<> 144:ef7eb2e8f9f7 1144 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1145 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1146
<> 144:ef7eb2e8f9f7 1147 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1148 the HAL_I2S_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1149 */
<> 144:ef7eb2e8f9f7 1150 }
<> 144:ef7eb2e8f9f7 1151
<> 144:ef7eb2e8f9f7 1152 /**
<> 144:ef7eb2e8f9f7 1153 * @}
<> 144:ef7eb2e8f9f7 1154 */
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 1157 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 1158 *
<> 144:ef7eb2e8f9f7 1159 @verbatim
<> 144:ef7eb2e8f9f7 1160 ===============================================================================
<> 144:ef7eb2e8f9f7 1161 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 1162 ===============================================================================
<> 144:ef7eb2e8f9f7 1163 [..]
<> 144:ef7eb2e8f9f7 1164 This subsection permits to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 1165 and the data flow.
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 @endverbatim
<> 144:ef7eb2e8f9f7 1168 * @{
<> 144:ef7eb2e8f9f7 1169 */
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 /**
<> 144:ef7eb2e8f9f7 1172 * @brief Return the I2S state
Anna Bridge 180:96ed750bd169 1173 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1174 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1175 * @retval HAL state
<> 144:ef7eb2e8f9f7 1176 */
<> 144:ef7eb2e8f9f7 1177 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1178 {
<> 144:ef7eb2e8f9f7 1179 return hi2s->State;
<> 144:ef7eb2e8f9f7 1180 }
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 /**
<> 144:ef7eb2e8f9f7 1183 * @brief Return the I2S error code
Anna Bridge 180:96ed750bd169 1184 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1185 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1186 * @retval I2S Error Code
<> 144:ef7eb2e8f9f7 1187 */
<> 144:ef7eb2e8f9f7 1188 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1189 {
<> 144:ef7eb2e8f9f7 1190 return hi2s->ErrorCode;
<> 144:ef7eb2e8f9f7 1191 }
<> 144:ef7eb2e8f9f7 1192 /**
<> 144:ef7eb2e8f9f7 1193 * @}
<> 144:ef7eb2e8f9f7 1194 */
<> 144:ef7eb2e8f9f7 1195
<> 144:ef7eb2e8f9f7 1196 /**
<> 144:ef7eb2e8f9f7 1197 * @}
<> 144:ef7eb2e8f9f7 1198 */
<> 144:ef7eb2e8f9f7 1199
<> 144:ef7eb2e8f9f7 1200 /** @addtogroup I2S_Private_Functions I2S Private Functions
<> 144:ef7eb2e8f9f7 1201 * @{
<> 144:ef7eb2e8f9f7 1202 */
<> 144:ef7eb2e8f9f7 1203 /**
<> 144:ef7eb2e8f9f7 1204 * @brief DMA I2S transmit process complete callback
Anna Bridge 180:96ed750bd169 1205 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1206 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1207 * @retval None
<> 144:ef7eb2e8f9f7 1208 */
<> 144:ef7eb2e8f9f7 1209 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1210 {
<> 144:ef7eb2e8f9f7 1211 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1212
<> 156:95d6b41a828b 1213 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
<> 144:ef7eb2e8f9f7 1214 {
<> 144:ef7eb2e8f9f7 1215 /* Disable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1216 hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1217
<> 156:95d6b41a828b 1218 hi2s->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1219 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1220 }
<> 144:ef7eb2e8f9f7 1221 HAL_I2S_TxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1222 }
<> 144:ef7eb2e8f9f7 1223
<> 144:ef7eb2e8f9f7 1224 /**
<> 144:ef7eb2e8f9f7 1225 * @brief DMA I2S transmit process half complete callback
Anna Bridge 180:96ed750bd169 1226 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1227 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1228 * @retval None
<> 144:ef7eb2e8f9f7 1229 */
<> 144:ef7eb2e8f9f7 1230 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1231 {
<> 144:ef7eb2e8f9f7 1232 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1233
<> 144:ef7eb2e8f9f7 1234 HAL_I2S_TxHalfCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1235 }
<> 144:ef7eb2e8f9f7 1236
<> 144:ef7eb2e8f9f7 1237 /**
<> 144:ef7eb2e8f9f7 1238 * @brief DMA I2S receive process complete callback
Anna Bridge 180:96ed750bd169 1239 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1240 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1241 * @retval None
<> 144:ef7eb2e8f9f7 1242 */
<> 144:ef7eb2e8f9f7 1243 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1244 {
<> 144:ef7eb2e8f9f7 1245 I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1246
<> 156:95d6b41a828b 1247 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
<> 144:ef7eb2e8f9f7 1248 {
<> 144:ef7eb2e8f9f7 1249 /* Disable Rx DMA Request */
<> 144:ef7eb2e8f9f7 1250 hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1251 hi2s->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 1252 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1253 }
<> 144:ef7eb2e8f9f7 1254 HAL_I2S_RxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1255 }
<> 144:ef7eb2e8f9f7 1256
<> 144:ef7eb2e8f9f7 1257 /**
<> 144:ef7eb2e8f9f7 1258 * @brief DMA I2S receive process half complete callback
Anna Bridge 180:96ed750bd169 1259 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1260 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1261 * @retval None
<> 144:ef7eb2e8f9f7 1262 */
<> 144:ef7eb2e8f9f7 1263 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1264 {
<> 144:ef7eb2e8f9f7 1265 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1266
<> 144:ef7eb2e8f9f7 1267 HAL_I2S_RxHalfCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1268 }
<> 144:ef7eb2e8f9f7 1269
<> 144:ef7eb2e8f9f7 1270 /**
<> 144:ef7eb2e8f9f7 1271 * @brief DMA I2S communication error callback
Anna Bridge 180:96ed750bd169 1272 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1273 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1274 * @retval None
<> 144:ef7eb2e8f9f7 1275 */
<> 144:ef7eb2e8f9f7 1276 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1277 {
<> 144:ef7eb2e8f9f7 1278 I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 /* Disable Rx and Tx DMA Request */
<> 144:ef7eb2e8f9f7 1281 hi2s->Instance->CR2 &= (uint16_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
<> 156:95d6b41a828b 1282 hi2s->TxXferCount = 0U;
<> 156:95d6b41a828b 1283 hi2s->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1284
<> 144:ef7eb2e8f9f7 1285 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1286
<> 144:ef7eb2e8f9f7 1287 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 1288 hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
<> 144:ef7eb2e8f9f7 1289 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 1290 }
<> 144:ef7eb2e8f9f7 1291
<> 144:ef7eb2e8f9f7 1292 /**
<> 144:ef7eb2e8f9f7 1293 * @brief Transmit an amount of data in non-blocking mode with Interrupt
Anna Bridge 180:96ed750bd169 1294 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1295 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1296 * @retval None
<> 144:ef7eb2e8f9f7 1297 */
<> 144:ef7eb2e8f9f7 1298 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1299 {
<> 144:ef7eb2e8f9f7 1300 /* Transmit data */
<> 144:ef7eb2e8f9f7 1301 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 1302 hi2s->TxXferCount--;
<> 144:ef7eb2e8f9f7 1303
<> 144:ef7eb2e8f9f7 1304 if(hi2s->TxXferCount == 0)
<> 144:ef7eb2e8f9f7 1305 {
<> 144:ef7eb2e8f9f7 1306 /* Disable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1307 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1308
<> 144:ef7eb2e8f9f7 1309 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1310 HAL_I2S_TxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1311 }
<> 144:ef7eb2e8f9f7 1312 }
<> 144:ef7eb2e8f9f7 1313
<> 144:ef7eb2e8f9f7 1314 /**
<> 144:ef7eb2e8f9f7 1315 * @brief Receive an amount of data in non-blocking mode with Interrupt
Anna Bridge 180:96ed750bd169 1316 * @param hi2s I2S handle
<> 144:ef7eb2e8f9f7 1317 * @retval None
<> 144:ef7eb2e8f9f7 1318 */
<> 144:ef7eb2e8f9f7 1319 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1320 {
<> 144:ef7eb2e8f9f7 1321 /* Receive data */
<> 144:ef7eb2e8f9f7 1322 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
<> 144:ef7eb2e8f9f7 1323 hi2s->RxXferCount--;
<> 144:ef7eb2e8f9f7 1324
<> 156:95d6b41a828b 1325 if(hi2s->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 1326 {
<> 144:ef7eb2e8f9f7 1327 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1328 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1331 HAL_I2S_RxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1332 }
<> 144:ef7eb2e8f9f7 1333 }
<> 144:ef7eb2e8f9f7 1334
<> 144:ef7eb2e8f9f7 1335
<> 144:ef7eb2e8f9f7 1336 /**
<> 144:ef7eb2e8f9f7 1337 * @brief This function handles I2S Communication Timeout.
Anna Bridge 180:96ed750bd169 1338 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1339 * the configuration information for I2S module
Anna Bridge 180:96ed750bd169 1340 * @param Flag Flag checked
Anna Bridge 180:96ed750bd169 1341 * @param State Value of the flag expected
Anna Bridge 180:96ed750bd169 1342 * @param Timeout Duration of the timeout
<> 144:ef7eb2e8f9f7 1343 * @retval HAL status
<> 144:ef7eb2e8f9f7 1344 */
<> 144:ef7eb2e8f9f7 1345 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1346 {
<> 144:ef7eb2e8f9f7 1347 uint32_t tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1348
<> 144:ef7eb2e8f9f7 1349 /* Wait until flag is set */
<> 144:ef7eb2e8f9f7 1350 if(State == RESET)
<> 144:ef7eb2e8f9f7 1351 {
<> 144:ef7eb2e8f9f7 1352 while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
<> 144:ef7eb2e8f9f7 1353 {
<> 144:ef7eb2e8f9f7 1354 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1355 {
<> 156:95d6b41a828b 1356 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 1357 {
<> 144:ef7eb2e8f9f7 1358 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 1359 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1360
<> 144:ef7eb2e8f9f7 1361 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1362 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1363
<> 144:ef7eb2e8f9f7 1364 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1365 }
<> 144:ef7eb2e8f9f7 1366 }
<> 144:ef7eb2e8f9f7 1367 }
<> 144:ef7eb2e8f9f7 1368 }
<> 144:ef7eb2e8f9f7 1369 else
<> 144:ef7eb2e8f9f7 1370 {
<> 144:ef7eb2e8f9f7 1371 while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
<> 144:ef7eb2e8f9f7 1372 {
<> 144:ef7eb2e8f9f7 1373 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1374 {
<> 156:95d6b41a828b 1375 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 1376 {
<> 144:ef7eb2e8f9f7 1377 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 1378 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1379
<> 144:ef7eb2e8f9f7 1380 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1381 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1382
<> 144:ef7eb2e8f9f7 1383 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1384 }
<> 144:ef7eb2e8f9f7 1385 }
<> 144:ef7eb2e8f9f7 1386 }
<> 144:ef7eb2e8f9f7 1387 }
<> 144:ef7eb2e8f9f7 1388 return HAL_OK;
<> 144:ef7eb2e8f9f7 1389 }
<> 144:ef7eb2e8f9f7 1390
<> 144:ef7eb2e8f9f7 1391 /**
<> 144:ef7eb2e8f9f7 1392 * @}
<> 144:ef7eb2e8f9f7 1393 */
<> 144:ef7eb2e8f9f7 1394
<> 144:ef7eb2e8f9f7 1395 /**
<> 144:ef7eb2e8f9f7 1396 * @}
<> 144:ef7eb2e8f9f7 1397 */
<> 144:ef7eb2e8f9f7 1398
<> 144:ef7eb2e8f9f7 1399 /**
<> 144:ef7eb2e8f9f7 1400 * @}
<> 144:ef7eb2e8f9f7 1401 */
<> 144:ef7eb2e8f9f7 1402
<> 144:ef7eb2e8f9f7 1403 #endif /* defined(STM32F031x6) || defined(STM32F038xx) || */
<> 144:ef7eb2e8f9f7 1404 /* defined(STM32F051x8) || defined(STM32F058xx) || */
<> 144:ef7eb2e8f9f7 1405 /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */
<> 144:ef7eb2e8f9f7 1406 /* defined(STM32F042x6) || defined(STM32F048xx) || */
<> 144:ef7eb2e8f9f7 1407 /* defined(STM32F091xC) || defined(STM32F098xx) */
<> 144:ef7eb2e8f9f7 1408
<> 144:ef7eb2e8f9f7 1409 #endif /* HAL_I2S_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1410
<> 144:ef7eb2e8f9f7 1411 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/