mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_gpio.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_gpio.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief GPIO HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the General Purpose Input/Output (GPIO) peripheral:
<> 144:ef7eb2e8f9f7 8 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 9 * + IO operation functions
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### GPIO Peripheral features #####
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 [..]
<> 144:ef7eb2e8f9f7 16 (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
<> 144:ef7eb2e8f9f7 17 configured by software in several modes:
<> 144:ef7eb2e8f9f7 18 (++) Input mode
<> 144:ef7eb2e8f9f7 19 (++) Analog mode
<> 144:ef7eb2e8f9f7 20 (++) Output mode
<> 144:ef7eb2e8f9f7 21 (++) Alternate function mode
<> 144:ef7eb2e8f9f7 22 (++) External interrupt/event lines
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 (+) During and just after reset, the alternate functions and external interrupt
<> 144:ef7eb2e8f9f7 25 lines are not active and the I/O ports are configured in input floating mode.
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
<> 144:ef7eb2e8f9f7 28 activated or not.
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
<> 144:ef7eb2e8f9f7 31 type and the IO speed can be selected depending on the VDD value.
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
<> 144:ef7eb2e8f9f7 34 multiplexer that allows only one peripheral alternate function (AF) connected
<> 144:ef7eb2e8f9f7 35 to an IO pin at a time. In this way, there can be no conflict between peripherals
<> 144:ef7eb2e8f9f7 36 sharing the same IO pin.
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 (+) All ports have external interrupt/event capability. To use external interrupt
<> 144:ef7eb2e8f9f7 39 lines, the port must be configured in input mode. All available GPIO pins are
<> 144:ef7eb2e8f9f7 40 connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 (+) The external interrupt/event controller consists of up to 28 edge detectors
<> 144:ef7eb2e8f9f7 43 (16 lines are connected to GPIO) for generating event/interrupt requests (each
<> 144:ef7eb2e8f9f7 44 input line can be independently configured to select the type (interrupt or event)
<> 144:ef7eb2e8f9f7 45 and the corresponding trigger event (rising or falling or both). Each line can
<> 144:ef7eb2e8f9f7 46 also be masked independently.
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 49 ==============================================================================
<> 144:ef7eb2e8f9f7 50 [..]
<> 144:ef7eb2e8f9f7 51 (#) Enable the GPIO AHB clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE().
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
<> 144:ef7eb2e8f9f7 54 (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
<> 144:ef7eb2e8f9f7 55 (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
<> 144:ef7eb2e8f9f7 56 structure.
<> 144:ef7eb2e8f9f7 57 (++) In case of Output or alternate function mode selection: the speed is
<> 144:ef7eb2e8f9f7 58 configured through "Speed" member from GPIO_InitTypeDef structure.
<> 144:ef7eb2e8f9f7 59 (++) In alternate mode is selection, the alternate function connected to the IO
<> 144:ef7eb2e8f9f7 60 is configured through "Alternate" member from GPIO_InitTypeDef structure.
<> 144:ef7eb2e8f9f7 61 (++) Analog mode is required when a pin is to be used as ADC channel
<> 144:ef7eb2e8f9f7 62 or DAC output.
<> 144:ef7eb2e8f9f7 63 (++) In case of external interrupt/event selection the "Mode" member from
<> 144:ef7eb2e8f9f7 64 GPIO_InitTypeDef structure select the type (interrupt or event) and
<> 144:ef7eb2e8f9f7 65 the corresponding trigger event (rising or falling or both).
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
<> 144:ef7eb2e8f9f7 68 mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
<> 144:ef7eb2e8f9f7 69 HAL_NVIC_EnableIRQ().
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 (#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also
<> 144:ef7eb2e8f9f7 72 recommended to use it to unconfigure pin which was used as an external interrupt
<> 144:ef7eb2e8f9f7 73 or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG
<> 144:ef7eb2e8f9f7 74 registers.
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 (#) To set/reset the level of a pin configured in output mode use
<> 144:ef7eb2e8f9f7 79 HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 (#) During and just after reset, the alternate functions are not
<> 144:ef7eb2e8f9f7 84 active and the GPIO pins are configured in input floating mode (except JTAG
<> 144:ef7eb2e8f9f7 85 pins).
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
<> 144:ef7eb2e8f9f7 88 (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
<> 144:ef7eb2e8f9f7 89 priority over the GPIO function.
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
<> 144:ef7eb2e8f9f7 92 general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
<> 144:ef7eb2e8f9f7 93 The HSE has priority over the GPIO function.
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 @endverbatim
<> 144:ef7eb2e8f9f7 96 ******************************************************************************
<> 144:ef7eb2e8f9f7 97 * @attention
<> 144:ef7eb2e8f9f7 98 *
<> 144:ef7eb2e8f9f7 99 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 100 *
<> 144:ef7eb2e8f9f7 101 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 102 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 103 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 104 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 105 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 106 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 107 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 108 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 109 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 110 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 111 *
<> 144:ef7eb2e8f9f7 112 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 113 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 114 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 115 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 116 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 117 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 118 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 119 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 120 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 121 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 122 *
<> 144:ef7eb2e8f9f7 123 ******************************************************************************
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 127 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 130 * @{
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /** @defgroup GPIO GPIO
<> 144:ef7eb2e8f9f7 134 * @brief GPIO HAL module driver
<> 144:ef7eb2e8f9f7 135 * @{
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 #ifdef HAL_GPIO_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 141 /* Private defines -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 142 /** @defgroup GPIO_Private_Defines GPIO Private Defines
<> 144:ef7eb2e8f9f7 143 * @{
<> 144:ef7eb2e8f9f7 144 */
<> 156:95d6b41a828b 145 #define GPIO_MODE (0x00000003U)
<> 156:95d6b41a828b 146 #define EXTI_MODE (0x10000000U)
<> 156:95d6b41a828b 147 #define GPIO_MODE_IT (0x00010000U)
<> 156:95d6b41a828b 148 #define GPIO_MODE_EVT (0x00020000U)
<> 156:95d6b41a828b 149 #define RISING_EDGE (0x00100000U)
<> 156:95d6b41a828b 150 #define FALLING_EDGE (0x00200000U)
<> 156:95d6b41a828b 151 #define GPIO_OUTPUT_TYPE (0x00000010U)
<> 144:ef7eb2e8f9f7 152
<> 156:95d6b41a828b 153 #define GPIO_NUMBER (16U)
<> 144:ef7eb2e8f9f7 154 /**
<> 144:ef7eb2e8f9f7 155 * @}
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 159 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 160 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 161 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
<> 144:ef7eb2e8f9f7 164 * @{
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 168 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 169 *
<> 144:ef7eb2e8f9f7 170 @verbatim
<> 144:ef7eb2e8f9f7 171 ===============================================================================
<> 144:ef7eb2e8f9f7 172 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 173 ===============================================================================
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 @endverbatim
<> 144:ef7eb2e8f9f7 176 * @{
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /**
<> 144:ef7eb2e8f9f7 180 * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
Anna Bridge 180:96ed750bd169 181 * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
Anna Bridge 180:96ed750bd169 182 * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 183 * the configuration information for the specified GPIO peripheral.
<> 144:ef7eb2e8f9f7 184 * @retval None
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186 void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
<> 144:ef7eb2e8f9f7 187 {
<> 156:95d6b41a828b 188 uint32_t position = 0x00U;
<> 156:95d6b41a828b 189 uint32_t iocurrent = 0x00U;
<> 156:95d6b41a828b 190 uint32_t temp = 0x00U;
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /* Check the parameters */
<> 144:ef7eb2e8f9f7 193 assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
<> 144:ef7eb2e8f9f7 194 assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
<> 144:ef7eb2e8f9f7 195 assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
<> 144:ef7eb2e8f9f7 196 assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /* Configure the port pins */
<> 144:ef7eb2e8f9f7 199 while (((GPIO_Init->Pin) >> position) != RESET)
<> 144:ef7eb2e8f9f7 200 {
<> 144:ef7eb2e8f9f7 201 /* Get current io position */
<> 144:ef7eb2e8f9f7 202 iocurrent = (GPIO_Init->Pin) & (1U << position);
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 if(iocurrent)
<> 144:ef7eb2e8f9f7 205 {
<> 144:ef7eb2e8f9f7 206 /*--------------------- GPIO Mode Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 207 /* In case of Alternate function mode selection */
<> 144:ef7eb2e8f9f7 208 if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
<> 144:ef7eb2e8f9f7 209 {
<> 144:ef7eb2e8f9f7 210 /* Check the Alternate function parameters */
<> 144:ef7eb2e8f9f7 211 assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
<> 144:ef7eb2e8f9f7 212 assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Configure Alternate function mapped with the current IO */
<> 144:ef7eb2e8f9f7 215 temp = GPIOx->AFR[position >> 3];
<> 156:95d6b41a828b 216 CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
<> 156:95d6b41a828b 217 SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
<> 156:95d6b41a828b 218 GPIOx->AFR[position >> 3U] = temp;
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
<> 144:ef7eb2e8f9f7 222 temp = GPIOx->MODER;
<> 156:95d6b41a828b 223 CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2U));
<> 156:95d6b41a828b 224 SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
<> 144:ef7eb2e8f9f7 225 GPIOx->MODER = temp;
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /* In case of Output or Alternate function mode selection */
<> 144:ef7eb2e8f9f7 228 if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
<> 144:ef7eb2e8f9f7 229 (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
<> 144:ef7eb2e8f9f7 230 {
<> 144:ef7eb2e8f9f7 231 /* Check the Speed parameter */
<> 144:ef7eb2e8f9f7 232 assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
<> 144:ef7eb2e8f9f7 233 /* Configure the IO Speed */
<> 144:ef7eb2e8f9f7 234 temp = GPIOx->OSPEEDR;
<> 156:95d6b41a828b 235 CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
<> 156:95d6b41a828b 236 SET_BIT(temp, GPIO_Init->Speed << (position * 2U));
<> 144:ef7eb2e8f9f7 237 GPIOx->OSPEEDR = temp;
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /* Configure the IO Output Type */
<> 144:ef7eb2e8f9f7 240 temp = GPIOx->OTYPER;
<> 144:ef7eb2e8f9f7 241 CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ;
<> 156:95d6b41a828b 242 SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
<> 144:ef7eb2e8f9f7 243 GPIOx->OTYPER = temp;
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Activate the Pull-up or Pull down resistor for the current IO */
<> 144:ef7eb2e8f9f7 247 temp = GPIOx->PUPDR;
<> 156:95d6b41a828b 248 CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2U));
<> 156:95d6b41a828b 249 SET_BIT(temp, (GPIO_Init->Pull) << (position * 2U));
<> 144:ef7eb2e8f9f7 250 GPIOx->PUPDR = temp;
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /*--------------------- EXTI Mode Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 253 /* Configure the External Interrupt or event for the current IO */
<> 144:ef7eb2e8f9f7 254 if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
<> 144:ef7eb2e8f9f7 255 {
<> 144:ef7eb2e8f9f7 256 /* Enable SYSCFG Clock */
<> 144:ef7eb2e8f9f7 257 __HAL_RCC_SYSCFG_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 temp = SYSCFG->EXTICR[position >> 2];
<> 156:95d6b41a828b 260 CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
<> 156:95d6b41a828b 261 SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
<> 144:ef7eb2e8f9f7 262 SYSCFG->EXTICR[position >> 2] = temp;
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /* Clear EXTI line configuration */
<> 144:ef7eb2e8f9f7 265 temp = EXTI->IMR;
<> 144:ef7eb2e8f9f7 266 CLEAR_BIT(temp, (uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 267 if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
<> 144:ef7eb2e8f9f7 268 {
<> 144:ef7eb2e8f9f7 269 SET_BIT(temp, iocurrent);
<> 144:ef7eb2e8f9f7 270 }
<> 144:ef7eb2e8f9f7 271 EXTI->IMR = temp;
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 temp = EXTI->EMR;
<> 144:ef7eb2e8f9f7 274 CLEAR_BIT(temp, (uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 275 if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
<> 144:ef7eb2e8f9f7 276 {
<> 144:ef7eb2e8f9f7 277 SET_BIT(temp, iocurrent);
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279 EXTI->EMR = temp;
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /* Clear Rising Falling edge configuration */
<> 144:ef7eb2e8f9f7 282 temp = EXTI->RTSR;
<> 144:ef7eb2e8f9f7 283 CLEAR_BIT(temp, (uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 284 if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
<> 144:ef7eb2e8f9f7 285 {
<> 144:ef7eb2e8f9f7 286 SET_BIT(temp, iocurrent);
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288 EXTI->RTSR = temp;
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 temp = EXTI->FTSR;
<> 144:ef7eb2e8f9f7 291 CLEAR_BIT(temp, (uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 292 if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
<> 144:ef7eb2e8f9f7 293 {
<> 144:ef7eb2e8f9f7 294 SET_BIT(temp, iocurrent);
<> 144:ef7eb2e8f9f7 295 }
<> 144:ef7eb2e8f9f7 296 EXTI->FTSR = temp;
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298 }
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 position++;
<> 144:ef7eb2e8f9f7 301 }
<> 144:ef7eb2e8f9f7 302 }
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /**
<> 144:ef7eb2e8f9f7 305 * @brief De-initialize the GPIOx peripheral registers to their default reset values.
Anna Bridge 180:96ed750bd169 306 * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
Anna Bridge 180:96ed750bd169 307 * @param GPIO_Pin specifies the port bit to be written.
<> 144:ef7eb2e8f9f7 308 * This parameter can be one of GPIO_PIN_x where x can be (0..15).
<> 144:ef7eb2e8f9f7 309 * @retval None
<> 144:ef7eb2e8f9f7 310 */
<> 144:ef7eb2e8f9f7 311 void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 312 {
<> 156:95d6b41a828b 313 uint32_t position = 0x00U;
<> 156:95d6b41a828b 314 uint32_t iocurrent = 0x00U;
<> 156:95d6b41a828b 315 uint32_t tmp = 0x00U;
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Check the parameters */
<> 144:ef7eb2e8f9f7 318 assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
<> 144:ef7eb2e8f9f7 319 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /* Configure the port pins */
<> 144:ef7eb2e8f9f7 322 while ((GPIO_Pin >> position) != RESET)
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 /* Get current io position */
<> 144:ef7eb2e8f9f7 325 iocurrent = GPIO_Pin & (1U << position);
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 if (iocurrent)
<> 144:ef7eb2e8f9f7 328 {
<> 144:ef7eb2e8f9f7 329 /*------------------------- GPIO Mode Configuration --------------------*/
<> 144:ef7eb2e8f9f7 330 /* Configure IO Direction in Input Floting Mode */
<> 156:95d6b41a828b 331 CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2U));
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /* Configure the default Alternate Function in current IO */
<> 156:95d6b41a828b 334 CLEAR_BIT(GPIOx->AFR[position >> 3U], 0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /* Configure the default value for IO Speed */
<> 156:95d6b41a828b 337 CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /* Configure the default value IO Output Type */
<> 144:ef7eb2e8f9f7 340 CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ;
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /* Deactivate the Pull-up oand Pull-down resistor for the current IO */
<> 156:95d6b41a828b 343 CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2U));
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /*------------------------- EXTI Mode Configuration --------------------*/
<> 144:ef7eb2e8f9f7 346 /* Clear the External Interrupt or Event for the current IO */
<> 144:ef7eb2e8f9f7 347
<> 156:95d6b41a828b 348 tmp = SYSCFG->EXTICR[position >> 2U];
<> 156:95d6b41a828b 349 tmp &= ((0x0FU) << (4U * (position & 0x03U)));
<> 156:95d6b41a828b 350 if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
<> 144:ef7eb2e8f9f7 351 {
<> 156:95d6b41a828b 352 tmp = (0x0FU) << (4U * (position & 0x03U));
<> 156:95d6b41a828b 353 CLEAR_BIT(SYSCFG->EXTICR[position >> 2U], tmp);
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /* Clear EXTI line configuration */
<> 144:ef7eb2e8f9f7 356 CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 357 CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /* Clear Rising Falling edge configuration */
<> 144:ef7eb2e8f9f7 360 CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 361 CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 362 }
<> 144:ef7eb2e8f9f7 363 }
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 position++;
<> 144:ef7eb2e8f9f7 366 }
<> 144:ef7eb2e8f9f7 367 }
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /**
<> 144:ef7eb2e8f9f7 370 * @}
<> 144:ef7eb2e8f9f7 371 */
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 374 * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
<> 144:ef7eb2e8f9f7 375 *
<> 144:ef7eb2e8f9f7 376 @verbatim
<> 144:ef7eb2e8f9f7 377 ===============================================================================
<> 144:ef7eb2e8f9f7 378 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 379 ===============================================================================
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 @endverbatim
<> 144:ef7eb2e8f9f7 382 * @{
<> 144:ef7eb2e8f9f7 383 */
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /**
<> 144:ef7eb2e8f9f7 386 * @brief Read the specified input port pin.
Anna Bridge 180:96ed750bd169 387 * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
Anna Bridge 180:96ed750bd169 388 * @param GPIO_Pin specifies the port bit to read.
<> 144:ef7eb2e8f9f7 389 * This parameter can be GPIO_PIN_x where x can be (0..15).
<> 144:ef7eb2e8f9f7 390 * @retval The input port pin value.
<> 144:ef7eb2e8f9f7 391 */
<> 144:ef7eb2e8f9f7 392 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 393 {
<> 144:ef7eb2e8f9f7 394 GPIO_PinState bitstatus;
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /* Check the parameters */
<> 144:ef7eb2e8f9f7 397 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 bitstatus = GPIO_PIN_SET;
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403 else
<> 144:ef7eb2e8f9f7 404 {
<> 144:ef7eb2e8f9f7 405 bitstatus = GPIO_PIN_RESET;
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407 return bitstatus;
<> 144:ef7eb2e8f9f7 408 }
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /**
<> 144:ef7eb2e8f9f7 411 * @brief Set or clear the selected data port bit.
<> 144:ef7eb2e8f9f7 412 * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
<> 144:ef7eb2e8f9f7 413 * accesses. In this way, there is no risk of an IRQ occurring between
<> 144:ef7eb2e8f9f7 414 * the read and the modify access.
<> 144:ef7eb2e8f9f7 415 *
Anna Bridge 180:96ed750bd169 416 * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32F0 family
Anna Bridge 180:96ed750bd169 417 * @param GPIO_Pin specifies the port bit to be written.
<> 144:ef7eb2e8f9f7 418 * This parameter can be one of GPIO_PIN_x where x can be (0..15).
Anna Bridge 180:96ed750bd169 419 * @param PinState specifies the value to be written to the selected bit.
<> 144:ef7eb2e8f9f7 420 * This parameter can be one of the GPIO_PinState enum values:
<> 144:ef7eb2e8f9f7 421 * @arg GPIO_PIN_RESET: to clear the port pin
<> 144:ef7eb2e8f9f7 422 * @arg GPIO_PIN_SET: to set the port pin
<> 144:ef7eb2e8f9f7 423 * @retval None
<> 144:ef7eb2e8f9f7 424 */
<> 144:ef7eb2e8f9f7 425 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
<> 144:ef7eb2e8f9f7 426 {
<> 144:ef7eb2e8f9f7 427 /* Check the parameters */
<> 144:ef7eb2e8f9f7 428 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 429 assert_param(IS_GPIO_PIN_ACTION(PinState));
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 if (PinState != GPIO_PIN_RESET)
<> 144:ef7eb2e8f9f7 432 {
<> 144:ef7eb2e8f9f7 433 GPIOx->BSRR = (uint32_t)GPIO_Pin;
<> 144:ef7eb2e8f9f7 434 }
<> 144:ef7eb2e8f9f7 435 else
<> 144:ef7eb2e8f9f7 436 {
<> 144:ef7eb2e8f9f7 437 GPIOx->BRR = (uint32_t)GPIO_Pin;
<> 144:ef7eb2e8f9f7 438 }
<> 144:ef7eb2e8f9f7 439 }
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /**
<> 144:ef7eb2e8f9f7 442 * @brief Toggle the specified GPIO pin.
Anna Bridge 180:96ed750bd169 443 * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
Anna Bridge 180:96ed750bd169 444 * @param GPIO_Pin specifies the pin to be toggled.
<> 144:ef7eb2e8f9f7 445 * @retval None
<> 144:ef7eb2e8f9f7 446 */
<> 144:ef7eb2e8f9f7 447 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 448 {
<> 144:ef7eb2e8f9f7 449 /* Check the parameters */
<> 144:ef7eb2e8f9f7 450 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 GPIOx->ODR ^= GPIO_Pin;
<> 144:ef7eb2e8f9f7 453 }
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /**
<> 144:ef7eb2e8f9f7 456 * @brief Locks GPIO Pins configuration registers.
<> 144:ef7eb2e8f9f7 457 * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
<> 144:ef7eb2e8f9f7 458 * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
<> 144:ef7eb2e8f9f7 459 * @note The configuration of the locked GPIO pins can no longer be modified
<> 144:ef7eb2e8f9f7 460 * until the next reset.
Anna Bridge 180:96ed750bd169 461 * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
Anna Bridge 180:96ed750bd169 462 * @param GPIO_Pin specifies the port bits to be locked.
<> 144:ef7eb2e8f9f7 463 * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
<> 144:ef7eb2e8f9f7 464 * @retval None
<> 144:ef7eb2e8f9f7 465 */
<> 144:ef7eb2e8f9f7 466 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 467 {
<> 144:ef7eb2e8f9f7 468 __IO uint32_t tmp = GPIO_LCKR_LCKK;
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /* Check the parameters */
<> 144:ef7eb2e8f9f7 471 assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
<> 144:ef7eb2e8f9f7 472 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /* Apply lock key write sequence */
<> 144:ef7eb2e8f9f7 475 SET_BIT(tmp, GPIO_Pin);
<> 144:ef7eb2e8f9f7 476 /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
<> 144:ef7eb2e8f9f7 477 GPIOx->LCKR = tmp;
<> 144:ef7eb2e8f9f7 478 /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
<> 144:ef7eb2e8f9f7 479 GPIOx->LCKR = GPIO_Pin;
<> 144:ef7eb2e8f9f7 480 /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
<> 144:ef7eb2e8f9f7 481 GPIOx->LCKR = tmp;
<> 144:ef7eb2e8f9f7 482 /* Read LCKK bit*/
<> 144:ef7eb2e8f9f7 483 tmp = GPIOx->LCKR;
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
<> 144:ef7eb2e8f9f7 486 {
<> 144:ef7eb2e8f9f7 487 return HAL_OK;
<> 144:ef7eb2e8f9f7 488 }
<> 144:ef7eb2e8f9f7 489 else
<> 144:ef7eb2e8f9f7 490 {
<> 144:ef7eb2e8f9f7 491 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 492 }
<> 144:ef7eb2e8f9f7 493 }
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /**
<> 144:ef7eb2e8f9f7 496 * @brief Handle EXTI interrupt request.
Anna Bridge 180:96ed750bd169 497 * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
<> 144:ef7eb2e8f9f7 498 * @retval None
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 501 {
<> 144:ef7eb2e8f9f7 502 /* EXTI line interrupt detected */
<> 144:ef7eb2e8f9f7 503 if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
<> 144:ef7eb2e8f9f7 504 {
<> 144:ef7eb2e8f9f7 505 __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
<> 144:ef7eb2e8f9f7 506 HAL_GPIO_EXTI_Callback(GPIO_Pin);
<> 144:ef7eb2e8f9f7 507 }
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /**
<> 144:ef7eb2e8f9f7 511 * @brief EXTI line detection callback.
Anna Bridge 180:96ed750bd169 512 * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
<> 144:ef7eb2e8f9f7 513 * @retval None
<> 144:ef7eb2e8f9f7 514 */
<> 144:ef7eb2e8f9f7 515 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 518 UNUSED(GPIO_Pin);
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /* NOTE: This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 521 the HAL_GPIO_EXTI_Callback could be implemented in the user file
<> 144:ef7eb2e8f9f7 522 */
<> 144:ef7eb2e8f9f7 523 }
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /**
<> 144:ef7eb2e8f9f7 526 * @}
<> 144:ef7eb2e8f9f7 527 */
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /**
<> 144:ef7eb2e8f9f7 531 * @}
<> 144:ef7eb2e8f9f7 532 */
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 #endif /* HAL_GPIO_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 535 /**
<> 144:ef7eb2e8f9f7 536 * @}
<> 144:ef7eb2e8f9f7 537 */
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /**
<> 144:ef7eb2e8f9f7 540 * @}
<> 144:ef7eb2e8f9f7 541 */
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/