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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma_ex.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_dma_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of DMA HAL Extension module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F0xx_HAL_DMA_EX_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F0xx_HAL_DMA_EX_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @defgroup DMAEx DMAEx
<> 144:ef7eb2e8f9f7 52 * @brief DMA HAL module driver
<> 144:ef7eb2e8f9f7 53 * @{
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 59 /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62 #define DMA1_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */
<> 144:ef7eb2e8f9f7 63 #define DMA1_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */
<> 144:ef7eb2e8f9f7 64 #define DMA1_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */
<> 144:ef7eb2e8f9f7 65 #define DMA1_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */
<> 144:ef7eb2e8f9f7 66 #define DMA1_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */
<> 144:ef7eb2e8f9f7 67 #if !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 68 #define DMA1_CHANNEL6_RMP 0x50000000 /*!< Internal define for remaping on STM32F09x/30xC */
<> 144:ef7eb2e8f9f7 69 #define DMA1_CHANNEL7_RMP 0x60000000 /*!< Internal define for remaping on STM32F09x/30xC */
<> 144:ef7eb2e8f9f7 70 #define DMA2_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */
<> 144:ef7eb2e8f9f7 71 #define DMA2_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */
<> 144:ef7eb2e8f9f7 72 #define DMA2_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */
<> 144:ef7eb2e8f9f7 73 #define DMA2_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */
<> 144:ef7eb2e8f9f7 74 #define DMA2_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */
<> 144:ef7eb2e8f9f7 75 #endif /* !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /****************** DMA1 remap bit field definition********************/
<> 144:ef7eb2e8f9f7 78 /* DMA1 - Channel 1 */
<> 144:ef7eb2e8f9f7 79 #define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
<> 144:ef7eb2e8f9f7 80 #define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/
<> 144:ef7eb2e8f9f7 81 #define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
<> 144:ef7eb2e8f9f7 82 #define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */
<> 144:ef7eb2e8f9f7 83 #define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */
<> 144:ef7eb2e8f9f7 84 #define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */
<> 144:ef7eb2e8f9f7 85 #define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */
<> 144:ef7eb2e8f9f7 86 #define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */
<> 144:ef7eb2e8f9f7 87 #define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */
<> 144:ef7eb2e8f9f7 88 #define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */
<> 144:ef7eb2e8f9f7 89 #if !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 90 #define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */
<> 144:ef7eb2e8f9f7 91 #define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */
<> 144:ef7eb2e8f9f7 92 #endif /* !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /* DMA1 - Channel 2 */
<> 144:ef7eb2e8f9f7 95 #define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
<> 144:ef7eb2e8f9f7 96 #define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */
<> 144:ef7eb2e8f9f7 97 #define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */
<> 144:ef7eb2e8f9f7 98 #define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */
<> 144:ef7eb2e8f9f7 99 #define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
<> 144:ef7eb2e8f9f7 100 #define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
<> 144:ef7eb2e8f9f7 101 #define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */
<> 144:ef7eb2e8f9f7 102 #define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */
<> 144:ef7eb2e8f9f7 103 #define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */
<> 144:ef7eb2e8f9f7 104 #define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */
<> 144:ef7eb2e8f9f7 105 #define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */
<> 144:ef7eb2e8f9f7 106 #define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */
<> 144:ef7eb2e8f9f7 107 #define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */
<> 144:ef7eb2e8f9f7 108 #if !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 109 #define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */
<> 144:ef7eb2e8f9f7 110 #define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */
<> 144:ef7eb2e8f9f7 111 #endif /* !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /* DMA1 - Channel 3 */
<> 144:ef7eb2e8f9f7 114 #define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
<> 144:ef7eb2e8f9f7 115 #define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */
<> 144:ef7eb2e8f9f7 116 #if !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 117 #define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */
<> 144:ef7eb2e8f9f7 118 #endif /* !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 119 #define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */
<> 144:ef7eb2e8f9f7 120 #define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */
<> 144:ef7eb2e8f9f7 121 #define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
<> 144:ef7eb2e8f9f7 122 #if !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 123 #define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
<> 144:ef7eb2e8f9f7 124 #endif /* !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 125 #define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
<> 144:ef7eb2e8f9f7 126 #define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */
<> 144:ef7eb2e8f9f7 127 #define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */
<> 144:ef7eb2e8f9f7 128 #define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */
<> 144:ef7eb2e8f9f7 129 #define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */
<> 144:ef7eb2e8f9f7 130 #define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */
<> 144:ef7eb2e8f9f7 131 #define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */
<> 144:ef7eb2e8f9f7 132 #define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */
<> 144:ef7eb2e8f9f7 133 #if !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 134 #define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */
<> 144:ef7eb2e8f9f7 135 #define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */
<> 144:ef7eb2e8f9f7 136 #endif /* !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /* DMA1 - Channel 4 */
<> 144:ef7eb2e8f9f7 139 #define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
<> 144:ef7eb2e8f9f7 140 #define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */
<> 144:ef7eb2e8f9f7 141 #if !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 142 #define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */
<> 144:ef7eb2e8f9f7 143 #endif /* !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 144 #define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */
<> 144:ef7eb2e8f9f7 145 #define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */
<> 144:ef7eb2e8f9f7 146 #if !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 147 #define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
<> 144:ef7eb2e8f9f7 148 #endif /* !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 149 #define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
<> 144:ef7eb2e8f9f7 150 #define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */
<> 144:ef7eb2e8f9f7 151 #define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
<> 144:ef7eb2e8f9f7 152 #define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */
<> 144:ef7eb2e8f9f7 153 #define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */
<> 144:ef7eb2e8f9f7 154 #define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */
<> 144:ef7eb2e8f9f7 155 #define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */
<> 144:ef7eb2e8f9f7 156 #define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */
<> 144:ef7eb2e8f9f7 157 #define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */
<> 144:ef7eb2e8f9f7 158 #define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */
<> 144:ef7eb2e8f9f7 159 #if !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 160 #define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */
<> 144:ef7eb2e8f9f7 161 #define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */
<> 144:ef7eb2e8f9f7 162 #endif /* !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* DMA1 - Channel 5 */
<> 144:ef7eb2e8f9f7 165 #define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
<> 144:ef7eb2e8f9f7 166 #define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */
<> 144:ef7eb2e8f9f7 167 #define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */
<> 144:ef7eb2e8f9f7 168 #define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
<> 144:ef7eb2e8f9f7 169 #define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */
<> 144:ef7eb2e8f9f7 170 #define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */
<> 144:ef7eb2e8f9f7 171 #define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */
<> 144:ef7eb2e8f9f7 172 #define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */
<> 144:ef7eb2e8f9f7 173 #define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */
<> 144:ef7eb2e8f9f7 174 #define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */
<> 144:ef7eb2e8f9f7 175 #if !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 176 #define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */
<> 144:ef7eb2e8f9f7 177 #define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */
<> 144:ef7eb2e8f9f7 178 #endif /* !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 #if !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 181 /* DMA1 - Channel 6 */
<> 144:ef7eb2e8f9f7 182 #define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
<> 144:ef7eb2e8f9f7 183 #define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */
<> 144:ef7eb2e8f9f7 184 #define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */
<> 144:ef7eb2e8f9f7 185 #define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
<> 144:ef7eb2e8f9f7 186 #define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
<> 144:ef7eb2e8f9f7 187 #define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
<> 144:ef7eb2e8f9f7 188 #define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
<> 144:ef7eb2e8f9f7 189 #define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */
<> 144:ef7eb2e8f9f7 190 #define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
<> 144:ef7eb2e8f9f7 191 #define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */
<> 144:ef7eb2e8f9f7 192 #define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */
<> 144:ef7eb2e8f9f7 193 #define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */
<> 144:ef7eb2e8f9f7 194 #define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */
<> 144:ef7eb2e8f9f7 195 #define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */
<> 144:ef7eb2e8f9f7 196 #define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */
<> 144:ef7eb2e8f9f7 197 #define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */
<> 144:ef7eb2e8f9f7 198 #define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */
<> 144:ef7eb2e8f9f7 199 #define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */
<> 144:ef7eb2e8f9f7 200 /* DMA1 - Channel 7 */
<> 144:ef7eb2e8f9f7 201 #define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
<> 144:ef7eb2e8f9f7 202 #define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */
<> 144:ef7eb2e8f9f7 203 #define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */
<> 144:ef7eb2e8f9f7 204 #define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
<> 144:ef7eb2e8f9f7 205 #define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
<> 144:ef7eb2e8f9f7 206 #define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
<> 144:ef7eb2e8f9f7 207 #define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */
<> 144:ef7eb2e8f9f7 208 #define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */
<> 144:ef7eb2e8f9f7 209 #define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */
<> 144:ef7eb2e8f9f7 210 #define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */
<> 144:ef7eb2e8f9f7 211 #define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */
<> 144:ef7eb2e8f9f7 212 #define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */
<> 144:ef7eb2e8f9f7 213 #define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */
<> 144:ef7eb2e8f9f7 214 #define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */
<> 144:ef7eb2e8f9f7 215 #define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /****************** DMA2 remap bit field definition********************/
<> 144:ef7eb2e8f9f7 218 /* DMA2 - Channel 1 */
<> 144:ef7eb2e8f9f7 219 #define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
<> 144:ef7eb2e8f9f7 220 #define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */
<> 144:ef7eb2e8f9f7 221 #define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */
<> 144:ef7eb2e8f9f7 222 #define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */
<> 144:ef7eb2e8f9f7 223 #define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */
<> 144:ef7eb2e8f9f7 224 #define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */
<> 144:ef7eb2e8f9f7 225 #define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */
<> 144:ef7eb2e8f9f7 226 #define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */
<> 144:ef7eb2e8f9f7 227 #define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */
<> 144:ef7eb2e8f9f7 228 #define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */
<> 144:ef7eb2e8f9f7 229 /* DMA2 - Channel 2 */
<> 144:ef7eb2e8f9f7 230 #define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
<> 144:ef7eb2e8f9f7 231 #define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */
<> 144:ef7eb2e8f9f7 232 #define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */
<> 144:ef7eb2e8f9f7 233 #define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */
<> 144:ef7eb2e8f9f7 234 #define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */
<> 144:ef7eb2e8f9f7 235 #define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */
<> 144:ef7eb2e8f9f7 236 #define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */
<> 144:ef7eb2e8f9f7 237 #define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */
<> 144:ef7eb2e8f9f7 238 #define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */
<> 144:ef7eb2e8f9f7 239 #define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */
<> 144:ef7eb2e8f9f7 240 /* DMA2 - Channel 3 */
<> 144:ef7eb2e8f9f7 241 #define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
<> 144:ef7eb2e8f9f7 242 #define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */
<> 144:ef7eb2e8f9f7 243 #define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */
<> 144:ef7eb2e8f9f7 244 #define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */
<> 144:ef7eb2e8f9f7 245 #define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */
<> 144:ef7eb2e8f9f7 246 #define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */
<> 144:ef7eb2e8f9f7 247 #define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */
<> 144:ef7eb2e8f9f7 248 #define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */
<> 144:ef7eb2e8f9f7 249 #define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */
<> 144:ef7eb2e8f9f7 250 #define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */
<> 144:ef7eb2e8f9f7 251 #define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */
<> 144:ef7eb2e8f9f7 252 #define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */
<> 144:ef7eb2e8f9f7 253 /* DMA2 - Channel 4 */
<> 144:ef7eb2e8f9f7 254 #define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
<> 144:ef7eb2e8f9f7 255 #define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */
<> 144:ef7eb2e8f9f7 256 #define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */
<> 144:ef7eb2e8f9f7 257 #define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */
<> 144:ef7eb2e8f9f7 258 #define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */
<> 144:ef7eb2e8f9f7 259 #define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */
<> 144:ef7eb2e8f9f7 260 #define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */
<> 144:ef7eb2e8f9f7 261 #define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */
<> 144:ef7eb2e8f9f7 262 #define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */
<> 144:ef7eb2e8f9f7 263 #define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */
<> 144:ef7eb2e8f9f7 264 #define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */
<> 144:ef7eb2e8f9f7 265 #define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */
<> 144:ef7eb2e8f9f7 266 /* DMA2 - Channel 5 */
<> 144:ef7eb2e8f9f7 267 #define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
<> 144:ef7eb2e8f9f7 268 #define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */
<> 144:ef7eb2e8f9f7 269 #define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */
<> 144:ef7eb2e8f9f7 270 #define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */
<> 144:ef7eb2e8f9f7 271 #define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */
<> 144:ef7eb2e8f9f7 272 #define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */
<> 144:ef7eb2e8f9f7 273 #define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */
<> 144:ef7eb2e8f9f7 274 #define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */
<> 144:ef7eb2e8f9f7 275 #define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */
<> 144:ef7eb2e8f9f7 276 #define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */
<> 144:ef7eb2e8f9f7 277 #endif /* !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 280 #define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
<> 144:ef7eb2e8f9f7 281 ((REQUEST) == HAL_DMA1_CH1_ADC) ||\
<> 144:ef7eb2e8f9f7 282 ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
<> 144:ef7eb2e8f9f7 283 ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\
<> 144:ef7eb2e8f9f7 284 ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\
<> 144:ef7eb2e8f9f7 285 ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\
<> 144:ef7eb2e8f9f7 286 ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\
<> 144:ef7eb2e8f9f7 287 ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\
<> 144:ef7eb2e8f9f7 288 ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\
<> 144:ef7eb2e8f9f7 289 ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\
<> 144:ef7eb2e8f9f7 290 ((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\
<> 144:ef7eb2e8f9f7 291 ((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\
<> 144:ef7eb2e8f9f7 292 ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\
<> 144:ef7eb2e8f9f7 293 ((REQUEST) == HAL_DMA1_CH2_ADC) ||\
<> 144:ef7eb2e8f9f7 294 ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
<> 144:ef7eb2e8f9f7 295 ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\
<> 144:ef7eb2e8f9f7 296 ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\
<> 144:ef7eb2e8f9f7 297 ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
<> 144:ef7eb2e8f9f7 298 ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\
<> 144:ef7eb2e8f9f7 299 ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\
<> 144:ef7eb2e8f9f7 300 ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\
<> 144:ef7eb2e8f9f7 301 ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\
<> 144:ef7eb2e8f9f7 302 ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\
<> 144:ef7eb2e8f9f7 303 ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\
<> 144:ef7eb2e8f9f7 304 ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\
<> 144:ef7eb2e8f9f7 305 ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\
<> 144:ef7eb2e8f9f7 306 ((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\
<> 144:ef7eb2e8f9f7 307 ((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\
<> 144:ef7eb2e8f9f7 308 ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\
<> 144:ef7eb2e8f9f7 309 ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\
<> 144:ef7eb2e8f9f7 310 ((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\
<> 144:ef7eb2e8f9f7 311 ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\
<> 144:ef7eb2e8f9f7 312 ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\
<> 144:ef7eb2e8f9f7 313 ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\
<> 144:ef7eb2e8f9f7 314 ((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\
<> 144:ef7eb2e8f9f7 315 ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\
<> 144:ef7eb2e8f9f7 316 ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\
<> 144:ef7eb2e8f9f7 317 ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\
<> 144:ef7eb2e8f9f7 318 ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\
<> 144:ef7eb2e8f9f7 319 ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\
<> 144:ef7eb2e8f9f7 320 ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\
<> 144:ef7eb2e8f9f7 321 ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\
<> 144:ef7eb2e8f9f7 322 ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\
<> 144:ef7eb2e8f9f7 323 ((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\
<> 144:ef7eb2e8f9f7 324 ((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\
<> 144:ef7eb2e8f9f7 325 ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\
<> 144:ef7eb2e8f9f7 326 ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\
<> 144:ef7eb2e8f9f7 327 ((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\
<> 144:ef7eb2e8f9f7 328 ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\
<> 144:ef7eb2e8f9f7 329 ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\
<> 144:ef7eb2e8f9f7 330 ((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\
<> 144:ef7eb2e8f9f7 331 ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\
<> 144:ef7eb2e8f9f7 332 ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\
<> 144:ef7eb2e8f9f7 333 ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\
<> 144:ef7eb2e8f9f7 334 ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\
<> 144:ef7eb2e8f9f7 335 ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\
<> 144:ef7eb2e8f9f7 336 ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\
<> 144:ef7eb2e8f9f7 337 ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\
<> 144:ef7eb2e8f9f7 338 ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\
<> 144:ef7eb2e8f9f7 339 ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\
<> 144:ef7eb2e8f9f7 340 ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\
<> 144:ef7eb2e8f9f7 341 ((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\
<> 144:ef7eb2e8f9f7 342 ((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\
<> 144:ef7eb2e8f9f7 343 ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\
<> 144:ef7eb2e8f9f7 344 ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\
<> 144:ef7eb2e8f9f7 345 ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\
<> 144:ef7eb2e8f9f7 346 ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\
<> 144:ef7eb2e8f9f7 347 ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\
<> 144:ef7eb2e8f9f7 348 ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\
<> 144:ef7eb2e8f9f7 349 ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\
<> 144:ef7eb2e8f9f7 350 ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\
<> 144:ef7eb2e8f9f7 351 ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\
<> 144:ef7eb2e8f9f7 352 ((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\
<> 144:ef7eb2e8f9f7 353 ((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\
<> 144:ef7eb2e8f9f7 354 ((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\
<> 144:ef7eb2e8f9f7 355 ((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\
<> 144:ef7eb2e8f9f7 356 ((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\
<> 144:ef7eb2e8f9f7 357 ((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\
<> 144:ef7eb2e8f9f7 358 ((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\
<> 144:ef7eb2e8f9f7 359 ((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\
<> 144:ef7eb2e8f9f7 360 ((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\
<> 144:ef7eb2e8f9f7 361 ((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\
<> 144:ef7eb2e8f9f7 362 ((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\
<> 144:ef7eb2e8f9f7 363 ((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\
<> 144:ef7eb2e8f9f7 364 ((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\
<> 144:ef7eb2e8f9f7 365 ((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\
<> 144:ef7eb2e8f9f7 366 ((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\
<> 144:ef7eb2e8f9f7 367 ((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\
<> 144:ef7eb2e8f9f7 368 ((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\
<> 144:ef7eb2e8f9f7 369 ((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\
<> 144:ef7eb2e8f9f7 370 ((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\
<> 144:ef7eb2e8f9f7 371 ((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\
<> 144:ef7eb2e8f9f7 372 ((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\
<> 144:ef7eb2e8f9f7 373 ((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\
<> 144:ef7eb2e8f9f7 374 ((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\
<> 144:ef7eb2e8f9f7 375 ((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\
<> 144:ef7eb2e8f9f7 376 ((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\
<> 144:ef7eb2e8f9f7 377 ((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\
<> 144:ef7eb2e8f9f7 378 ((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\
<> 144:ef7eb2e8f9f7 379 ((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\
<> 144:ef7eb2e8f9f7 380 ((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\
<> 144:ef7eb2e8f9f7 381 ((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\
<> 144:ef7eb2e8f9f7 382 ((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\
<> 144:ef7eb2e8f9f7 383 ((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\
<> 144:ef7eb2e8f9f7 384 ((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\
<> 144:ef7eb2e8f9f7 385 ((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\
<> 144:ef7eb2e8f9f7 386 ((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\
<> 144:ef7eb2e8f9f7 387 ((REQUEST) == HAL_DMA1_CH7_USART8_TX))
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 #define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\
<> 144:ef7eb2e8f9f7 390 ((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\
<> 144:ef7eb2e8f9f7 391 ((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\
<> 144:ef7eb2e8f9f7 392 ((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\
<> 144:ef7eb2e8f9f7 393 ((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\
<> 144:ef7eb2e8f9f7 394 ((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\
<> 144:ef7eb2e8f9f7 395 ((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\
<> 144:ef7eb2e8f9f7 396 ((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\
<> 144:ef7eb2e8f9f7 397 ((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\
<> 144:ef7eb2e8f9f7 398 ((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\
<> 144:ef7eb2e8f9f7 399 ((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\
<> 144:ef7eb2e8f9f7 400 ((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\
<> 144:ef7eb2e8f9f7 401 ((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\
<> 144:ef7eb2e8f9f7 402 ((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\
<> 144:ef7eb2e8f9f7 403 ((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\
<> 144:ef7eb2e8f9f7 404 ((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\
<> 144:ef7eb2e8f9f7 405 ((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\
<> 144:ef7eb2e8f9f7 406 ((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\
<> 144:ef7eb2e8f9f7 407 ((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\
<> 144:ef7eb2e8f9f7 408 ((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\
<> 144:ef7eb2e8f9f7 409 ((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\
<> 144:ef7eb2e8f9f7 410 ((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\
<> 144:ef7eb2e8f9f7 411 ((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\
<> 144:ef7eb2e8f9f7 412 ((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\
<> 144:ef7eb2e8f9f7 413 ((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\
<> 144:ef7eb2e8f9f7 414 ((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\
<> 144:ef7eb2e8f9f7 415 ((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\
<> 144:ef7eb2e8f9f7 416 ((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\
<> 144:ef7eb2e8f9f7 417 ((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\
<> 144:ef7eb2e8f9f7 418 ((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\
<> 144:ef7eb2e8f9f7 419 ((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\
<> 144:ef7eb2e8f9f7 420 ((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\
<> 144:ef7eb2e8f9f7 421 ((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\
<> 144:ef7eb2e8f9f7 422 ((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\
<> 144:ef7eb2e8f9f7 423 ((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\
<> 144:ef7eb2e8f9f7 424 ((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\
<> 144:ef7eb2e8f9f7 425 ((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\
<> 144:ef7eb2e8f9f7 426 ((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\
<> 144:ef7eb2e8f9f7 427 ((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\
<> 144:ef7eb2e8f9f7 428 ((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\
<> 144:ef7eb2e8f9f7 429 ((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\
<> 144:ef7eb2e8f9f7 430 ((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\
<> 144:ef7eb2e8f9f7 431 ((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\
<> 144:ef7eb2e8f9f7 432 ((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\
<> 144:ef7eb2e8f9f7 433 ((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\
<> 144:ef7eb2e8f9f7 434 ((REQUEST) == HAL_DMA2_CH5_ADC) ||\
<> 144:ef7eb2e8f9f7 435 ((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\
<> 144:ef7eb2e8f9f7 436 ((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\
<> 144:ef7eb2e8f9f7 437 ((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\
<> 144:ef7eb2e8f9f7 438 ((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\
<> 144:ef7eb2e8f9f7 439 ((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\
<> 144:ef7eb2e8f9f7 440 ((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\
<> 144:ef7eb2e8f9f7 441 ((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\
<> 144:ef7eb2e8f9f7 442 ((REQUEST) == HAL_DMA2_CH5_USART8_TX ))
<> 144:ef7eb2e8f9f7 443 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 #if defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 446 #define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
<> 144:ef7eb2e8f9f7 447 ((REQUEST) == HAL_DMA1_CH1_ADC) ||\
<> 144:ef7eb2e8f9f7 448 ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
<> 144:ef7eb2e8f9f7 449 ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\
<> 144:ef7eb2e8f9f7 450 ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\
<> 144:ef7eb2e8f9f7 451 ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\
<> 144:ef7eb2e8f9f7 452 ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\
<> 144:ef7eb2e8f9f7 453 ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\
<> 144:ef7eb2e8f9f7 454 ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\
<> 144:ef7eb2e8f9f7 455 ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\
<> 144:ef7eb2e8f9f7 456 ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\
<> 144:ef7eb2e8f9f7 457 ((REQUEST) == HAL_DMA1_CH2_ADC) ||\
<> 144:ef7eb2e8f9f7 458 ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
<> 144:ef7eb2e8f9f7 459 ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\
<> 144:ef7eb2e8f9f7 460 ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\
<> 144:ef7eb2e8f9f7 461 ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
<> 144:ef7eb2e8f9f7 462 ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\
<> 144:ef7eb2e8f9f7 463 ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\
<> 144:ef7eb2e8f9f7 464 ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\
<> 144:ef7eb2e8f9f7 465 ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\
<> 144:ef7eb2e8f9f7 466 ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\
<> 144:ef7eb2e8f9f7 467 ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\
<> 144:ef7eb2e8f9f7 468 ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\
<> 144:ef7eb2e8f9f7 469 ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\
<> 144:ef7eb2e8f9f7 470 ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\
<> 144:ef7eb2e8f9f7 471 ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\
<> 144:ef7eb2e8f9f7 472 ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\
<> 144:ef7eb2e8f9f7 473 ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\
<> 144:ef7eb2e8f9f7 474 ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\
<> 144:ef7eb2e8f9f7 475 ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\
<> 144:ef7eb2e8f9f7 476 ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\
<> 144:ef7eb2e8f9f7 477 ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\
<> 144:ef7eb2e8f9f7 478 ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\
<> 144:ef7eb2e8f9f7 479 ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\
<> 144:ef7eb2e8f9f7 480 ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\
<> 144:ef7eb2e8f9f7 481 ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\
<> 144:ef7eb2e8f9f7 482 ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\
<> 144:ef7eb2e8f9f7 483 ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\
<> 144:ef7eb2e8f9f7 484 ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\
<> 144:ef7eb2e8f9f7 485 ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\
<> 144:ef7eb2e8f9f7 486 ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\
<> 144:ef7eb2e8f9f7 487 ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\
<> 144:ef7eb2e8f9f7 488 ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\
<> 144:ef7eb2e8f9f7 489 ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\
<> 144:ef7eb2e8f9f7 490 ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\
<> 144:ef7eb2e8f9f7 491 ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\
<> 144:ef7eb2e8f9f7 492 ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\
<> 144:ef7eb2e8f9f7 493 ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\
<> 144:ef7eb2e8f9f7 494 ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\
<> 144:ef7eb2e8f9f7 495 ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\
<> 144:ef7eb2e8f9f7 496 ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\
<> 144:ef7eb2e8f9f7 497 ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\
<> 144:ef7eb2e8f9f7 498 ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\
<> 144:ef7eb2e8f9f7 499 ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\
<> 144:ef7eb2e8f9f7 500 ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\
<> 144:ef7eb2e8f9f7 501 ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\
<> 144:ef7eb2e8f9f7 502 ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\
<> 144:ef7eb2e8f9f7 503 ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\
<> 144:ef7eb2e8f9f7 504 ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\
<> 144:ef7eb2e8f9f7 505 ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\
<> 144:ef7eb2e8f9f7 506 ((REQUEST) == HAL_DMA1_CH5_USART6_RX))
<> 144:ef7eb2e8f9f7 507 #endif /* STM32F030xC */
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /**
<> 144:ef7eb2e8f9f7 510 * @}
<> 144:ef7eb2e8f9f7 511 */
<> 144:ef7eb2e8f9f7 512 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 /** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros
<> 144:ef7eb2e8f9f7 517 * @{
<> 144:ef7eb2e8f9f7 518 */
<> 144:ef7eb2e8f9f7 519 /* Interrupt & Flag management */
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
<> 144:ef7eb2e8f9f7 522 /**
<> 144:ef7eb2e8f9f7 523 * @brief Returns the current DMA Channel transfer complete flag.
Anna Bridge 180:96ed750bd169 524 * @param __HANDLE__ DMA handle
<> 144:ef7eb2e8f9f7 525 * @retval The specified transfer complete flag index.
<> 144:ef7eb2e8f9f7 526 */
<> 144:ef7eb2e8f9f7 527 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
<> 144:ef7eb2e8f9f7 528 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
<> 144:ef7eb2e8f9f7 529 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
<> 144:ef7eb2e8f9f7 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
<> 144:ef7eb2e8f9f7 531 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
<> 144:ef7eb2e8f9f7 532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
<> 144:ef7eb2e8f9f7 533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
<> 144:ef7eb2e8f9f7 534 DMA_FLAG_TC7)
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /**
<> 144:ef7eb2e8f9f7 537 * @brief Returns the current DMA Channel half transfer complete flag.
Anna Bridge 180:96ed750bd169 538 * @param __HANDLE__ DMA handle
<> 144:ef7eb2e8f9f7 539 * @retval The specified half transfer complete flag index.
<> 144:ef7eb2e8f9f7 540 */
<> 144:ef7eb2e8f9f7 541 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 542 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
<> 144:ef7eb2e8f9f7 543 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
<> 144:ef7eb2e8f9f7 544 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
<> 144:ef7eb2e8f9f7 545 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
<> 144:ef7eb2e8f9f7 546 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
<> 144:ef7eb2e8f9f7 547 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
<> 144:ef7eb2e8f9f7 548 DMA_FLAG_HT7)
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /**
<> 144:ef7eb2e8f9f7 551 * @brief Returns the current DMA Channel transfer error flag.
Anna Bridge 180:96ed750bd169 552 * @param __HANDLE__ DMA handle
<> 144:ef7eb2e8f9f7 553 * @retval The specified transfer error flag index.
<> 144:ef7eb2e8f9f7 554 */
<> 144:ef7eb2e8f9f7 555 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 556 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
<> 144:ef7eb2e8f9f7 557 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
<> 144:ef7eb2e8f9f7 558 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
<> 144:ef7eb2e8f9f7 559 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
<> 144:ef7eb2e8f9f7 560 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
<> 144:ef7eb2e8f9f7 561 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
<> 144:ef7eb2e8f9f7 562 DMA_FLAG_TE7)
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 /**
<> 144:ef7eb2e8f9f7 565 * @brief Return the current DMA Channel Global interrupt flag.
Anna Bridge 180:96ed750bd169 566 * @param __HANDLE__ DMA handle
<> 144:ef7eb2e8f9f7 567 * @retval The specified transfer error flag index.
<> 144:ef7eb2e8f9f7 568 */
<> 144:ef7eb2e8f9f7 569 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 570 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
<> 144:ef7eb2e8f9f7 571 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
<> 144:ef7eb2e8f9f7 572 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
<> 144:ef7eb2e8f9f7 573 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
<> 144:ef7eb2e8f9f7 574 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
<> 144:ef7eb2e8f9f7 575 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
<> 144:ef7eb2e8f9f7 576 DMA_FLAG_GL7)
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /**
<> 144:ef7eb2e8f9f7 579 * @brief Get the DMA Channel pending flags.
Anna Bridge 180:96ed750bd169 580 * @param __HANDLE__ DMA handle
Anna Bridge 180:96ed750bd169 581 * @param __FLAG__ Get the specified flag.
<> 144:ef7eb2e8f9f7 582 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 583 * @arg DMA_FLAG_TCx: Transfer complete flag
<> 144:ef7eb2e8f9f7 584 * @arg DMA_FLAG_HTx: Half transfer complete flag
<> 144:ef7eb2e8f9f7 585 * @arg DMA_FLAG_TEx: Transfer error flag
<> 144:ef7eb2e8f9f7 586 * Where x can be 1_7 to select the DMA Channel flag.
<> 144:ef7eb2e8f9f7 587 * @retval The state of FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 588 */
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /**
<> 144:ef7eb2e8f9f7 593 * @brief Clears the DMA Channel pending flags.
Anna Bridge 180:96ed750bd169 594 * @param __HANDLE__ DMA handle
Anna Bridge 180:96ed750bd169 595 * @param __FLAG__ specifies the flag to clear.
<> 144:ef7eb2e8f9f7 596 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 597 * @arg DMA_FLAG_TCx: Transfer complete flag
<> 144:ef7eb2e8f9f7 598 * @arg DMA_FLAG_HTx: Half transfer complete flag
<> 144:ef7eb2e8f9f7 599 * @arg DMA_FLAG_TEx: Transfer error flag
<> 144:ef7eb2e8f9f7 600 * Where x can be 1_7 to select the DMA Channel flag.
<> 144:ef7eb2e8f9f7 601 * @retval None
<> 144:ef7eb2e8f9f7 602 */
<> 144:ef7eb2e8f9f7 603 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 #elif defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 606 /**
<> 144:ef7eb2e8f9f7 607 * @brief Returns the current DMA Channel transfer complete flag.
Anna Bridge 180:96ed750bd169 608 * @param __HANDLE__ DMA handle
<> 144:ef7eb2e8f9f7 609 * @retval The specified transfer complete flag index.
<> 144:ef7eb2e8f9f7 610 */
<> 144:ef7eb2e8f9f7 611 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
<> 144:ef7eb2e8f9f7 612 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
<> 144:ef7eb2e8f9f7 613 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
<> 144:ef7eb2e8f9f7 614 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
<> 144:ef7eb2e8f9f7 615 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
<> 144:ef7eb2e8f9f7 616 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
<> 144:ef7eb2e8f9f7 617 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
<> 144:ef7eb2e8f9f7 618 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
<> 144:ef7eb2e8f9f7 619 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
<> 144:ef7eb2e8f9f7 620 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
<> 144:ef7eb2e8f9f7 621 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
<> 144:ef7eb2e8f9f7 622 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
<> 144:ef7eb2e8f9f7 623 DMA_FLAG_TC5)
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /**
<> 144:ef7eb2e8f9f7 626 * @brief Returns the current DMA Channel half transfer complete flag.
Anna Bridge 180:96ed750bd169 627 * @param __HANDLE__ DMA handle
<> 144:ef7eb2e8f9f7 628 * @retval The specified half transfer complete flag index.
<> 144:ef7eb2e8f9f7 629 */
<> 144:ef7eb2e8f9f7 630 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 631 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
<> 144:ef7eb2e8f9f7 632 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
<> 144:ef7eb2e8f9f7 633 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
<> 144:ef7eb2e8f9f7 634 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
<> 144:ef7eb2e8f9f7 635 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
<> 144:ef7eb2e8f9f7 636 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
<> 144:ef7eb2e8f9f7 637 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
<> 144:ef7eb2e8f9f7 638 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
<> 144:ef7eb2e8f9f7 639 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
<> 144:ef7eb2e8f9f7 640 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
<> 144:ef7eb2e8f9f7 641 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
<> 144:ef7eb2e8f9f7 642 DMA_FLAG_HT5)
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 /**
<> 144:ef7eb2e8f9f7 645 * @brief Returns the current DMA Channel transfer error flag.
Anna Bridge 180:96ed750bd169 646 * @param __HANDLE__ DMA handle
<> 144:ef7eb2e8f9f7 647 * @retval The specified transfer error flag index.
<> 144:ef7eb2e8f9f7 648 */
<> 144:ef7eb2e8f9f7 649 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 650 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
<> 144:ef7eb2e8f9f7 651 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
<> 144:ef7eb2e8f9f7 652 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
<> 144:ef7eb2e8f9f7 653 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
<> 144:ef7eb2e8f9f7 654 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
<> 144:ef7eb2e8f9f7 655 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
<> 144:ef7eb2e8f9f7 656 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
<> 144:ef7eb2e8f9f7 657 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
<> 144:ef7eb2e8f9f7 658 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
<> 144:ef7eb2e8f9f7 659 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
<> 144:ef7eb2e8f9f7 660 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
<> 144:ef7eb2e8f9f7 661 DMA_FLAG_TE5)
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /**
<> 144:ef7eb2e8f9f7 664 * @brief Return the current DMA Channel Global interrupt flag.
Anna Bridge 180:96ed750bd169 665 * @param __HANDLE__ DMA handle
<> 144:ef7eb2e8f9f7 666 * @retval The specified transfer error flag index.
<> 144:ef7eb2e8f9f7 667 */
<> 144:ef7eb2e8f9f7 668 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 669 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
<> 144:ef7eb2e8f9f7 670 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
<> 144:ef7eb2e8f9f7 671 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
<> 144:ef7eb2e8f9f7 672 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
<> 144:ef7eb2e8f9f7 673 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
<> 144:ef7eb2e8f9f7 674 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
<> 144:ef7eb2e8f9f7 675 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
<> 144:ef7eb2e8f9f7 676 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
<> 144:ef7eb2e8f9f7 677 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
<> 144:ef7eb2e8f9f7 678 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
<> 144:ef7eb2e8f9f7 679 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
<> 144:ef7eb2e8f9f7 680 DMA_FLAG_GL5)
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 /**
<> 144:ef7eb2e8f9f7 683 * @brief Get the DMA Channel pending flags.
Anna Bridge 180:96ed750bd169 684 * @param __HANDLE__ DMA handle
Anna Bridge 180:96ed750bd169 685 * @param __FLAG__ Get the specified flag.
<> 144:ef7eb2e8f9f7 686 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 687 * @arg DMA_FLAG_TCx: Transfer complete flag
<> 144:ef7eb2e8f9f7 688 * @arg DMA_FLAG_HTx: Half transfer complete flag
<> 144:ef7eb2e8f9f7 689 * @arg DMA_FLAG_TEx: Transfer error flag
<> 144:ef7eb2e8f9f7 690 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
<> 144:ef7eb2e8f9f7 691 * @retval The state of FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 692 */
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
<> 144:ef7eb2e8f9f7 695 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
<> 144:ef7eb2e8f9f7 696 (DMA1->ISR & (__FLAG__)))
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /**
<> 144:ef7eb2e8f9f7 699 * @brief Clears the DMA Channel pending flags.
Anna Bridge 180:96ed750bd169 700 * @param __HANDLE__ DMA handle
Anna Bridge 180:96ed750bd169 701 * @param __FLAG__ specifies the flag to clear.
<> 144:ef7eb2e8f9f7 702 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 703 * @arg DMA_FLAG_TCx: Transfer complete flag
<> 144:ef7eb2e8f9f7 704 * @arg DMA_FLAG_HTx: Half transfer complete flag
<> 144:ef7eb2e8f9f7 705 * @arg DMA_FLAG_TEx: Transfer error flag
<> 144:ef7eb2e8f9f7 706 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
<> 144:ef7eb2e8f9f7 707 * @retval None
<> 144:ef7eb2e8f9f7 708 */
<> 144:ef7eb2e8f9f7 709 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
<> 144:ef7eb2e8f9f7 710 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
<> 144:ef7eb2e8f9f7 711 (DMA1->IFCR = (__FLAG__)))
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 #else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */
<> 144:ef7eb2e8f9f7 714 /**
<> 144:ef7eb2e8f9f7 715 * @brief Returns the current DMA Channel transfer complete flag.
Anna Bridge 180:96ed750bd169 716 * @param __HANDLE__ DMA handle
<> 144:ef7eb2e8f9f7 717 * @retval The specified transfer complete flag index.
<> 144:ef7eb2e8f9f7 718 */
<> 144:ef7eb2e8f9f7 719 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
<> 144:ef7eb2e8f9f7 720 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
<> 144:ef7eb2e8f9f7 721 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
<> 144:ef7eb2e8f9f7 722 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
<> 144:ef7eb2e8f9f7 723 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
<> 144:ef7eb2e8f9f7 724 DMA_FLAG_TC5)
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /**
<> 144:ef7eb2e8f9f7 727 * @brief Returns the current DMA Channel half transfer complete flag.
Anna Bridge 180:96ed750bd169 728 * @param __HANDLE__ DMA handle
<> 144:ef7eb2e8f9f7 729 * @retval The specified half transfer complete flag index.
<> 144:ef7eb2e8f9f7 730 */
<> 144:ef7eb2e8f9f7 731 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 732 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
<> 144:ef7eb2e8f9f7 733 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
<> 144:ef7eb2e8f9f7 734 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
<> 144:ef7eb2e8f9f7 735 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
<> 144:ef7eb2e8f9f7 736 DMA_FLAG_HT5)
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /**
<> 144:ef7eb2e8f9f7 739 * @brief Returns the current DMA Channel transfer error flag.
Anna Bridge 180:96ed750bd169 740 * @param __HANDLE__ DMA handle
<> 144:ef7eb2e8f9f7 741 * @retval The specified transfer error flag index.
<> 144:ef7eb2e8f9f7 742 */
<> 144:ef7eb2e8f9f7 743 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 744 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
<> 144:ef7eb2e8f9f7 745 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
<> 144:ef7eb2e8f9f7 746 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
<> 144:ef7eb2e8f9f7 747 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
<> 144:ef7eb2e8f9f7 748 DMA_FLAG_TE5)
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /**
<> 144:ef7eb2e8f9f7 751 * @brief Return the current DMA Channel Global interrupt flag.
Anna Bridge 180:96ed750bd169 752 * @param __HANDLE__ DMA handle
<> 144:ef7eb2e8f9f7 753 * @retval The specified transfer error flag index.
<> 144:ef7eb2e8f9f7 754 */
<> 144:ef7eb2e8f9f7 755 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
<> 144:ef7eb2e8f9f7 756 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
<> 144:ef7eb2e8f9f7 757 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
<> 144:ef7eb2e8f9f7 758 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
<> 144:ef7eb2e8f9f7 759 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
<> 144:ef7eb2e8f9f7 760 DMA_FLAG_GL5)
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /**
<> 144:ef7eb2e8f9f7 763 * @brief Get the DMA Channel pending flags.
Anna Bridge 180:96ed750bd169 764 * @param __HANDLE__ DMA handle
Anna Bridge 180:96ed750bd169 765 * @param __FLAG__ Get the specified flag.
<> 144:ef7eb2e8f9f7 766 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 767 * @arg DMA_FLAG_TCx: Transfer complete flag
<> 144:ef7eb2e8f9f7 768 * @arg DMA_FLAG_HTx: Half transfer complete flag
<> 144:ef7eb2e8f9f7 769 * @arg DMA_FLAG_TEx: Transfer error flag
<> 144:ef7eb2e8f9f7 770 * Where x can be 1_5 to select the DMA Channel flag.
<> 144:ef7eb2e8f9f7 771 * @retval The state of FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 772 */
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 /**
<> 144:ef7eb2e8f9f7 777 * @brief Clears the DMA Channel pending flags.
Anna Bridge 180:96ed750bd169 778 * @param __HANDLE__ DMA handle
Anna Bridge 180:96ed750bd169 779 * @param __FLAG__ specifies the flag to clear.
<> 144:ef7eb2e8f9f7 780 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 781 * @arg DMA_FLAG_TCx: Transfer complete flag
<> 144:ef7eb2e8f9f7 782 * @arg DMA_FLAG_HTx: Half transfer complete flag
<> 144:ef7eb2e8f9f7 783 * @arg DMA_FLAG_TEx: Transfer error flag
<> 144:ef7eb2e8f9f7 784 * Where x can be 1_5 to select the DMA Channel flag.
<> 144:ef7eb2e8f9f7 785 * @retval None
<> 144:ef7eb2e8f9f7 786 */
<> 144:ef7eb2e8f9f7 787 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 #endif
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 793 #define __HAL_DMA1_REMAP(__REQUEST__) \
<> 144:ef7eb2e8f9f7 794 do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \
<> 156:95d6b41a828b 795 DMA1->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \
<> 156:95d6b41a828b 796 DMA1->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \
<> 144:ef7eb2e8f9f7 797 }while(0)
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 800 #define __HAL_DMA2_REMAP(__REQUEST__) \
<> 144:ef7eb2e8f9f7 801 do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \
<> 156:95d6b41a828b 802 DMA2->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \
<> 156:95d6b41a828b 803 DMA2->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \
<> 144:ef7eb2e8f9f7 804 }while(0)
<> 144:ef7eb2e8f9f7 805 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /**
<> 144:ef7eb2e8f9f7 810 * @}
<> 144:ef7eb2e8f9f7 811 */
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /**
<> 144:ef7eb2e8f9f7 814 * @}
<> 144:ef7eb2e8f9f7 815 */
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /**
<> 144:ef7eb2e8f9f7 818 * @}
<> 144:ef7eb2e8f9f7 819 */
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 822 }
<> 144:ef7eb2e8f9f7 823 #endif
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 #endif /* __STM32F0xx_HAL_DMA_EX_H */
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/