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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_dac_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief DAC HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the extended
<> 144:ef7eb2e8f9f7 7 * functionalities of the DAC peripheral.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 @verbatim
<> 144:ef7eb2e8f9f7 11 ==============================================================================
<> 144:ef7eb2e8f9f7 12 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 13 ==============================================================================
<> 144:ef7eb2e8f9f7 14 [..]
<> 144:ef7eb2e8f9f7 15 (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
<> 144:ef7eb2e8f9f7 16 Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
<> 144:ef7eb2e8f9f7 17 HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
<> 144:ef7eb2e8f9f7 18 (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
<> 144:ef7eb2e8f9f7 19 (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 @endverbatim
<> 144:ef7eb2e8f9f7 22 ******************************************************************************
<> 144:ef7eb2e8f9f7 23 * @attention
<> 144:ef7eb2e8f9f7 24 *
<> 144:ef7eb2e8f9f7 25 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 28 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 29 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 30 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 31 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 32 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 33 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 34 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 35 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 36 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 37 *
<> 144:ef7eb2e8f9f7 38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 39 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 40 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 41 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 42 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 43 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 44 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 45 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 46 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 48 *
<> 144:ef7eb2e8f9f7 49 ******************************************************************************
<> 144:ef7eb2e8f9f7 50 */
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 54 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 57 * @{
<> 144:ef7eb2e8f9f7 58 */
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 #ifdef HAL_DAC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /** @addtogroup DAC
<> 144:ef7eb2e8f9f7 63 * @{
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 #if defined(STM32F051x8) || defined(STM32F058xx) || \
<> 144:ef7eb2e8f9f7 67 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 68 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /** @addtogroup DAC_Private_Functions
<> 144:ef7eb2e8f9f7 71 * @{
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 74 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 75 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 76 /**
<> 144:ef7eb2e8f9f7 77 * @}
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 #endif /* STM32F051x8 STM32F058xx */
<> 144:ef7eb2e8f9f7 81 /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 82 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 85 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /** @addtogroup DAC_Private_Functions
<> 144:ef7eb2e8f9f7 88 * @{
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
<> 144:ef7eb2e8f9f7 92 /* are set by HAL_DAC_Start_DMA */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 95 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 96 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 97 /**
<> 144:ef7eb2e8f9f7 98 * @}
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 #endif /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 102 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /** @addtogroup DAC_Exported_Functions
<> 144:ef7eb2e8f9f7 105 * @{
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /** @addtogroup DAC_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 109 * @{
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 113 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /**
<> 144:ef7eb2e8f9f7 116 * @brief Configures the selected DAC channel.
Anna Bridge 180:96ed750bd169 117 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 118 * the configuration information for the specified DAC.
Anna Bridge 180:96ed750bd169 119 * @param sConfig DAC configuration structure.
Anna Bridge 180:96ed750bd169 120 * @param Channel The selected DAC channel.
<> 144:ef7eb2e8f9f7 121 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 122 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 123 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 124 * @retval HAL status
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 127 {
<> 156:95d6b41a828b 128 uint32_t tmpreg1 = 0U, tmpreg2 = 0U;
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /* Check the DAC parameters */
<> 144:ef7eb2e8f9f7 131 assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
<> 144:ef7eb2e8f9f7 132 assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
<> 144:ef7eb2e8f9f7 133 assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
<> 144:ef7eb2e8f9f7 134 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /* Process locked */
<> 144:ef7eb2e8f9f7 137 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /* Change DAC state */
<> 144:ef7eb2e8f9f7 140 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /* Get the DAC CR value */
<> 144:ef7eb2e8f9f7 143 tmpreg1 = hdac->Instance->CR;
<> 144:ef7eb2e8f9f7 144 /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
<> 144:ef7eb2e8f9f7 145 tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
<> 144:ef7eb2e8f9f7 146 /* Configure for the selected DAC channel: buffer output, trigger */
<> 144:ef7eb2e8f9f7 147 /* Set TSELx and TENx bits according to DAC_Trigger value */
<> 144:ef7eb2e8f9f7 148 /* Set BOFFx bit according to DAC_OutputBuffer value */
<> 144:ef7eb2e8f9f7 149 tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
<> 144:ef7eb2e8f9f7 150 /* Calculate CR register value depending on DAC_Channel */
<> 144:ef7eb2e8f9f7 151 tmpreg1 |= tmpreg2 << Channel;
<> 144:ef7eb2e8f9f7 152 /* Write to DAC CR */
<> 144:ef7eb2e8f9f7 153 hdac->Instance->CR = tmpreg1;
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /* Change DAC state */
<> 144:ef7eb2e8f9f7 156 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /* Process unlocked */
<> 144:ef7eb2e8f9f7 159 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /* Return function status */
<> 144:ef7eb2e8f9f7 162 return HAL_OK;
<> 144:ef7eb2e8f9f7 163 }
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 #endif /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 166 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 #if defined (STM32F051x8) || defined (STM32F058xx)
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /**
<> 144:ef7eb2e8f9f7 171 * @brief Configures the selected DAC channel.
Anna Bridge 180:96ed750bd169 172 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 173 * the configuration information for the specified DAC.
Anna Bridge 180:96ed750bd169 174 * @param sConfig DAC configuration structure.
Anna Bridge 180:96ed750bd169 175 * @param Channel The selected DAC channel.
<> 144:ef7eb2e8f9f7 176 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 177 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 178 * @retval HAL status
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 181 {
<> 156:95d6b41a828b 182 uint32_t tmpreg1 = 0U, tmpreg2 = 0U;
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /* Check the DAC parameters */
<> 144:ef7eb2e8f9f7 185 assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
<> 144:ef7eb2e8f9f7 186 assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
<> 144:ef7eb2e8f9f7 187 assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
<> 144:ef7eb2e8f9f7 188 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /* Process locked */
<> 144:ef7eb2e8f9f7 191 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /* Change DAC state */
<> 144:ef7eb2e8f9f7 194 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /* Get the DAC CR value */
<> 144:ef7eb2e8f9f7 197 tmpreg1 = hdac->Instance->CR;
<> 144:ef7eb2e8f9f7 198 /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
<> 144:ef7eb2e8f9f7 199 tmpreg1 &= ~(((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
<> 144:ef7eb2e8f9f7 200 /* Configure for the selected DAC channel: buffer output, trigger */
<> 144:ef7eb2e8f9f7 201 /* Set TSELx and TENx bits according to DAC_Trigger value */
<> 144:ef7eb2e8f9f7 202 /* Set BOFFx bit according to DAC_OutputBuffer value */
<> 144:ef7eb2e8f9f7 203 tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
<> 144:ef7eb2e8f9f7 204 /* Calculate CR register value depending on DAC_Channel */
<> 144:ef7eb2e8f9f7 205 tmpreg1 |= tmpreg2 << Channel;
<> 144:ef7eb2e8f9f7 206 /* Write to DAC CR */
<> 144:ef7eb2e8f9f7 207 hdac->Instance->CR = tmpreg1;
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* Change DAC state */
<> 144:ef7eb2e8f9f7 210 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /* Process unlocked */
<> 144:ef7eb2e8f9f7 213 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /* Return function status */
<> 144:ef7eb2e8f9f7 216 return HAL_OK;
<> 144:ef7eb2e8f9f7 217 }
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 #endif /* STM32F051x8 STM32F058xx */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 222 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 223 /* DAC 1 has 2 channels 1 & 2 */
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /**
<> 144:ef7eb2e8f9f7 226 * @brief Returns the last data output value of the selected DAC channel.
Anna Bridge 180:96ed750bd169 227 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 228 * the configuration information for the specified DAC.
Anna Bridge 180:96ed750bd169 229 * @param Channel The selected DAC channel.
<> 144:ef7eb2e8f9f7 230 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 231 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 232 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 233 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 236 {
<> 144:ef7eb2e8f9f7 237 /* Check the parameters */
<> 144:ef7eb2e8f9f7 238 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 241 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 242 {
<> 144:ef7eb2e8f9f7 243 return hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245 else
<> 144:ef7eb2e8f9f7 246 {
<> 144:ef7eb2e8f9f7 247 return hdac->Instance->DOR2;
<> 144:ef7eb2e8f9f7 248 }
<> 144:ef7eb2e8f9f7 249 }
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 #endif /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 252 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 #if defined (STM32F051x8) || defined (STM32F058xx)
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* DAC 1 has 1 channels */
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /**
<> 144:ef7eb2e8f9f7 259 * @brief Returns the last data output value of the selected DAC channel.
Anna Bridge 180:96ed750bd169 260 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 261 * the configuration information for the specified DAC.
Anna Bridge 180:96ed750bd169 262 * @param Channel The selected DAC channel.
<> 144:ef7eb2e8f9f7 263 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 264 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 265 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 268 {
<> 144:ef7eb2e8f9f7 269 /* Check the parameters */
<> 144:ef7eb2e8f9f7 270 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 273 return hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 #endif /* STM32F051x8 STM32F058xx */
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /**
<> 144:ef7eb2e8f9f7 281 * @}
<> 144:ef7eb2e8f9f7 282 */
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /** @addtogroup DAC_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 285 * @{
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 289 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /**
<> 144:ef7eb2e8f9f7 292 * @brief Enables DAC and starts conversion of channel.
Anna Bridge 180:96ed750bd169 293 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 294 * the configuration information for the specified DAC.
Anna Bridge 180:96ed750bd169 295 * @param Channel The selected DAC channel.
<> 144:ef7eb2e8f9f7 296 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 297 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 298 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 299 * @retval HAL status
<> 144:ef7eb2e8f9f7 300 */
<> 144:ef7eb2e8f9f7 301 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 /* Check the parameters */
<> 144:ef7eb2e8f9f7 304 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /* Process locked */
<> 144:ef7eb2e8f9f7 307 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /* Change DAC state */
<> 144:ef7eb2e8f9f7 310 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 313 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 316 {
<> 144:ef7eb2e8f9f7 317 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 318 if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
<> 144:ef7eb2e8f9f7 319 {
<> 144:ef7eb2e8f9f7 320 /* Enable the selected DAC software conversion */
<> 144:ef7eb2e8f9f7 321 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
<> 144:ef7eb2e8f9f7 322 }
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324 else
<> 144:ef7eb2e8f9f7 325 {
<> 144:ef7eb2e8f9f7 326 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 327 if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2))
<> 144:ef7eb2e8f9f7 328 {
<> 144:ef7eb2e8f9f7 329 /* Enable the selected DAC software conversion*/
<> 144:ef7eb2e8f9f7 330 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
<> 144:ef7eb2e8f9f7 331 }
<> 144:ef7eb2e8f9f7 332 }
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Change DAC state */
<> 144:ef7eb2e8f9f7 335 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /* Process unlocked */
<> 144:ef7eb2e8f9f7 338 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /* Return function status */
<> 144:ef7eb2e8f9f7 341 return HAL_OK;
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /**
<> 144:ef7eb2e8f9f7 345 * @brief Enables DAC and starts conversion of channel.
Anna Bridge 180:96ed750bd169 346 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 347 * the configuration information for the specified DAC.
Anna Bridge 180:96ed750bd169 348 * @param Channel The selected DAC channel.
<> 144:ef7eb2e8f9f7 349 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 350 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 351 * @arg DAC_CHANNEL_2: DAC Channel2 selected
Anna Bridge 180:96ed750bd169 352 * @param pData The destination peripheral Buffer address.
Anna Bridge 180:96ed750bd169 353 * @param Length The length of data to be transferred from memory to DAC peripheral
Anna Bridge 180:96ed750bd169 354 * @param Alignment Specifies the data alignment for DAC channel.
<> 144:ef7eb2e8f9f7 355 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 356 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 357 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 358 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 359 * @retval HAL status
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
<> 144:ef7eb2e8f9f7 362 {
<> 156:95d6b41a828b 363 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /* Check the parameters */
<> 144:ef7eb2e8f9f7 366 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 367 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* Process locked */
<> 144:ef7eb2e8f9f7 370 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /* Change DAC state */
<> 144:ef7eb2e8f9f7 373 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 376 {
<> 144:ef7eb2e8f9f7 377 /* Set the DMA transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 378 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /* Set the DMA half transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 381 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /* Set the DMA error callback for channel1 */
<> 144:ef7eb2e8f9f7 384 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /* Enable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 387 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /* Case of use of channel 1 */
<> 144:ef7eb2e8f9f7 390 switch(Alignment)
<> 144:ef7eb2e8f9f7 391 {
<> 144:ef7eb2e8f9f7 392 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 393 /* Get DHR12R1 address */
<> 144:ef7eb2e8f9f7 394 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
<> 144:ef7eb2e8f9f7 395 break;
<> 144:ef7eb2e8f9f7 396 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 397 /* Get DHR12L1 address */
<> 144:ef7eb2e8f9f7 398 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
<> 144:ef7eb2e8f9f7 399 break;
<> 144:ef7eb2e8f9f7 400 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 401 /* Get DHR8R1 address */
<> 144:ef7eb2e8f9f7 402 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
<> 144:ef7eb2e8f9f7 403 break;
<> 144:ef7eb2e8f9f7 404 default:
<> 144:ef7eb2e8f9f7 405 break;
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407 }
<> 144:ef7eb2e8f9f7 408 else
<> 144:ef7eb2e8f9f7 409 {
<> 144:ef7eb2e8f9f7 410 /* Set the DMA transfer complete callback for channel2 */
<> 144:ef7eb2e8f9f7 411 hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /* Set the DMA half transfer complete callback for channel2 */
<> 144:ef7eb2e8f9f7 414 hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /* Set the DMA error callback for channel2 */
<> 144:ef7eb2e8f9f7 417 hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Enable the selected DAC channel2 DMA request */
<> 144:ef7eb2e8f9f7 420 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* Case of use of channel 2 */
<> 144:ef7eb2e8f9f7 423 switch(Alignment)
<> 144:ef7eb2e8f9f7 424 {
<> 144:ef7eb2e8f9f7 425 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 426 /* Get DHR12R2 address */
<> 144:ef7eb2e8f9f7 427 tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
<> 144:ef7eb2e8f9f7 428 break;
<> 144:ef7eb2e8f9f7 429 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 430 /* Get DHR12L2 address */
<> 144:ef7eb2e8f9f7 431 tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
<> 144:ef7eb2e8f9f7 432 break;
<> 144:ef7eb2e8f9f7 433 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 434 /* Get DHR8R2 address */
<> 144:ef7eb2e8f9f7 435 tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
<> 144:ef7eb2e8f9f7 436 break;
<> 144:ef7eb2e8f9f7 437 default:
<> 144:ef7eb2e8f9f7 438 break;
<> 144:ef7eb2e8f9f7 439 }
<> 144:ef7eb2e8f9f7 440 }
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 443 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 444 {
<> 144:ef7eb2e8f9f7 445 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 446 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 449 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 450 }
<> 144:ef7eb2e8f9f7 451 else
<> 144:ef7eb2e8f9f7 452 {
<> 144:ef7eb2e8f9f7 453 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 454 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 457 HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 458 }
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 461 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 464 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* Return function status */
<> 144:ef7eb2e8f9f7 467 return HAL_OK;
<> 144:ef7eb2e8f9f7 468 }
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 #endif /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 473 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 #if defined (STM32F051x8) || defined (STM32F058xx)
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 478 {
<> 144:ef7eb2e8f9f7 479 /* Check the parameters */
<> 144:ef7eb2e8f9f7 480 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /* Process locked */
<> 144:ef7eb2e8f9f7 483 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /* Change DAC state */
<> 144:ef7eb2e8f9f7 486 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 489 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 492 {
<> 144:ef7eb2e8f9f7 493 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 494 if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
<> 144:ef7eb2e8f9f7 495 {
<> 144:ef7eb2e8f9f7 496 /* Enable the selected DAC software conversion */
<> 144:ef7eb2e8f9f7 497 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
<> 144:ef7eb2e8f9f7 498 }
<> 144:ef7eb2e8f9f7 499 }
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /* Change DAC state */
<> 144:ef7eb2e8f9f7 502 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /* Process unlocked */
<> 144:ef7eb2e8f9f7 505 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /* Return function status */
<> 144:ef7eb2e8f9f7 508 return HAL_OK;
<> 144:ef7eb2e8f9f7 509 }
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /**
<> 144:ef7eb2e8f9f7 512 * @brief Enables DAC and starts conversion of channel.
Anna Bridge 180:96ed750bd169 513 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 514 * the configuration information for the specified DAC.
Anna Bridge 180:96ed750bd169 515 * @param Channel The selected DAC channel.
<> 144:ef7eb2e8f9f7 516 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 517 * @arg DAC_CHANNEL_1: DAC Channel1 selected
Anna Bridge 180:96ed750bd169 518 * @param pData The destination peripheral Buffer address.
Anna Bridge 180:96ed750bd169 519 * @param Length The length of data to be transferred from memory to DAC peripheral
Anna Bridge 180:96ed750bd169 520 * @param Alignment Specifies the data alignment for DAC channel.
<> 144:ef7eb2e8f9f7 521 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 522 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 523 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 524 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 525 * @retval HAL status
<> 144:ef7eb2e8f9f7 526 */
<> 144:ef7eb2e8f9f7 527 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
<> 144:ef7eb2e8f9f7 528 {
<> 156:95d6b41a828b 529 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /* Check the parameters */
<> 144:ef7eb2e8f9f7 532 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 533 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /* Process locked */
<> 144:ef7eb2e8f9f7 536 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /* Change DAC state */
<> 144:ef7eb2e8f9f7 539 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /* Set the DMA transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 542 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /* Set the DMA half transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 545 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /* Set the DMA error callback for channel1 */
<> 144:ef7eb2e8f9f7 548 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /* Enable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 551 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /* Case of use of channel 1 */
<> 144:ef7eb2e8f9f7 554 switch(Alignment)
<> 144:ef7eb2e8f9f7 555 {
<> 144:ef7eb2e8f9f7 556 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 557 /* Get DHR12R1 address */
<> 144:ef7eb2e8f9f7 558 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
<> 144:ef7eb2e8f9f7 559 break;
<> 144:ef7eb2e8f9f7 560 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 561 /* Get DHR12L1 address */
<> 144:ef7eb2e8f9f7 562 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
<> 144:ef7eb2e8f9f7 563 break;
<> 144:ef7eb2e8f9f7 564 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 565 /* Get DHR8R1 address */
<> 144:ef7eb2e8f9f7 566 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
<> 144:ef7eb2e8f9f7 567 break;
<> 144:ef7eb2e8f9f7 568 default:
<> 144:ef7eb2e8f9f7 569 break;
<> 144:ef7eb2e8f9f7 570 }
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 573 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 574 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 577 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 580 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 583 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 586 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 589 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /* Return function status */
<> 144:ef7eb2e8f9f7 592 return HAL_OK;
<> 144:ef7eb2e8f9f7 593 }
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 #endif /* STM32F051x8 STM32F058xx */
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 598 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 599 /* DAC channel 2 is available on top of DAC channel 1 */
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /**
<> 144:ef7eb2e8f9f7 602 * @brief Handles DAC interrupt request
Anna Bridge 180:96ed750bd169 603 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 604 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 605 * @retval None
<> 144:ef7eb2e8f9f7 606 */
<> 144:ef7eb2e8f9f7 607 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 608 {
<> 144:ef7eb2e8f9f7 609 if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
<> 144:ef7eb2e8f9f7 610 {
<> 144:ef7eb2e8f9f7 611 /* Check underrun channel 1 flag */
<> 144:ef7eb2e8f9f7 612 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
<> 144:ef7eb2e8f9f7 613 {
<> 144:ef7eb2e8f9f7 614 /* Change DAC state to error state */
<> 144:ef7eb2e8f9f7 615 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 /* Set DAC error code to channel1 DMA underrun error */
<> 144:ef7eb2e8f9f7 618 hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /* Clear the underrun flag */
<> 144:ef7eb2e8f9f7 621 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /* Disable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 624 hdac->Instance->CR &= ~DAC_CR_DMAEN1;
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 /* Error callback */
<> 144:ef7eb2e8f9f7 627 HAL_DAC_DMAUnderrunCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 628 }
<> 144:ef7eb2e8f9f7 629 }
<> 144:ef7eb2e8f9f7 630 if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
<> 144:ef7eb2e8f9f7 631 {
<> 144:ef7eb2e8f9f7 632 /* Check underrun channel 2 flag */
<> 144:ef7eb2e8f9f7 633 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
<> 144:ef7eb2e8f9f7 634 {
<> 144:ef7eb2e8f9f7 635 /* Change DAC state to error state */
<> 144:ef7eb2e8f9f7 636 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 /* Set DAC error code to channel2 DMA underrun error */
<> 144:ef7eb2e8f9f7 639 hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /* Clear the underrun flag */
<> 144:ef7eb2e8f9f7 642 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 /* Disable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 645 hdac->Instance->CR &= ~DAC_CR_DMAEN2;
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /* Error callback */
<> 144:ef7eb2e8f9f7 648 HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 649 }
<> 144:ef7eb2e8f9f7 650 }
<> 144:ef7eb2e8f9f7 651 }
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 #endif /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 654 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 #if defined (STM32F051x8) || defined (STM32F058xx)
<> 144:ef7eb2e8f9f7 657 /* DAC channel 2 is NOT available. Only DAC channel 1 is available */
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /**
<> 144:ef7eb2e8f9f7 660 * @brief Handles DAC interrupt request
Anna Bridge 180:96ed750bd169 661 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 662 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 663 * @retval None
<> 144:ef7eb2e8f9f7 664 */
<> 144:ef7eb2e8f9f7 665 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 666 {
<> 144:ef7eb2e8f9f7 667 if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
<> 144:ef7eb2e8f9f7 668 {
<> 144:ef7eb2e8f9f7 669 /* Check Overrun flag */
<> 144:ef7eb2e8f9f7 670 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
<> 144:ef7eb2e8f9f7 671 {
<> 144:ef7eb2e8f9f7 672 /* Change DAC state to error state */
<> 144:ef7eb2e8f9f7 673 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /* Set DAC error code to chanel1 DMA underrun error */
<> 144:ef7eb2e8f9f7 676 hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /* Clear the underrun flag */
<> 144:ef7eb2e8f9f7 679 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /* Disable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 682 hdac->Instance->CR &= ~DAC_CR_DMAEN1;
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /* Error callback */
<> 144:ef7eb2e8f9f7 685 HAL_DAC_DMAUnderrunCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 686 }
<> 144:ef7eb2e8f9f7 687 }
<> 144:ef7eb2e8f9f7 688 }
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 #endif /* STM32F051x8 STM32F058xx */
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 /**
<> 144:ef7eb2e8f9f7 693 * @}
<> 144:ef7eb2e8f9f7 694 */
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /**
<> 144:ef7eb2e8f9f7 697 * @}
<> 144:ef7eb2e8f9f7 698 */
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 #if defined(STM32F051x8) || defined(STM32F058xx) || \
<> 144:ef7eb2e8f9f7 701 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 702 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 /** @addtogroup DAC_Private_Functions
<> 144:ef7eb2e8f9f7 705 * @{
<> 144:ef7eb2e8f9f7 706 */
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /**
<> 144:ef7eb2e8f9f7 709 * @brief DMA conversion complete callback.
Anna Bridge 180:96ed750bd169 710 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 711 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 712 * @retval None
<> 144:ef7eb2e8f9f7 713 */
<> 144:ef7eb2e8f9f7 714 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 715 {
<> 144:ef7eb2e8f9f7 716 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 HAL_DAC_ConvCpltCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 721 }
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 /**
<> 144:ef7eb2e8f9f7 724 * @brief DMA half transfer complete callback.
Anna Bridge 180:96ed750bd169 725 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 726 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 727 * @retval None
<> 144:ef7eb2e8f9f7 728 */
<> 144:ef7eb2e8f9f7 729 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 732 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 733 HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 734 }
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /**
<> 144:ef7eb2e8f9f7 737 * @brief DMA error callback
Anna Bridge 180:96ed750bd169 738 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 739 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 740 * @retval None
<> 144:ef7eb2e8f9f7 741 */
<> 144:ef7eb2e8f9f7 742 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 743 {
<> 144:ef7eb2e8f9f7 744 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 /* Set DAC error code to DMA error */
<> 144:ef7eb2e8f9f7 747 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 HAL_DAC_ErrorCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 752 }
<> 144:ef7eb2e8f9f7 753 /**
<> 144:ef7eb2e8f9f7 754 * @}
<> 144:ef7eb2e8f9f7 755 */
<> 144:ef7eb2e8f9f7 756 #endif /* STM32F051x8 STM32F058xx */
<> 144:ef7eb2e8f9f7 757 /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 758 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 761 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 /** @addtogroup DAC_Private_Functions
<> 144:ef7eb2e8f9f7 764 * @{
<> 144:ef7eb2e8f9f7 765 */
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /**
<> 144:ef7eb2e8f9f7 768 * @brief DMA conversion complete callback.
Anna Bridge 180:96ed750bd169 769 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 770 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 771 * @retval None
<> 144:ef7eb2e8f9f7 772 */
<> 144:ef7eb2e8f9f7 773 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 774 {
<> 144:ef7eb2e8f9f7 775 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 HAL_DACEx_ConvCpltCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 780 }
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 /**
<> 144:ef7eb2e8f9f7 783 * @brief DMA half transfer complete callback.
Anna Bridge 180:96ed750bd169 784 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 785 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 786 * @retval None
<> 144:ef7eb2e8f9f7 787 */
<> 144:ef7eb2e8f9f7 788 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 789 {
<> 144:ef7eb2e8f9f7 790 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 791 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 792 HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 793 }
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 /**
<> 144:ef7eb2e8f9f7 796 * @brief DMA error callback
Anna Bridge 180:96ed750bd169 797 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 798 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 799 * @retval None
<> 144:ef7eb2e8f9f7 800 */
<> 144:ef7eb2e8f9f7 801 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 802 {
<> 144:ef7eb2e8f9f7 803 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 /* Set DAC error code to DMA error */
<> 144:ef7eb2e8f9f7 806 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 HAL_DACEx_ErrorCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 811 }
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /**
<> 144:ef7eb2e8f9f7 814 * @}
<> 144:ef7eb2e8f9f7 815 */
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 #endif /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 818 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 /**
<> 144:ef7eb2e8f9f7 821 * @}
<> 144:ef7eb2e8f9f7 822 */
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 /** @defgroup DACEx DACEx
<> 144:ef7eb2e8f9f7 825 * @brief DACEx driver module
<> 144:ef7eb2e8f9f7 826 * @{
<> 144:ef7eb2e8f9f7 827 */
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 830 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 831 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 832 /** @defgroup DACEx_Private_Macros DACEx Private Macros
<> 144:ef7eb2e8f9f7 833 * @{
<> 144:ef7eb2e8f9f7 834 */
<> 144:ef7eb2e8f9f7 835 /**
<> 144:ef7eb2e8f9f7 836 * @}
<> 144:ef7eb2e8f9f7 837 */
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 840 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 841 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /** @defgroup DACEx_Exported_Functions DACEx Exported Functions
<> 144:ef7eb2e8f9f7 844 * @{
<> 144:ef7eb2e8f9f7 845 */
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
<> 144:ef7eb2e8f9f7 848 * @brief Extended features functions
<> 144:ef7eb2e8f9f7 849 *
<> 144:ef7eb2e8f9f7 850 @verbatim
<> 144:ef7eb2e8f9f7 851 ==============================================================================
<> 144:ef7eb2e8f9f7 852 ##### Extended features functions #####
<> 144:ef7eb2e8f9f7 853 ==============================================================================
<> 144:ef7eb2e8f9f7 854 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 855 (+) Start conversion.
<> 144:ef7eb2e8f9f7 856 (+) Stop conversion.
<> 144:ef7eb2e8f9f7 857 (+) Start conversion and enable DMA transfer.
<> 144:ef7eb2e8f9f7 858 (+) Stop conversion and disable DMA transfer.
<> 144:ef7eb2e8f9f7 859 (+) Get result of conversion.
<> 144:ef7eb2e8f9f7 860 (+) Get result of dual mode conversion.
<> 144:ef7eb2e8f9f7 861
<> 144:ef7eb2e8f9f7 862 @endverbatim
<> 144:ef7eb2e8f9f7 863 * @{
<> 144:ef7eb2e8f9f7 864 */
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 867 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 /**
<> 144:ef7eb2e8f9f7 870 * @brief Returns the last data output value of the selected DAC channel.
Anna Bridge 180:96ed750bd169 871 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 872 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 873 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 874 */
<> 144:ef7eb2e8f9f7 875 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 876 {
<> 156:95d6b41a828b 877 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 tmp |= hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 /* DAC channel 2 is present in DAC 1 */
<> 156:95d6b41a828b 882 tmp |= hdac->Instance->DOR2 << 16U;
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 885 return tmp;
<> 144:ef7eb2e8f9f7 886 }
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 #endif /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 889 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 #if defined (STM32F051x8) || defined (STM32F058xx)
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 /**
<> 144:ef7eb2e8f9f7 894 * @brief Returns the last data output value of the selected DAC channel.
Anna Bridge 180:96ed750bd169 895 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 896 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 897 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 898 */
<> 144:ef7eb2e8f9f7 899 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 900 {
<> 156:95d6b41a828b 901 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 902
<> 144:ef7eb2e8f9f7 903 tmp |= hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 906 return tmp;
<> 144:ef7eb2e8f9f7 907 }
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 #endif /* STM32F051x8 STM32F058xx */
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 912 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914 /**
<> 144:ef7eb2e8f9f7 915 * @brief Enables or disables the selected DAC channel wave generation.
Anna Bridge 180:96ed750bd169 916 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 917 * the configuration information for the specified DAC.
Anna Bridge 180:96ed750bd169 918 * @param Channel The selected DAC channel.
<> 144:ef7eb2e8f9f7 919 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 920 * DAC_CHANNEL_1 / DAC_CHANNEL_2
Anna Bridge 180:96ed750bd169 921 * @param Amplitude Select max triangle amplitude.
<> 144:ef7eb2e8f9f7 922 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 923 * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
<> 144:ef7eb2e8f9f7 924 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
<> 144:ef7eb2e8f9f7 925 * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
<> 144:ef7eb2e8f9f7 926 * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
<> 144:ef7eb2e8f9f7 927 * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
<> 144:ef7eb2e8f9f7 928 * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
<> 144:ef7eb2e8f9f7 929 * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
<> 144:ef7eb2e8f9f7 930 * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
<> 144:ef7eb2e8f9f7 931 * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
<> 144:ef7eb2e8f9f7 932 * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
<> 144:ef7eb2e8f9f7 933 * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
<> 144:ef7eb2e8f9f7 934 * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
<> 144:ef7eb2e8f9f7 935 * @retval HAL status
<> 144:ef7eb2e8f9f7 936 */
<> 144:ef7eb2e8f9f7 937 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
<> 144:ef7eb2e8f9f7 938 {
<> 144:ef7eb2e8f9f7 939 /* Check the parameters */
<> 144:ef7eb2e8f9f7 940 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 941 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
<> 144:ef7eb2e8f9f7 942
<> 144:ef7eb2e8f9f7 943 /* Process locked */
<> 144:ef7eb2e8f9f7 944 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 945
<> 144:ef7eb2e8f9f7 946 /* Change DAC state */
<> 144:ef7eb2e8f9f7 947 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949 /* Enable the selected wave generation for the selected DAC channel */
<> 144:ef7eb2e8f9f7 950 MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
<> 144:ef7eb2e8f9f7 951
<> 144:ef7eb2e8f9f7 952 /* Change DAC state */
<> 144:ef7eb2e8f9f7 953 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 954
<> 144:ef7eb2e8f9f7 955 /* Process unlocked */
<> 144:ef7eb2e8f9f7 956 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958 /* Return function status */
<> 144:ef7eb2e8f9f7 959 return HAL_OK;
<> 144:ef7eb2e8f9f7 960 }
<> 144:ef7eb2e8f9f7 961
<> 144:ef7eb2e8f9f7 962 /**
<> 144:ef7eb2e8f9f7 963 * @brief Enables or disables the selected DAC channel wave generation.
Anna Bridge 180:96ed750bd169 964 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 965 * the configuration information for the specified DAC.
Anna Bridge 180:96ed750bd169 966 * @param Channel The selected DAC channel.
<> 144:ef7eb2e8f9f7 967 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 968 * DAC_CHANNEL_1 / DAC_CHANNEL_2
Anna Bridge 180:96ed750bd169 969 * @param Amplitude Unmask DAC channel LFSR for noise wave generation.
<> 144:ef7eb2e8f9f7 970 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 971 * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
<> 144:ef7eb2e8f9f7 972 * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
<> 144:ef7eb2e8f9f7 973 * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
<> 144:ef7eb2e8f9f7 974 * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
<> 144:ef7eb2e8f9f7 975 * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
<> 144:ef7eb2e8f9f7 976 * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
<> 144:ef7eb2e8f9f7 977 * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
<> 144:ef7eb2e8f9f7 978 * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
<> 144:ef7eb2e8f9f7 979 * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
<> 144:ef7eb2e8f9f7 980 * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
<> 144:ef7eb2e8f9f7 981 * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
<> 144:ef7eb2e8f9f7 982 * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
<> 144:ef7eb2e8f9f7 983 * @retval HAL status
<> 144:ef7eb2e8f9f7 984 */
<> 144:ef7eb2e8f9f7 985 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
<> 144:ef7eb2e8f9f7 986 {
<> 144:ef7eb2e8f9f7 987 /* Check the parameters */
<> 144:ef7eb2e8f9f7 988 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 989 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
<> 144:ef7eb2e8f9f7 990
<> 144:ef7eb2e8f9f7 991 /* Process locked */
<> 144:ef7eb2e8f9f7 992 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 993
<> 144:ef7eb2e8f9f7 994 /* Change DAC state */
<> 144:ef7eb2e8f9f7 995 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 996
<> 144:ef7eb2e8f9f7 997 /* Enable the selected wave generation for the selected DAC channel */
<> 144:ef7eb2e8f9f7 998 MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
<> 144:ef7eb2e8f9f7 999
<> 144:ef7eb2e8f9f7 1000 /* Change DAC state */
<> 144:ef7eb2e8f9f7 1001 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1004 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006 /* Return function status */
<> 144:ef7eb2e8f9f7 1007 return HAL_OK;
<> 144:ef7eb2e8f9f7 1008 }
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 #endif /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 1011 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /**
<> 144:ef7eb2e8f9f7 1014 * @}
<> 144:ef7eb2e8f9f7 1015 */
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 /**
<> 144:ef7eb2e8f9f7 1018 * @}
<> 144:ef7eb2e8f9f7 1019 */
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 #if defined(STM32F051x8) || defined(STM32F058xx) || \
<> 144:ef7eb2e8f9f7 1022 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 1023 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1024
<> 144:ef7eb2e8f9f7 1025 /** @addtogroup DACEx_Exported_Functions
<> 144:ef7eb2e8f9f7 1026 * @{
<> 144:ef7eb2e8f9f7 1027 */
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 /** @addtogroup DACEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 1030 * @brief Extended features functions
<> 144:ef7eb2e8f9f7 1031 * @{
<> 144:ef7eb2e8f9f7 1032 */
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 /**
<> 144:ef7eb2e8f9f7 1035 * @brief Set the specified data holding register value for dual DAC channel.
Anna Bridge 180:96ed750bd169 1036 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1037 * the configuration information for the specified DAC.
Anna Bridge 180:96ed750bd169 1038 * @param Alignment Specifies the data alignment for dual channel DAC.
<> 144:ef7eb2e8f9f7 1039 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1040 * DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 1041 * DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 1042 * DAC_ALIGN_12B_R: 12bit right data alignment selected
Anna Bridge 180:96ed750bd169 1043 * @param Data1 Data for DAC Channel2 to be loaded in the selected data holding register.
Anna Bridge 180:96ed750bd169 1044 * @param Data2 Data for DAC Channel1 to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 1045 * @note In dual mode, a unique register access is required to write in both
<> 144:ef7eb2e8f9f7 1046 * DAC channels at the same time.
<> 144:ef7eb2e8f9f7 1047 * @retval HAL status
<> 144:ef7eb2e8f9f7 1048 */
<> 144:ef7eb2e8f9f7 1049 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
<> 144:ef7eb2e8f9f7 1050 {
<> 156:95d6b41a828b 1051 uint32_t data = 0U, tmp = 0U;
<> 144:ef7eb2e8f9f7 1052
<> 144:ef7eb2e8f9f7 1053 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1054 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 1055 assert_param(IS_DAC_DATA(Data1));
<> 144:ef7eb2e8f9f7 1056 assert_param(IS_DAC_DATA(Data2));
<> 144:ef7eb2e8f9f7 1057
<> 144:ef7eb2e8f9f7 1058 /* Calculate and set dual DAC data holding register value */
<> 144:ef7eb2e8f9f7 1059 if (Alignment == DAC_ALIGN_8B_R)
<> 144:ef7eb2e8f9f7 1060 {
<> 156:95d6b41a828b 1061 data = ((uint32_t)Data2 << 8U) | Data1;
<> 144:ef7eb2e8f9f7 1062 }
<> 144:ef7eb2e8f9f7 1063 else
<> 144:ef7eb2e8f9f7 1064 {
<> 156:95d6b41a828b 1065 data = ((uint32_t)Data2 << 16U) | Data1;
<> 144:ef7eb2e8f9f7 1066 }
<> 144:ef7eb2e8f9f7 1067
<> 144:ef7eb2e8f9f7 1068 tmp = (uint32_t)hdac->Instance;
<> 144:ef7eb2e8f9f7 1069 tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071 /* Set the dual DAC selected data holding register */
<> 144:ef7eb2e8f9f7 1072 *(__IO uint32_t *)tmp = data;
<> 144:ef7eb2e8f9f7 1073
<> 144:ef7eb2e8f9f7 1074 /* Return function status */
<> 144:ef7eb2e8f9f7 1075 return HAL_OK;
<> 144:ef7eb2e8f9f7 1076 }
<> 144:ef7eb2e8f9f7 1077
<> 144:ef7eb2e8f9f7 1078 /**
<> 144:ef7eb2e8f9f7 1079 * @}
<> 144:ef7eb2e8f9f7 1080 */
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082 /**
<> 144:ef7eb2e8f9f7 1083 * @}
<> 144:ef7eb2e8f9f7 1084 */
<> 144:ef7eb2e8f9f7 1085
<> 144:ef7eb2e8f9f7 1086 #endif /* STM32F051x8 STM32F058xx */
<> 144:ef7eb2e8f9f7 1087 /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 1088 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 1091 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 /** @addtogroup DACEx_Exported_Functions
<> 144:ef7eb2e8f9f7 1094 * @{
<> 144:ef7eb2e8f9f7 1095 */
<> 144:ef7eb2e8f9f7 1096
<> 144:ef7eb2e8f9f7 1097 /** @addtogroup DACEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 1098 * @brief Extended features functions
<> 144:ef7eb2e8f9f7 1099 * @{
<> 144:ef7eb2e8f9f7 1100 */
<> 144:ef7eb2e8f9f7 1101
<> 144:ef7eb2e8f9f7 1102 /**
<> 144:ef7eb2e8f9f7 1103 * @brief Conversion complete callback in non blocking mode for Channel2
Anna Bridge 180:96ed750bd169 1104 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1105 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 1106 * @retval None
<> 144:ef7eb2e8f9f7 1107 */
<> 144:ef7eb2e8f9f7 1108 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 1109 {
<> 144:ef7eb2e8f9f7 1110 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1111 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1114 the HAL_DAC_ConvCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1115 */
<> 144:ef7eb2e8f9f7 1116 }
<> 144:ef7eb2e8f9f7 1117
<> 144:ef7eb2e8f9f7 1118 /**
<> 144:ef7eb2e8f9f7 1119 * @brief Conversion half DMA transfer callback in non blocking mode for Channel2
Anna Bridge 180:96ed750bd169 1120 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1121 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 1122 * @retval None
<> 144:ef7eb2e8f9f7 1123 */
<> 144:ef7eb2e8f9f7 1124 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 1125 {
<> 144:ef7eb2e8f9f7 1126 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1127 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 1128
<> 144:ef7eb2e8f9f7 1129 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1130 the HAL_DAC_ConvHalfCpltCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 1131 */
<> 144:ef7eb2e8f9f7 1132 }
<> 144:ef7eb2e8f9f7 1133
<> 144:ef7eb2e8f9f7 1134 /**
<> 144:ef7eb2e8f9f7 1135 * @brief Error DAC callback for Channel2.
Anna Bridge 180:96ed750bd169 1136 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1137 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 1138 * @retval None
<> 144:ef7eb2e8f9f7 1139 */
<> 144:ef7eb2e8f9f7 1140 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 1141 {
<> 144:ef7eb2e8f9f7 1142 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1143 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 1144
<> 144:ef7eb2e8f9f7 1145 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1146 the HAL_DAC_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1147 */
<> 144:ef7eb2e8f9f7 1148 }
<> 144:ef7eb2e8f9f7 1149
<> 144:ef7eb2e8f9f7 1150 /**
<> 144:ef7eb2e8f9f7 1151 * @brief DMA underrun DAC callback for channel2.
Anna Bridge 180:96ed750bd169 1152 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1153 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 1154 * @retval None
<> 144:ef7eb2e8f9f7 1155 */
<> 144:ef7eb2e8f9f7 1156 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 1157 {
<> 144:ef7eb2e8f9f7 1158 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1159 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1162 the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 1163 */
<> 144:ef7eb2e8f9f7 1164 }
<> 144:ef7eb2e8f9f7 1165
<> 144:ef7eb2e8f9f7 1166 /**
<> 144:ef7eb2e8f9f7 1167 * @}
<> 144:ef7eb2e8f9f7 1168 */
<> 144:ef7eb2e8f9f7 1169
<> 144:ef7eb2e8f9f7 1170 /**
<> 144:ef7eb2e8f9f7 1171 * @}
<> 144:ef7eb2e8f9f7 1172 */
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 #endif /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 1175 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177 /**
<> 144:ef7eb2e8f9f7 1178 * @}
<> 144:ef7eb2e8f9f7 1179 */
<> 144:ef7eb2e8f9f7 1180
<> 144:ef7eb2e8f9f7 1181 #endif /* HAL_DAC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1182
<> 144:ef7eb2e8f9f7 1183 /**
<> 144:ef7eb2e8f9f7 1184 * @}
<> 144:ef7eb2e8f9f7 1185 */
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/