mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cec.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_cec.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of CEC HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F0xx_HAL_CEC_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F0xx_HAL_CEC_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #if defined(STM32F042x6) || defined(STM32F048xx) ||\
<> 144:ef7eb2e8f9f7 45 defined(STM32F051x8) || defined(STM32F058xx) ||\
<> 144:ef7eb2e8f9f7 46 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||\
<> 144:ef7eb2e8f9f7 47 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 48 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 49 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 156:95d6b41a828b 55 /** @addtogroup CEC
<> 144:ef7eb2e8f9f7 56 * @{
<> 156:95d6b41a828b 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /** @defgroup CEC_Exported_Types CEC Exported Types
<> 144:ef7eb2e8f9f7 61 * @{
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /**
<> 144:ef7eb2e8f9f7 65 * @brief CEC Init Structure definition
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67 typedef struct
<> 144:ef7eb2e8f9f7 68 {
<> 144:ef7eb2e8f9f7 69 uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
<> 144:ef7eb2e8f9f7 70 It can be one of @ref CEC_Signal_Free_Time
<> 144:ef7eb2e8f9f7 71 and belongs to the set {0,...,7} where
<> 144:ef7eb2e8f9f7 72 0x0 is the default configuration
<> 144:ef7eb2e8f9f7 73 else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
<> 144:ef7eb2e8f9f7 76 it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
<> 144:ef7eb2e8f9f7 77 or CEC_EXTENDED_TOLERANCE */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
<> 144:ef7eb2e8f9f7 80 CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
<> 144:ef7eb2e8f9f7 81 CEC_RX_STOP_ON_BRE: reception is stopped. */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
<> 144:ef7eb2e8f9f7 84 CEC line upon Bit Rising Error detection.
<> 144:ef7eb2e8f9f7 85 CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
<> 144:ef7eb2e8f9f7 86 CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
<> 144:ef7eb2e8f9f7 89 CEC line upon Long Bit Period Error detection.
<> 144:ef7eb2e8f9f7 90 CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
<> 144:ef7eb2e8f9f7 91 CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
<> 144:ef7eb2e8f9f7 94 upon an error detected on a broadcast message.
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
<> 144:ef7eb2e8f9f7 99 a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
<> 144:ef7eb2e8f9f7 100 and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
<> 144:ef7eb2e8f9f7 101 b) LBPE detection: error-bit generation on the CEC line
<> 144:ef7eb2e8f9f7 102 if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
<> 144:ef7eb2e8f9f7 105 no error-bit generation in case neither a) nor b) are satisfied. Additionally,
<> 144:ef7eb2e8f9f7 106 there is no error-bit generation in case of Short Bit Period Error detection in
<> 144:ef7eb2e8f9f7 107 a broadcast message while LSTN bit is set. */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
<> 144:ef7eb2e8f9f7 110 CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
<> 144:ef7eb2e8f9f7 111 CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
<> 144:ef7eb2e8f9f7 116 own address (OAR). Messages addressed to different destination are ignored.
<> 144:ef7eb2e8f9f7 117 Broadcast messages are always received.
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
<> 144:ef7eb2e8f9f7 120 address (OAR) with positive acknowledge. Messages addressed to different destination
<> 144:ef7eb2e8f9f7 121 are received, but without interfering with the CEC bus: no acknowledge sent. */
<> 144:ef7eb2e8f9f7 122
<> 156:95d6b41a828b 123 uint16_t OwnAddress; /*!< Own addresses configuration
<> 156:95d6b41a828b 124 This parameter can be a value of @ref CEC_OWN_ADDRESS */
<> 156:95d6b41a828b 125
<> 156:95d6b41a828b 126 uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
<> 156:95d6b41a828b 127
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 }CEC_InitTypeDef;
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /**
<> 156:95d6b41a828b 132 * @brief HAL CEC State structures definition
<> 156:95d6b41a828b 133 * @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
<> 156:95d6b41a828b 134 * - gState contains CEC state information related to global Handle management
<> 156:95d6b41a828b 135 * and also information related to Tx operations.
<> 156:95d6b41a828b 136 * gState value coding follow below described bitmap :
<> 156:95d6b41a828b 137 * b7 (not used)
<> 156:95d6b41a828b 138 * x : Should be set to 0
<> 156:95d6b41a828b 139 * b6 Error information
<> 156:95d6b41a828b 140 * 0 : No Error
<> 156:95d6b41a828b 141 * 1 : Error
<> 156:95d6b41a828b 142 * b5 IP initilisation status
<> 156:95d6b41a828b 143 * 0 : Reset (IP not initialized)
<> 156:95d6b41a828b 144 * 1 : Init done (IP initialized. HAL CEC Init function already called)
<> 156:95d6b41a828b 145 * b4-b3 (not used)
<> 156:95d6b41a828b 146 * xx : Should be set to 00
<> 156:95d6b41a828b 147 * b2 Intrinsic process state
<> 156:95d6b41a828b 148 * 0 : Ready
<> 156:95d6b41a828b 149 * 1 : Busy (IP busy with some configuration or internal operations)
<> 156:95d6b41a828b 150 * b1 (not used)
<> 156:95d6b41a828b 151 * x : Should be set to 0
<> 156:95d6b41a828b 152 * b0 Tx state
<> 156:95d6b41a828b 153 * 0 : Ready (no Tx operation ongoing)
<> 156:95d6b41a828b 154 * 1 : Busy (Tx operation ongoing)
<> 156:95d6b41a828b 155 * - RxState contains information related to Rx operations.
<> 156:95d6b41a828b 156 * RxState value coding follow below described bitmap :
<> 156:95d6b41a828b 157 * b7-b6 (not used)
<> 156:95d6b41a828b 158 * xx : Should be set to 00
<> 156:95d6b41a828b 159 * b5 IP initilisation status
<> 156:95d6b41a828b 160 * 0 : Reset (IP not initialized)
<> 156:95d6b41a828b 161 * 1 : Init done (IP initialized)
<> 156:95d6b41a828b 162 * b4-b2 (not used)
<> 156:95d6b41a828b 163 * xxx : Should be set to 000
<> 156:95d6b41a828b 164 * b1 Rx state
<> 156:95d6b41a828b 165 * 0 : Ready (no Rx operation ongoing)
<> 156:95d6b41a828b 166 * 1 : Busy (Rx operation ongoing)
<> 156:95d6b41a828b 167 * b0 (not used)
<> 156:95d6b41a828b 168 * x : Should be set to 0.
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170 typedef enum
<> 144:ef7eb2e8f9f7 171 {
<> 156:95d6b41a828b 172 HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
<> 156:95d6b41a828b 173 Value is allowed for gState and RxState */
<> 156:95d6b41a828b 174 HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
<> 156:95d6b41a828b 175 Value is allowed for gState and RxState */
<> 156:95d6b41a828b 176 HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
<> 156:95d6b41a828b 177 Value is allowed for gState only */
<> 156:95d6b41a828b 178 HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
<> 156:95d6b41a828b 179 Value is allowed for RxState only */
<> 156:95d6b41a828b 180 HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
<> 156:95d6b41a828b 181 Value is allowed for gState only */
<> 156:95d6b41a828b 182 HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
<> 156:95d6b41a828b 183 Value is allowed for gState only */
<> 156:95d6b41a828b 184 HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 185 }HAL_CEC_StateTypeDef;
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /**
<> 144:ef7eb2e8f9f7 188 * @brief CEC handle Structure definition
<> 144:ef7eb2e8f9f7 189 */
<> 144:ef7eb2e8f9f7 190 typedef struct
<> 144:ef7eb2e8f9f7 191 {
<> 156:95d6b41a828b 192 CEC_TypeDef *Instance; /*!< CEC registers base address */
<> 144:ef7eb2e8f9f7 193
<> 156:95d6b41a828b 194 CEC_InitTypeDef Init; /*!< CEC communication parameters */
<> 144:ef7eb2e8f9f7 195
<> 156:95d6b41a828b 196 uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
<> 144:ef7eb2e8f9f7 197
<> 156:95d6b41a828b 198 uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
<> 144:ef7eb2e8f9f7 199
<> 156:95d6b41a828b 200 uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
<> 144:ef7eb2e8f9f7 201
<> 156:95d6b41a828b 202 HAL_LockTypeDef Lock; /*!< Locking object */
<> 156:95d6b41a828b 203
<> 156:95d6b41a828b 204 HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
<> 156:95d6b41a828b 205 and also related to Tx operations.
<> 156:95d6b41a828b 206 This parameter can be a value of @ref HAL_CEC_StateTypeDef */
<> 144:ef7eb2e8f9f7 207
<> 156:95d6b41a828b 208 HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
<> 156:95d6b41a828b 209 This parameter can be a value of @ref HAL_CEC_StateTypeDef */
<> 144:ef7eb2e8f9f7 210
<> 156:95d6b41a828b 211 uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
<> 156:95d6b41a828b 212 in case error is reported */
<> 144:ef7eb2e8f9f7 213 }CEC_HandleTypeDef;
<> 144:ef7eb2e8f9f7 214 /**
<> 144:ef7eb2e8f9f7 215 * @}
<> 144:ef7eb2e8f9f7 216 */
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 219 /** @defgroup CEC_Exported_Constants CEC Exported Constants
<> 144:ef7eb2e8f9f7 220 * @{
<> 144:ef7eb2e8f9f7 221 */
<> 156:95d6b41a828b 222
<> 144:ef7eb2e8f9f7 223 /** @defgroup CEC_Error_Code CEC Error Code
<> 144:ef7eb2e8f9f7 224 * @{
<> 144:ef7eb2e8f9f7 225 */
<> 156:95d6b41a828b 226 #define HAL_CEC_ERROR_NONE (0x00000000U) /*!< no error */
<> 144:ef7eb2e8f9f7 227 #define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
<> 144:ef7eb2e8f9f7 228 #define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
<> 144:ef7eb2e8f9f7 229 #define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
<> 144:ef7eb2e8f9f7 230 #define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
<> 144:ef7eb2e8f9f7 231 #define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
<> 144:ef7eb2e8f9f7 232 #define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
<> 144:ef7eb2e8f9f7 233 #define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
<> 144:ef7eb2e8f9f7 234 #define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
<> 144:ef7eb2e8f9f7 235 #define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
<> 144:ef7eb2e8f9f7 236 /**
<> 144:ef7eb2e8f9f7 237 * @}
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239
<> 156:95d6b41a828b 240 /** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
<> 144:ef7eb2e8f9f7 241 * @{
<> 144:ef7eb2e8f9f7 242 */
<> 156:95d6b41a828b 243 #define CEC_DEFAULT_SFT (0x00000000U)
<> 156:95d6b41a828b 244 #define CEC_0_5_BITPERIOD_SFT (0x00000001U)
<> 156:95d6b41a828b 245 #define CEC_1_5_BITPERIOD_SFT (0x00000002U)
<> 156:95d6b41a828b 246 #define CEC_2_5_BITPERIOD_SFT (0x00000003U)
<> 156:95d6b41a828b 247 #define CEC_3_5_BITPERIOD_SFT (0x00000004U)
<> 156:95d6b41a828b 248 #define CEC_4_5_BITPERIOD_SFT (0x00000005U)
<> 156:95d6b41a828b 249 #define CEC_5_5_BITPERIOD_SFT (0x00000006U)
<> 156:95d6b41a828b 250 #define CEC_6_5_BITPERIOD_SFT (0x00000007U)
<> 144:ef7eb2e8f9f7 251 /**
<> 144:ef7eb2e8f9f7 252 * @}
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254
<> 156:95d6b41a828b 255 /** @defgroup CEC_Tolerance CEC Receiver Tolerance
<> 144:ef7eb2e8f9f7 256 * @{
<> 144:ef7eb2e8f9f7 257 */
<> 156:95d6b41a828b 258 #define CEC_STANDARD_TOLERANCE (0x00000000U)
<> 144:ef7eb2e8f9f7 259 #define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
<> 144:ef7eb2e8f9f7 260 /**
<> 144:ef7eb2e8f9f7 261 * @}
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263
<> 156:95d6b41a828b 264 /** @defgroup CEC_BRERxStop CEC Reception Stop on Error
<> 144:ef7eb2e8f9f7 265 * @{
<> 144:ef7eb2e8f9f7 266 */
<> 156:95d6b41a828b 267 #define CEC_NO_RX_STOP_ON_BRE (0x00000000U)
<> 144:ef7eb2e8f9f7 268 #define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
<> 144:ef7eb2e8f9f7 269 /**
<> 144:ef7eb2e8f9f7 270 * @}
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272
<> 156:95d6b41a828b 273 /** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
<> 144:ef7eb2e8f9f7 274 * @{
<> 144:ef7eb2e8f9f7 275 */
<> 156:95d6b41a828b 276 #define CEC_BRE_ERRORBIT_NO_GENERATION (0x00000000U)
<> 144:ef7eb2e8f9f7 277 #define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @}
<> 144:ef7eb2e8f9f7 280 */
<> 144:ef7eb2e8f9f7 281
<> 156:95d6b41a828b 282 /** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
<> 144:ef7eb2e8f9f7 283 * @{
<> 144:ef7eb2e8f9f7 284 */
<> 156:95d6b41a828b 285 #define CEC_LBPE_ERRORBIT_NO_GENERATION (0x00000000U)
<> 144:ef7eb2e8f9f7 286 #define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
<> 144:ef7eb2e8f9f7 287 /**
<> 144:ef7eb2e8f9f7 288 * @}
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290
<> 156:95d6b41a828b 291 /** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
<> 144:ef7eb2e8f9f7 292 * @{
<> 144:ef7eb2e8f9f7 293 */
<> 156:95d6b41a828b 294 #define CEC_BROADCASTERROR_ERRORBIT_GENERATION (0x00000000U)
<> 144:ef7eb2e8f9f7 295 #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
<> 144:ef7eb2e8f9f7 296 /**
<> 144:ef7eb2e8f9f7 297 * @}
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299
<> 156:95d6b41a828b 300 /** @defgroup CEC_SFT_Option CEC Signal Free Time start option
<> 144:ef7eb2e8f9f7 301 * @{
<> 144:ef7eb2e8f9f7 302 */
<> 156:95d6b41a828b 303 #define CEC_SFT_START_ON_TXSOM (0x00000000U)
<> 144:ef7eb2e8f9f7 304 #define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
<> 144:ef7eb2e8f9f7 305 /**
<> 144:ef7eb2e8f9f7 306 * @}
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308
<> 156:95d6b41a828b 309 /** @defgroup CEC_Listening_Mode CEC Listening mode option
<> 144:ef7eb2e8f9f7 310 * @{
<> 144:ef7eb2e8f9f7 311 */
<> 156:95d6b41a828b 312 #define CEC_REDUCED_LISTENING_MODE (0x00000000U)
<> 144:ef7eb2e8f9f7 313 #define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @}
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317
<> 156:95d6b41a828b 318 /** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
<> 144:ef7eb2e8f9f7 319 * @{
<> 144:ef7eb2e8f9f7 320 */
<> 156:95d6b41a828b 321 #define CEC_CFGR_OAR_LSB_POS (16U)
<> 144:ef7eb2e8f9f7 322 /**
<> 144:ef7eb2e8f9f7 323 * @}
<> 144:ef7eb2e8f9f7 324 */
<> 144:ef7eb2e8f9f7 325
<> 156:95d6b41a828b 326 /** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
<> 144:ef7eb2e8f9f7 327 * @{
<> 144:ef7eb2e8f9f7 328 */
<> 156:95d6b41a828b 329 #define CEC_INITIATOR_LSB_POS (4U)
<> 144:ef7eb2e8f9f7 330 /**
<> 144:ef7eb2e8f9f7 331 * @}
<> 144:ef7eb2e8f9f7 332 */
<> 156:95d6b41a828b 333
<> 156:95d6b41a828b 334 /** @defgroup CEC_OWN_ADDRESS CEC Own Address
<> 156:95d6b41a828b 335 * @{
<> 156:95d6b41a828b 336 */
<> 156:95d6b41a828b 337 #define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
<> 156:95d6b41a828b 338 #define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
<> 156:95d6b41a828b 339 #define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
<> 156:95d6b41a828b 340 #define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
<> 156:95d6b41a828b 341 #define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
<> 156:95d6b41a828b 342 #define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
<> 156:95d6b41a828b 343 #define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
<> 156:95d6b41a828b 344 #define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
<> 156:95d6b41a828b 345 #define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
<> 156:95d6b41a828b 346 #define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
<> 156:95d6b41a828b 347 #define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
<> 156:95d6b41a828b 348 #define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
<> 156:95d6b41a828b 349 #define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
<> 156:95d6b41a828b 350 #define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
<> 156:95d6b41a828b 351 #define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
<> 156:95d6b41a828b 352 #define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
<> 156:95d6b41a828b 353 /**
<> 156:95d6b41a828b 354 * @}
<> 156:95d6b41a828b 355 */
<> 156:95d6b41a828b 356
<> 144:ef7eb2e8f9f7 357 /** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
<> 144:ef7eb2e8f9f7 358 * @{
<> 144:ef7eb2e8f9f7 359 */
<> 144:ef7eb2e8f9f7 360 #define CEC_IT_TXACKE CEC_IER_TXACKEIE
<> 144:ef7eb2e8f9f7 361 #define CEC_IT_TXERR CEC_IER_TXERRIE
<> 144:ef7eb2e8f9f7 362 #define CEC_IT_TXUDR CEC_IER_TXUDRIE
<> 144:ef7eb2e8f9f7 363 #define CEC_IT_TXEND CEC_IER_TXENDIE
<> 144:ef7eb2e8f9f7 364 #define CEC_IT_TXBR CEC_IER_TXBRIE
<> 144:ef7eb2e8f9f7 365 #define CEC_IT_ARBLST CEC_IER_ARBLSTIE
<> 144:ef7eb2e8f9f7 366 #define CEC_IT_RXACKE CEC_IER_RXACKEIE
<> 144:ef7eb2e8f9f7 367 #define CEC_IT_LBPE CEC_IER_LBPEIE
<> 144:ef7eb2e8f9f7 368 #define CEC_IT_SBPE CEC_IER_SBPEIE
<> 144:ef7eb2e8f9f7 369 #define CEC_IT_BRE CEC_IER_BREIE
<> 144:ef7eb2e8f9f7 370 #define CEC_IT_RXOVR CEC_IER_RXOVRIE
<> 144:ef7eb2e8f9f7 371 #define CEC_IT_RXEND CEC_IER_RXENDIE
<> 144:ef7eb2e8f9f7 372 #define CEC_IT_RXBR CEC_IER_RXBRIE
<> 144:ef7eb2e8f9f7 373 /**
<> 144:ef7eb2e8f9f7 374 * @}
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /** @defgroup CEC_Flags_Definitions CEC Flags definition
<> 144:ef7eb2e8f9f7 378 * @{
<> 144:ef7eb2e8f9f7 379 */
<> 144:ef7eb2e8f9f7 380 #define CEC_FLAG_TXACKE CEC_ISR_TXACKE
<> 144:ef7eb2e8f9f7 381 #define CEC_FLAG_TXERR CEC_ISR_TXERR
<> 144:ef7eb2e8f9f7 382 #define CEC_FLAG_TXUDR CEC_ISR_TXUDR
<> 144:ef7eb2e8f9f7 383 #define CEC_FLAG_TXEND CEC_ISR_TXEND
<> 144:ef7eb2e8f9f7 384 #define CEC_FLAG_TXBR CEC_ISR_TXBR
<> 144:ef7eb2e8f9f7 385 #define CEC_FLAG_ARBLST CEC_ISR_ARBLST
<> 144:ef7eb2e8f9f7 386 #define CEC_FLAG_RXACKE CEC_ISR_RXACKE
<> 144:ef7eb2e8f9f7 387 #define CEC_FLAG_LBPE CEC_ISR_LBPE
<> 144:ef7eb2e8f9f7 388 #define CEC_FLAG_SBPE CEC_ISR_SBPE
<> 144:ef7eb2e8f9f7 389 #define CEC_FLAG_BRE CEC_ISR_BRE
<> 144:ef7eb2e8f9f7 390 #define CEC_FLAG_RXOVR CEC_ISR_RXOVR
<> 144:ef7eb2e8f9f7 391 #define CEC_FLAG_RXEND CEC_ISR_RXEND
<> 144:ef7eb2e8f9f7 392 #define CEC_FLAG_RXBR CEC_ISR_RXBR
<> 144:ef7eb2e8f9f7 393 /**
<> 144:ef7eb2e8f9f7 394 * @}
<> 144:ef7eb2e8f9f7 395 */
<> 156:95d6b41a828b 396
<> 156:95d6b41a828b 397 /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
<> 144:ef7eb2e8f9f7 398 * @{
<> 144:ef7eb2e8f9f7 399 */
<> 144:ef7eb2e8f9f7 400 #define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
<> 144:ef7eb2e8f9f7 401 CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
<> 144:ef7eb2e8f9f7 402 /**
<> 144:ef7eb2e8f9f7 403 * @}
<> 144:ef7eb2e8f9f7 404 */
<> 144:ef7eb2e8f9f7 405
<> 156:95d6b41a828b 406 /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
<> 144:ef7eb2e8f9f7 407 * @{
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409 #define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
<> 144:ef7eb2e8f9f7 410 /**
<> 144:ef7eb2e8f9f7 411 * @}
<> 144:ef7eb2e8f9f7 412 */
<> 144:ef7eb2e8f9f7 413
<> 156:95d6b41a828b 414 /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
<> 144:ef7eb2e8f9f7 415 * @{
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417 #define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
<> 144:ef7eb2e8f9f7 418 /**
<> 144:ef7eb2e8f9f7 419 * @}
<> 156:95d6b41a828b 420 */
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /**
<> 144:ef7eb2e8f9f7 423 * @}
<> 144:ef7eb2e8f9f7 424 */
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 427 /** @defgroup CEC_Exported_Macros CEC Exported Macros
<> 144:ef7eb2e8f9f7 428 * @{
<> 144:ef7eb2e8f9f7 429 */
<> 144:ef7eb2e8f9f7 430
<> 156:95d6b41a828b 431 /** @brief Reset CEC handle gstate & RxState
Anna Bridge 180:96ed750bd169 432 * @param __HANDLE__ CEC handle.
<> 144:ef7eb2e8f9f7 433 * @retval None
<> 144:ef7eb2e8f9f7 434 */
<> 156:95d6b41a828b 435 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
<> 156:95d6b41a828b 436 (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
<> 156:95d6b41a828b 437 (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
<> 156:95d6b41a828b 438 } while(0)
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 /** @brief Checks whether or not the specified CEC interrupt flag is set.
Anna Bridge 180:96ed750bd169 441 * @param __HANDLE__ specifies the CEC Handle.
Anna Bridge 180:96ed750bd169 442 * @param __FLAG__ specifies the flag to check.
<> 144:ef7eb2e8f9f7 443 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
<> 144:ef7eb2e8f9f7 444 * @arg CEC_FLAG_TXERR: Tx Error.
<> 144:ef7eb2e8f9f7 445 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
<> 144:ef7eb2e8f9f7 446 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
<> 144:ef7eb2e8f9f7 447 * @arg CEC_FLAG_TXBR: Tx-Byte Request.
<> 144:ef7eb2e8f9f7 448 * @arg CEC_FLAG_ARBLST: Arbitration Lost
<> 144:ef7eb2e8f9f7 449 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
<> 144:ef7eb2e8f9f7 450 * @arg CEC_FLAG_LBPE: Rx Long period Error
<> 144:ef7eb2e8f9f7 451 * @arg CEC_FLAG_SBPE: Rx Short period Error
<> 156:95d6b41a828b 452 * @arg CEC_FLAG_BRE: Rx Bit Rising Error
<> 144:ef7eb2e8f9f7 453 * @arg CEC_FLAG_RXOVR: Rx Overrun.
<> 144:ef7eb2e8f9f7 454 * @arg CEC_FLAG_RXEND: End Of Reception.
<> 156:95d6b41a828b 455 * @arg CEC_FLAG_RXBR: Rx-Byte Received.
<> 156:95d6b41a828b 456 * @retval ITStatus
<> 144:ef7eb2e8f9f7 457 */
<> 144:ef7eb2e8f9f7 458 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /** @brief Clears the interrupt or status flag when raised (write at 1)
Anna Bridge 180:96ed750bd169 461 * @param __HANDLE__ specifies the CEC Handle.
Anna Bridge 180:96ed750bd169 462 * @param __FLAG__ specifies the interrupt/status flag to clear.
<> 144:ef7eb2e8f9f7 463 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 464 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
<> 144:ef7eb2e8f9f7 465 * @arg CEC_FLAG_TXERR: Tx Error.
<> 144:ef7eb2e8f9f7 466 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
<> 144:ef7eb2e8f9f7 467 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
<> 144:ef7eb2e8f9f7 468 * @arg CEC_FLAG_TXBR: Tx-Byte Request.
<> 144:ef7eb2e8f9f7 469 * @arg CEC_FLAG_ARBLST: Arbitration Lost
<> 144:ef7eb2e8f9f7 470 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
<> 144:ef7eb2e8f9f7 471 * @arg CEC_FLAG_LBPE: Rx Long period Error
<> 144:ef7eb2e8f9f7 472 * @arg CEC_FLAG_SBPE: Rx Short period Error
<> 156:95d6b41a828b 473 * @arg CEC_FLAG_BRE: Rx Bit Rising Error
<> 144:ef7eb2e8f9f7 474 * @arg CEC_FLAG_RXOVR: Rx Overrun.
<> 144:ef7eb2e8f9f7 475 * @arg CEC_FLAG_RXEND: End Of Reception.
<> 144:ef7eb2e8f9f7 476 * @arg CEC_FLAG_RXBR: Rx-Byte Received.
<> 144:ef7eb2e8f9f7 477 * @retval none
<> 144:ef7eb2e8f9f7 478 */
<> 144:ef7eb2e8f9f7 479 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /** @brief Enables the specified CEC interrupt.
Anna Bridge 180:96ed750bd169 482 * @param __HANDLE__ specifies the CEC Handle.
Anna Bridge 180:96ed750bd169 483 * @param __INTERRUPT__ specifies the CEC interrupt to enable.
<> 144:ef7eb2e8f9f7 484 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 485 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
<> 144:ef7eb2e8f9f7 486 * @arg CEC_IT_TXERR: Tx Error IT Enable
<> 144:ef7eb2e8f9f7 487 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
<> 144:ef7eb2e8f9f7 488 * @arg CEC_IT_TXEND: End of transmission IT Enable
<> 144:ef7eb2e8f9f7 489 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
<> 144:ef7eb2e8f9f7 490 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
<> 144:ef7eb2e8f9f7 491 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
<> 144:ef7eb2e8f9f7 492 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
<> 144:ef7eb2e8f9f7 493 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
<> 144:ef7eb2e8f9f7 494 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
<> 144:ef7eb2e8f9f7 495 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
<> 144:ef7eb2e8f9f7 496 * @arg CEC_IT_RXEND: End Of Reception IT Enable
<> 144:ef7eb2e8f9f7 497 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
<> 144:ef7eb2e8f9f7 498 * @retval none
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /** @brief Disables the specified CEC interrupt.
Anna Bridge 180:96ed750bd169 503 * @param __HANDLE__ specifies the CEC Handle.
Anna Bridge 180:96ed750bd169 504 * @param __INTERRUPT__ specifies the CEC interrupt to disable.
<> 144:ef7eb2e8f9f7 505 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 506 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
<> 144:ef7eb2e8f9f7 507 * @arg CEC_IT_TXERR: Tx Error IT Enable
<> 144:ef7eb2e8f9f7 508 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
<> 144:ef7eb2e8f9f7 509 * @arg CEC_IT_TXEND: End of transmission IT Enable
<> 144:ef7eb2e8f9f7 510 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
<> 144:ef7eb2e8f9f7 511 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
<> 144:ef7eb2e8f9f7 512 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
<> 144:ef7eb2e8f9f7 513 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
<> 144:ef7eb2e8f9f7 514 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
<> 144:ef7eb2e8f9f7 515 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
<> 144:ef7eb2e8f9f7 516 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
<> 144:ef7eb2e8f9f7 517 * @arg CEC_IT_RXEND: End Of Reception IT Enable
<> 144:ef7eb2e8f9f7 518 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
<> 144:ef7eb2e8f9f7 519 * @retval none
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /** @brief Checks whether or not the specified CEC interrupt is enabled.
Anna Bridge 180:96ed750bd169 524 * @param __HANDLE__ specifies the CEC Handle.
Anna Bridge 180:96ed750bd169 525 * @param __INTERRUPT__ specifies the CEC interrupt to check.
<> 144:ef7eb2e8f9f7 526 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 527 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
<> 144:ef7eb2e8f9f7 528 * @arg CEC_IT_TXERR: Tx Error IT Enable
<> 144:ef7eb2e8f9f7 529 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
<> 144:ef7eb2e8f9f7 530 * @arg CEC_IT_TXEND: End of transmission IT Enable
<> 144:ef7eb2e8f9f7 531 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
<> 144:ef7eb2e8f9f7 532 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
<> 144:ef7eb2e8f9f7 533 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
<> 144:ef7eb2e8f9f7 534 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
<> 144:ef7eb2e8f9f7 535 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
<> 144:ef7eb2e8f9f7 536 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
<> 144:ef7eb2e8f9f7 537 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
<> 144:ef7eb2e8f9f7 538 * @arg CEC_IT_RXEND: End Of Reception IT Enable
<> 144:ef7eb2e8f9f7 539 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
<> 144:ef7eb2e8f9f7 540 * @retval FlagStatus
<> 144:ef7eb2e8f9f7 541 */
<> 144:ef7eb2e8f9f7 542 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /** @brief Enables the CEC device
Anna Bridge 180:96ed750bd169 545 * @param __HANDLE__ specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 546 * @retval none
<> 144:ef7eb2e8f9f7 547 */
<> 144:ef7eb2e8f9f7 548 #define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /** @brief Disables the CEC device
Anna Bridge 180:96ed750bd169 551 * @param __HANDLE__ specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 552 * @retval none
<> 144:ef7eb2e8f9f7 553 */
<> 144:ef7eb2e8f9f7 554 #define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /** @brief Set Transmission Start flag
Anna Bridge 180:96ed750bd169 557 * @param __HANDLE__ specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 558 * @retval none
<> 144:ef7eb2e8f9f7 559 */
<> 144:ef7eb2e8f9f7 560 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /** @brief Set Transmission End flag
Anna Bridge 180:96ed750bd169 563 * @param __HANDLE__ specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 564 * @retval none
<> 144:ef7eb2e8f9f7 565 * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
<> 144:ef7eb2e8f9f7 566 */
<> 144:ef7eb2e8f9f7 567 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /** @brief Get Transmission Start flag
Anna Bridge 180:96ed750bd169 570 * @param __HANDLE__ specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 571 * @retval FlagStatus
<> 144:ef7eb2e8f9f7 572 */
<> 144:ef7eb2e8f9f7 573 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /** @brief Get Transmission End flag
Anna Bridge 180:96ed750bd169 576 * @param __HANDLE__ specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 577 * @retval FlagStatus
<> 144:ef7eb2e8f9f7 578 */
<> 144:ef7eb2e8f9f7 579 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /** @brief Clear OAR register
Anna Bridge 180:96ed750bd169 582 * @param __HANDLE__ specifies the CEC Handle.
<> 144:ef7eb2e8f9f7 583 * @retval none
<> 144:ef7eb2e8f9f7 584 */
<> 144:ef7eb2e8f9f7 585 #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
<> 144:ef7eb2e8f9f7 588 * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
Anna Bridge 180:96ed750bd169 589 * @param __HANDLE__ specifies the CEC Handle.
Anna Bridge 180:96ed750bd169 590 * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
<> 144:ef7eb2e8f9f7 591 * @retval none
<> 144:ef7eb2e8f9f7 592 */
<> 144:ef7eb2e8f9f7 593 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
<> 156:95d6b41a828b 594
<> 144:ef7eb2e8f9f7 595 /**
<> 144:ef7eb2e8f9f7 596 * @}
<> 144:ef7eb2e8f9f7 597 */
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 600 /** @addtogroup CEC_Exported_Functions
<> 144:ef7eb2e8f9f7 601 * @{
<> 144:ef7eb2e8f9f7 602 */
<> 156:95d6b41a828b 603
<> 156:95d6b41a828b 604 /** @addtogroup CEC_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 605 * @{
<> 144:ef7eb2e8f9f7 606 */
<> 144:ef7eb2e8f9f7 607 /* Initialization and de-initialization functions ****************************/
<> 144:ef7eb2e8f9f7 608 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 609 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
<> 156:95d6b41a828b 610 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
<> 144:ef7eb2e8f9f7 611 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 612 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 613 /**
<> 144:ef7eb2e8f9f7 614 * @}
<> 156:95d6b41a828b 615 */
<> 144:ef7eb2e8f9f7 616
<> 156:95d6b41a828b 617 /** @addtogroup CEC_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 618 * @{
<> 156:95d6b41a828b 619 */
<> 144:ef7eb2e8f9f7 620 /* I/O operation functions ***************************************************/
<> 156:95d6b41a828b 621 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
<> 156:95d6b41a828b 622 uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
<> 156:95d6b41a828b 623 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
<> 144:ef7eb2e8f9f7 624 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 625 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
<> 156:95d6b41a828b 626 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
<> 144:ef7eb2e8f9f7 627 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 628 /**
<> 144:ef7eb2e8f9f7 629 * @}
<> 144:ef7eb2e8f9f7 630 */
<> 144:ef7eb2e8f9f7 631
<> 156:95d6b41a828b 632 /** @addtogroup CEC_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 633 * @{
<> 156:95d6b41a828b 634 */
<> 144:ef7eb2e8f9f7 635 /* Peripheral State functions ************************************************/
<> 144:ef7eb2e8f9f7 636 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 637 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
<> 144:ef7eb2e8f9f7 638 /**
<> 144:ef7eb2e8f9f7 639 * @}
<> 144:ef7eb2e8f9f7 640 */
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 /**
<> 144:ef7eb2e8f9f7 643 * @}
<> 144:ef7eb2e8f9f7 644 */
<> 156:95d6b41a828b 645
<> 144:ef7eb2e8f9f7 646 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 647 /** @defgroup CEC_Private_Types CEC Private Types
<> 144:ef7eb2e8f9f7 648 * @{
<> 144:ef7eb2e8f9f7 649 */
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /**
<> 144:ef7eb2e8f9f7 652 * @}
<> 144:ef7eb2e8f9f7 653 */
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 656 /** @defgroup CEC_Private_Variables CEC Private Variables
<> 144:ef7eb2e8f9f7 657 * @{
<> 144:ef7eb2e8f9f7 658 */
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /**
<> 144:ef7eb2e8f9f7 661 * @}
<> 144:ef7eb2e8f9f7 662 */
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 665 /** @defgroup CEC_Private_Constants CEC Private Constants
<> 144:ef7eb2e8f9f7 666 * @{
<> 144:ef7eb2e8f9f7 667 */
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /**
<> 144:ef7eb2e8f9f7 670 * @}
<> 144:ef7eb2e8f9f7 671 */
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 674 /** @defgroup CEC_Private_Macros CEC Private Macros
<> 144:ef7eb2e8f9f7 675 * @{
<> 144:ef7eb2e8f9f7 676 */
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 #define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 #define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
<> 144:ef7eb2e8f9f7 681 ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
<> 156:95d6b41a828b 682
<> 144:ef7eb2e8f9f7 683 #define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
<> 144:ef7eb2e8f9f7 684 ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
<> 156:95d6b41a828b 685
<> 144:ef7eb2e8f9f7 686 #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
<> 144:ef7eb2e8f9f7 687 ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
<> 144:ef7eb2e8f9f7 690 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
<> 156:95d6b41a828b 691
<> 144:ef7eb2e8f9f7 692 #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
<> 144:ef7eb2e8f9f7 693 ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
<> 156:95d6b41a828b 694
<> 144:ef7eb2e8f9f7 695 #define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
<> 144:ef7eb2e8f9f7 696 ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
<> 156:95d6b41a828b 697
<> 144:ef7eb2e8f9f7 698 #define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
<> 144:ef7eb2e8f9f7 699 ((__MODE__) == CEC_FULL_LISTENING_MODE))
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /** @brief Check CEC message size.
<> 144:ef7eb2e8f9f7 702 * The message size is the payload size: without counting the header,
<> 144:ef7eb2e8f9f7 703 * it varies from 0 byte (ping operation, one header only, no payload) to
<> 144:ef7eb2e8f9f7 704 * 15 bytes (1 opcode and up to 14 operands following the header).
Anna Bridge 180:96ed750bd169 705 * @param __SIZE__ CEC message size.
<> 144:ef7eb2e8f9f7 706 * @retval Test result (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 707 */
<> 156:95d6b41a828b 708 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
<> 156:95d6b41a828b 709
<> 156:95d6b41a828b 710 /** @brief Check CEC device Own Address Register (OAR) setting.
<> 156:95d6b41a828b 711 * OAR address is written in a 15-bit field within CEC_CFGR register.
Anna Bridge 180:96ed750bd169 712 * @param __ADDRESS__ CEC own address.
<> 156:95d6b41a828b 713 * @retval Test result (TRUE or FALSE).
<> 156:95d6b41a828b 714 */
<> 156:95d6b41a828b 715 #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
<> 156:95d6b41a828b 716
<> 156:95d6b41a828b 717 /** @brief Check CEC initiator or destination logical address setting.
<> 156:95d6b41a828b 718 * Initiator and destination addresses are coded over 4 bits.
Anna Bridge 180:96ed750bd169 719 * @param __ADDRESS__ CEC initiator or logical address.
<> 156:95d6b41a828b 720 * @retval Test result (TRUE or FALSE).
<> 156:95d6b41a828b 721 */
<> 156:95d6b41a828b 722 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU)
<> 144:ef7eb2e8f9f7 723 /**
<> 144:ef7eb2e8f9f7 724 * @}
<> 156:95d6b41a828b 725 */
<> 144:ef7eb2e8f9f7 726 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 727 /** @defgroup CEC_Private_Functions CEC Private Functions
<> 144:ef7eb2e8f9f7 728 * @{
<> 144:ef7eb2e8f9f7 729 */
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /**
<> 144:ef7eb2e8f9f7 732 * @}
<> 144:ef7eb2e8f9f7 733 */
<> 156:95d6b41a828b 734
<> 144:ef7eb2e8f9f7 735 /**
<> 144:ef7eb2e8f9f7 736 * @}
<> 144:ef7eb2e8f9f7 737 */
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /**
<> 144:ef7eb2e8f9f7 740 * @}
<> 144:ef7eb2e8f9f7 741 */
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 #endif /* defined(STM32F042x6) || defined(STM32F048xx) || */
<> 144:ef7eb2e8f9f7 744 /* defined(STM32F051x8) || defined(STM32F058xx) || */
<> 144:ef7eb2e8f9f7 745 /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */
<> 144:ef7eb2e8f9f7 746 /* defined(STM32F091xC) || defined(STM32F098xx) */
<> 144:ef7eb2e8f9f7 747 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 748 }
<> 144:ef7eb2e8f9f7 749 #endif
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 #endif /* __STM32F0xx_HAL_CEC_H */
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/