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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_can.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief CAN HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the Controller Area Network (CAN) peripheral:
<> 144:ef7eb2e8f9f7 8 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 9 * + IO operation functions
<> 144:ef7eb2e8f9f7 10 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 (#) Enable the CAN controller interface clock using __HAL_RCC_CAN1_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (#) CAN pins configuration
<> 144:ef7eb2e8f9f7 21 (++) Enable the clock for the CAN GPIOs using the following function:
<> 144:ef7eb2e8f9f7 22 __HAL_RCC_GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 23 (++) Connect and configure the involved CAN pins to AF9 using the
<> 144:ef7eb2e8f9f7 24 following function HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 (#) Initialise and configure the CAN using HAL_CAN_Init() function.
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
Anna Bridge 180:96ed750bd169 29
Anna Bridge 180:96ed750bd169 30 (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
Anna Bridge 180:96ed750bd169 31
<> 144:ef7eb2e8f9f7 32 (#) Receive a CAN frame using HAL_CAN_Receive() function.
<> 144:ef7eb2e8f9f7 33
Anna Bridge 180:96ed750bd169 34 (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
Anna Bridge 180:96ed750bd169 35
<> 144:ef7eb2e8f9f7 36 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 37 =================================
<> 144:ef7eb2e8f9f7 38 [..]
<> 144:ef7eb2e8f9f7 39 (+) Start the CAN peripheral transmission and wait the end of this operation
<> 144:ef7eb2e8f9f7 40 using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
<> 144:ef7eb2e8f9f7 41 according to his end application
<> 144:ef7eb2e8f9f7 42 (+) Start the CAN peripheral reception and wait the end of this operation
<> 144:ef7eb2e8f9f7 43 using HAL_CAN_Receive(), at this stage user can specify the value of timeout
<> 144:ef7eb2e8f9f7 44 according to his end application
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 47 ===================================
<> 144:ef7eb2e8f9f7 48 [..]
<> 144:ef7eb2e8f9f7 49 (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
<> 144:ef7eb2e8f9f7 50 (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
<> 144:ef7eb2e8f9f7 51 (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
<> 144:ef7eb2e8f9f7 52 (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 53 add his own code by customization of function pointer HAL_CAN_TxCpltCallback
<> 144:ef7eb2e8f9f7 54 (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 55 add his own code by customization of function pointer HAL_CAN_ErrorCallback
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 *** CAN HAL driver macros list ***
<> 144:ef7eb2e8f9f7 58 =============================================
<> 144:ef7eb2e8f9f7 59 [..]
<> 144:ef7eb2e8f9f7 60 Below the list of most used macros in CAN HAL driver.
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
<> 144:ef7eb2e8f9f7 63 (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
<> 144:ef7eb2e8f9f7 64 (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
<> 144:ef7eb2e8f9f7 65 (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
<> 144:ef7eb2e8f9f7 66 (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 [..]
<> 144:ef7eb2e8f9f7 69 (@) You can refer to the CAN HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 @endverbatim
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 ******************************************************************************
<> 144:ef7eb2e8f9f7 74 * @attention
<> 144:ef7eb2e8f9f7 75 *
<> 144:ef7eb2e8f9f7 76 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 77 *
<> 144:ef7eb2e8f9f7 78 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 79 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 80 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 81 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 82 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 83 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 84 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 85 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 86 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 87 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 88 *
<> 144:ef7eb2e8f9f7 89 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 90 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 91 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 92 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 93 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 94 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 95 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 96 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 97 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 98 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 99 *
<> 144:ef7eb2e8f9f7 100 ******************************************************************************
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 104 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 #ifdef HAL_CAN_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 #if defined(STM32F072xB) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 111 * @{
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /** @defgroup CAN CAN
<> 144:ef7eb2e8f9f7 115 * @brief CAN driver modules
<> 144:ef7eb2e8f9f7 116 * @{
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 120 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 121 /** @defgroup CAN_Private_Constants CAN Private Constants
<> 144:ef7eb2e8f9f7 122 * @{
<> 144:ef7eb2e8f9f7 123 */
<> 156:95d6b41a828b 124 #define CAN_TIMEOUT_VALUE 10U
<> 144:ef7eb2e8f9f7 125 /**
<> 144:ef7eb2e8f9f7 126 * @}
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 129 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 130 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 131 /** @defgroup CAN_Private_Functions CAN Private Functions
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
<> 144:ef7eb2e8f9f7 135 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 136 /**
<> 144:ef7eb2e8f9f7 137 * @}
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /** @defgroup CAN_Exported_Functions CAN Exported Functions
<> 144:ef7eb2e8f9f7 143 * @{
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 147 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 148 *
<> 144:ef7eb2e8f9f7 149 @verbatim
<> 144:ef7eb2e8f9f7 150 ==============================================================================
<> 144:ef7eb2e8f9f7 151 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 152 ==============================================================================
<> 144:ef7eb2e8f9f7 153 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 154 (+) Initialize and configure the CAN.
<> 144:ef7eb2e8f9f7 155 (+) De-initialize the CAN.
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 @endverbatim
<> 144:ef7eb2e8f9f7 158 * @{
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /**
Anna Bridge 180:96ed750bd169 162 * @brief Initializes the CAN peripheral according to the specified
Anna Bridge 180:96ed750bd169 163 * parameters in the CAN_InitStruct.
Anna Bridge 180:96ed750bd169 164 * @param hcan pointer to a CAN_HandleTypeDef structure that contains
Anna Bridge 180:96ed750bd169 165 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 166 * @retval HAL status
<> 144:ef7eb2e8f9f7 167 */
<> 144:ef7eb2e8f9f7 168 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 169 {
<> 144:ef7eb2e8f9f7 170 uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
<> 156:95d6b41a828b 171 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /* Check CAN handle */
<> 144:ef7eb2e8f9f7 174 if(hcan == NULL)
<> 144:ef7eb2e8f9f7 175 {
<> 144:ef7eb2e8f9f7 176 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 177 }
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /* Check the parameters */
<> 144:ef7eb2e8f9f7 180 assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
<> 144:ef7eb2e8f9f7 181 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
<> 144:ef7eb2e8f9f7 182 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
<> 144:ef7eb2e8f9f7 183 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
<> 144:ef7eb2e8f9f7 184 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
<> 144:ef7eb2e8f9f7 185 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
<> 144:ef7eb2e8f9f7 186 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
<> 144:ef7eb2e8f9f7 187 assert_param(IS_CAN_MODE(hcan->Init.Mode));
<> 144:ef7eb2e8f9f7 188 assert_param(IS_CAN_SJW(hcan->Init.SJW));
<> 144:ef7eb2e8f9f7 189 assert_param(IS_CAN_BS1(hcan->Init.BS1));
<> 144:ef7eb2e8f9f7 190 assert_param(IS_CAN_BS2(hcan->Init.BS2));
<> 144:ef7eb2e8f9f7 191 assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 if(hcan->State == HAL_CAN_STATE_RESET)
<> 144:ef7eb2e8f9f7 194 {
<> 144:ef7eb2e8f9f7 195 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 196 hcan->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 197 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 198 HAL_CAN_MspInit(hcan);
<> 144:ef7eb2e8f9f7 199 }
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* Initialize the CAN state*/
<> 144:ef7eb2e8f9f7 202 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* Exit from sleep mode */
Anna Bridge 180:96ed750bd169 205 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* Request initialisation */
Anna Bridge 180:96ed750bd169 208 SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /* Get tick */
<> 144:ef7eb2e8f9f7 211 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Wait the acknowledge */
Anna Bridge 180:96ed750bd169 214 while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
<> 144:ef7eb2e8f9f7 215 {
Anna Bridge 180:96ed750bd169 216 if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 217 {
<> 144:ef7eb2e8f9f7 218 hcan->State= HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 219 /* Process unlocked */
<> 144:ef7eb2e8f9f7 220 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 221 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223 }
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /* Check acknowledge */
Anna Bridge 180:96ed750bd169 226 if (HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
<> 144:ef7eb2e8f9f7 227 {
<> 144:ef7eb2e8f9f7 228 /* Set the time triggered communication mode */
<> 144:ef7eb2e8f9f7 229 if (hcan->Init.TTCM == ENABLE)
<> 144:ef7eb2e8f9f7 230 {
Anna Bridge 180:96ed750bd169 231 SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
<> 144:ef7eb2e8f9f7 232 }
<> 144:ef7eb2e8f9f7 233 else
<> 144:ef7eb2e8f9f7 234 {
Anna Bridge 180:96ed750bd169 235 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /* Set the automatic bus-off management */
<> 144:ef7eb2e8f9f7 239 if (hcan->Init.ABOM == ENABLE)
<> 144:ef7eb2e8f9f7 240 {
Anna Bridge 180:96ed750bd169 241 SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
<> 144:ef7eb2e8f9f7 242 }
<> 144:ef7eb2e8f9f7 243 else
<> 144:ef7eb2e8f9f7 244 {
Anna Bridge 180:96ed750bd169 245 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Set the automatic wake-up mode */
<> 144:ef7eb2e8f9f7 249 if (hcan->Init.AWUM == ENABLE)
<> 144:ef7eb2e8f9f7 250 {
Anna Bridge 180:96ed750bd169 251 SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253 else
<> 144:ef7eb2e8f9f7 254 {
Anna Bridge 180:96ed750bd169 255 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
<> 144:ef7eb2e8f9f7 256 }
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* Set the no automatic retransmission */
<> 144:ef7eb2e8f9f7 259 if (hcan->Init.NART == ENABLE)
<> 144:ef7eb2e8f9f7 260 {
Anna Bridge 180:96ed750bd169 261 SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
<> 144:ef7eb2e8f9f7 262 }
<> 144:ef7eb2e8f9f7 263 else
<> 144:ef7eb2e8f9f7 264 {
Anna Bridge 180:96ed750bd169 265 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
<> 144:ef7eb2e8f9f7 266 }
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /* Set the receive FIFO locked mode */
<> 144:ef7eb2e8f9f7 269 if (hcan->Init.RFLM == ENABLE)
<> 144:ef7eb2e8f9f7 270 {
Anna Bridge 180:96ed750bd169 271 SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273 else
<> 144:ef7eb2e8f9f7 274 {
Anna Bridge 180:96ed750bd169 275 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
<> 144:ef7eb2e8f9f7 276 }
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /* Set the transmit FIFO priority */
<> 144:ef7eb2e8f9f7 279 if (hcan->Init.TXFP == ENABLE)
<> 144:ef7eb2e8f9f7 280 {
Anna Bridge 180:96ed750bd169 281 SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283 else
<> 144:ef7eb2e8f9f7 284 {
Anna Bridge 180:96ed750bd169 285 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /* Set the bit timing register */
Anna Bridge 180:96ed750bd169 289 WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
Anna Bridge 180:96ed750bd169 290 hcan->Init.SJW |
Anna Bridge 180:96ed750bd169 291 hcan->Init.BS1 |
Anna Bridge 180:96ed750bd169 292 hcan->Init.BS2 |
Anna Bridge 180:96ed750bd169 293 (hcan->Init.Prescaler - 1U) ));
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /* Request leave initialisation */
Anna Bridge 180:96ed750bd169 296 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /* Get tick */
<> 144:ef7eb2e8f9f7 299 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /* Wait the acknowledge */
Anna Bridge 180:96ed750bd169 302 while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
<> 144:ef7eb2e8f9f7 303 {
Anna Bridge 180:96ed750bd169 304 if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 305 {
Anna Bridge 180:96ed750bd169 306 hcan->State= HAL_CAN_STATE_TIMEOUT;
Anna Bridge 180:96ed750bd169 307
<> 144:ef7eb2e8f9f7 308 /* Process unlocked */
<> 144:ef7eb2e8f9f7 309 __HAL_UNLOCK(hcan);
Anna Bridge 180:96ed750bd169 310
Anna Bridge 180:96ed750bd169 311 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /* Check acknowledged */
Anna Bridge 180:96ed750bd169 316 if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
<> 144:ef7eb2e8f9f7 317 {
<> 144:ef7eb2e8f9f7 318 status = CAN_INITSTATUS_SUCCESS;
<> 144:ef7eb2e8f9f7 319 }
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 if(status == CAN_INITSTATUS_SUCCESS)
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 /* Set CAN error code to none */
<> 144:ef7eb2e8f9f7 325 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /* Initialize the CAN state */
<> 144:ef7eb2e8f9f7 328 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /* Return function status */
<> 144:ef7eb2e8f9f7 331 return HAL_OK;
<> 144:ef7eb2e8f9f7 332 }
<> 144:ef7eb2e8f9f7 333 else
<> 144:ef7eb2e8f9f7 334 {
<> 144:ef7eb2e8f9f7 335 /* Initialize the CAN state */
<> 144:ef7eb2e8f9f7 336 hcan->State = HAL_CAN_STATE_ERROR;
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /* Return function status */
<> 144:ef7eb2e8f9f7 339 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341 }
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /**
<> 144:ef7eb2e8f9f7 344 * @brief Configures the CAN reception filter according to the specified
<> 144:ef7eb2e8f9f7 345 * parameters in the CAN_FilterInitStruct.
Anna Bridge 180:96ed750bd169 346 * @param hcan pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 347 * the configuration information for the specified CAN.
Anna Bridge 180:96ed750bd169 348 * @param sFilterConfig pointer to a CAN_FilterConfTypeDef structure that
<> 144:ef7eb2e8f9f7 349 * contains the filter configuration information.
<> 144:ef7eb2e8f9f7 350 * @retval None
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
<> 144:ef7eb2e8f9f7 353 {
Anna Bridge 180:96ed750bd169 354 uint32_t filternbrbitpos = 0U;
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Check the parameters */
<> 144:ef7eb2e8f9f7 357 assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
<> 144:ef7eb2e8f9f7 358 assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
<> 144:ef7eb2e8f9f7 359 assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
<> 144:ef7eb2e8f9f7 360 assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
<> 144:ef7eb2e8f9f7 361 assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
<> 144:ef7eb2e8f9f7 362 assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
<> 144:ef7eb2e8f9f7 363
<> 156:95d6b41a828b 364 filternbrbitpos = (1U) << sFilterConfig->FilterNumber;
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /* Initialisation mode for the filter */
<> 144:ef7eb2e8f9f7 367 /* Select the start slave bank */
Anna Bridge 180:96ed750bd169 368 MODIFY_REG(hcan->Instance->FMR ,
Anna Bridge 180:96ed750bd169 369 CAN_FMR_CAN2SB ,
Anna Bridge 180:96ed750bd169 370 CAN_FMR_FINIT |
Anna Bridge 180:96ed750bd169 371 (uint32_t)(sFilterConfig->BankNumber << 8U) ); /* Filter Deactivation */
Anna Bridge 180:96ed750bd169 372 CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos);
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /* Filter Scale */
<> 144:ef7eb2e8f9f7 375 if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
<> 144:ef7eb2e8f9f7 376 {
<> 144:ef7eb2e8f9f7 377 /* 16-bit scale for the filter */
Anna Bridge 180:96ed750bd169 378 CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos);
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /* First 16-bit identifier and First 16-bit mask */
<> 144:ef7eb2e8f9f7 381 /* Or First 16-bit identifier and Second 16-bit identifier */
<> 144:ef7eb2e8f9f7 382 hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
Anna Bridge 180:96ed750bd169 383 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
Anna Bridge 180:96ed750bd169 384 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /* Second 16-bit identifier and Second 16-bit mask */
<> 144:ef7eb2e8f9f7 387 /* Or Third 16-bit identifier and Fourth 16-bit identifier */
<> 144:ef7eb2e8f9f7 388 hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
Anna Bridge 180:96ed750bd169 389 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
Anna Bridge 180:96ed750bd169 390 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
<> 144:ef7eb2e8f9f7 391 }
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
<> 144:ef7eb2e8f9f7 394 {
<> 144:ef7eb2e8f9f7 395 /* 32-bit scale for the filter */
Anna Bridge 180:96ed750bd169 396 SET_BIT(hcan->Instance->FS1R, filternbrbitpos);
Anna Bridge 180:96ed750bd169 397
<> 144:ef7eb2e8f9f7 398 /* 32-bit identifier or First 32-bit identifier */
<> 144:ef7eb2e8f9f7 399 hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
Anna Bridge 180:96ed750bd169 400 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
Anna Bridge 180:96ed750bd169 401 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
Anna Bridge 180:96ed750bd169 402
<> 144:ef7eb2e8f9f7 403 /* 32-bit mask or Second 32-bit identifier */
<> 144:ef7eb2e8f9f7 404 hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
Anna Bridge 180:96ed750bd169 405 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
Anna Bridge 180:96ed750bd169 406 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
<> 144:ef7eb2e8f9f7 407 }
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /* Filter Mode */
<> 144:ef7eb2e8f9f7 410 if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
<> 144:ef7eb2e8f9f7 411 {
<> 144:ef7eb2e8f9f7 412 /*Id/Mask mode for the filter*/
Anna Bridge 180:96ed750bd169 413 CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos);
<> 144:ef7eb2e8f9f7 414 }
<> 144:ef7eb2e8f9f7 415 else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
<> 144:ef7eb2e8f9f7 416 {
<> 144:ef7eb2e8f9f7 417 /*Identifier list mode for the filter*/
Anna Bridge 180:96ed750bd169 418 SET_BIT(hcan->Instance->FM1R, filternbrbitpos);
<> 144:ef7eb2e8f9f7 419 }
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /* Filter FIFO assignment */
<> 144:ef7eb2e8f9f7 422 if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
<> 144:ef7eb2e8f9f7 423 {
<> 144:ef7eb2e8f9f7 424 /* FIFO 0 assignation for the filter */
Anna Bridge 180:96ed750bd169 425 CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos);
<> 144:ef7eb2e8f9f7 426 }
Anna Bridge 180:96ed750bd169 427 else
<> 144:ef7eb2e8f9f7 428 {
<> 144:ef7eb2e8f9f7 429 /* FIFO 1 assignation for the filter */
Anna Bridge 180:96ed750bd169 430 SET_BIT(hcan->Instance->FFA1R, filternbrbitpos);
<> 144:ef7eb2e8f9f7 431 }
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /* Filter activation */
<> 144:ef7eb2e8f9f7 434 if (sFilterConfig->FilterActivation == ENABLE)
<> 144:ef7eb2e8f9f7 435 {
Anna Bridge 180:96ed750bd169 436 SET_BIT(hcan->Instance->FA1R, filternbrbitpos);
<> 144:ef7eb2e8f9f7 437 }
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /* Leave the initialisation mode for the filter */
Anna Bridge 180:96ed750bd169 440 CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT));
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /* Return function status */
<> 144:ef7eb2e8f9f7 443 return HAL_OK;
<> 144:ef7eb2e8f9f7 444 }
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /**
<> 144:ef7eb2e8f9f7 447 * @brief Deinitializes the CANx peripheral registers to their default reset values.
Anna Bridge 180:96ed750bd169 448 * @param hcan pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 449 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 450 * @retval HAL status
<> 144:ef7eb2e8f9f7 451 */
<> 144:ef7eb2e8f9f7 452 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 453 {
<> 144:ef7eb2e8f9f7 454 /* Check CAN handle */
<> 144:ef7eb2e8f9f7 455 if(hcan == NULL)
<> 144:ef7eb2e8f9f7 456 {
<> 144:ef7eb2e8f9f7 457 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 458 }
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /* Check the parameters */
<> 144:ef7eb2e8f9f7 461 assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /* Change CAN state */
<> 144:ef7eb2e8f9f7 464 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 467 HAL_CAN_MspDeInit(hcan);
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Change CAN state */
<> 144:ef7eb2e8f9f7 470 hcan->State = HAL_CAN_STATE_RESET;
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /* Release Lock */
<> 144:ef7eb2e8f9f7 473 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /* Return function status */
<> 144:ef7eb2e8f9f7 476 return HAL_OK;
<> 144:ef7eb2e8f9f7 477 }
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /**
<> 144:ef7eb2e8f9f7 480 * @brief Initializes the CAN MSP.
Anna Bridge 180:96ed750bd169 481 * @param hcan pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 482 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 483 * @retval None
<> 144:ef7eb2e8f9f7 484 */
<> 144:ef7eb2e8f9f7 485 __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 486 {
<> 144:ef7eb2e8f9f7 487 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 488 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 491 the HAL_CAN_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 492 */
<> 144:ef7eb2e8f9f7 493 }
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /**
<> 144:ef7eb2e8f9f7 496 * @brief DeInitializes the CAN MSP.
Anna Bridge 180:96ed750bd169 497 * @param hcan pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 498 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 499 * @retval None
<> 144:ef7eb2e8f9f7 500 */
<> 144:ef7eb2e8f9f7 501 __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 502 {
<> 144:ef7eb2e8f9f7 503 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 504 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 507 the HAL_CAN_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 508 */
<> 144:ef7eb2e8f9f7 509 }
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /**
<> 144:ef7eb2e8f9f7 512 * @}
<> 144:ef7eb2e8f9f7 513 */
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 516 * @brief IO operation functions
<> 144:ef7eb2e8f9f7 517 *
<> 144:ef7eb2e8f9f7 518 @verbatim
<> 144:ef7eb2e8f9f7 519 ==============================================================================
<> 144:ef7eb2e8f9f7 520 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 521 ==============================================================================
<> 144:ef7eb2e8f9f7 522 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 523 (+) Transmit a CAN frame message.
<> 144:ef7eb2e8f9f7 524 (+) Receive a CAN frame message.
<> 144:ef7eb2e8f9f7 525 (+) Enter CAN peripheral in sleep mode.
<> 144:ef7eb2e8f9f7 526 (+) Wake up the CAN peripheral from sleep mode.
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 @endverbatim
<> 144:ef7eb2e8f9f7 529 * @{
<> 144:ef7eb2e8f9f7 530 */
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /**
<> 144:ef7eb2e8f9f7 533 * @brief Initiates and transmits a CAN frame message.
Anna Bridge 180:96ed750bd169 534 * @param hcan pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 535 * the configuration information for the specified CAN.
Anna Bridge 180:96ed750bd169 536 * @param Timeout Timeout duration.
<> 144:ef7eb2e8f9f7 537 * @retval HAL status
<> 144:ef7eb2e8f9f7 538 */
<> 144:ef7eb2e8f9f7 539 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 540 {
<> 144:ef7eb2e8f9f7 541 uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
<> 156:95d6b41a828b 542 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /* Check the parameters */
<> 144:ef7eb2e8f9f7 545 assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
<> 144:ef7eb2e8f9f7 546 assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
<> 144:ef7eb2e8f9f7 547 assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
Anna Bridge 180:96ed750bd169 548
<> 144:ef7eb2e8f9f7 549 if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
<> 144:ef7eb2e8f9f7 550 ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
<> 144:ef7eb2e8f9f7 551 ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
Anna Bridge 180:96ed750bd169 552 {
<> 144:ef7eb2e8f9f7 553 /* Process locked */
<> 144:ef7eb2e8f9f7 554 __HAL_LOCK(hcan);
Anna Bridge 180:96ed750bd169 555
Anna Bridge 180:96ed750bd169 556 /* Change CAN state */
Anna Bridge 180:96ed750bd169 557 switch(hcan->State)
<> 144:ef7eb2e8f9f7 558 {
Anna Bridge 180:96ed750bd169 559 case(HAL_CAN_STATE_BUSY_RX0):
Anna Bridge 180:96ed750bd169 560 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
Anna Bridge 180:96ed750bd169 561 break;
Anna Bridge 180:96ed750bd169 562 case(HAL_CAN_STATE_BUSY_RX1):
Anna Bridge 180:96ed750bd169 563 hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
Anna Bridge 180:96ed750bd169 564 break;
Anna Bridge 180:96ed750bd169 565 case(HAL_CAN_STATE_BUSY_RX0_RX1):
Anna Bridge 180:96ed750bd169 566 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
Anna Bridge 180:96ed750bd169 567 break;
Anna Bridge 180:96ed750bd169 568 default: /* HAL_CAN_STATE_READY */
Anna Bridge 180:96ed750bd169 569 hcan->State = HAL_CAN_STATE_BUSY_TX;
Anna Bridge 180:96ed750bd169 570 break;
Anna Bridge 180:96ed750bd169 571 }
Anna Bridge 180:96ed750bd169 572
Anna Bridge 180:96ed750bd169 573 /* Select one empty transmit mailbox */
Anna Bridge 180:96ed750bd169 574 if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
Anna Bridge 180:96ed750bd169 575 {
Anna Bridge 180:96ed750bd169 576 transmitmailbox = CAN_TXMAILBOX_0;
Anna Bridge 180:96ed750bd169 577 }
Anna Bridge 180:96ed750bd169 578 else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
Anna Bridge 180:96ed750bd169 579 {
Anna Bridge 180:96ed750bd169 580 transmitmailbox = CAN_TXMAILBOX_1;
<> 144:ef7eb2e8f9f7 581 }
<> 144:ef7eb2e8f9f7 582 else
<> 144:ef7eb2e8f9f7 583 {
Anna Bridge 180:96ed750bd169 584 transmitmailbox = CAN_TXMAILBOX_2;
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /* Set up the Id */
<> 144:ef7eb2e8f9f7 588 hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 589 if (hcan->pTxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 590 {
<> 144:ef7eb2e8f9f7 591 assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
Anna Bridge 180:96ed750bd169 592 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
Anna Bridge 180:96ed750bd169 593 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 594 }
<> 144:ef7eb2e8f9f7 595 else
<> 144:ef7eb2e8f9f7 596 {
<> 144:ef7eb2e8f9f7 597 assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
Anna Bridge 180:96ed750bd169 598 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
Anna Bridge 180:96ed750bd169 599 hcan->pTxMsg->IDE | \
Anna Bridge 180:96ed750bd169 600 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 601 }
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /* Set up the DLC */
<> 156:95d6b41a828b 604 hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
<> 156:95d6b41a828b 605 hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
<> 144:ef7eb2e8f9f7 606 hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /* Set up the data field */
Anna Bridge 180:96ed750bd169 609 WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
Anna Bridge 180:96ed750bd169 610 ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
Anna Bridge 180:96ed750bd169 611 ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
Anna Bridge 180:96ed750bd169 612 ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
Anna Bridge 180:96ed750bd169 613 WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
Anna Bridge 180:96ed750bd169 614 ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
Anna Bridge 180:96ed750bd169 615 ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
Anna Bridge 180:96ed750bd169 616 ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
Anna Bridge 180:96ed750bd169 617
<> 144:ef7eb2e8f9f7 618 /* Request transmission */
Anna Bridge 180:96ed750bd169 619 SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /* Get tick */
<> 144:ef7eb2e8f9f7 622 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Check End of transmission flag */
<> 144:ef7eb2e8f9f7 625 while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
<> 144:ef7eb2e8f9f7 626 {
<> 144:ef7eb2e8f9f7 627 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 628 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 629 {
Anna Bridge 180:96ed750bd169 630 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 631 {
<> 144:ef7eb2e8f9f7 632 hcan->State = HAL_CAN_STATE_TIMEOUT;
Anna Bridge 180:96ed750bd169 633
Anna Bridge 180:96ed750bd169 634 /* Cancel transmission */
Anna Bridge 180:96ed750bd169 635 __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
Anna Bridge 180:96ed750bd169 636
<> 144:ef7eb2e8f9f7 637 /* Process unlocked */
<> 144:ef7eb2e8f9f7 638 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 639 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 640 }
<> 144:ef7eb2e8f9f7 641 }
<> 144:ef7eb2e8f9f7 642 }
Anna Bridge 180:96ed750bd169 643
Anna Bridge 180:96ed750bd169 644 /* Change CAN state */
Anna Bridge 180:96ed750bd169 645 switch(hcan->State)
<> 144:ef7eb2e8f9f7 646 {
Anna Bridge 180:96ed750bd169 647 case(HAL_CAN_STATE_BUSY_TX_RX0):
Anna Bridge 180:96ed750bd169 648 hcan->State = HAL_CAN_STATE_BUSY_RX0;
Anna Bridge 180:96ed750bd169 649 break;
Anna Bridge 180:96ed750bd169 650 case(HAL_CAN_STATE_BUSY_TX_RX1):
Anna Bridge 180:96ed750bd169 651 hcan->State = HAL_CAN_STATE_BUSY_RX1;
Anna Bridge 180:96ed750bd169 652 break;
Anna Bridge 180:96ed750bd169 653 case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
Anna Bridge 180:96ed750bd169 654 hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
Anna Bridge 180:96ed750bd169 655 break;
Anna Bridge 180:96ed750bd169 656 default: /* HAL_CAN_STATE_BUSY_TX */
Anna Bridge 180:96ed750bd169 657 hcan->State = HAL_CAN_STATE_READY;
Anna Bridge 180:96ed750bd169 658 break;
<> 144:ef7eb2e8f9f7 659 }
Anna Bridge 180:96ed750bd169 660
<> 144:ef7eb2e8f9f7 661 /* Process unlocked */
<> 144:ef7eb2e8f9f7 662 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /* Return function status */
<> 144:ef7eb2e8f9f7 665 return HAL_OK;
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667 else
<> 144:ef7eb2e8f9f7 668 {
<> 144:ef7eb2e8f9f7 669 /* Change CAN state */
<> 144:ef7eb2e8f9f7 670 hcan->State = HAL_CAN_STATE_ERROR;
Anna Bridge 180:96ed750bd169 671
<> 144:ef7eb2e8f9f7 672 /* Return function status */
<> 144:ef7eb2e8f9f7 673 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 674 }
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /**
<> 144:ef7eb2e8f9f7 678 * @brief Initiates and transmits a CAN frame message.
Anna Bridge 180:96ed750bd169 679 * @param hcan pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 680 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 681 * @retval HAL status
<> 144:ef7eb2e8f9f7 682 */
<> 144:ef7eb2e8f9f7 683 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 684 {
<> 144:ef7eb2e8f9f7 685 uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /* Check the parameters */
<> 144:ef7eb2e8f9f7 688 assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
<> 144:ef7eb2e8f9f7 689 assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
<> 144:ef7eb2e8f9f7 690 assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
Anna Bridge 180:96ed750bd169 691
<> 144:ef7eb2e8f9f7 692 if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
<> 144:ef7eb2e8f9f7 693 ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
<> 144:ef7eb2e8f9f7 694 ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
<> 144:ef7eb2e8f9f7 695 {
<> 144:ef7eb2e8f9f7 696 /* Process Locked */
<> 144:ef7eb2e8f9f7 697 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /* Select one empty transmit mailbox */
Anna Bridge 180:96ed750bd169 700 if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
<> 144:ef7eb2e8f9f7 701 {
Anna Bridge 180:96ed750bd169 702 transmitmailbox = CAN_TXMAILBOX_0;
<> 144:ef7eb2e8f9f7 703 }
Anna Bridge 180:96ed750bd169 704 else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
<> 144:ef7eb2e8f9f7 705 {
Anna Bridge 180:96ed750bd169 706 transmitmailbox = CAN_TXMAILBOX_1;
<> 144:ef7eb2e8f9f7 707 }
<> 144:ef7eb2e8f9f7 708 else
<> 144:ef7eb2e8f9f7 709 {
Anna Bridge 180:96ed750bd169 710 transmitmailbox = CAN_TXMAILBOX_2;
<> 144:ef7eb2e8f9f7 711 }
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 /* Set up the Id */
<> 144:ef7eb2e8f9f7 714 hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 715 if(hcan->pTxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 716 {
Anna Bridge 180:96ed750bd169 717 assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
Anna Bridge 180:96ed750bd169 718 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
Anna Bridge 180:96ed750bd169 719 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 720 }
<> 144:ef7eb2e8f9f7 721 else
<> 144:ef7eb2e8f9f7 722 {
<> 144:ef7eb2e8f9f7 723 assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
Anna Bridge 180:96ed750bd169 724 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
Anna Bridge 180:96ed750bd169 725 hcan->pTxMsg->IDE | \
Anna Bridge 180:96ed750bd169 726 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 727 }
Anna Bridge 180:96ed750bd169 728
<> 144:ef7eb2e8f9f7 729 /* Set up the DLC */
<> 156:95d6b41a828b 730 hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
<> 156:95d6b41a828b 731 hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
<> 144:ef7eb2e8f9f7 732 hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /* Set up the data field */
Anna Bridge 180:96ed750bd169 735 WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
Anna Bridge 180:96ed750bd169 736 ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
Anna Bridge 180:96ed750bd169 737 ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
Anna Bridge 180:96ed750bd169 738 ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
Anna Bridge 180:96ed750bd169 739 WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
Anna Bridge 180:96ed750bd169 740 ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
Anna Bridge 180:96ed750bd169 741 ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
Anna Bridge 180:96ed750bd169 742 ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
Anna Bridge 180:96ed750bd169 743
Anna Bridge 180:96ed750bd169 744 /* Change CAN state */
Anna Bridge 180:96ed750bd169 745 switch(hcan->State)
<> 144:ef7eb2e8f9f7 746 {
Anna Bridge 180:96ed750bd169 747 case(HAL_CAN_STATE_BUSY_RX0):
Anna Bridge 180:96ed750bd169 748 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
Anna Bridge 180:96ed750bd169 749 break;
Anna Bridge 180:96ed750bd169 750 case(HAL_CAN_STATE_BUSY_RX1):
Anna Bridge 180:96ed750bd169 751 hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
Anna Bridge 180:96ed750bd169 752 break;
Anna Bridge 180:96ed750bd169 753 case(HAL_CAN_STATE_BUSY_RX0_RX1):
Anna Bridge 180:96ed750bd169 754 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
Anna Bridge 180:96ed750bd169 755 break;
Anna Bridge 180:96ed750bd169 756 default: /* HAL_CAN_STATE_READY */
Anna Bridge 180:96ed750bd169 757 hcan->State = HAL_CAN_STATE_BUSY_TX;
Anna Bridge 180:96ed750bd169 758 break;
<> 144:ef7eb2e8f9f7 759 }
Anna Bridge 180:96ed750bd169 760
<> 144:ef7eb2e8f9f7 761 /* Set CAN error code to none */
<> 144:ef7eb2e8f9f7 762 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
Anna Bridge 180:96ed750bd169 763
<> 144:ef7eb2e8f9f7 764 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 765 __HAL_UNLOCK(hcan);
Anna Bridge 180:96ed750bd169 766
<> 144:ef7eb2e8f9f7 767 /* Request transmission */
<> 144:ef7eb2e8f9f7 768 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
Anna Bridge 180:96ed750bd169 769
Anna Bridge 180:96ed750bd169 770 /* Enable interrupts: */
Anna Bridge 180:96ed750bd169 771 /* - Enable Error warning Interrupt */
Anna Bridge 180:96ed750bd169 772 /* - Enable Error passive Interrupt */
Anna Bridge 180:96ed750bd169 773 /* - Enable Bus-off Interrupt */
Anna Bridge 180:96ed750bd169 774 /* - Enable Last error code Interrupt */
Anna Bridge 180:96ed750bd169 775 /* - Enable Error Interrupt */
Anna Bridge 180:96ed750bd169 776 /* - Enable Transmit mailbox empty Interrupt */
Anna Bridge 180:96ed750bd169 777 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
Anna Bridge 180:96ed750bd169 778 CAN_IT_EPV |
Anna Bridge 180:96ed750bd169 779 CAN_IT_BOF |
Anna Bridge 180:96ed750bd169 780 CAN_IT_LEC |
Anna Bridge 180:96ed750bd169 781 CAN_IT_ERR |
Anna Bridge 180:96ed750bd169 782 CAN_IT_TME );
<> 144:ef7eb2e8f9f7 783 }
<> 144:ef7eb2e8f9f7 784 else
<> 144:ef7eb2e8f9f7 785 {
<> 144:ef7eb2e8f9f7 786 /* Change CAN state */
Anna Bridge 180:96ed750bd169 787 hcan->State = HAL_CAN_STATE_ERROR;
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /* Return function status */
<> 144:ef7eb2e8f9f7 790 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 791 }
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 return HAL_OK;
<> 144:ef7eb2e8f9f7 794 }
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /**
<> 144:ef7eb2e8f9f7 797 * @brief Receives a correct CAN frame.
Anna Bridge 180:96ed750bd169 798 * @param hcan pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 799 * the configuration information for the specified CAN.
Anna Bridge 180:96ed750bd169 800 * @param FIFONumber FIFO number.
Anna Bridge 180:96ed750bd169 801 * @param Timeout Timeout duration.
<> 144:ef7eb2e8f9f7 802 * @retval HAL status
<> 144:ef7eb2e8f9f7 803 */
<> 144:ef7eb2e8f9f7 804 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 805 {
Anna Bridge 180:96ed750bd169 806 uint32_t tickstart = 0U;
Anna Bridge 180:96ed750bd169 807 CanRxMsgTypeDef* pRxMsg = NULL;
Anna Bridge 180:96ed750bd169 808
<> 144:ef7eb2e8f9f7 809 /* Check the parameters */
<> 144:ef7eb2e8f9f7 810 assert_param(IS_CAN_FIFO(FIFONumber));
Anna Bridge 180:96ed750bd169 811
<> 144:ef7eb2e8f9f7 812 /* Process locked */
<> 144:ef7eb2e8f9f7 813 __HAL_LOCK(hcan);
Anna Bridge 180:96ed750bd169 814
Anna Bridge 180:96ed750bd169 815 /* Check if CAN state is not busy for RX FIFO0 */
Anna Bridge 180:96ed750bd169 816 if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
Anna Bridge 180:96ed750bd169 817 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
Anna Bridge 180:96ed750bd169 818 (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
Anna Bridge 180:96ed750bd169 819 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
<> 144:ef7eb2e8f9f7 820 {
Anna Bridge 180:96ed750bd169 821 /* Process unlocked */
Anna Bridge 180:96ed750bd169 822 __HAL_UNLOCK(hcan);
Anna Bridge 180:96ed750bd169 823
Anna Bridge 180:96ed750bd169 824 return HAL_BUSY;
Anna Bridge 180:96ed750bd169 825 }
Anna Bridge 180:96ed750bd169 826
Anna Bridge 180:96ed750bd169 827 /* Check if CAN state is not busy for RX FIFO1 */
Anna Bridge 180:96ed750bd169 828 if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
Anna Bridge 180:96ed750bd169 829 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
Anna Bridge 180:96ed750bd169 830 (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
Anna Bridge 180:96ed750bd169 831 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
Anna Bridge 180:96ed750bd169 832 {
Anna Bridge 180:96ed750bd169 833 /* Process unlocked */
Anna Bridge 180:96ed750bd169 834 __HAL_UNLOCK(hcan);
Anna Bridge 180:96ed750bd169 835
Anna Bridge 180:96ed750bd169 836 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 837 }
Anna Bridge 180:96ed750bd169 838
Anna Bridge 180:96ed750bd169 839 /* Change CAN state */
Anna Bridge 180:96ed750bd169 840 if (FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 841 {
Anna Bridge 180:96ed750bd169 842 switch(hcan->State)
Anna Bridge 180:96ed750bd169 843 {
Anna Bridge 180:96ed750bd169 844 case(HAL_CAN_STATE_BUSY_TX):
Anna Bridge 180:96ed750bd169 845 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
Anna Bridge 180:96ed750bd169 846 break;
Anna Bridge 180:96ed750bd169 847 case(HAL_CAN_STATE_BUSY_RX1):
Anna Bridge 180:96ed750bd169 848 hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
Anna Bridge 180:96ed750bd169 849 break;
Anna Bridge 180:96ed750bd169 850 case(HAL_CAN_STATE_BUSY_TX_RX1):
Anna Bridge 180:96ed750bd169 851 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
Anna Bridge 180:96ed750bd169 852 break;
Anna Bridge 180:96ed750bd169 853 default: /* HAL_CAN_STATE_READY */
Anna Bridge 180:96ed750bd169 854 hcan->State = HAL_CAN_STATE_BUSY_RX0;
Anna Bridge 180:96ed750bd169 855 break;
Anna Bridge 180:96ed750bd169 856 }
<> 144:ef7eb2e8f9f7 857 }
Anna Bridge 180:96ed750bd169 858 else /* FIFONumber == CAN_FIFO1 */
Anna Bridge 180:96ed750bd169 859 {
Anna Bridge 180:96ed750bd169 860 switch(hcan->State)
Anna Bridge 180:96ed750bd169 861 {
Anna Bridge 180:96ed750bd169 862 case(HAL_CAN_STATE_BUSY_TX):
Anna Bridge 180:96ed750bd169 863 hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
Anna Bridge 180:96ed750bd169 864 break;
Anna Bridge 180:96ed750bd169 865 case(HAL_CAN_STATE_BUSY_RX0):
Anna Bridge 180:96ed750bd169 866 hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
Anna Bridge 180:96ed750bd169 867 break;
Anna Bridge 180:96ed750bd169 868 case(HAL_CAN_STATE_BUSY_TX_RX0):
Anna Bridge 180:96ed750bd169 869 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
Anna Bridge 180:96ed750bd169 870 break;
Anna Bridge 180:96ed750bd169 871 default: /* HAL_CAN_STATE_READY */
Anna Bridge 180:96ed750bd169 872 hcan->State = HAL_CAN_STATE_BUSY_RX1;
Anna Bridge 180:96ed750bd169 873 break;
Anna Bridge 180:96ed750bd169 874 }
Anna Bridge 180:96ed750bd169 875 }
Anna Bridge 180:96ed750bd169 876
<> 144:ef7eb2e8f9f7 877 /* Get tick */
<> 144:ef7eb2e8f9f7 878 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 /* Check pending message */
<> 156:95d6b41a828b 881 while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
<> 144:ef7eb2e8f9f7 882 {
<> 144:ef7eb2e8f9f7 883 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 884 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 885 {
Anna Bridge 180:96ed750bd169 886 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 887 {
<> 144:ef7eb2e8f9f7 888 hcan->State = HAL_CAN_STATE_TIMEOUT;
Anna Bridge 180:96ed750bd169 889
<> 144:ef7eb2e8f9f7 890 /* Process unlocked */
<> 144:ef7eb2e8f9f7 891 __HAL_UNLOCK(hcan);
Anna Bridge 180:96ed750bd169 892
<> 144:ef7eb2e8f9f7 893 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 894 }
<> 144:ef7eb2e8f9f7 895 }
<> 144:ef7eb2e8f9f7 896 }
Anna Bridge 180:96ed750bd169 897
Anna Bridge 180:96ed750bd169 898 /* Set RxMsg pointer */
Anna Bridge 180:96ed750bd169 899 if(FIFONumber == CAN_FIFO0)
Anna Bridge 180:96ed750bd169 900 {
Anna Bridge 180:96ed750bd169 901 pRxMsg = hcan->pRxMsg;
Anna Bridge 180:96ed750bd169 902 }
Anna Bridge 180:96ed750bd169 903 else /* FIFONumber == CAN_FIFO1 */
Anna Bridge 180:96ed750bd169 904 {
Anna Bridge 180:96ed750bd169 905 pRxMsg = hcan->pRx1Msg;
Anna Bridge 180:96ed750bd169 906 }
Anna Bridge 180:96ed750bd169 907
<> 144:ef7eb2e8f9f7 908 /* Get the Id */
Anna Bridge 180:96ed750bd169 909 pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
Anna Bridge 180:96ed750bd169 910 if (pRxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 911 {
Anna Bridge 180:96ed750bd169 912 pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos;
<> 144:ef7eb2e8f9f7 913 }
<> 144:ef7eb2e8f9f7 914 else
<> 144:ef7eb2e8f9f7 915 {
Anna Bridge 180:96ed750bd169 916 pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos;
<> 144:ef7eb2e8f9f7 917 }
Anna Bridge 180:96ed750bd169 918 pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos;
<> 144:ef7eb2e8f9f7 919 /* Get the DLC */
Anna Bridge 180:96ed750bd169 920 pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos;
<> 144:ef7eb2e8f9f7 921 /* Get the FMI */
Anna Bridge 180:96ed750bd169 922 pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos;
Anna Bridge 180:96ed750bd169 923 /* Get the FIFONumber */
Anna Bridge 180:96ed750bd169 924 pRxMsg->FIFONumber = FIFONumber;
<> 144:ef7eb2e8f9f7 925 /* Get the data field */
Anna Bridge 180:96ed750bd169 926 pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos;
Anna Bridge 180:96ed750bd169 927 pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos;
Anna Bridge 180:96ed750bd169 928 pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos;
Anna Bridge 180:96ed750bd169 929 pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos;
Anna Bridge 180:96ed750bd169 930 pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos;
Anna Bridge 180:96ed750bd169 931 pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos;
Anna Bridge 180:96ed750bd169 932 pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos;
Anna Bridge 180:96ed750bd169 933 pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos;
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /* Release the FIFO */
<> 144:ef7eb2e8f9f7 936 if(FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 937 {
<> 144:ef7eb2e8f9f7 938 /* Release FIFO0 */
<> 144:ef7eb2e8f9f7 939 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 940 }
<> 144:ef7eb2e8f9f7 941 else /* FIFONumber == CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 942 {
<> 144:ef7eb2e8f9f7 943 /* Release FIFO1 */
<> 144:ef7eb2e8f9f7 944 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 945 }
Anna Bridge 180:96ed750bd169 946
Anna Bridge 180:96ed750bd169 947 /* Change CAN state */
Anna Bridge 180:96ed750bd169 948 if (FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 949 {
Anna Bridge 180:96ed750bd169 950 switch(hcan->State)
Anna Bridge 180:96ed750bd169 951 {
Anna Bridge 180:96ed750bd169 952 case(HAL_CAN_STATE_BUSY_TX_RX0):
Anna Bridge 180:96ed750bd169 953 hcan->State = HAL_CAN_STATE_BUSY_TX;
Anna Bridge 180:96ed750bd169 954 break;
Anna Bridge 180:96ed750bd169 955 case(HAL_CAN_STATE_BUSY_RX0_RX1):
Anna Bridge 180:96ed750bd169 956 hcan->State = HAL_CAN_STATE_BUSY_RX1;
Anna Bridge 180:96ed750bd169 957 break;
Anna Bridge 180:96ed750bd169 958 case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
Anna Bridge 180:96ed750bd169 959 hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
Anna Bridge 180:96ed750bd169 960 break;
Anna Bridge 180:96ed750bd169 961 default: /* HAL_CAN_STATE_BUSY_RX0 */
Anna Bridge 180:96ed750bd169 962 hcan->State = HAL_CAN_STATE_READY;
Anna Bridge 180:96ed750bd169 963 break;
Anna Bridge 180:96ed750bd169 964 }
<> 144:ef7eb2e8f9f7 965 }
Anna Bridge 180:96ed750bd169 966 else /* FIFONumber == CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 967 {
Anna Bridge 180:96ed750bd169 968 switch(hcan->State)
Anna Bridge 180:96ed750bd169 969 {
Anna Bridge 180:96ed750bd169 970 case(HAL_CAN_STATE_BUSY_TX_RX1):
Anna Bridge 180:96ed750bd169 971 hcan->State = HAL_CAN_STATE_BUSY_TX;
Anna Bridge 180:96ed750bd169 972 break;
Anna Bridge 180:96ed750bd169 973 case(HAL_CAN_STATE_BUSY_RX0_RX1):
Anna Bridge 180:96ed750bd169 974 hcan->State = HAL_CAN_STATE_BUSY_RX0;
Anna Bridge 180:96ed750bd169 975 break;
Anna Bridge 180:96ed750bd169 976 case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
Anna Bridge 180:96ed750bd169 977 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
Anna Bridge 180:96ed750bd169 978 break;
Anna Bridge 180:96ed750bd169 979 default: /* HAL_CAN_STATE_BUSY_RX1 */
Anna Bridge 180:96ed750bd169 980 hcan->State = HAL_CAN_STATE_READY;
Anna Bridge 180:96ed750bd169 981 break;
Anna Bridge 180:96ed750bd169 982 }
<> 144:ef7eb2e8f9f7 983 }
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 /* Process unlocked */
<> 144:ef7eb2e8f9f7 986 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 /* Return function status */
<> 144:ef7eb2e8f9f7 989 return HAL_OK;
<> 144:ef7eb2e8f9f7 990 }
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992 /**
<> 144:ef7eb2e8f9f7 993 * @brief Receives a correct CAN frame.
Anna Bridge 180:96ed750bd169 994 * @param hcan pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 995 * the configuration information for the specified CAN.
Anna Bridge 180:96ed750bd169 996 * @param FIFONumber FIFO number.
<> 144:ef7eb2e8f9f7 997 * @retval HAL status
<> 144:ef7eb2e8f9f7 998 */
<> 144:ef7eb2e8f9f7 999 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
<> 144:ef7eb2e8f9f7 1000 {
<> 144:ef7eb2e8f9f7 1001 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1002 assert_param(IS_CAN_FIFO(FIFONumber));
Anna Bridge 180:96ed750bd169 1003
Anna Bridge 180:96ed750bd169 1004 /* Process locked */
Anna Bridge 180:96ed750bd169 1005 __HAL_LOCK(hcan);
Anna Bridge 180:96ed750bd169 1006
Anna Bridge 180:96ed750bd169 1007 /* Check if CAN state is not busy for RX FIFO0 */
Anna Bridge 180:96ed750bd169 1008 if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
Anna Bridge 180:96ed750bd169 1009 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
Anna Bridge 180:96ed750bd169 1010 (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
Anna Bridge 180:96ed750bd169 1011 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
<> 144:ef7eb2e8f9f7 1012 {
Anna Bridge 180:96ed750bd169 1013 /* Process unlocked */
Anna Bridge 180:96ed750bd169 1014 __HAL_UNLOCK(hcan);
Anna Bridge 180:96ed750bd169 1015
Anna Bridge 180:96ed750bd169 1016 return HAL_BUSY;
Anna Bridge 180:96ed750bd169 1017 }
<> 144:ef7eb2e8f9f7 1018
Anna Bridge 180:96ed750bd169 1019 /* Check if CAN state is not busy for RX FIFO1 */
Anna Bridge 180:96ed750bd169 1020 if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
Anna Bridge 180:96ed750bd169 1021 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
Anna Bridge 180:96ed750bd169 1022 (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
Anna Bridge 180:96ed750bd169 1023 (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
Anna Bridge 180:96ed750bd169 1024 {
<> 144:ef7eb2e8f9f7 1025 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1026 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1027
Anna Bridge 180:96ed750bd169 1028 return HAL_BUSY;
Anna Bridge 180:96ed750bd169 1029 }
Anna Bridge 180:96ed750bd169 1030
Anna Bridge 180:96ed750bd169 1031 /* Change CAN state */
Anna Bridge 180:96ed750bd169 1032 if (FIFONumber == CAN_FIFO0)
Anna Bridge 180:96ed750bd169 1033 {
Anna Bridge 180:96ed750bd169 1034 switch(hcan->State)
<> 144:ef7eb2e8f9f7 1035 {
Anna Bridge 180:96ed750bd169 1036 case(HAL_CAN_STATE_BUSY_TX):
Anna Bridge 180:96ed750bd169 1037 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
Anna Bridge 180:96ed750bd169 1038 break;
Anna Bridge 180:96ed750bd169 1039 case(HAL_CAN_STATE_BUSY_RX1):
Anna Bridge 180:96ed750bd169 1040 hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
Anna Bridge 180:96ed750bd169 1041 break;
Anna Bridge 180:96ed750bd169 1042 case(HAL_CAN_STATE_BUSY_TX_RX1):
Anna Bridge 180:96ed750bd169 1043 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
Anna Bridge 180:96ed750bd169 1044 break;
Anna Bridge 180:96ed750bd169 1045 default: /* HAL_CAN_STATE_READY */
Anna Bridge 180:96ed750bd169 1046 hcan->State = HAL_CAN_STATE_BUSY_RX0;
Anna Bridge 180:96ed750bd169 1047 break;
<> 144:ef7eb2e8f9f7 1048 }
Anna Bridge 180:96ed750bd169 1049 }
Anna Bridge 180:96ed750bd169 1050 else /* FIFONumber == CAN_FIFO1 */
Anna Bridge 180:96ed750bd169 1051 {
Anna Bridge 180:96ed750bd169 1052 switch(hcan->State)
<> 144:ef7eb2e8f9f7 1053 {
Anna Bridge 180:96ed750bd169 1054 case(HAL_CAN_STATE_BUSY_TX):
Anna Bridge 180:96ed750bd169 1055 hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
Anna Bridge 180:96ed750bd169 1056 break;
Anna Bridge 180:96ed750bd169 1057 case(HAL_CAN_STATE_BUSY_RX0):
Anna Bridge 180:96ed750bd169 1058 hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
Anna Bridge 180:96ed750bd169 1059 break;
Anna Bridge 180:96ed750bd169 1060 case(HAL_CAN_STATE_BUSY_TX_RX0):
Anna Bridge 180:96ed750bd169 1061 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
Anna Bridge 180:96ed750bd169 1062 break;
Anna Bridge 180:96ed750bd169 1063 default: /* HAL_CAN_STATE_READY */
Anna Bridge 180:96ed750bd169 1064 hcan->State = HAL_CAN_STATE_BUSY_RX1;
Anna Bridge 180:96ed750bd169 1065 break;
<> 144:ef7eb2e8f9f7 1066 }
Anna Bridge 180:96ed750bd169 1067 }
Anna Bridge 180:96ed750bd169 1068
Anna Bridge 180:96ed750bd169 1069 /* Set CAN error code to none */
Anna Bridge 180:96ed750bd169 1070 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
Anna Bridge 180:96ed750bd169 1071
Anna Bridge 180:96ed750bd169 1072 /* Enable interrupts: */
Anna Bridge 180:96ed750bd169 1073 /* - Enable Error warning Interrupt */
Anna Bridge 180:96ed750bd169 1074 /* - Enable Error passive Interrupt */
Anna Bridge 180:96ed750bd169 1075 /* - Enable Bus-off Interrupt */
Anna Bridge 180:96ed750bd169 1076 /* - Enable Last error code Interrupt */
Anna Bridge 180:96ed750bd169 1077 /* - Enable Error Interrupt */
Anna Bridge 180:96ed750bd169 1078 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
Anna Bridge 180:96ed750bd169 1079 CAN_IT_EPV |
Anna Bridge 180:96ed750bd169 1080 CAN_IT_BOF |
Anna Bridge 180:96ed750bd169 1081 CAN_IT_LEC |
Anna Bridge 180:96ed750bd169 1082 CAN_IT_ERR);
Anna Bridge 180:96ed750bd169 1083
Anna Bridge 180:96ed750bd169 1084 /* Process unlocked */
Anna Bridge 180:96ed750bd169 1085 __HAL_UNLOCK(hcan);
Anna Bridge 180:96ed750bd169 1086
Anna Bridge 180:96ed750bd169 1087 if(FIFONumber == CAN_FIFO0)
Anna Bridge 180:96ed750bd169 1088 {
Anna Bridge 180:96ed750bd169 1089 /* Enable FIFO 0 overrun and message pending Interrupt */
Anna Bridge 180:96ed750bd169 1090 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
<> 144:ef7eb2e8f9f7 1091 }
<> 144:ef7eb2e8f9f7 1092 else
<> 144:ef7eb2e8f9f7 1093 {
Anna Bridge 180:96ed750bd169 1094 /* Enable FIFO 1 overrun and message pending Interrupt */
Anna Bridge 180:96ed750bd169 1095 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
<> 144:ef7eb2e8f9f7 1096 }
<> 144:ef7eb2e8f9f7 1097
<> 144:ef7eb2e8f9f7 1098 /* Return function status */
<> 144:ef7eb2e8f9f7 1099 return HAL_OK;
<> 144:ef7eb2e8f9f7 1100 }
<> 144:ef7eb2e8f9f7 1101
<> 144:ef7eb2e8f9f7 1102 /**
<> 144:ef7eb2e8f9f7 1103 * @brief Enters the Sleep (low power) mode.
Anna Bridge 180:96ed750bd169 1104 * @param hcan pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1105 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1106 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1107 */
<> 144:ef7eb2e8f9f7 1108 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1109 {
<> 156:95d6b41a828b 1110 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1111
<> 144:ef7eb2e8f9f7 1112 /* Process locked */
<> 144:ef7eb2e8f9f7 1113 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 1114
<> 144:ef7eb2e8f9f7 1115 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1116 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1117
<> 144:ef7eb2e8f9f7 1118 /* Request Sleep mode */
Anna Bridge 180:96ed750bd169 1119 MODIFY_REG(hcan->Instance->MCR,
Anna Bridge 180:96ed750bd169 1120 CAN_MCR_INRQ ,
Anna Bridge 180:96ed750bd169 1121 CAN_MCR_SLEEP );
<> 144:ef7eb2e8f9f7 1122
<> 144:ef7eb2e8f9f7 1123 /* Sleep mode status */
Anna Bridge 180:96ed750bd169 1124 if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
Anna Bridge 180:96ed750bd169 1125 HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
<> 144:ef7eb2e8f9f7 1126 {
<> 144:ef7eb2e8f9f7 1127 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1128 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1129
<> 144:ef7eb2e8f9f7 1130 /* Return function status */
<> 144:ef7eb2e8f9f7 1131 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1132 }
<> 144:ef7eb2e8f9f7 1133
<> 144:ef7eb2e8f9f7 1134 /* Get tick */
<> 144:ef7eb2e8f9f7 1135 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1136
<> 144:ef7eb2e8f9f7 1137 /* Wait the acknowledge */
Anna Bridge 180:96ed750bd169 1138 while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
Anna Bridge 180:96ed750bd169 1139 HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
<> 144:ef7eb2e8f9f7 1140 {
<> 144:ef7eb2e8f9f7 1141 if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 1142 {
<> 144:ef7eb2e8f9f7 1143 hcan->State = HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1144 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1145 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1146 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1147 }
<> 144:ef7eb2e8f9f7 1148 }
<> 144:ef7eb2e8f9f7 1149
<> 144:ef7eb2e8f9f7 1150 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1151 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1152
<> 144:ef7eb2e8f9f7 1153 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1154 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 /* Return function status */
<> 144:ef7eb2e8f9f7 1157 return HAL_OK;
<> 144:ef7eb2e8f9f7 1158 }
<> 144:ef7eb2e8f9f7 1159
<> 144:ef7eb2e8f9f7 1160 /**
<> 144:ef7eb2e8f9f7 1161 * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
<> 144:ef7eb2e8f9f7 1162 * is in the normal mode.
Anna Bridge 180:96ed750bd169 1163 * @param hcan pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1164 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1165 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1166 */
<> 144:ef7eb2e8f9f7 1167 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1168 {
<> 156:95d6b41a828b 1169 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 /* Process locked */
<> 144:ef7eb2e8f9f7 1172 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1175 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177 /* Wake up request */
Anna Bridge 180:96ed750bd169 1178 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
<> 144:ef7eb2e8f9f7 1179
<> 144:ef7eb2e8f9f7 1180 /* Get tick */
<> 144:ef7eb2e8f9f7 1181 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1182
<> 144:ef7eb2e8f9f7 1183 /* Sleep mode status */
Anna Bridge 180:96ed750bd169 1184 while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
<> 144:ef7eb2e8f9f7 1185 {
<> 144:ef7eb2e8f9f7 1186 if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 1187 {
<> 144:ef7eb2e8f9f7 1188 hcan->State= HAL_CAN_STATE_TIMEOUT;
Anna Bridge 180:96ed750bd169 1189
<> 144:ef7eb2e8f9f7 1190 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1191 __HAL_UNLOCK(hcan);
Anna Bridge 180:96ed750bd169 1192
<> 144:ef7eb2e8f9f7 1193 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1194 }
<> 144:ef7eb2e8f9f7 1195 }
Anna Bridge 180:96ed750bd169 1196
Anna Bridge 180:96ed750bd169 1197 if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
<> 144:ef7eb2e8f9f7 1198 {
<> 144:ef7eb2e8f9f7 1199 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1200 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1201
<> 144:ef7eb2e8f9f7 1202 /* Return function status */
<> 144:ef7eb2e8f9f7 1203 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1204 }
<> 144:ef7eb2e8f9f7 1205
<> 144:ef7eb2e8f9f7 1206 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1207 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1210 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1211
<> 144:ef7eb2e8f9f7 1212 /* Return function status */
<> 144:ef7eb2e8f9f7 1213 return HAL_OK;
<> 144:ef7eb2e8f9f7 1214 }
<> 144:ef7eb2e8f9f7 1215
<> 144:ef7eb2e8f9f7 1216 /**
<> 144:ef7eb2e8f9f7 1217 * @brief Handles CAN interrupt request
Anna Bridge 180:96ed750bd169 1218 * @param hcan pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1219 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1220 * @retval None
<> 144:ef7eb2e8f9f7 1221 */
<> 144:ef7eb2e8f9f7 1222 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1223 {
Anna Bridge 180:96ed750bd169 1224 uint32_t errorcode = HAL_CAN_ERROR_NONE;
Anna Bridge 180:96ed750bd169 1225
Anna Bridge 180:96ed750bd169 1226 /* Check Overrun flag for FIFO0 */
Anna Bridge 180:96ed750bd169 1227 if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0)) &&
Anna Bridge 180:96ed750bd169 1228 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0)))
Anna Bridge 180:96ed750bd169 1229 {
Anna Bridge 180:96ed750bd169 1230 /* Set CAN error code to FOV0 error */
Anna Bridge 180:96ed750bd169 1231 errorcode |= HAL_CAN_ERROR_FOV0;
Anna Bridge 180:96ed750bd169 1232
Anna Bridge 180:96ed750bd169 1233 /* Clear FIFO0 Overrun Flag */
Anna Bridge 180:96ed750bd169 1234 __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
Anna Bridge 180:96ed750bd169 1235 }
Anna Bridge 180:96ed750bd169 1236
Anna Bridge 180:96ed750bd169 1237 /* Check Overrun flag for FIFO1 */
Anna Bridge 180:96ed750bd169 1238 if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1)) &&
Anna Bridge 180:96ed750bd169 1239 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1)))
Anna Bridge 180:96ed750bd169 1240 {
Anna Bridge 180:96ed750bd169 1241 /* Set CAN error code to FOV1 error */
Anna Bridge 180:96ed750bd169 1242 errorcode |= HAL_CAN_ERROR_FOV1;
Anna Bridge 180:96ed750bd169 1243
Anna Bridge 180:96ed750bd169 1244 /* Clear FIFO1 Overrun Flag */
Anna Bridge 180:96ed750bd169 1245 __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
Anna Bridge 180:96ed750bd169 1246 }
Anna Bridge 180:96ed750bd169 1247
<> 144:ef7eb2e8f9f7 1248 /* Check End of transmission flag */
<> 144:ef7eb2e8f9f7 1249 if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
<> 144:ef7eb2e8f9f7 1250 {
Anna Bridge 180:96ed750bd169 1251 /* Check Transmit request completion status */
<> 144:ef7eb2e8f9f7 1252 if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) ||
<> 144:ef7eb2e8f9f7 1253 (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) ||
<> 144:ef7eb2e8f9f7 1254 (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2)))
<> 144:ef7eb2e8f9f7 1255 {
Anna Bridge 180:96ed750bd169 1256 /* Check Transmit success */
Anna Bridge 180:96ed750bd169 1257 if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0)) ||
Anna Bridge 180:96ed750bd169 1258 (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1)) ||
Anna Bridge 180:96ed750bd169 1259 (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2)))
Anna Bridge 180:96ed750bd169 1260 {
Anna Bridge 180:96ed750bd169 1261 /* Call transmit function */
Anna Bridge 180:96ed750bd169 1262 CAN_Transmit_IT(hcan);
Anna Bridge 180:96ed750bd169 1263 }
Anna Bridge 180:96ed750bd169 1264 else /* Transmit failure */
Anna Bridge 180:96ed750bd169 1265 {
Anna Bridge 180:96ed750bd169 1266 /* Set CAN error code to TXFAIL error */
Anna Bridge 180:96ed750bd169 1267 errorcode |= HAL_CAN_ERROR_TXFAIL;
Anna Bridge 180:96ed750bd169 1268 }
Anna Bridge 180:96ed750bd169 1269
Anna Bridge 180:96ed750bd169 1270 /* Clear transmission status flags (RQCPx and TXOKx) */
Anna Bridge 180:96ed750bd169 1271 SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
Anna Bridge 180:96ed750bd169 1272 CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
<> 144:ef7eb2e8f9f7 1273 }
<> 144:ef7eb2e8f9f7 1274 }
<> 144:ef7eb2e8f9f7 1275
<> 144:ef7eb2e8f9f7 1276 /* Check End of reception flag for FIFO0 */
<> 144:ef7eb2e8f9f7 1277 if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) &&
Anna Bridge 180:96ed750bd169 1278 (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0U))
<> 144:ef7eb2e8f9f7 1279 {
<> 144:ef7eb2e8f9f7 1280 /* Call receive function */
<> 144:ef7eb2e8f9f7 1281 CAN_Receive_IT(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 1282 }
<> 144:ef7eb2e8f9f7 1283
<> 144:ef7eb2e8f9f7 1284 /* Check End of reception flag for FIFO1 */
<> 144:ef7eb2e8f9f7 1285 if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) &&
Anna Bridge 180:96ed750bd169 1286 (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0U))
<> 144:ef7eb2e8f9f7 1287 {
<> 144:ef7eb2e8f9f7 1288 /* Call receive function */
<> 144:ef7eb2e8f9f7 1289 CAN_Receive_IT(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 1290 }
<> 144:ef7eb2e8f9f7 1291
Anna Bridge 180:96ed750bd169 1292 /* Set error code in handle */
Anna Bridge 180:96ed750bd169 1293 hcan->ErrorCode |= errorcode;
Anna Bridge 180:96ed750bd169 1294
<> 144:ef7eb2e8f9f7 1295 /* Check Error Warning Flag */
<> 144:ef7eb2e8f9f7 1296 if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) &&
<> 144:ef7eb2e8f9f7 1297 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) &&
<> 144:ef7eb2e8f9f7 1298 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
<> 144:ef7eb2e8f9f7 1299 {
<> 144:ef7eb2e8f9f7 1300 /* Set CAN error code to EWG error */
<> 144:ef7eb2e8f9f7 1301 hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
<> 144:ef7eb2e8f9f7 1302 /* No need for clear of Error Warning Flag as read-only */
<> 144:ef7eb2e8f9f7 1303 }
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305 /* Check Error Passive Flag */
<> 144:ef7eb2e8f9f7 1306 if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) &&
<> 144:ef7eb2e8f9f7 1307 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) &&
<> 144:ef7eb2e8f9f7 1308 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
<> 144:ef7eb2e8f9f7 1309 {
<> 144:ef7eb2e8f9f7 1310 /* Set CAN error code to EPV error */
<> 144:ef7eb2e8f9f7 1311 hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
Anna Bridge 180:96ed750bd169 1312 /* No need for clear of Error Passive Flag as read-only */
<> 144:ef7eb2e8f9f7 1313 }
<> 144:ef7eb2e8f9f7 1314
<> 144:ef7eb2e8f9f7 1315 /* Check Bus-Off Flag */
<> 144:ef7eb2e8f9f7 1316 if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) &&
<> 144:ef7eb2e8f9f7 1317 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) &&
<> 144:ef7eb2e8f9f7 1318 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
<> 144:ef7eb2e8f9f7 1319 {
<> 144:ef7eb2e8f9f7 1320 /* Set CAN error code to BOF error */
<> 144:ef7eb2e8f9f7 1321 hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
<> 144:ef7eb2e8f9f7 1322 /* No need for clear of Bus-Off Flag as read-only */
<> 144:ef7eb2e8f9f7 1323 }
<> 144:ef7eb2e8f9f7 1324
<> 144:ef7eb2e8f9f7 1325 /* Check Last error code Flag */
<> 144:ef7eb2e8f9f7 1326 if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) &&
<> 144:ef7eb2e8f9f7 1327 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) &&
<> 144:ef7eb2e8f9f7 1328 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
<> 144:ef7eb2e8f9f7 1329 {
<> 144:ef7eb2e8f9f7 1330 switch(hcan->Instance->ESR & CAN_ESR_LEC)
<> 144:ef7eb2e8f9f7 1331 {
<> 144:ef7eb2e8f9f7 1332 case(CAN_ESR_LEC_0):
<> 144:ef7eb2e8f9f7 1333 /* Set CAN error code to STF error */
<> 144:ef7eb2e8f9f7 1334 hcan->ErrorCode |= HAL_CAN_ERROR_STF;
<> 144:ef7eb2e8f9f7 1335 break;
<> 144:ef7eb2e8f9f7 1336 case(CAN_ESR_LEC_1):
<> 144:ef7eb2e8f9f7 1337 /* Set CAN error code to FOR error */
<> 144:ef7eb2e8f9f7 1338 hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
<> 144:ef7eb2e8f9f7 1339 break;
<> 144:ef7eb2e8f9f7 1340 case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
<> 144:ef7eb2e8f9f7 1341 /* Set CAN error code to ACK error */
<> 144:ef7eb2e8f9f7 1342 hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
<> 144:ef7eb2e8f9f7 1343 break;
<> 144:ef7eb2e8f9f7 1344 case(CAN_ESR_LEC_2):
<> 144:ef7eb2e8f9f7 1345 /* Set CAN error code to BR error */
<> 144:ef7eb2e8f9f7 1346 hcan->ErrorCode |= HAL_CAN_ERROR_BR;
<> 144:ef7eb2e8f9f7 1347 break;
<> 144:ef7eb2e8f9f7 1348 case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
<> 144:ef7eb2e8f9f7 1349 /* Set CAN error code to BD error */
<> 144:ef7eb2e8f9f7 1350 hcan->ErrorCode |= HAL_CAN_ERROR_BD;
<> 144:ef7eb2e8f9f7 1351 break;
<> 144:ef7eb2e8f9f7 1352 case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
<> 144:ef7eb2e8f9f7 1353 /* Set CAN error code to CRC error */
<> 144:ef7eb2e8f9f7 1354 hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
<> 144:ef7eb2e8f9f7 1355 break;
<> 144:ef7eb2e8f9f7 1356 default:
<> 144:ef7eb2e8f9f7 1357 break;
<> 144:ef7eb2e8f9f7 1358 }
<> 144:ef7eb2e8f9f7 1359
<> 144:ef7eb2e8f9f7 1360 /* Clear Last error code Flag */
Anna Bridge 180:96ed750bd169 1361 CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
<> 144:ef7eb2e8f9f7 1362 }
<> 144:ef7eb2e8f9f7 1363
<> 144:ef7eb2e8f9f7 1364 /* Call the Error call Back in case of Errors */
<> 144:ef7eb2e8f9f7 1365 if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1366 {
<> 144:ef7eb2e8f9f7 1367 /* Clear ERRI Flag */
Anna Bridge 180:96ed750bd169 1368 SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI);
Anna Bridge 180:96ed750bd169 1369
<> 144:ef7eb2e8f9f7 1370 /* Set the CAN state ready to be able to start again the process */
<> 144:ef7eb2e8f9f7 1371 hcan->State = HAL_CAN_STATE_READY;
Anna Bridge 180:96ed750bd169 1372
Anna Bridge 180:96ed750bd169 1373 /* Disable interrupts: */
Anna Bridge 180:96ed750bd169 1374 /* - Disable Error warning Interrupt */
Anna Bridge 180:96ed750bd169 1375 /* - Disable Error passive Interrupt */
Anna Bridge 180:96ed750bd169 1376 /* - Disable Bus-off Interrupt */
Anna Bridge 180:96ed750bd169 1377 /* - Disable Last error code Interrupt */
Anna Bridge 180:96ed750bd169 1378 /* - Disable Error Interrupt */
Anna Bridge 180:96ed750bd169 1379 /* - Disable FIFO 0 message pending Interrupt */
Anna Bridge 180:96ed750bd169 1380 /* - Disable FIFO 0 Overrun Interrupt */
Anna Bridge 180:96ed750bd169 1381 /* - Disable FIFO 1 message pending Interrupt */
Anna Bridge 180:96ed750bd169 1382 /* - Disable FIFO 1 Overrun Interrupt */
Anna Bridge 180:96ed750bd169 1383 /* - Disable Transmit mailbox empty Interrupt */
Anna Bridge 180:96ed750bd169 1384 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
Anna Bridge 180:96ed750bd169 1385 CAN_IT_EPV |
Anna Bridge 180:96ed750bd169 1386 CAN_IT_BOF |
Anna Bridge 180:96ed750bd169 1387 CAN_IT_LEC |
Anna Bridge 180:96ed750bd169 1388 CAN_IT_ERR |
Anna Bridge 180:96ed750bd169 1389 CAN_IT_FMP0|
Anna Bridge 180:96ed750bd169 1390 CAN_IT_FOV0|
Anna Bridge 180:96ed750bd169 1391 CAN_IT_FMP1|
Anna Bridge 180:96ed750bd169 1392 CAN_IT_FOV1|
Anna Bridge 180:96ed750bd169 1393 CAN_IT_TME );
Anna Bridge 180:96ed750bd169 1394
<> 144:ef7eb2e8f9f7 1395 /* Call Error callback function */
<> 144:ef7eb2e8f9f7 1396 HAL_CAN_ErrorCallback(hcan);
<> 144:ef7eb2e8f9f7 1397 }
<> 144:ef7eb2e8f9f7 1398 }
<> 144:ef7eb2e8f9f7 1399
<> 144:ef7eb2e8f9f7 1400 /**
<> 144:ef7eb2e8f9f7 1401 * @brief Transmission complete callback in non blocking mode
Anna Bridge 180:96ed750bd169 1402 * @param hcan pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1403 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1404 * @retval None
<> 144:ef7eb2e8f9f7 1405 */
<> 144:ef7eb2e8f9f7 1406 __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1407 {
<> 144:ef7eb2e8f9f7 1408 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1409 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 1410
<> 144:ef7eb2e8f9f7 1411 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1412 the HAL_CAN_TxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1413 */
<> 144:ef7eb2e8f9f7 1414 }
<> 144:ef7eb2e8f9f7 1415
<> 144:ef7eb2e8f9f7 1416 /**
<> 144:ef7eb2e8f9f7 1417 * @brief Transmission complete callback in non blocking mode
Anna Bridge 180:96ed750bd169 1418 * @param hcan pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1419 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1420 * @retval None
<> 144:ef7eb2e8f9f7 1421 */
<> 144:ef7eb2e8f9f7 1422 __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1423 {
<> 144:ef7eb2e8f9f7 1424 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1425 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 1426
<> 144:ef7eb2e8f9f7 1427 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1428 the HAL_CAN_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1429 */
<> 144:ef7eb2e8f9f7 1430 }
<> 144:ef7eb2e8f9f7 1431
<> 144:ef7eb2e8f9f7 1432 /**
<> 144:ef7eb2e8f9f7 1433 * @brief Error CAN callback.
Anna Bridge 180:96ed750bd169 1434 * @param hcan pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1435 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1436 * @retval None
<> 144:ef7eb2e8f9f7 1437 */
<> 144:ef7eb2e8f9f7 1438 __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
<> 144:ef7eb2e8f9f7 1439 {
<> 144:ef7eb2e8f9f7 1440 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1441 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 1442
<> 144:ef7eb2e8f9f7 1443 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1444 the HAL_CAN_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1445 */
<> 144:ef7eb2e8f9f7 1446 }
<> 144:ef7eb2e8f9f7 1447
<> 144:ef7eb2e8f9f7 1448 /**
<> 144:ef7eb2e8f9f7 1449 * @}
<> 144:ef7eb2e8f9f7 1450 */
<> 144:ef7eb2e8f9f7 1451
<> 144:ef7eb2e8f9f7 1452 /** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 1453 * @brief CAN Peripheral State functions
<> 144:ef7eb2e8f9f7 1454 *
<> 144:ef7eb2e8f9f7 1455 @verbatim
<> 144:ef7eb2e8f9f7 1456 ==============================================================================
<> 144:ef7eb2e8f9f7 1457 ##### Peripheral State and Error functions #####
<> 144:ef7eb2e8f9f7 1458 ==============================================================================
<> 144:ef7eb2e8f9f7 1459 [..]
<> 144:ef7eb2e8f9f7 1460 This subsection provides functions allowing to :
<> 144:ef7eb2e8f9f7 1461 (+) Check the CAN state.
<> 144:ef7eb2e8f9f7 1462 (+) Check CAN Errors detected during interrupt process
<> 144:ef7eb2e8f9f7 1463
<> 144:ef7eb2e8f9f7 1464 @endverbatim
<> 144:ef7eb2e8f9f7 1465 * @{
<> 144:ef7eb2e8f9f7 1466 */
<> 144:ef7eb2e8f9f7 1467
<> 144:ef7eb2e8f9f7 1468 /**
<> 144:ef7eb2e8f9f7 1469 * @brief return the CAN state
Anna Bridge 180:96ed750bd169 1470 * @param hcan pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1471 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1472 * @retval HAL state
<> 144:ef7eb2e8f9f7 1473 */
<> 144:ef7eb2e8f9f7 1474 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1475 {
<> 144:ef7eb2e8f9f7 1476 /* Return CAN state */
<> 144:ef7eb2e8f9f7 1477 return hcan->State;
<> 144:ef7eb2e8f9f7 1478 }
<> 144:ef7eb2e8f9f7 1479
<> 144:ef7eb2e8f9f7 1480 /**
<> 144:ef7eb2e8f9f7 1481 * @brief Return the CAN error code
Anna Bridge 180:96ed750bd169 1482 * @param hcan pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1483 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1484 * @retval CAN Error Code
<> 144:ef7eb2e8f9f7 1485 */
<> 144:ef7eb2e8f9f7 1486 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
<> 144:ef7eb2e8f9f7 1487 {
<> 144:ef7eb2e8f9f7 1488 return hcan->ErrorCode;
<> 144:ef7eb2e8f9f7 1489 }
<> 144:ef7eb2e8f9f7 1490
<> 144:ef7eb2e8f9f7 1491 /**
<> 144:ef7eb2e8f9f7 1492 * @}
<> 144:ef7eb2e8f9f7 1493 */
<> 144:ef7eb2e8f9f7 1494
<> 144:ef7eb2e8f9f7 1495 /**
<> 144:ef7eb2e8f9f7 1496 * @}
<> 144:ef7eb2e8f9f7 1497 */
<> 144:ef7eb2e8f9f7 1498
<> 144:ef7eb2e8f9f7 1499 /** @addtogroup CAN_Private_Functions CAN Private Functions
<> 144:ef7eb2e8f9f7 1500 * @brief CAN Frame message Rx/Tx functions
<> 144:ef7eb2e8f9f7 1501 *
<> 144:ef7eb2e8f9f7 1502 * @{
<> 144:ef7eb2e8f9f7 1503 */
Anna Bridge 180:96ed750bd169 1504
<> 144:ef7eb2e8f9f7 1505 /**
<> 144:ef7eb2e8f9f7 1506 * @brief Initiates and transmits a CAN frame message.
Anna Bridge 180:96ed750bd169 1507 * @param hcan pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1508 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1509 * @retval HAL status
<> 144:ef7eb2e8f9f7 1510 */
<> 144:ef7eb2e8f9f7 1511 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1512 {
<> 144:ef7eb2e8f9f7 1513 /* Disable Transmit mailbox empty Interrupt */
<> 144:ef7eb2e8f9f7 1514 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
<> 144:ef7eb2e8f9f7 1515
<> 144:ef7eb2e8f9f7 1516 if(hcan->State == HAL_CAN_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1517 {
Anna Bridge 180:96ed750bd169 1518 /* Disable interrupts: */
Anna Bridge 180:96ed750bd169 1519 /* - Disable Error warning Interrupt */
Anna Bridge 180:96ed750bd169 1520 /* - Disable Error passive Interrupt */
Anna Bridge 180:96ed750bd169 1521 /* - Disable Bus-off Interrupt */
Anna Bridge 180:96ed750bd169 1522 /* - Disable Last error code Interrupt */
Anna Bridge 180:96ed750bd169 1523 /* - Disable Error Interrupt */
Anna Bridge 180:96ed750bd169 1524 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
Anna Bridge 180:96ed750bd169 1525 CAN_IT_EPV |
Anna Bridge 180:96ed750bd169 1526 CAN_IT_BOF |
Anna Bridge 180:96ed750bd169 1527 CAN_IT_LEC |
Anna Bridge 180:96ed750bd169 1528 CAN_IT_ERR );
<> 144:ef7eb2e8f9f7 1529 }
Anna Bridge 180:96ed750bd169 1530
Anna Bridge 180:96ed750bd169 1531 /* Change CAN state */
Anna Bridge 180:96ed750bd169 1532 switch(hcan->State)
<> 144:ef7eb2e8f9f7 1533 {
Anna Bridge 180:96ed750bd169 1534 case(HAL_CAN_STATE_BUSY_TX_RX0):
Anna Bridge 180:96ed750bd169 1535 hcan->State = HAL_CAN_STATE_BUSY_RX0;
Anna Bridge 180:96ed750bd169 1536 break;
Anna Bridge 180:96ed750bd169 1537 case(HAL_CAN_STATE_BUSY_TX_RX1):
Anna Bridge 180:96ed750bd169 1538 hcan->State = HAL_CAN_STATE_BUSY_RX1;
Anna Bridge 180:96ed750bd169 1539 break;
Anna Bridge 180:96ed750bd169 1540 case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
Anna Bridge 180:96ed750bd169 1541 hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
Anna Bridge 180:96ed750bd169 1542 break;
Anna Bridge 180:96ed750bd169 1543 default: /* HAL_CAN_STATE_BUSY_TX */
Anna Bridge 180:96ed750bd169 1544 hcan->State = HAL_CAN_STATE_READY;
Anna Bridge 180:96ed750bd169 1545 break;
<> 144:ef7eb2e8f9f7 1546 }
Anna Bridge 180:96ed750bd169 1547
<> 144:ef7eb2e8f9f7 1548 /* Transmission complete callback */
<> 144:ef7eb2e8f9f7 1549 HAL_CAN_TxCpltCallback(hcan);
<> 144:ef7eb2e8f9f7 1550
<> 144:ef7eb2e8f9f7 1551 return HAL_OK;
<> 144:ef7eb2e8f9f7 1552 }
<> 144:ef7eb2e8f9f7 1553
<> 144:ef7eb2e8f9f7 1554 /**
<> 144:ef7eb2e8f9f7 1555 * @brief Receives a correct CAN frame.
Anna Bridge 180:96ed750bd169 1556 * @param hcan Pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1557 * the configuration information for the specified CAN.
Anna Bridge 180:96ed750bd169 1558 * @param FIFONumber Specify the FIFO number
<> 144:ef7eb2e8f9f7 1559 * @retval HAL status
<> 144:ef7eb2e8f9f7 1560 * @retval None
<> 144:ef7eb2e8f9f7 1561 */
<> 144:ef7eb2e8f9f7 1562 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
<> 144:ef7eb2e8f9f7 1563 {
Anna Bridge 180:96ed750bd169 1564 CanRxMsgTypeDef* pRxMsg = NULL;
Anna Bridge 180:96ed750bd169 1565
Anna Bridge 180:96ed750bd169 1566 /* Set RxMsg pointer */
Anna Bridge 180:96ed750bd169 1567 if(FIFONumber == CAN_FIFO0)
Anna Bridge 180:96ed750bd169 1568 {
Anna Bridge 180:96ed750bd169 1569 pRxMsg = hcan->pRxMsg;
Anna Bridge 180:96ed750bd169 1570 }
Anna Bridge 180:96ed750bd169 1571 else /* FIFONumber == CAN_FIFO1 */
Anna Bridge 180:96ed750bd169 1572 {
Anna Bridge 180:96ed750bd169 1573 pRxMsg = hcan->pRx1Msg;
Anna Bridge 180:96ed750bd169 1574 }
Anna Bridge 180:96ed750bd169 1575
<> 144:ef7eb2e8f9f7 1576 /* Get the Id */
Anna Bridge 180:96ed750bd169 1577 pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
Anna Bridge 180:96ed750bd169 1578 if (pRxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 1579 {
Anna Bridge 180:96ed750bd169 1580 pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos;
<> 144:ef7eb2e8f9f7 1581 }
<> 144:ef7eb2e8f9f7 1582 else
<> 144:ef7eb2e8f9f7 1583 {
Anna Bridge 180:96ed750bd169 1584 pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos;
<> 144:ef7eb2e8f9f7 1585 }
Anna Bridge 180:96ed750bd169 1586 pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos;
<> 144:ef7eb2e8f9f7 1587 /* Get the DLC */
Anna Bridge 180:96ed750bd169 1588 pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos;
<> 144:ef7eb2e8f9f7 1589 /* Get the FMI */
Anna Bridge 180:96ed750bd169 1590 pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos;
Anna Bridge 180:96ed750bd169 1591 /* Get the FIFONumber */
Anna Bridge 180:96ed750bd169 1592 pRxMsg->FIFONumber = FIFONumber;
<> 144:ef7eb2e8f9f7 1593 /* Get the data field */
Anna Bridge 180:96ed750bd169 1594 pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos;
Anna Bridge 180:96ed750bd169 1595 pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos;
Anna Bridge 180:96ed750bd169 1596 pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos;
Anna Bridge 180:96ed750bd169 1597 pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos;
Anna Bridge 180:96ed750bd169 1598 pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos;
Anna Bridge 180:96ed750bd169 1599 pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos;
Anna Bridge 180:96ed750bd169 1600 pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos;
Anna Bridge 180:96ed750bd169 1601 pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos;
Anna Bridge 180:96ed750bd169 1602
<> 144:ef7eb2e8f9f7 1603 /* Release the FIFO */
<> 144:ef7eb2e8f9f7 1604 /* Release FIFO0 */
<> 144:ef7eb2e8f9f7 1605 if (FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 1606 {
<> 144:ef7eb2e8f9f7 1607 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 1608
Anna Bridge 180:96ed750bd169 1609 /* Disable FIFO 0 overrun and message pending Interrupt */
Anna Bridge 180:96ed750bd169 1610 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
<> 144:ef7eb2e8f9f7 1611 }
<> 144:ef7eb2e8f9f7 1612 /* Release FIFO1 */
<> 144:ef7eb2e8f9f7 1613 else /* FIFONumber == CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 1614 {
<> 144:ef7eb2e8f9f7 1615 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 1616
Anna Bridge 180:96ed750bd169 1617 /* Disable FIFO 1 overrun and message pending Interrupt */
Anna Bridge 180:96ed750bd169 1618 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
<> 144:ef7eb2e8f9f7 1619 }
<> 144:ef7eb2e8f9f7 1620
Anna Bridge 180:96ed750bd169 1621 if((hcan->State == HAL_CAN_STATE_BUSY_RX0) || (hcan->State == HAL_CAN_STATE_BUSY_RX1))
<> 144:ef7eb2e8f9f7 1622 {
Anna Bridge 180:96ed750bd169 1623 /* Disable interrupts: */
Anna Bridge 180:96ed750bd169 1624 /* - Disable Error warning Interrupt */
Anna Bridge 180:96ed750bd169 1625 /* - Disable Error passive Interrupt */
Anna Bridge 180:96ed750bd169 1626 /* - Disable Bus-off Interrupt */
Anna Bridge 180:96ed750bd169 1627 /* - Disable Last error code Interrupt */
Anna Bridge 180:96ed750bd169 1628 /* - Disable Error Interrupt */
Anna Bridge 180:96ed750bd169 1629 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
Anna Bridge 180:96ed750bd169 1630 CAN_IT_EPV |
Anna Bridge 180:96ed750bd169 1631 CAN_IT_BOF |
Anna Bridge 180:96ed750bd169 1632 CAN_IT_LEC |
Anna Bridge 180:96ed750bd169 1633 CAN_IT_ERR );
<> 144:ef7eb2e8f9f7 1634 }
Anna Bridge 180:96ed750bd169 1635
Anna Bridge 180:96ed750bd169 1636 /* Change CAN state */
Anna Bridge 180:96ed750bd169 1637 if (FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 1638 {
Anna Bridge 180:96ed750bd169 1639 switch(hcan->State)
Anna Bridge 180:96ed750bd169 1640 {
Anna Bridge 180:96ed750bd169 1641 case(HAL_CAN_STATE_BUSY_TX_RX0):
Anna Bridge 180:96ed750bd169 1642 hcan->State = HAL_CAN_STATE_BUSY_TX;
Anna Bridge 180:96ed750bd169 1643 break;
Anna Bridge 180:96ed750bd169 1644 case(HAL_CAN_STATE_BUSY_RX0_RX1):
Anna Bridge 180:96ed750bd169 1645 hcan->State = HAL_CAN_STATE_BUSY_RX1;
Anna Bridge 180:96ed750bd169 1646 break;
Anna Bridge 180:96ed750bd169 1647 case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
Anna Bridge 180:96ed750bd169 1648 hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
Anna Bridge 180:96ed750bd169 1649 break;
Anna Bridge 180:96ed750bd169 1650 default: /* HAL_CAN_STATE_BUSY_RX0 */
Anna Bridge 180:96ed750bd169 1651 hcan->State = HAL_CAN_STATE_READY;
Anna Bridge 180:96ed750bd169 1652 break;
Anna Bridge 180:96ed750bd169 1653 }
<> 144:ef7eb2e8f9f7 1654 }
Anna Bridge 180:96ed750bd169 1655 else /* FIFONumber == CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 1656 {
Anna Bridge 180:96ed750bd169 1657 switch(hcan->State)
Anna Bridge 180:96ed750bd169 1658 {
Anna Bridge 180:96ed750bd169 1659 case(HAL_CAN_STATE_BUSY_TX_RX1):
Anna Bridge 180:96ed750bd169 1660 hcan->State = HAL_CAN_STATE_BUSY_TX;
Anna Bridge 180:96ed750bd169 1661 break;
Anna Bridge 180:96ed750bd169 1662 case(HAL_CAN_STATE_BUSY_RX0_RX1):
Anna Bridge 180:96ed750bd169 1663 hcan->State = HAL_CAN_STATE_BUSY_RX0;
Anna Bridge 180:96ed750bd169 1664 break;
Anna Bridge 180:96ed750bd169 1665 case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
Anna Bridge 180:96ed750bd169 1666 hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
Anna Bridge 180:96ed750bd169 1667 break;
Anna Bridge 180:96ed750bd169 1668 default: /* HAL_CAN_STATE_BUSY_RX1 */
Anna Bridge 180:96ed750bd169 1669 hcan->State = HAL_CAN_STATE_READY;
Anna Bridge 180:96ed750bd169 1670 break;
Anna Bridge 180:96ed750bd169 1671 }
<> 144:ef7eb2e8f9f7 1672 }
<> 144:ef7eb2e8f9f7 1673
<> 144:ef7eb2e8f9f7 1674 /* Receive complete callback */
<> 144:ef7eb2e8f9f7 1675 HAL_CAN_RxCpltCallback(hcan);
<> 144:ef7eb2e8f9f7 1676
<> 144:ef7eb2e8f9f7 1677 /* Return function status */
<> 144:ef7eb2e8f9f7 1678 return HAL_OK;
<> 144:ef7eb2e8f9f7 1679 }
Anna Bridge 180:96ed750bd169 1680
<> 144:ef7eb2e8f9f7 1681 /**
<> 144:ef7eb2e8f9f7 1682 * @}
<> 144:ef7eb2e8f9f7 1683 */
<> 144:ef7eb2e8f9f7 1684
<> 144:ef7eb2e8f9f7 1685 /**
<> 144:ef7eb2e8f9f7 1686 * @}
<> 144:ef7eb2e8f9f7 1687 */
<> 144:ef7eb2e8f9f7 1688
<> 144:ef7eb2e8f9f7 1689 /**
<> 144:ef7eb2e8f9f7 1690 * @}
<> 144:ef7eb2e8f9f7 1691 */
<> 144:ef7eb2e8f9f7 1692
<> 144:ef7eb2e8f9f7 1693 #endif /* defined(STM32F072xB) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) */
<> 144:ef7eb2e8f9f7 1694
<> 144:ef7eb2e8f9f7 1695 #endif /* HAL_CAN_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1696
<> 144:ef7eb2e8f9f7 1697 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/