mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_adc.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file containing functions prototypes of ADC HAL library.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F0xx_HAL_ADC_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F0xx_HAL_ADC_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
Anna Bridge 186:707f6e361f3e 47 /* Include low level driver */
Anna Bridge 186:707f6e361f3e 48 #include "stm32f0xx_ll_adc.h"
Anna Bridge 186:707f6e361f3e 49
<> 144:ef7eb2e8f9f7 50 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @addtogroup ADC
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /** @defgroup ADC_Exported_Types ADC Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief Structure definition of ADC initialization and regular group
<> 144:ef7eb2e8f9f7 65 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 66 * ADC state can be either:
<> 144:ef7eb2e8f9f7 67 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ClockPrescaler')
<> 144:ef7eb2e8f9f7 68 * - For all parameters except 'ClockPrescaler' and 'resolution': ADC enabled without conversion on going on regular group.
<> 144:ef7eb2e8f9f7 69 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
<> 144:ef7eb2e8f9f7 70 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
<> 144:ef7eb2e8f9f7 71 */
<> 144:ef7eb2e8f9f7 72 typedef struct
<> 144:ef7eb2e8f9f7 73 {
<> 144:ef7eb2e8f9f7 74 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator 14MHz) and clock prescaler.
<> 144:ef7eb2e8f9f7 75 This parameter can be a value of @ref ADC_ClockPrescaler
<> 144:ef7eb2e8f9f7 76 Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level.
<> 144:ef7eb2e8f9f7 77 Note: This parameter can be modified only if the ADC is disabled */
<> 144:ef7eb2e8f9f7 78 uint32_t Resolution; /*!< Configures the ADC resolution.
<> 144:ef7eb2e8f9f7 79 This parameter can be a value of @ref ADC_Resolution */
<> 144:ef7eb2e8f9f7 80 uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
<> 144:ef7eb2e8f9f7 81 This parameter can be a value of @ref ADC_Data_align */
<> 144:ef7eb2e8f9f7 82 uint32_t ScanConvMode; /*!< Configures the sequencer of regular group.
<> 144:ef7eb2e8f9f7 83 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
<> 144:ef7eb2e8f9f7 84 Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices):
<> 144:ef7eb2e8f9f7 85 If only 1 channel is set: Conversion is performed in single mode.
<> 144:ef7eb2e8f9f7 86 If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
<> 144:ef7eb2e8f9f7 87 Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0).
<> 144:ef7eb2e8f9f7 88 This parameter can be a value of @ref ADC_Scan_mode */
<> 144:ef7eb2e8f9f7 89 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
<> 144:ef7eb2e8f9f7 90 This parameter can be a value of @ref ADC_EOCSelection. */
<> 144:ef7eb2e8f9f7 91 uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
<> 144:ef7eb2e8f9f7 92 conversion (for regular group) has been treated by user software, using function HAL_ADC_GetValue().
<> 144:ef7eb2e8f9f7 93 This feature automatically adapts the ADC conversions trigs to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
<> 144:ef7eb2e8f9f7 94 This parameter can be set to ENABLE or DISABLE.
<> 144:ef7eb2e8f9f7 95 Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
<> 144:ef7eb2e8f9f7 96 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
<> 144:ef7eb2e8f9f7 97 and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. */
<> 144:ef7eb2e8f9f7 98 uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
<> 144:ef7eb2e8f9f7 99 This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
<> 144:ef7eb2e8f9f7 100 This parameter can be set to ENABLE or DISABLE.
<> 144:ef7eb2e8f9f7 101 Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */
<> 144:ef7eb2e8f9f7 102 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
<> 144:ef7eb2e8f9f7 103 after the selected trigger occurred (software start or external trigger).
<> 144:ef7eb2e8f9f7 104 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 105 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
<> 144:ef7eb2e8f9f7 106 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
<> 144:ef7eb2e8f9f7 107 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
<> 144:ef7eb2e8f9f7 108 This parameter can be set to ENABLE or DISABLE
<> 144:ef7eb2e8f9f7 109 Note: Number of discontinuous ranks increment is fixed to one-by-one. */
<> 144:ef7eb2e8f9f7 110 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
<> 144:ef7eb2e8f9f7 111 If set to ADC_SOFTWARE_START, external triggers are disabled.
<> 144:ef7eb2e8f9f7 112 This parameter can be a value of @ref ADC_External_trigger_source_Regular */
<> 144:ef7eb2e8f9f7 113 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
<> 144:ef7eb2e8f9f7 114 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
<> 144:ef7eb2e8f9f7 115 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
<> 144:ef7eb2e8f9f7 116 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
<> 144:ef7eb2e8f9f7 117 or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
<> 144:ef7eb2e8f9f7 118 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
<> 144:ef7eb2e8f9f7 119 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 120 uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten
<> 144:ef7eb2e8f9f7 121 This parameter has an effect on regular group only, including in DMA mode.
<> 144:ef7eb2e8f9f7 122 This parameter can be a value of @ref ADC_Overrun */
<> 144:ef7eb2e8f9f7 123 uint32_t SamplingTimeCommon; /*!< Sampling time value to be set for the selected channel.
<> 144:ef7eb2e8f9f7 124 Unit: ADC clock cycles
<> 144:ef7eb2e8f9f7 125 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
<> 144:ef7eb2e8f9f7 126 Note: On STM32F0 devices, the sampling time setting is common to all channels. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure.
<> 144:ef7eb2e8f9f7 127 This parameter can be a value of @ref ADC_sampling_times
<> 144:ef7eb2e8f9f7 128 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
<> 144:ef7eb2e8f9f7 129 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
<> 144:ef7eb2e8f9f7 130 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */
<> 144:ef7eb2e8f9f7 131 }ADC_InitTypeDef;
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /**
<> 144:ef7eb2e8f9f7 134 * @brief Structure definition of ADC channel for regular group
<> 144:ef7eb2e8f9f7 135 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 136 * ADC state can be either:
<> 144:ef7eb2e8f9f7 137 * - For all parameters: ADC disabled or enabled without conversion on going on regular group.
<> 144:ef7eb2e8f9f7 138 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
<> 144:ef7eb2e8f9f7 139 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
<> 144:ef7eb2e8f9f7 140 */
<> 144:ef7eb2e8f9f7 141 typedef struct
<> 144:ef7eb2e8f9f7 142 {
<> 144:ef7eb2e8f9f7 143 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
<> 144:ef7eb2e8f9f7 144 This parameter can be a value of @ref ADC_channels
<> 144:ef7eb2e8f9f7 145 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
<> 144:ef7eb2e8f9f7 146 uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer.
<> 144:ef7eb2e8f9f7 147 On STM32F0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...)..
<> 144:ef7eb2e8f9f7 148 Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
<> 144:ef7eb2e8f9f7 149 This parameter can be a value of @ref ADC_rank */
<> 144:ef7eb2e8f9f7 150 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
<> 144:ef7eb2e8f9f7 151 Unit: ADC clock cycles
<> 144:ef7eb2e8f9f7 152 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
<> 144:ef7eb2e8f9f7 153 This parameter can be a value of @ref ADC_sampling_times
<> 144:ef7eb2e8f9f7 154 Caution: this setting impacts the entire regular group. Therefore, call of HAL_ADC_ConfigChannel() to configure a channel can impact the configuration of other channels previously set.
<> 144:ef7eb2e8f9f7 155 Caution: Obsolete parameter. Use parameter "SamplingTimeCommon" in ADC initialization structure.
<> 144:ef7eb2e8f9f7 156 If parameter "SamplingTimeCommon" is set to a valid sampling time, parameter "SamplingTime" is discarded.
<> 144:ef7eb2e8f9f7 157 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
<> 144:ef7eb2e8f9f7 158 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
<> 144:ef7eb2e8f9f7 159 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */
<> 144:ef7eb2e8f9f7 160 }ADC_ChannelConfTypeDef;
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /**
<> 144:ef7eb2e8f9f7 163 * @brief Structure definition of ADC analog watchdog
<> 144:ef7eb2e8f9f7 164 * @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 165 * ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular group.
<> 144:ef7eb2e8f9f7 166 */
<> 144:ef7eb2e8f9f7 167 typedef struct
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all/none channels.
<> 144:ef7eb2e8f9f7 170 This parameter can be a value of @ref ADC_analog_watchdog_mode. */
<> 144:ef7eb2e8f9f7 171 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
<> 144:ef7eb2e8f9f7 172 This parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored.
<> 144:ef7eb2e8f9f7 173 This parameter can be a value of @ref ADC_channels. */
<> 144:ef7eb2e8f9f7 174 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
<> 144:ef7eb2e8f9f7 175 This parameter can be set to ENABLE or DISABLE */
<> 144:ef7eb2e8f9f7 176 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<> 144:ef7eb2e8f9f7 177 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
<> 144:ef7eb2e8f9f7 178 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<> 144:ef7eb2e8f9f7 179 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
<> 144:ef7eb2e8f9f7 180 }ADC_AnalogWDGConfTypeDef;
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /**
<> 144:ef7eb2e8f9f7 183 * @brief HAL ADC state machine: ADC states definition (bitfields)
<> 144:ef7eb2e8f9f7 184 * @note ADC state machine is managed by bitfields, state must be compared
<> 144:ef7eb2e8f9f7 185 * with bit by bit.
<> 144:ef7eb2e8f9f7 186 * For example:
<> 144:ef7eb2e8f9f7 187 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
<> 144:ef7eb2e8f9f7 188 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
<> 144:ef7eb2e8f9f7 189 */
<> 144:ef7eb2e8f9f7 190 /* States of ADC global scope */
<> 156:95d6b41a828b 191 #define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */
<> 156:95d6b41a828b 192 #define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */
<> 156:95d6b41a828b 193 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
<> 156:95d6b41a828b 194 #define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /* States of ADC errors */
<> 156:95d6b41a828b 197 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */
<> 156:95d6b41a828b 198 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */
<> 156:95d6b41a828b 199 #define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* States of ADC group regular */
<> 156:95d6b41a828b 202 #define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
<> 144:ef7eb2e8f9f7 203 external trigger, low power auto power-on, multimode ADC master control) */
<> 156:95d6b41a828b 204 #define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */
<> 156:95d6b41a828b 205 #define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */
<> 156:95d6b41a828b 206 #define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on STM32F0 device: End Of Sampling flag raised */
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* States of ADC group injected */
<> 156:95d6b41a828b 209 #define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
<> 144:ef7eb2e8f9f7 210 external trigger, low power auto power-on, multimode ADC master control) */
<> 156:95d6b41a828b 211 #define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Not available on STM32F0 device: Conversion data available on group injected */
<> 156:95d6b41a828b 212 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* States of ADC analog watchdogs */
<> 156:95d6b41a828b 215 #define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
<> 156:95d6b41a828b 216 #define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */
<> 156:95d6b41a828b 217 #define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /* States of ADC multi-mode */
<> 156:95d6b41a828b 220 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @brief ADC handle Structure definition
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226 typedef struct
<> 144:ef7eb2e8f9f7 227 {
<> 144:ef7eb2e8f9f7 228 ADC_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 ADC_InitTypeDef Init; /*!< ADC required parameters */
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 HAL_LockTypeDef Lock; /*!< ADC locking object */
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 __IO uint32_t ErrorCode; /*!< ADC Error code */
<> 144:ef7eb2e8f9f7 239 }ADC_HandleTypeDef;
<> 144:ef7eb2e8f9f7 240 /**
<> 144:ef7eb2e8f9f7 241 * @}
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /** @defgroup ADC_Exported_Constants ADC Exported Constants
<> 144:ef7eb2e8f9f7 249 * @{
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /** @defgroup ADC_Error_Code ADC Error Code
<> 144:ef7eb2e8f9f7 253 * @{
<> 144:ef7eb2e8f9f7 254 */
<> 156:95d6b41a828b 255 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
<> 156:95d6b41a828b 256 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking,
<> 144:ef7eb2e8f9f7 257 enable/disable, erroneous state */
<> 156:95d6b41a828b 258 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
<> 156:95d6b41a828b 259 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /**
<> 144:ef7eb2e8f9f7 262 * @}
<> 144:ef7eb2e8f9f7 263 */
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /** @defgroup ADC_ClockPrescaler ADC ClockPrescaler
<> 144:ef7eb2e8f9f7 266 * @{
<> 144:ef7eb2e8f9f7 267 */
<> 156:95d6b41a828b 268 #define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated HSI */
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */
<> 144:ef7eb2e8f9f7 271 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /**
<> 144:ef7eb2e8f9f7 274 * @}
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /** @defgroup ADC_Resolution ADC Resolution
<> 144:ef7eb2e8f9f7 278 * @{
<> 144:ef7eb2e8f9f7 279 */
<> 156:95d6b41a828b 280 #define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */
<> 144:ef7eb2e8f9f7 281 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */
<> 144:ef7eb2e8f9f7 282 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */
<> 144:ef7eb2e8f9f7 283 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */
<> 144:ef7eb2e8f9f7 284 /**
<> 144:ef7eb2e8f9f7 285 * @}
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /** @defgroup ADC_Data_align ADC Data_align
<> 144:ef7eb2e8f9f7 289 * @{
<> 144:ef7eb2e8f9f7 290 */
<> 156:95d6b41a828b 291 #define ADC_DATAALIGN_RIGHT (0x00000000U)
<> 144:ef7eb2e8f9f7 292 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN)
<> 144:ef7eb2e8f9f7 293 /**
<> 144:ef7eb2e8f9f7 294 * @}
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /** @defgroup ADC_Scan_mode ADC Scan mode
<> 144:ef7eb2e8f9f7 298 * @{
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300 /* Note: Scan mode values must be compatible with other STM32 devices having */
<> 144:ef7eb2e8f9f7 301 /* a configurable sequencer. */
<> 144:ef7eb2e8f9f7 302 /* Scan direction setting values are defined by taking in account */
<> 144:ef7eb2e8f9f7 303 /* already defined values for other STM32 devices: */
<> 156:95d6b41a828b 304 /* ADC_SCAN_DISABLE (0x00000000U) */
<> 156:95d6b41a828b 305 /* ADC_SCAN_ENABLE (0x00000001U) */
<> 144:ef7eb2e8f9f7 306 /* Scan direction forward is considered as default setting equivalent */
<> 144:ef7eb2e8f9f7 307 /* to scan enable. */
<> 144:ef7eb2e8f9f7 308 /* Scan direction backward is considered as additional setting. */
<> 144:ef7eb2e8f9f7 309 /* In case of migration from another STM32 device, the user will be */
<> 144:ef7eb2e8f9f7 310 /* warned of change of setting choices with assert check. */
<> 156:95d6b41a828b 311 #define ADC_SCAN_DIRECTION_FORWARD (0x00000001U) /*!< Scan direction forward: from channel 0 to channel 18 */
<> 156:95d6b41a828b 312 #define ADC_SCAN_DIRECTION_BACKWARD (0x00000002U) /*!< Scan direction backward: from channel 18 to channel 0 */
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 #define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /**
<> 144:ef7eb2e8f9f7 317 * @}
<> 144:ef7eb2e8f9f7 318 */
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular
<> 144:ef7eb2e8f9f7 321 * @{
<> 144:ef7eb2e8f9f7 322 */
<> 156:95d6b41a828b 323 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U)
<> 144:ef7eb2e8f9f7 324 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0)
<> 144:ef7eb2e8f9f7 325 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1)
<> 144:ef7eb2e8f9f7 326 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN)
<> 144:ef7eb2e8f9f7 327 /**
<> 144:ef7eb2e8f9f7 328 * @}
<> 144:ef7eb2e8f9f7 329 */
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /** @defgroup ADC_EOCSelection ADC EOCSelection
<> 144:ef7eb2e8f9f7 332 * @{
<> 144:ef7eb2e8f9f7 333 */
<> 144:ef7eb2e8f9f7 334 #define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
<> 144:ef7eb2e8f9f7 335 #define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
<> 144:ef7eb2e8f9f7 336 /**
<> 144:ef7eb2e8f9f7 337 * @}
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /** @defgroup ADC_Overrun ADC Overrun
<> 144:ef7eb2e8f9f7 341 * @{
<> 144:ef7eb2e8f9f7 342 */
<> 156:95d6b41a828b 343 #define ADC_OVR_DATA_OVERWRITTEN (0x00000000U)
<> 156:95d6b41a828b 344 #define ADC_OVR_DATA_PRESERVED (0x00000001U)
<> 144:ef7eb2e8f9f7 345 /**
<> 144:ef7eb2e8f9f7 346 * @}
<> 144:ef7eb2e8f9f7 347 */
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /** @defgroup ADC_rank ADC rank
<> 144:ef7eb2e8f9f7 350 * @{
<> 144:ef7eb2e8f9f7 351 */
<> 156:95d6b41a828b 352 #define ADC_RANK_CHANNEL_NUMBER (0x00001000U) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
<> 156:95d6b41a828b 353 #define ADC_RANK_NONE (0x00001001U) /*!< Disable the selected rank (selected channel) from sequencer */
<> 144:ef7eb2e8f9f7 354 /**
<> 144:ef7eb2e8f9f7 355 * @}
<> 144:ef7eb2e8f9f7 356 */
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /** @defgroup ADC_sampling_times ADC sampling times
<> 144:ef7eb2e8f9f7 359 * @{
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361 /* Note: Parameter "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit */
<> 144:ef7eb2e8f9f7 362 /* to distinguish this parameter versus reset value 0x00000000, */
<> 144:ef7eb2e8f9f7 363 /* in the context of management of parameters "SamplingTimeCommon" */
<> 144:ef7eb2e8f9f7 364 /* and "SamplingTime" (obsolete)). */
<> 156:95d6b41a828b 365 #define ADC_SAMPLETIME_1CYCLE_5 (0x10000000U) /*!< Sampling time 1.5 ADC clock cycle */
<> 144:ef7eb2e8f9f7 366 #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR_SMP_0) /*!< Sampling time 7.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 367 #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR_SMP_1) /*!< Sampling time 13.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 368 #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)) /*!< Sampling time 28.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 369 #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR_SMP_2) /*!< Sampling time 41.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 370 #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0)) /*!< Sampling time 55.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 371 #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1)) /*!< Sampling time 71.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 372 #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR_SMP) /*!< Sampling time 239.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 373 /**
<> 144:ef7eb2e8f9f7 374 * @}
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
<> 144:ef7eb2e8f9f7 378 * @{
<> 144:ef7eb2e8f9f7 379 */
<> 156:95d6b41a828b 380 #define ADC_ANALOGWATCHDOG_NONE ( 0x00000000U)
<> 144:ef7eb2e8f9f7 381 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN))
<> 144:ef7eb2e8f9f7 382 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN)
<> 144:ef7eb2e8f9f7 383 /**
<> 144:ef7eb2e8f9f7 384 * @}
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /** @defgroup ADC_Event_type ADC Event type
<> 144:ef7eb2e8f9f7 388 * @{
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog 1 event */
<> 144:ef7eb2e8f9f7 391 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */
<> 144:ef7eb2e8f9f7 392 /**
<> 144:ef7eb2e8f9f7 393 * @}
<> 144:ef7eb2e8f9f7 394 */
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /** @defgroup ADC_interrupts_definition ADC interrupts definition
<> 144:ef7eb2e8f9f7 397 * @{
<> 144:ef7eb2e8f9f7 398 */
<> 144:ef7eb2e8f9f7 399 #define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog interrupt source */
<> 144:ef7eb2e8f9f7 400 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
<> 144:ef7eb2e8f9f7 401 #define ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC End of Regular sequence of Conversions interrupt source */
<> 144:ef7eb2e8f9f7 402 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of Regular Conversion interrupt source */
<> 144:ef7eb2e8f9f7 403 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of Sampling interrupt source */
<> 144:ef7eb2e8f9f7 404 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */
<> 144:ef7eb2e8f9f7 405 /**
<> 144:ef7eb2e8f9f7 406 * @}
<> 144:ef7eb2e8f9f7 407 */
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /** @defgroup ADC_flags_definition ADC flags definition
<> 144:ef7eb2e8f9f7 410 * @{
<> 144:ef7eb2e8f9f7 411 */
<> 144:ef7eb2e8f9f7 412 #define ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC Analog watchdog flag */
<> 144:ef7eb2e8f9f7 413 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
<> 144:ef7eb2e8f9f7 414 #define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */
<> 144:ef7eb2e8f9f7 415 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
<> 144:ef7eb2e8f9f7 416 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
<> 144:ef7eb2e8f9f7 417 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
<> 144:ef7eb2e8f9f7 418 /**
<> 144:ef7eb2e8f9f7 419 * @}
<> 144:ef7eb2e8f9f7 420 */
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /**
<> 144:ef7eb2e8f9f7 423 * @}
<> 144:ef7eb2e8f9f7 424 */
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /** @addtogroup ADC_Private_Constants ADC Private Constants
<> 144:ef7eb2e8f9f7 430 * @{
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular
<> 144:ef7eb2e8f9f7 434 * @{
<> 144:ef7eb2e8f9f7 435 */
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /* List of external triggers of regular group for ADC1: */
<> 144:ef7eb2e8f9f7 438 /* (used internally by HAL driver. To not use into HAL structure parameters) */
<> 156:95d6b41a828b 439 #define ADC1_2_EXTERNALTRIG_T1_TRGO (0x00000000U)
<> 144:ef7eb2e8f9f7 440 #define ADC1_2_EXTERNALTRIG_T1_CC4 ((uint32_t)ADC_CFGR1_EXTSEL_0)
<> 144:ef7eb2e8f9f7 441 #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_1)
<> 144:ef7eb2e8f9f7 442 #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0))
<> 144:ef7eb2e8f9f7 443 #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_2)
<> 144:ef7eb2e8f9f7 444 /**
<> 144:ef7eb2e8f9f7 445 * @}
<> 144:ef7eb2e8f9f7 446 */
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */
<> 144:ef7eb2e8f9f7 449 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /**
<> 144:ef7eb2e8f9f7 452 * @}
<> 144:ef7eb2e8f9f7 453 */
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /** @defgroup ADC_Exported_Macros ADC Exported Macros
<> 144:ef7eb2e8f9f7 459 * @{
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461 /* Macro for internal HAL driver usage, and possibly can be used into code of */
<> 144:ef7eb2e8f9f7 462 /* final user. */
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /**
<> 144:ef7eb2e8f9f7 465 * @brief Enable the ADC peripheral
Anna Bridge 180:96ed750bd169 466 * @param __HANDLE__ ADC handle
<> 144:ef7eb2e8f9f7 467 * @retval None
<> 144:ef7eb2e8f9f7 468 */
<> 144:ef7eb2e8f9f7 469 #define __HAL_ADC_ENABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 470 ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /**
<> 144:ef7eb2e8f9f7 473 * @brief Disable the ADC peripheral
Anna Bridge 180:96ed750bd169 474 * @param __HANDLE__ ADC handle
<> 144:ef7eb2e8f9f7 475 * @retval None
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477 #define __HAL_ADC_DISABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 478 do{ \
<> 144:ef7eb2e8f9f7 479 (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \
<> 144:ef7eb2e8f9f7 480 __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
<> 144:ef7eb2e8f9f7 481 } while(0)
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /**
<> 144:ef7eb2e8f9f7 484 * @brief Enable the ADC end of conversion interrupt.
Anna Bridge 180:96ed750bd169 485 * @param __HANDLE__ ADC handle
Anna Bridge 180:96ed750bd169 486 * @param __INTERRUPT__ ADC Interrupt
<> 144:ef7eb2e8f9f7 487 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 488 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<> 144:ef7eb2e8f9f7 489 * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
<> 144:ef7eb2e8f9f7 490 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<> 144:ef7eb2e8f9f7 491 * @arg ADC_IT_OVR: ADC overrun interrupt source
<> 144:ef7eb2e8f9f7 492 * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
<> 144:ef7eb2e8f9f7 493 * @arg ADC_IT_RDY: ADC Ready interrupt source
<> 144:ef7eb2e8f9f7 494 * @retval None
<> 144:ef7eb2e8f9f7 495 */
<> 144:ef7eb2e8f9f7 496 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
<> 144:ef7eb2e8f9f7 497 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /**
<> 144:ef7eb2e8f9f7 500 * @brief Disable the ADC end of conversion interrupt.
Anna Bridge 180:96ed750bd169 501 * @param __HANDLE__ ADC handle
Anna Bridge 180:96ed750bd169 502 * @param __INTERRUPT__ ADC Interrupt
<> 144:ef7eb2e8f9f7 503 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 504 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<> 144:ef7eb2e8f9f7 505 * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
<> 144:ef7eb2e8f9f7 506 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<> 144:ef7eb2e8f9f7 507 * @arg ADC_IT_OVR: ADC overrun interrupt source
<> 144:ef7eb2e8f9f7 508 * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
<> 144:ef7eb2e8f9f7 509 * @arg ADC_IT_RDY: ADC Ready interrupt source
<> 144:ef7eb2e8f9f7 510 * @retval None
<> 144:ef7eb2e8f9f7 511 */
<> 144:ef7eb2e8f9f7 512 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
<> 144:ef7eb2e8f9f7 513 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /** @brief Checks if the specified ADC interrupt source is enabled or disabled.
Anna Bridge 180:96ed750bd169 516 * @param __HANDLE__ ADC handle
Anna Bridge 180:96ed750bd169 517 * @param __INTERRUPT__ ADC interrupt source to check
<> 144:ef7eb2e8f9f7 518 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 519 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<> 144:ef7eb2e8f9f7 520 * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
<> 144:ef7eb2e8f9f7 521 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<> 144:ef7eb2e8f9f7 522 * @arg ADC_IT_OVR: ADC overrun interrupt source
<> 144:ef7eb2e8f9f7 523 * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
<> 144:ef7eb2e8f9f7 524 * @arg ADC_IT_RDY: ADC Ready interrupt source
<> 144:ef7eb2e8f9f7 525 * @retval State ofinterruption (SET or RESET)
<> 144:ef7eb2e8f9f7 526 */
<> 144:ef7eb2e8f9f7 527 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
<> 144:ef7eb2e8f9f7 528 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /**
<> 144:ef7eb2e8f9f7 531 * @brief Get the selected ADC's flag status.
Anna Bridge 180:96ed750bd169 532 * @param __HANDLE__ ADC handle
Anna Bridge 180:96ed750bd169 533 * @param __FLAG__ ADC flag
<> 144:ef7eb2e8f9f7 534 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 535 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
<> 144:ef7eb2e8f9f7 536 * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
<> 144:ef7eb2e8f9f7 537 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
<> 144:ef7eb2e8f9f7 538 * @arg ADC_FLAG_OVR: ADC overrun flag
<> 144:ef7eb2e8f9f7 539 * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
<> 144:ef7eb2e8f9f7 540 * @arg ADC_FLAG_RDY: ADC Ready flag
<> 144:ef7eb2e8f9f7 541 * @retval None
<> 144:ef7eb2e8f9f7 542 */
<> 144:ef7eb2e8f9f7 543 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
<> 144:ef7eb2e8f9f7 544 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /**
<> 144:ef7eb2e8f9f7 547 * @brief Clear the ADC's pending flags
Anna Bridge 180:96ed750bd169 548 * @param __HANDLE__ ADC handle
Anna Bridge 180:96ed750bd169 549 * @param __FLAG__ ADC flag
<> 144:ef7eb2e8f9f7 550 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 551 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
<> 144:ef7eb2e8f9f7 552 * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
<> 144:ef7eb2e8f9f7 553 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
<> 144:ef7eb2e8f9f7 554 * @arg ADC_FLAG_OVR: ADC overrun flag
<> 144:ef7eb2e8f9f7 555 * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
<> 144:ef7eb2e8f9f7 556 * @arg ADC_FLAG_RDY: ADC Ready flag
<> 144:ef7eb2e8f9f7 557 * @retval None
<> 144:ef7eb2e8f9f7 558 */
<> 144:ef7eb2e8f9f7 559 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
<> 144:ef7eb2e8f9f7 560 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
<> 144:ef7eb2e8f9f7 561 (((__HANDLE__)->Instance->ISR) = (__FLAG__))
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /** @brief Reset ADC handle state
Anna Bridge 180:96ed750bd169 564 * @param __HANDLE__ ADC handle
<> 144:ef7eb2e8f9f7 565 * @retval None
<> 144:ef7eb2e8f9f7 566 */
<> 144:ef7eb2e8f9f7 567 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 568 ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /**
<> 144:ef7eb2e8f9f7 571 * @}
<> 144:ef7eb2e8f9f7 572 */
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /** @defgroup ADC_Private_Macros ADC Private Macros
<> 144:ef7eb2e8f9f7 578 * @{
<> 144:ef7eb2e8f9f7 579 */
<> 144:ef7eb2e8f9f7 580 /* Macro reserved for internal HAL driver usage, not intended to be used in */
<> 144:ef7eb2e8f9f7 581 /* code of final user. */
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /**
<> 144:ef7eb2e8f9f7 585 * @brief Verification of hardware constraints before ADC can be enabled
Anna Bridge 180:96ed750bd169 586 * @param __HANDLE__ ADC handle
<> 144:ef7eb2e8f9f7 587 * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
<> 144:ef7eb2e8f9f7 588 */
<> 144:ef7eb2e8f9f7 589 #define ADC_ENABLING_CONDITIONS(__HANDLE__) \
<> 144:ef7eb2e8f9f7 590 (( ( ((__HANDLE__)->Instance->CR) & \
<> 144:ef7eb2e8f9f7 591 (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) \
<> 144:ef7eb2e8f9f7 592 ) == RESET \
<> 144:ef7eb2e8f9f7 593 ) ? SET : RESET)
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /**
<> 144:ef7eb2e8f9f7 596 * @brief Verification of hardware constraints before ADC can be disabled
Anna Bridge 180:96ed750bd169 597 * @param __HANDLE__ ADC handle
<> 144:ef7eb2e8f9f7 598 * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
<> 144:ef7eb2e8f9f7 599 */
<> 144:ef7eb2e8f9f7 600 #define ADC_DISABLING_CONDITIONS(__HANDLE__) \
<> 144:ef7eb2e8f9f7 601 (( ( ((__HANDLE__)->Instance->CR) & \
<> 144:ef7eb2e8f9f7 602 (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \
<> 144:ef7eb2e8f9f7 603 ) ? SET : RESET)
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /**
<> 144:ef7eb2e8f9f7 606 * @brief Verification of ADC state: enabled or disabled
Anna Bridge 180:96ed750bd169 607 * @param __HANDLE__ ADC handle
<> 144:ef7eb2e8f9f7 608 * @retval SET (ADC enabled) or RESET (ADC disabled)
<> 144:ef7eb2e8f9f7 609 */
<> 144:ef7eb2e8f9f7 610 /* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are */
<> 144:ef7eb2e8f9f7 611 /* performed automatically by hardware and flag ADC_FLAG_RDY is not */
<> 144:ef7eb2e8f9f7 612 /* set. */
<> 144:ef7eb2e8f9f7 613 #define ADC_IS_ENABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 614 (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
<> 144:ef7eb2e8f9f7 615 (((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) || \
<> 144:ef7eb2e8f9f7 616 ((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_AUTOFF) == ADC_CFGR1_AUTOFF) ) \
<> 144:ef7eb2e8f9f7 617 ) ? SET : RESET)
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /**
<> 144:ef7eb2e8f9f7 620 * @brief Test if conversion trigger of regular group is software start
<> 144:ef7eb2e8f9f7 621 * or external trigger.
Anna Bridge 180:96ed750bd169 622 * @param __HANDLE__ ADC handle
<> 144:ef7eb2e8f9f7 623 * @retval SET (software start) or RESET (external trigger)
<> 144:ef7eb2e8f9f7 624 */
<> 144:ef7eb2e8f9f7 625 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
<> 144:ef7eb2e8f9f7 626 (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /**
<> 144:ef7eb2e8f9f7 629 * @brief Check if no conversion on going on regular group
Anna Bridge 180:96ed750bd169 630 * @param __HANDLE__ ADC handle
<> 144:ef7eb2e8f9f7 631 * @retval SET (conversion is on going) or RESET (no conversion is on going)
<> 144:ef7eb2e8f9f7 632 */
<> 144:ef7eb2e8f9f7 633 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
<> 144:ef7eb2e8f9f7 634 (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
<> 144:ef7eb2e8f9f7 635 ) ? RESET : SET)
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /**
<> 144:ef7eb2e8f9f7 638 * @brief Returns resolution bits in CFGR1 register: RES[1:0].
<> 144:ef7eb2e8f9f7 639 * Returned value is among parameters to @ref ADC_Resolution.
Anna Bridge 180:96ed750bd169 640 * @param __HANDLE__ ADC handle
<> 144:ef7eb2e8f9f7 641 * @retval None
<> 144:ef7eb2e8f9f7 642 */
<> 144:ef7eb2e8f9f7 643 #define ADC_GET_RESOLUTION(__HANDLE__) \
<> 144:ef7eb2e8f9f7 644 (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /**
<> 144:ef7eb2e8f9f7 647 * @brief Returns ADC sample time bits in SMPR register: SMP[2:0].
<> 144:ef7eb2e8f9f7 648 * Returned value is among parameters to @ref ADC_Resolution.
Anna Bridge 180:96ed750bd169 649 * @param __HANDLE__ ADC handle
<> 144:ef7eb2e8f9f7 650 * @retval None
<> 144:ef7eb2e8f9f7 651 */
<> 144:ef7eb2e8f9f7 652 #define ADC_GET_SAMPLINGTIME(__HANDLE__) \
<> 144:ef7eb2e8f9f7 653 (((__HANDLE__)->Instance->SMPR) & ADC_SMPR_SMP)
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 /**
<> 144:ef7eb2e8f9f7 656 * @brief Simultaneously clears and sets specific bits of the handle State
<> 144:ef7eb2e8f9f7 657 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
<> 144:ef7eb2e8f9f7 658 * the first parameter is the ADC handle State, the second parameter is the
<> 144:ef7eb2e8f9f7 659 * bit field to clear, the third and last parameter is the bit field to set.
<> 144:ef7eb2e8f9f7 660 * @retval None
<> 144:ef7eb2e8f9f7 661 */
<> 144:ef7eb2e8f9f7 662 #define ADC_STATE_CLR_SET MODIFY_REG
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /**
<> 144:ef7eb2e8f9f7 665 * @brief Clear ADC error code (set it to error code: "no error")
Anna Bridge 180:96ed750bd169 666 * @param __HANDLE__ ADC handle
<> 144:ef7eb2e8f9f7 667 * @retval None
<> 144:ef7eb2e8f9f7 668 */
<> 144:ef7eb2e8f9f7 669 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 670 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /**
<> 144:ef7eb2e8f9f7 674 * @brief Configure the channel number into channel selection register
Anna Bridge 180:96ed750bd169 675 * @param _CHANNEL_ ADC Channel
<> 144:ef7eb2e8f9f7 676 * @retval None
<> 144:ef7eb2e8f9f7 677 */
<> 144:ef7eb2e8f9f7 678 /* This function converts ADC channels from numbers (see defgroup ADC_channels)
<> 144:ef7eb2e8f9f7 679 to bitfields, to get the equivalence of CMSIS channels:
<> 144:ef7eb2e8f9f7 680 ADC_CHANNEL_0 ((uint32_t) ADC_CHSELR_CHSEL0)
<> 144:ef7eb2e8f9f7 681 ADC_CHANNEL_1 ((uint32_t) ADC_CHSELR_CHSEL1)
<> 144:ef7eb2e8f9f7 682 ADC_CHANNEL_2 ((uint32_t) ADC_CHSELR_CHSEL2)
<> 144:ef7eb2e8f9f7 683 ADC_CHANNEL_3 ((uint32_t) ADC_CHSELR_CHSEL3)
<> 144:ef7eb2e8f9f7 684 ADC_CHANNEL_4 ((uint32_t) ADC_CHSELR_CHSEL4)
<> 144:ef7eb2e8f9f7 685 ADC_CHANNEL_5 ((uint32_t) ADC_CHSELR_CHSEL5)
<> 144:ef7eb2e8f9f7 686 ADC_CHANNEL_6 ((uint32_t) ADC_CHSELR_CHSEL6)
<> 144:ef7eb2e8f9f7 687 ADC_CHANNEL_7 ((uint32_t) ADC_CHSELR_CHSEL7)
<> 144:ef7eb2e8f9f7 688 ADC_CHANNEL_8 ((uint32_t) ADC_CHSELR_CHSEL8)
<> 144:ef7eb2e8f9f7 689 ADC_CHANNEL_9 ((uint32_t) ADC_CHSELR_CHSEL9)
<> 144:ef7eb2e8f9f7 690 ADC_CHANNEL_10 ((uint32_t) ADC_CHSELR_CHSEL10)
<> 144:ef7eb2e8f9f7 691 ADC_CHANNEL_11 ((uint32_t) ADC_CHSELR_CHSEL11)
<> 144:ef7eb2e8f9f7 692 ADC_CHANNEL_12 ((uint32_t) ADC_CHSELR_CHSEL12)
<> 144:ef7eb2e8f9f7 693 ADC_CHANNEL_13 ((uint32_t) ADC_CHSELR_CHSEL13)
<> 144:ef7eb2e8f9f7 694 ADC_CHANNEL_14 ((uint32_t) ADC_CHSELR_CHSEL14)
<> 144:ef7eb2e8f9f7 695 ADC_CHANNEL_15 ((uint32_t) ADC_CHSELR_CHSEL15)
<> 144:ef7eb2e8f9f7 696 ADC_CHANNEL_16 ((uint32_t) ADC_CHSELR_CHSEL16)
<> 144:ef7eb2e8f9f7 697 ADC_CHANNEL_17 ((uint32_t) ADC_CHSELR_CHSEL17)
<> 144:ef7eb2e8f9f7 698 ADC_CHANNEL_18 ((uint32_t) ADC_CHSELR_CHSEL18)
<> 144:ef7eb2e8f9f7 699 */
<> 144:ef7eb2e8f9f7 700 #define ADC_CHSELR_CHANNEL(_CHANNEL_) \
<> 144:ef7eb2e8f9f7 701 ( 1U << (_CHANNEL_))
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /**
<> 144:ef7eb2e8f9f7 704 * @brief Set the ADC's sample time
Anna Bridge 180:96ed750bd169 705 * @param _SAMPLETIME_ Sample time parameter.
<> 144:ef7eb2e8f9f7 706 * @retval None
<> 144:ef7eb2e8f9f7 707 */
<> 144:ef7eb2e8f9f7 708 /* Note: ADC sampling time set using mask ADC_SMPR_SMP due to parameter */
<> 144:ef7eb2e8f9f7 709 /* "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit (bit used to */
<> 144:ef7eb2e8f9f7 710 /* distinguish this parameter versus reset value 0x00000000, */
<> 144:ef7eb2e8f9f7 711 /* in the context of management of parameters "SamplingTimeCommon" */
<> 144:ef7eb2e8f9f7 712 /* and "SamplingTime" (obsolete)). */
<> 144:ef7eb2e8f9f7 713 #define ADC_SMPR_SET(_SAMPLETIME_) \
<> 144:ef7eb2e8f9f7 714 ((_SAMPLETIME_) & (ADC_SMPR_SMP))
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716 /**
<> 144:ef7eb2e8f9f7 717 * @brief Set the Analog Watchdog 1 channel.
Anna Bridge 180:96ed750bd169 718 * @param _CHANNEL_ channel to be monitored by Analog Watchdog 1.
<> 144:ef7eb2e8f9f7 719 * @retval None
<> 144:ef7eb2e8f9f7 720 */
<> 144:ef7eb2e8f9f7 721 #define ADC_CFGR_AWDCH(_CHANNEL_) \
<> 156:95d6b41a828b 722 ((_CHANNEL_) << 26U)
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /**
<> 144:ef7eb2e8f9f7 725 * @brief Enable ADC discontinuous conversion mode for regular group
Anna Bridge 180:96ed750bd169 726 * @param _REG_DISCONTINUOUS_MODE_ Regular discontinuous mode.
<> 144:ef7eb2e8f9f7 727 * @retval None
<> 144:ef7eb2e8f9f7 728 */
<> 144:ef7eb2e8f9f7 729 #define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \
<> 156:95d6b41a828b 730 ((_REG_DISCONTINUOUS_MODE_) << 16U)
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 /**
<> 144:ef7eb2e8f9f7 733 * @brief Enable the ADC auto off mode.
Anna Bridge 180:96ed750bd169 734 * @param _AUTOOFF_ Auto off bit enable or disable.
<> 144:ef7eb2e8f9f7 735 * @retval None
<> 144:ef7eb2e8f9f7 736 */
<> 144:ef7eb2e8f9f7 737 #define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \
<> 156:95d6b41a828b 738 ((_AUTOOFF_) << 15U)
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 /**
<> 144:ef7eb2e8f9f7 741 * @brief Enable the ADC auto delay mode.
Anna Bridge 180:96ed750bd169 742 * @param _AUTOWAIT_ Auto delay bit enable or disable.
<> 144:ef7eb2e8f9f7 743 * @retval None
<> 144:ef7eb2e8f9f7 744 */
<> 144:ef7eb2e8f9f7 745 #define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \
<> 156:95d6b41a828b 746 ((_AUTOWAIT_) << 14U)
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /**
<> 144:ef7eb2e8f9f7 749 * @brief Enable ADC continuous conversion mode.
Anna Bridge 180:96ed750bd169 750 * @param _CONTINUOUS_MODE_ Continuous mode.
<> 144:ef7eb2e8f9f7 751 * @retval None
<> 144:ef7eb2e8f9f7 752 */
<> 144:ef7eb2e8f9f7 753 #define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \
<> 156:95d6b41a828b 754 ((_CONTINUOUS_MODE_) << 13U)
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 /**
<> 144:ef7eb2e8f9f7 757 * @brief Enable ADC overrun mode.
Anna Bridge 180:96ed750bd169 758 * @param _OVERRUN_MODE_ Overrun mode.
<> 144:ef7eb2e8f9f7 759 * @retval Overun bit setting to be programmed into CFGR register
<> 144:ef7eb2e8f9f7 760 */
<> 144:ef7eb2e8f9f7 761 /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */
<> 144:ef7eb2e8f9f7 762 /* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */
<> 144:ef7eb2e8f9f7 763 /* as the default case to be compliant with other STM32 devices. */
<> 144:ef7eb2e8f9f7 764 #define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \
<> 144:ef7eb2e8f9f7 765 ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \
<> 144:ef7eb2e8f9f7 766 )? (ADC_CFGR1_OVRMOD) : (0x00000000) \
<> 144:ef7eb2e8f9f7 767 )
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /**
<> 144:ef7eb2e8f9f7 770 * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
Anna Bridge 180:96ed750bd169 771 * @param _SCAN_MODE_ Scan conversion mode.
<> 144:ef7eb2e8f9f7 772 * @retval None
<> 144:ef7eb2e8f9f7 773 */
<> 144:ef7eb2e8f9f7 774 /* Note: Scan mode set using this macro (instead of parameter direct set) */
<> 144:ef7eb2e8f9f7 775 /* due to different modes on other STM32 devices: to avoid any */
<> 144:ef7eb2e8f9f7 776 /* unwanted setting, the exact parameter corresponding to the device */
<> 144:ef7eb2e8f9f7 777 /* must be passed to this macro. */
<> 144:ef7eb2e8f9f7 778 #define ADC_SCANDIR(_SCAN_MODE_) \
<> 144:ef7eb2e8f9f7 779 ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \
<> 144:ef7eb2e8f9f7 780 )? (ADC_CFGR1_SCANDIR) : (0x00000000) \
<> 144:ef7eb2e8f9f7 781 )
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 /**
<> 144:ef7eb2e8f9f7 784 * @brief Enable the ADC DMA continuous request.
Anna Bridge 180:96ed750bd169 785 * @param _DMACONTREQ_MODE_ DMA continuous request mode.
<> 144:ef7eb2e8f9f7 786 * @retval None
<> 144:ef7eb2e8f9f7 787 */
<> 144:ef7eb2e8f9f7 788 #define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \
<> 156:95d6b41a828b 789 ((_DMACONTREQ_MODE_) << 1U)
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 /**
<> 144:ef7eb2e8f9f7 792 * @brief Configure the analog watchdog high threshold into register TR.
Anna Bridge 180:96ed750bd169 793 * @param _Threshold_ Threshold value
<> 144:ef7eb2e8f9f7 794 * @retval None
<> 144:ef7eb2e8f9f7 795 */
<> 144:ef7eb2e8f9f7 796 #define ADC_TRX_HIGHTHRESHOLD(_Threshold_) \
<> 156:95d6b41a828b 797 ((_Threshold_) << 16U)
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 /**
<> 144:ef7eb2e8f9f7 800 * @brief Shift the AWD threshold in function of the selected ADC resolution.
<> 144:ef7eb2e8f9f7 801 * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
<> 144:ef7eb2e8f9f7 802 * If resolution 12 bits, no shift.
<> 144:ef7eb2e8f9f7 803 * If resolution 10 bits, shift of 2 ranks on the left.
<> 144:ef7eb2e8f9f7 804 * If resolution 8 bits, shift of 4 ranks on the left.
<> 144:ef7eb2e8f9f7 805 * If resolution 6 bits, shift of 6 ranks on the left.
<> 144:ef7eb2e8f9f7 806 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
Anna Bridge 180:96ed750bd169 807 * @param __HANDLE__ ADC handle
Anna Bridge 180:96ed750bd169 808 * @param _Threshold_ Value to be shifted
<> 144:ef7eb2e8f9f7 809 * @retval None
<> 144:ef7eb2e8f9f7 810 */
<> 144:ef7eb2e8f9f7 811 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
<> 156:95d6b41a828b 812 ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2))
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \
<> 144:ef7eb2e8f9f7 816 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
<> 144:ef7eb2e8f9f7 817 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) )
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
<> 144:ef7eb2e8f9f7 820 ((RESOLUTION) == ADC_RESOLUTION_10B) || \
<> 144:ef7eb2e8f9f7 821 ((RESOLUTION) == ADC_RESOLUTION_8B) || \
<> 144:ef7eb2e8f9f7 822 ((RESOLUTION) == ADC_RESOLUTION_6B) )
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
<> 144:ef7eb2e8f9f7 825 ((ALIGN) == ADC_DATAALIGN_LEFT) )
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \
<> 144:ef7eb2e8f9f7 828 ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD) )
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
<> 144:ef7eb2e8f9f7 831 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
<> 144:ef7eb2e8f9f7 832 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
<> 144:ef7eb2e8f9f7 833 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
Anna Bridge 180:96ed750bd169 836 ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) )
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
<> 144:ef7eb2e8f9f7 839 ((OVR) == ADC_OVR_DATA_OVERWRITTEN) )
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 #define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \
<> 144:ef7eb2e8f9f7 842 ((WATCHDOG) == ADC_RANK_NONE) )
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
<> 144:ef7eb2e8f9f7 845 ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
<> 144:ef7eb2e8f9f7 846 ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \
<> 144:ef7eb2e8f9f7 847 ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \
<> 144:ef7eb2e8f9f7 848 ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \
<> 144:ef7eb2e8f9f7 849 ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \
<> 144:ef7eb2e8f9f7 850 ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \
<> 144:ef7eb2e8f9f7 851 ((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
<> 144:ef7eb2e8f9f7 854 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
<> 144:ef7eb2e8f9f7 855 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) )
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
<> 144:ef7eb2e8f9f7 858 ((EVENT) == ADC_OVR_EVENT) )
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 /** @defgroup ADC_range_verification ADC range verification
<> 144:ef7eb2e8f9f7 861 * in function of ADC resolution selected (12, 10, 8 or 6 bits)
<> 144:ef7eb2e8f9f7 862 * @{
<> 144:ef7eb2e8f9f7 863 */
<> 144:ef7eb2e8f9f7 864 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
<> 156:95d6b41a828b 865 ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || \
<> 156:95d6b41a828b 866 (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || \
<> 156:95d6b41a828b 867 (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= (0x00FFU))) || \
<> 156:95d6b41a828b 868 (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= (0x003FU))) )
<> 144:ef7eb2e8f9f7 869 /**
<> 144:ef7eb2e8f9f7 870 * @}
<> 144:ef7eb2e8f9f7 871 */
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /** @defgroup ADC_regular_rank_verification ADC regular rank verification
<> 144:ef7eb2e8f9f7 874 * @{
<> 144:ef7eb2e8f9f7 875 */
<> 156:95d6b41a828b 876 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= (1U)) && ((RANK) <= (16U)))
<> 144:ef7eb2e8f9f7 877 /**
<> 144:ef7eb2e8f9f7 878 * @}
<> 144:ef7eb2e8f9f7 879 */
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 /**
<> 144:ef7eb2e8f9f7 882 * @}
<> 144:ef7eb2e8f9f7 883 */
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885 /* Include ADC HAL Extension module */
<> 144:ef7eb2e8f9f7 886 #include "stm32f0xx_hal_adc_ex.h"
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 889 /** @addtogroup ADC_Exported_Functions
<> 144:ef7eb2e8f9f7 890 * @{
<> 144:ef7eb2e8f9f7 891 */
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 /** @addtogroup ADC_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 894 * @{
<> 144:ef7eb2e8f9f7 895 */
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 /* Initialization and de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 899 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 900 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
<> 144:ef7eb2e8f9f7 901 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 902 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 903 /**
<> 144:ef7eb2e8f9f7 904 * @}
<> 144:ef7eb2e8f9f7 905 */
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 /** @addtogroup ADC_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 910 * @{
<> 144:ef7eb2e8f9f7 911 */
<> 144:ef7eb2e8f9f7 912
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 915 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 916 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 917 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 918 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 /* Non-blocking mode: Interruption */
<> 144:ef7eb2e8f9f7 921 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 922 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /* Non-blocking mode: DMA */
<> 144:ef7eb2e8f9f7 925 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
<> 144:ef7eb2e8f9f7 926 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 927
<> 144:ef7eb2e8f9f7 928 /* ADC retrieve conversion value intended to be used with polling or interruption */
<> 144:ef7eb2e8f9f7 929 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 930
<> 144:ef7eb2e8f9f7 931 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
<> 144:ef7eb2e8f9f7 932 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 933 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 934 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 935 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 936 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
<> 144:ef7eb2e8f9f7 937 /**
<> 144:ef7eb2e8f9f7 938 * @}
<> 144:ef7eb2e8f9f7 939 */
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 943 /** @addtogroup ADC_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 944 * @{
<> 144:ef7eb2e8f9f7 945 */
<> 144:ef7eb2e8f9f7 946 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
<> 144:ef7eb2e8f9f7 947 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
<> 144:ef7eb2e8f9f7 948 /**
<> 144:ef7eb2e8f9f7 949 * @}
<> 144:ef7eb2e8f9f7 950 */
<> 144:ef7eb2e8f9f7 951
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /* Peripheral State functions *************************************************/
<> 144:ef7eb2e8f9f7 954 /** @addtogroup ADC_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 955 * @{
<> 144:ef7eb2e8f9f7 956 */
<> 144:ef7eb2e8f9f7 957 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 958 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
<> 144:ef7eb2e8f9f7 959 /**
<> 144:ef7eb2e8f9f7 960 * @}
<> 144:ef7eb2e8f9f7 961 */
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963
<> 144:ef7eb2e8f9f7 964 /**
<> 144:ef7eb2e8f9f7 965 * @}
<> 144:ef7eb2e8f9f7 966 */
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968
<> 144:ef7eb2e8f9f7 969 /**
<> 144:ef7eb2e8f9f7 970 * @}
<> 144:ef7eb2e8f9f7 971 */
<> 144:ef7eb2e8f9f7 972
<> 144:ef7eb2e8f9f7 973 /**
<> 144:ef7eb2e8f9f7 974 * @}
<> 144:ef7eb2e8f9f7 975 */
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 978 }
<> 144:ef7eb2e8f9f7 979 #endif
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981
<> 144:ef7eb2e8f9f7 982 #endif /* __STM32F0xx_HAL_ADC_H */
<> 144:ef7eb2e8f9f7 983
<> 144:ef7eb2e8f9f7 984 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 985