mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
180:96ed750bd169 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief This file contains all the functions prototypes for the HAL
<> 144:ef7eb2e8f9f7 6 * module driver.
<> 144:ef7eb2e8f9f7 7 ******************************************************************************
<> 144:ef7eb2e8f9f7 8 * @attention
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 13 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 14 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 15 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 16 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 17 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 18 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 19 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 20 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 21 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 33 *
<> 144:ef7eb2e8f9f7 34 ******************************************************************************
<> 144:ef7eb2e8f9f7 35 */
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 38 #ifndef __STM32F0xx_HAL_H
<> 144:ef7eb2e8f9f7 39 #define __STM32F0xx_HAL_H
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 42 extern "C" {
<> 144:ef7eb2e8f9f7 43 #endif
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 46 #include "stm32f0xx_hal_conf.h"
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 49 * @{
<> 144:ef7eb2e8f9f7 50 */
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /** @addtogroup HAL
<> 144:ef7eb2e8f9f7 53 * @{
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 /** @addtogroup HAL_Private_Macros
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
<> 144:ef7eb2e8f9f7 61 defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
<> 144:ef7eb2e8f9f7 62 defined(STM32F070xB) || defined(STM32F030x6)
<> 144:ef7eb2e8f9f7 63 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \
<> 144:ef7eb2e8f9f7 64 (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \
<> 144:ef7eb2e8f9f7 65 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
<> 144:ef7eb2e8f9f7 66 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
<> 144:ef7eb2e8f9f7 67 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
<> 144:ef7eb2e8f9f7 68 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
<> 144:ef7eb2e8f9f7 69 #else
<> 144:ef7eb2e8f9f7 70 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
<> 144:ef7eb2e8f9f7 71 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
<> 144:ef7eb2e8f9f7 72 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
<> 144:ef7eb2e8f9f7 73 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
<> 144:ef7eb2e8f9f7 74 #endif
<> 144:ef7eb2e8f9f7 75 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
<> 144:ef7eb2e8f9f7 76 #define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12)
<> 144:ef7eb2e8f9f7 77 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
<> 144:ef7eb2e8f9f7 78 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 79 #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
<> 144:ef7eb2e8f9f7 80 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
<> 144:ef7eb2e8f9f7 81 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
<> 144:ef7eb2e8f9f7 82 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 83 /**
<> 144:ef7eb2e8f9f7 84 * @}
<> 144:ef7eb2e8f9f7 85 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 88 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 89 /** @defgroup HAL_Exported_Constants HAL Exported Constants
<> 144:ef7eb2e8f9f7 90 * @{
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
<> 144:ef7eb2e8f9f7 94 /** @defgroup HAL_Pin_remapping HAL Pin remapping
<> 144:ef7eb2e8f9f7 95 * @{
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97 #define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins).
<> 144:ef7eb2e8f9f7 98 0: No remap (pin pair PA9/10 mapped on the pins)
<> 144:ef7eb2e8f9f7 99 1: Remap (pin pair PA11/12 mapped instead of PA9/10) */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /**
<> 144:ef7eb2e8f9f7 102 * @}
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 107 /** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection
<> 144:ef7eb2e8f9f7 108 * @note Applicable on STM32F09x
<> 144:ef7eb2e8f9f7 109 * @{
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111 #define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation enveloppe source */
<> 144:ef7eb2e8f9f7 112 #define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */
<> 144:ef7eb2e8f9f7 113 #define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /**
<> 144:ef7eb2e8f9f7 116 * @}
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
<> 144:ef7eb2e8f9f7 122 * @{
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /** @brief Fast-mode Plus driving capability on a specific GPIO
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
<> 144:ef7eb2e8f9f7 128 defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
<> 144:ef7eb2e8f9f7 129 defined(STM32F070xB) || defined(STM32F030x6)
<> 144:ef7eb2e8f9f7 130 #define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast-mode Plus on PA9 */
<> 144:ef7eb2e8f9f7 131 #define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast-mode Plus on PA10 */
<> 144:ef7eb2e8f9f7 132 #endif
<> 144:ef7eb2e8f9f7 133 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast-mode Plus on PB6 */
<> 144:ef7eb2e8f9f7 134 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast-mode Plus on PB7 */
<> 144:ef7eb2e8f9f7 135 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast-mode Plus on PB8 */
<> 144:ef7eb2e8f9f7 136 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast-mode Plus on PB9 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /**
<> 144:ef7eb2e8f9f7 139 * @}
<> 144:ef7eb2e8f9f7 140 */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 #if defined(STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 144 /** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
<> 144:ef7eb2e8f9f7 145 * @brief ISR Wrapper
<> 144:ef7eb2e8f9f7 146 * @note applicable on STM32F09x
<> 144:ef7eb2e8f9f7 147 * @{
<> 144:ef7eb2e8f9f7 148 */
<> 156:95d6b41a828b 149 #define HAL_SYSCFG_ITLINE0 ( 0x00000000U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 150 #define HAL_SYSCFG_ITLINE1 ( 0x00000001U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 151 #define HAL_SYSCFG_ITLINE2 ( 0x00000002U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 152 #define HAL_SYSCFG_ITLINE3 ( 0x00000003U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 153 #define HAL_SYSCFG_ITLINE4 ( 0x00000004U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 154 #define HAL_SYSCFG_ITLINE5 ( 0x00000005U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 155 #define HAL_SYSCFG_ITLINE6 ( 0x00000006U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 156 #define HAL_SYSCFG_ITLINE7 ( 0x00000007U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 157 #define HAL_SYSCFG_ITLINE8 ( 0x00000008U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 158 #define HAL_SYSCFG_ITLINE9 ( 0x00000009U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 159 #define HAL_SYSCFG_ITLINE10 ( 0x0000000AU) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 160 #define HAL_SYSCFG_ITLINE11 ( 0x0000000BU) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 161 #define HAL_SYSCFG_ITLINE12 ( 0x0000000CU) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 162 #define HAL_SYSCFG_ITLINE13 ( 0x0000000DU) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 163 #define HAL_SYSCFG_ITLINE14 ( 0x0000000EU) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 164 #define HAL_SYSCFG_ITLINE15 ( 0x0000000FU) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 165 #define HAL_SYSCFG_ITLINE16 ( 0x00000010U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 166 #define HAL_SYSCFG_ITLINE17 ( 0x00000011U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 167 #define HAL_SYSCFG_ITLINE18 ( 0x00000012U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 168 #define HAL_SYSCFG_ITLINE19 ( 0x00000013U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 169 #define HAL_SYSCFG_ITLINE20 ( 0x00000014U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 170 #define HAL_SYSCFG_ITLINE21 ( 0x00000015U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 171 #define HAL_SYSCFG_ITLINE22 ( 0x00000016U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 172 #define HAL_SYSCFG_ITLINE23 ( 0x00000017U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 173 #define HAL_SYSCFG_ITLINE24 ( 0x00000018U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 174 #define HAL_SYSCFG_ITLINE25 ( 0x00000019U) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 175 #define HAL_SYSCFG_ITLINE26 ( 0x0000001AU) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 176 #define HAL_SYSCFG_ITLINE27 ( 0x0000001BU) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 177 #define HAL_SYSCFG_ITLINE28 ( 0x0000001CU) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 178 #define HAL_SYSCFG_ITLINE29 ( 0x0000001DU) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 179 #define HAL_SYSCFG_ITLINE30 ( 0x0000001EU) /*!< Internal define for macro handling */
<> 156:95d6b41a828b 180 #define HAL_SYSCFG_ITLINE31 ( 0x0000001FU) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 181
<> 156:95d6b41a828b 182 #define HAL_ITLINE_EWDG ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)) /*!< EWDG has expired .... */
<> 144:ef7eb2e8f9f7 183 #if defined(STM32F091xC)
<> 156:95d6b41a828b 184 #define HAL_ITLINE_PVDOUT ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)) /*!< Power voltage detection Interrupt .... */
<> 144:ef7eb2e8f9f7 185 #endif
<> 156:95d6b41a828b 186 #define HAL_ITLINE_VDDIO2 ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_VDDIO2)) /*!< VDDIO2 Interrupt .... */
<> 156:95d6b41a828b 187 #define HAL_ITLINE_RTC_WAKEUP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*!< RTC WAKEUP -> exti[20] Interrupt */
<> 156:95d6b41a828b 188 #define HAL_ITLINE_RTC_TSTAMP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*!< RTC Time Stamp -> exti[19] interrupt */
<> 156:95d6b41a828b 189 #define HAL_ITLINE_RTC_ALRA ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*!< RTC Alarm -> exti[17] interrupt .... */
<> 156:95d6b41a828b 190 #define HAL_ITLINE_FLASH_ITF ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*!< Flash ITF Interrupt */
<> 156:95d6b41a828b 191 #define HAL_ITLINE_CRS ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)) /*!< CRS Interrupt */
<> 156:95d6b41a828b 192 #define HAL_ITLINE_CLK_CTRL ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*!< CLK Control Interrupt */
<> 156:95d6b41a828b 193 #define HAL_ITLINE_EXTI0 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)) /*!< External Interrupt 0 */
<> 156:95d6b41a828b 194 #define HAL_ITLINE_EXTI1 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)) /*!< External Interrupt 1 */
<> 156:95d6b41a828b 195 #define HAL_ITLINE_EXTI2 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)) /*!< External Interrupt 2 */
<> 156:95d6b41a828b 196 #define HAL_ITLINE_EXTI3 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)) /*!< External Interrupt 3 */
<> 156:95d6b41a828b 197 #define HAL_ITLINE_EXTI4 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)) /*!< EXTI4 Interrupt */
<> 156:95d6b41a828b 198 #define HAL_ITLINE_EXTI5 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)) /*!< EXTI5 Interrupt */
<> 156:95d6b41a828b 199 #define HAL_ITLINE_EXTI6 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)) /*!< EXTI6 Interrupt */
<> 156:95d6b41a828b 200 #define HAL_ITLINE_EXTI7 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)) /*!< EXTI7 Interrupt */
<> 156:95d6b41a828b 201 #define HAL_ITLINE_EXTI8 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)) /*!< EXTI8 Interrupt */
<> 156:95d6b41a828b 202 #define HAL_ITLINE_EXTI9 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)) /*!< EXTI9 Interrupt */
<> 156:95d6b41a828b 203 #define HAL_ITLINE_EXTI10 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)) /*!< EXTI10 Interrupt */
<> 156:95d6b41a828b 204 #define HAL_ITLINE_EXTI11 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)) /*!< EXTI11 Interrupt */
<> 156:95d6b41a828b 205 #define HAL_ITLINE_EXTI12 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)) /*!< EXTI12 Interrupt */
<> 156:95d6b41a828b 206 #define HAL_ITLINE_EXTI13 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)) /*!< EXTI13 Interrupt */
<> 156:95d6b41a828b 207 #define HAL_ITLINE_EXTI14 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)) /*!< EXTI14 Interrupt */
<> 156:95d6b41a828b 208 #define HAL_ITLINE_EXTI15 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)) /*!< EXTI15 Interrupt */
<> 156:95d6b41a828b 209 #define HAL_ITLINE_TSC_EOA ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*!< Touch control EOA Interrupt */
<> 156:95d6b41a828b 210 #define HAL_ITLINE_TSC_MCE ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*!< Touch control MCE Interrupt */
<> 156:95d6b41a828b 211 #define HAL_ITLINE_DMA1_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*!< DMA1 Channel 1 Interrupt */
<> 156:95d6b41a828b 212 #define HAL_ITLINE_DMA1_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*!< DMA1 Channel 2 Interrupt */
<> 156:95d6b41a828b 213 #define HAL_ITLINE_DMA1_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*!< DMA1 Channel 3 Interrupt */
<> 156:95d6b41a828b 214 #define HAL_ITLINE_DMA2_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*!< DMA2 Channel 1 Interrupt */
<> 156:95d6b41a828b 215 #define HAL_ITLINE_DMA2_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*!< DMA2 Channel 2 Interrupt */
<> 156:95d6b41a828b 216 #define HAL_ITLINE_DMA1_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*!< DMA1 Channel 4 Interrupt */
<> 156:95d6b41a828b 217 #define HAL_ITLINE_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< DMA1 Channel 5 Interrupt */
<> 156:95d6b41a828b 218 #define HAL_ITLINE_DMA1_CH6 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*!< DMA1 Channel 6 Interrupt */
<> 156:95d6b41a828b 219 #define HAL_ITLINE_DMA1_CH7 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*!< DMA1 Channel 7 Interrupt */
<> 156:95d6b41a828b 220 #define HAL_ITLINE_DMA2_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*!< DMA2 Channel 3 Interrupt */
<> 156:95d6b41a828b 221 #define HAL_ITLINE_DMA2_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*!< DMA2 Channel 4 Interrupt */
<> 156:95d6b41a828b 222 #define HAL_ITLINE_DMA2_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*!< DMA2 Channel 5 Interrupt */
<> 156:95d6b41a828b 223 #define HAL_ITLINE_ADC ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)) /*!< ADC Interrupt */
<> 156:95d6b41a828b 224 #define HAL_ITLINE_COMP1 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)) /*!< COMP1 Interrupt -> exti[21] */
<> 156:95d6b41a828b 225 #define HAL_ITLINE_COMP2 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)) /*!< COMP2 Interrupt -> exti[21] */
<> 156:95d6b41a828b 226 #define HAL_ITLINE_TIM1_BRK ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*!< TIM1 BRK Interrupt */
<> 156:95d6b41a828b 227 #define HAL_ITLINE_TIM1_UPD ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*!< TIM1 UPD Interrupt */
<> 156:95d6b41a828b 228 #define HAL_ITLINE_TIM1_TRG ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*!< TIM1 TRG Interrupt */
<> 156:95d6b41a828b 229 #define HAL_ITLINE_TIM1_CCU ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*!< TIM1 CCU Interrupt */
<> 156:95d6b41a828b 230 #define HAL_ITLINE_TIM1_CC ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*!< TIM1 CC Interrupt */
<> 156:95d6b41a828b 231 #define HAL_ITLINE_TIM2 ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*!< TIM2 Interrupt */
<> 156:95d6b41a828b 232 #define HAL_ITLINE_TIM3 ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*!< TIM3 Interrupt */
<> 156:95d6b41a828b 233 #define HAL_ITLINE_DAC ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)) /*!< DAC Interrupt */
<> 156:95d6b41a828b 234 #define HAL_ITLINE_TIM6 ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*!< TIM6 Interrupt */
<> 156:95d6b41a828b 235 #define HAL_ITLINE_TIM7 ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*!< TIM7 Interrupt */
<> 156:95d6b41a828b 236 #define HAL_ITLINE_TIM14 ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*!< TIM14 Interrupt */
<> 156:95d6b41a828b 237 #define HAL_ITLINE_TIM15 ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*!< TIM15 Interrupt */
<> 156:95d6b41a828b 238 #define HAL_ITLINE_TIM16 ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*!< TIM16 Interrupt */
<> 156:95d6b41a828b 239 #define HAL_ITLINE_TIM17 ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*!< TIM17 Interrupt */
<> 156:95d6b41a828b 240 #define HAL_ITLINE_I2C1 ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*!< I2C1 Interrupt -> exti[23] */
<> 156:95d6b41a828b 241 #define HAL_ITLINE_I2C2 ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*!< I2C2 Interrupt */
<> 156:95d6b41a828b 242 #define HAL_ITLINE_SPI1 ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)) /*!< I2C1 Interrupt -> exti[23] */
<> 156:95d6b41a828b 243 #define HAL_ITLINE_SPI2 ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)) /*!< SPI1 Interrupt */
<> 156:95d6b41a828b 244 #define HAL_ITLINE_USART1 ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */
<> 156:95d6b41a828b 245 #define HAL_ITLINE_USART2 ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */
<> 156:95d6b41a828b 246 #define HAL_ITLINE_USART3 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*!< USART3 Interrupt .... */
<> 156:95d6b41a828b 247 #define HAL_ITLINE_USART4 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*!< USART4 Interrupt .... */
<> 156:95d6b41a828b 248 #define HAL_ITLINE_USART5 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*!< USART5 Interrupt .... */
<> 156:95d6b41a828b 249 #define HAL_ITLINE_USART6 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*!< USART6 Interrupt .... */
<> 156:95d6b41a828b 250 #define HAL_ITLINE_USART7 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*!< USART7 Interrupt .... */
<> 156:95d6b41a828b 251 #define HAL_ITLINE_USART8 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*!< USART8 Interrupt .... */
<> 156:95d6b41a828b 252 #define HAL_ITLINE_CAN ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CAN)) /*!< CAN Interrupt */
<> 156:95d6b41a828b 253 #define HAL_ITLINE_CEC ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)) /*!< CEC Interrupt -> exti[27] */
<> 144:ef7eb2e8f9f7 254 /**
<> 144:ef7eb2e8f9f7 255 * @}
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /**
<> 144:ef7eb2e8f9f7 260 * @}
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 264 /** @defgroup HAL_Exported_Macros HAL Exported Macros
<> 144:ef7eb2e8f9f7 265 * @{
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals
<> 144:ef7eb2e8f9f7 269 * @brief Freeze/Unfreeze Peripherals in Debug mode
<> 144:ef7eb2e8f9f7 270 * @{
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
<> 144:ef7eb2e8f9f7 274 #define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
<> 144:ef7eb2e8f9f7 275 #define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
<> 144:ef7eb2e8f9f7 276 #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
<> 144:ef7eb2e8f9f7 279 #define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
<> 144:ef7eb2e8f9f7 280 #define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
<> 144:ef7eb2e8f9f7 281 #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 284 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
<> 144:ef7eb2e8f9f7 285 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
<> 144:ef7eb2e8f9f7 286 #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
<> 144:ef7eb2e8f9f7 289 #define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
<> 144:ef7eb2e8f9f7 290 #define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
<> 144:ef7eb2e8f9f7 291 #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
<> 144:ef7eb2e8f9f7 294 #define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
<> 144:ef7eb2e8f9f7 295 #define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
<> 144:ef7eb2e8f9f7 296 #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<> 144:ef7eb2e8f9f7 299 #define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
<> 144:ef7eb2e8f9f7 300 #define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
<> 144:ef7eb2e8f9f7 301 #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 144:ef7eb2e8f9f7 304 #define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
<> 144:ef7eb2e8f9f7 305 #define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
<> 144:ef7eb2e8f9f7 306 #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<> 144:ef7eb2e8f9f7 309 #define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
<> 144:ef7eb2e8f9f7 310 #define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
<> 144:ef7eb2e8f9f7 311 #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 144:ef7eb2e8f9f7 314 #define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
<> 144:ef7eb2e8f9f7 315 #define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
<> 144:ef7eb2e8f9f7 316 #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
<> 144:ef7eb2e8f9f7 319 #define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
<> 144:ef7eb2e8f9f7 320 #define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
<> 144:ef7eb2e8f9f7 321 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
<> 144:ef7eb2e8f9f7 324 #define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
<> 144:ef7eb2e8f9f7 325 #define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
<> 144:ef7eb2e8f9f7 326 #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
<> 144:ef7eb2e8f9f7 329 #define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
<> 144:ef7eb2e8f9f7 330 #define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
<> 144:ef7eb2e8f9f7 331 #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
<> 144:ef7eb2e8f9f7 334 #define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
<> 144:ef7eb2e8f9f7 335 #define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
<> 144:ef7eb2e8f9f7 336 #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
<> 144:ef7eb2e8f9f7 339 #define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
<> 144:ef7eb2e8f9f7 340 #define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
<> 144:ef7eb2e8f9f7 341 #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /**
<> 144:ef7eb2e8f9f7 344 * @}
<> 144:ef7eb2e8f9f7 345 */
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /** @defgroup Memory_Mapping_Selection Memory Mapping Selection
<> 144:ef7eb2e8f9f7 348 * @{
<> 144:ef7eb2e8f9f7 349 */
<> 144:ef7eb2e8f9f7 350 #if defined(SYSCFG_CFGR1_MEM_MODE)
<> 144:ef7eb2e8f9f7 351 /** @brief Main Flash memory mapped at 0x00000000
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
<> 144:ef7eb2e8f9f7 354 #endif /* SYSCFG_CFGR1_MEM_MODE */
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 #if defined(SYSCFG_CFGR1_MEM_MODE_0)
<> 144:ef7eb2e8f9f7 357 /** @brief System Flash memory mapped at 0x00000000
<> 144:ef7eb2e8f9f7 358 */
<> 144:ef7eb2e8f9f7 359 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
<> 144:ef7eb2e8f9f7 360 SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
<> 144:ef7eb2e8f9f7 361 }while(0)
<> 144:ef7eb2e8f9f7 362 #endif /* SYSCFG_CFGR1_MEM_MODE_0 */
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
<> 144:ef7eb2e8f9f7 365 /** @brief Embedded SRAM mapped at 0x00000000
<> 144:ef7eb2e8f9f7 366 */
<> 144:ef7eb2e8f9f7 367 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
<> 144:ef7eb2e8f9f7 368 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
<> 144:ef7eb2e8f9f7 369 }while(0)
<> 144:ef7eb2e8f9f7 370 #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
<> 144:ef7eb2e8f9f7 371 /**
<> 144:ef7eb2e8f9f7 372 * @}
<> 144:ef7eb2e8f9f7 373 */
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
<> 144:ef7eb2e8f9f7 377 /** @defgroup HAL_Pin_remap HAL Pin remap
<> 144:ef7eb2e8f9f7 378 * @brief Pin remapping enable/disable macros
Anna Bridge 180:96ed750bd169 379 * @param __PIN_REMAP__ This parameter can be a value of @ref HAL_Pin_remapping
<> 144:ef7eb2e8f9f7 380 * @{
<> 144:ef7eb2e8f9f7 381 */
<> 144:ef7eb2e8f9f7 382 #define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
<> 144:ef7eb2e8f9f7 383 SYSCFG->CFGR1 |= (__PIN_REMAP__); \
<> 144:ef7eb2e8f9f7 384 }while(0)
<> 144:ef7eb2e8f9f7 385 #define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
<> 144:ef7eb2e8f9f7 386 SYSCFG->CFGR1 &= ~(__PIN_REMAP__); \
<> 144:ef7eb2e8f9f7 387 }while(0)
<> 144:ef7eb2e8f9f7 388 /**
<> 144:ef7eb2e8f9f7 389 * @}
<> 144:ef7eb2e8f9f7 390 */
<> 144:ef7eb2e8f9f7 391 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /** @brief Fast-mode Plus driving capability enable/disable macros
Anna Bridge 180:96ed750bd169 394 * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
<> 144:ef7eb2e8f9f7 395 * That you can find above these macros.
<> 144:ef7eb2e8f9f7 396 */
<> 144:ef7eb2e8f9f7 397 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
<> 144:ef7eb2e8f9f7 398 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
<> 144:ef7eb2e8f9f7 399 }while(0)
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
<> 144:ef7eb2e8f9f7 402 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
<> 144:ef7eb2e8f9f7 403 }while(0)
<> 144:ef7eb2e8f9f7 404 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
<> 144:ef7eb2e8f9f7 405 /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
<> 144:ef7eb2e8f9f7 406 * @{
<> 144:ef7eb2e8f9f7 407 */
<> 144:ef7eb2e8f9f7 408 /** @brief SYSCFG Break Lockup lock
<> 144:ef7eb2e8f9f7 409 * Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
<> 144:ef7eb2e8f9f7 410 * @note The selected configuration is locked and can be unlocked by system reset
<> 144:ef7eb2e8f9f7 411 */
<> 144:ef7eb2e8f9f7 412 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
<> 144:ef7eb2e8f9f7 413 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
<> 144:ef7eb2e8f9f7 414 }while(0)
<> 144:ef7eb2e8f9f7 415 /**
<> 144:ef7eb2e8f9f7 416 * @}
<> 144:ef7eb2e8f9f7 417 */
<> 144:ef7eb2e8f9f7 418 #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 #if defined(SYSCFG_CFGR2_PVD_LOCK)
<> 144:ef7eb2e8f9f7 421 /** @defgroup PVD_Lock_Enable PVD Lock
<> 144:ef7eb2e8f9f7 422 * @{
<> 144:ef7eb2e8f9f7 423 */
<> 144:ef7eb2e8f9f7 424 /** @brief SYSCFG Break PVD lock
<> 144:ef7eb2e8f9f7 425 * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
<> 144:ef7eb2e8f9f7 426 * @note The selected configuration is locked and can be unlocked by system reset
<> 144:ef7eb2e8f9f7 427 */
<> 144:ef7eb2e8f9f7 428 #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
<> 144:ef7eb2e8f9f7 429 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
<> 144:ef7eb2e8f9f7 430 }while(0)
<> 144:ef7eb2e8f9f7 431 /**
<> 144:ef7eb2e8f9f7 432 * @}
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434 #endif /* SYSCFG_CFGR2_PVD_LOCK */
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
<> 144:ef7eb2e8f9f7 437 /** @defgroup SRAM_Parity_Lock SRAM Parity Lock
<> 144:ef7eb2e8f9f7 438 * @{
<> 144:ef7eb2e8f9f7 439 */
<> 144:ef7eb2e8f9f7 440 /** @brief SYSCFG Break SRAM PARITY lock
<> 144:ef7eb2e8f9f7 441 * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
<> 144:ef7eb2e8f9f7 442 * @note The selected configuration is locked and can be unlocked by system reset
<> 144:ef7eb2e8f9f7 443 */
<> 144:ef7eb2e8f9f7 444 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
<> 144:ef7eb2e8f9f7 445 SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
<> 144:ef7eb2e8f9f7 446 }while(0)
<> 144:ef7eb2e8f9f7 447 /**
<> 144:ef7eb2e8f9f7 448 * @}
<> 144:ef7eb2e8f9f7 449 */
<> 144:ef7eb2e8f9f7 450 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 #if defined(SYSCFG_CFGR2_SRAM_PEF)
<> 144:ef7eb2e8f9f7 453 /** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM
<> 144:ef7eb2e8f9f7 454 * @brief Parity check on RAM disable macro
<> 144:ef7eb2e8f9f7 455 * @note Disabling the parity check on RAM locks the configuration bit.
<> 144:ef7eb2e8f9f7 456 * To re-enable the parity check on RAM perform a system reset.
<> 144:ef7eb2e8f9f7 457 * @{
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF)
<> 144:ef7eb2e8f9f7 460 /**
<> 144:ef7eb2e8f9f7 461 * @}
<> 144:ef7eb2e8f9f7 462 */
<> 144:ef7eb2e8f9f7 463 #endif /* SYSCFG_CFGR2_SRAM_PEF */
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 #if defined(STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 467 /** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check
<> 144:ef7eb2e8f9f7 468 * @brief ISR wrapper check
<> 144:ef7eb2e8f9f7 469 * @note This feature is applicable on STM32F09x
<> 144:ef7eb2e8f9f7 470 * @note Allow to determine interrupt source per line.
<> 144:ef7eb2e8f9f7 471 * @{
<> 144:ef7eb2e8f9f7 472 */
<> 156:95d6b41a828b 473 #define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))
<> 144:ef7eb2e8f9f7 474 /**
<> 144:ef7eb2e8f9f7 475 * @}
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477 #endif /* (STM32F091xC) || defined (STM32F098xx)*/
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 #if defined(STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 480 /** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection
<> 144:ef7eb2e8f9f7 481 * @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register
<> 144:ef7eb2e8f9f7 482 * @note This feature is applicable on STM32F09x
Anna Bridge 180:96ed750bd169 483 * @param __SOURCE__ This parameter can be a value of @ref HAL_IRDA_ENV_SEL
<> 144:ef7eb2e8f9f7 484 * @{
<> 144:ef7eb2e8f9f7 485 */
<> 144:ef7eb2e8f9f7 486 #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \
<> 144:ef7eb2e8f9f7 487 SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \
<> 144:ef7eb2e8f9f7 488 SYSCFG->CFGR1 |= (__SOURCE__); \
<> 144:ef7eb2e8f9f7 489 }while(0)
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 #define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0)
<> 144:ef7eb2e8f9f7 492 /**
<> 144:ef7eb2e8f9f7 493 * @}
<> 144:ef7eb2e8f9f7 494 */
<> 144:ef7eb2e8f9f7 495 #endif /* (STM32F091xC) || defined (STM32F098xx)*/
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /**
<> 144:ef7eb2e8f9f7 498 * @}
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /** @addtogroup HAL_Exported_Functions
<> 144:ef7eb2e8f9f7 504 * @{
<> 144:ef7eb2e8f9f7 505 */
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /** @addtogroup HAL_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 508 * @{
<> 144:ef7eb2e8f9f7 509 */
<> 144:ef7eb2e8f9f7 510 /* Initialization and de-initialization functions ******************************/
<> 144:ef7eb2e8f9f7 511 HAL_StatusTypeDef HAL_Init(void);
<> 144:ef7eb2e8f9f7 512 HAL_StatusTypeDef HAL_DeInit(void);
<> 144:ef7eb2e8f9f7 513 void HAL_MspInit(void);
<> 144:ef7eb2e8f9f7 514 void HAL_MspDeInit(void);
<> 144:ef7eb2e8f9f7 515 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
<> 144:ef7eb2e8f9f7 516 /**
<> 144:ef7eb2e8f9f7 517 * @}
<> 144:ef7eb2e8f9f7 518 */
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /** @addtogroup HAL_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 521 * @{
<> 144:ef7eb2e8f9f7 522 */
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /* Peripheral Control functions ************************************************/
<> 144:ef7eb2e8f9f7 525 void HAL_IncTick(void);
<> 144:ef7eb2e8f9f7 526 void HAL_Delay(__IO uint32_t Delay);
<> 144:ef7eb2e8f9f7 527 uint32_t HAL_GetTick(void);
<> 144:ef7eb2e8f9f7 528 void HAL_SuspendTick(void);
<> 144:ef7eb2e8f9f7 529 void HAL_ResumeTick(void);
<> 144:ef7eb2e8f9f7 530 uint32_t HAL_GetHalVersion(void);
<> 144:ef7eb2e8f9f7 531 uint32_t HAL_GetREVID(void);
<> 144:ef7eb2e8f9f7 532 uint32_t HAL_GetDEVID(void);
Anna Bridge 180:96ed750bd169 533 uint32_t HAL_GetUIDw0(void);
Anna Bridge 180:96ed750bd169 534 uint32_t HAL_GetUIDw1(void);
Anna Bridge 180:96ed750bd169 535 uint32_t HAL_GetUIDw2(void);
<> 144:ef7eb2e8f9f7 536 void HAL_DBGMCU_EnableDBGStopMode(void);
<> 144:ef7eb2e8f9f7 537 void HAL_DBGMCU_DisableDBGStopMode(void);
<> 144:ef7eb2e8f9f7 538 void HAL_DBGMCU_EnableDBGStandbyMode(void);
<> 144:ef7eb2e8f9f7 539 void HAL_DBGMCU_DisableDBGStandbyMode(void);
<> 144:ef7eb2e8f9f7 540 /**
<> 144:ef7eb2e8f9f7 541 * @}
<> 144:ef7eb2e8f9f7 542 */
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /**
<> 144:ef7eb2e8f9f7 545 * @}
<> 144:ef7eb2e8f9f7 546 */
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 /**
<> 144:ef7eb2e8f9f7 549 * @}
<> 144:ef7eb2e8f9f7 550 */
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /**
<> 144:ef7eb2e8f9f7 553 * @}
<> 144:ef7eb2e8f9f7 554 */
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 557 }
<> 144:ef7eb2e8f9f7 558 #endif
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 #endif /* __STM32F0xx_HAL_H */
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/