mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c@173:e131a1973e81, 2017-09-15 (annotated)

Committer:
AnnaBridge
Date:
Fri Sep 15 14:59:18 2017 +0100
Revision:
173:e131a1973e81
Parent:
167:e84263d55307
Child:
174:b96e65c34a4d
This updates the lib to the mbed lib v 151

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:e84263d55307 1 /*
AnnaBridge 167:e84263d55307 2 * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
AnnaBridge 167:e84263d55307 3 *
AnnaBridge 167:e84263d55307 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 167:e84263d55307 5 * you may not use this file except in compliance with the License.
AnnaBridge 167:e84263d55307 6 * You may obtain a copy of the License at
AnnaBridge 167:e84263d55307 7 *
AnnaBridge 167:e84263d55307 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 167:e84263d55307 9 *
AnnaBridge 167:e84263d55307 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 167:e84263d55307 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 167:e84263d55307 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 167:e84263d55307 13 * See the License for the specific language governing permissions and
AnnaBridge 167:e84263d55307 14 * limitations under the License.
AnnaBridge 167:e84263d55307 15 */
AnnaBridge 167:e84263d55307 16 #include "rtl8195a.h"
AnnaBridge 173:e131a1973e81 17
AnnaBridge 173:e131a1973e81 18 #if defined(__CC_ARM)
AnnaBridge 173:e131a1973e81 19 #include "cmsis_armcc.h"
AnnaBridge 173:e131a1973e81 20 #elif defined(__GNUC__)
AnnaBridge 173:e131a1973e81 21 #include "cmsis_gcc.h"
AnnaBridge 173:e131a1973e81 22 #else
AnnaBridge 173:e131a1973e81 23 #include <cmsis_iar.h>
AnnaBridge 173:e131a1973e81 24 #endif
AnnaBridge 173:e131a1973e81 25
AnnaBridge 173:e131a1973e81 26
AnnaBridge 173:e131a1973e81 27 #if defined(__CC_ARM) || \
AnnaBridge 173:e131a1973e81 28 (defined (__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050)
AnnaBridge 167:e84263d55307 29
AnnaBridge 173:e131a1973e81 30 extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
AnnaBridge 173:e131a1973e81 31 extern uint8_t Image$$RW_IRAM2$$ZI$$Base[];
AnnaBridge 173:e131a1973e81 32 extern uint8_t Image$$RW_IRAM2$$ZI$$Limit[];
AnnaBridge 173:e131a1973e81 33 extern uint8_t Image$$TCM_OVERLAY$$ZI$$Base[];
AnnaBridge 173:e131a1973e81 34 extern uint8_t Image$$TCM_OVERLAY$$ZI$$Limit[];
AnnaBridge 173:e131a1973e81 35 extern uint8_t Image$$RW_DRAM2$$ZI$$Base[];
AnnaBridge 173:e131a1973e81 36 extern uint8_t Image$$RW_DRAM2$$ZI$$Limit[];
AnnaBridge 173:e131a1973e81 37 #define __bss_sram_start__ Image$$RW_IRAM2$$ZI$$Base
AnnaBridge 173:e131a1973e81 38 #define __bss_sram_end__ Image$$RW_IRAM2$$ZI$$Limit
AnnaBridge 173:e131a1973e81 39 #define __bss_dtcm_start__ Image$$TCM_OVERLAY$$ZI$$Base
AnnaBridge 173:e131a1973e81 40 #define __bss_dtcm_end__ Image$$TCM_OVERLAY$$ZI$$Limit
AnnaBridge 173:e131a1973e81 41 #define __bss_dram_start__ Image$$RW_DRAM2$$ZI$$Base
AnnaBridge 173:e131a1973e81 42 #define __bss_dram_end__ Image$$RW_DRAM2$$ZI$$Limit
AnnaBridge 173:e131a1973e81 43 #define __stackp Image$$ARM_LIB_STACK$$ZI$$Limit
AnnaBridge 173:e131a1973e81 44
AnnaBridge 173:e131a1973e81 45 #elif defined (__ICCARM__)
AnnaBridge 173:e131a1973e81 46
AnnaBridge 167:e84263d55307 47 #pragma section=".ram.bss"
AnnaBridge 167:e84263d55307 48
AnnaBridge 173:e131a1973e81 49 extern uint32_t CSTACK$$Limit;
AnnaBridge 167:e84263d55307 50 uint8_t *__bss_start__;
AnnaBridge 167:e84263d55307 51 uint8_t *__bss_end__;
AnnaBridge 167:e84263d55307 52
AnnaBridge 167:e84263d55307 53 void __iar_data_init_app(void)
AnnaBridge 167:e84263d55307 54 {
AnnaBridge 167:e84263d55307 55 __bss_start__ = (uint8_t *)__section_begin(".ram.bss");
AnnaBridge 167:e84263d55307 56 __bss_end__ = (uint8_t *)__section_end(".ram.bss");
AnnaBridge 167:e84263d55307 57 }
AnnaBridge 173:e131a1973e81 58 #define __stackp CSTACK$$Limit
AnnaBridge 173:e131a1973e81 59
AnnaBridge 167:e84263d55307 60 #else
AnnaBridge 173:e131a1973e81 61
AnnaBridge 173:e131a1973e81 62 extern uint32_t __StackTop;
AnnaBridge 173:e131a1973e81 63 extern uint32_t __StackLimit;
AnnaBridge 173:e131a1973e81 64 extern uint8_t __bss_sram_start__[];
AnnaBridge 173:e131a1973e81 65 extern uint8_t __bss_sram_end__[];
AnnaBridge 173:e131a1973e81 66 extern uint8_t __bss_dtcm_start__[];
AnnaBridge 173:e131a1973e81 67 extern uint8_t __bss_dtcm_end__[];
AnnaBridge 173:e131a1973e81 68 extern uint8_t __bss_dram_start__[];
AnnaBridge 173:e131a1973e81 69 extern uint8_t __bss_dram_end__[];
AnnaBridge 173:e131a1973e81 70
AnnaBridge 173:e131a1973e81 71 #define __stackp __StackTop
AnnaBridge 167:e84263d55307 72 #endif
AnnaBridge 167:e84263d55307 73
AnnaBridge 167:e84263d55307 74 extern VECTOR_Func NewVectorTable[];
AnnaBridge 167:e84263d55307 75 extern void SystemCoreClockUpdate(void);
AnnaBridge 167:e84263d55307 76 extern void PLAT_Start(void);
AnnaBridge 167:e84263d55307 77 extern void PLAT_Main(void);
AnnaBridge 173:e131a1973e81 78
AnnaBridge 173:e131a1973e81 79 IMAGE2_START_RAM_FUN_SECTION
AnnaBridge 173:e131a1973e81 80 const RAM_START_FUNCTION gImage2EntryFun0 = {
AnnaBridge 167:e84263d55307 81 PLAT_Start
AnnaBridge 167:e84263d55307 82 };
AnnaBridge 167:e84263d55307 83
AnnaBridge 173:e131a1973e81 84 IMAGE2_VALID_PATTEN_SECTION
AnnaBridge 173:e131a1973e81 85 const uint8_t IMAGE2_SIGNATURE[20] = {
AnnaBridge 167:e84263d55307 86 'R', 'T', 'K', 'W', 'i', 'n', 0x0, 0xff,
AnnaBridge 167:e84263d55307 87 (FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff),
AnnaBridge 167:e84263d55307 88 (FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff),
AnnaBridge 167:e84263d55307 89 (FW_CHIP_ID&0xff), ((FW_CHIP_ID >> 8)&0xff),
AnnaBridge 167:e84263d55307 90 (FW_CHIP_VER),
AnnaBridge 167:e84263d55307 91 (FW_BUS_TYPE),
AnnaBridge 167:e84263d55307 92 (FW_INFO_RSV1),
AnnaBridge 167:e84263d55307 93 (FW_INFO_RSV2),
AnnaBridge 167:e84263d55307 94 (FW_INFO_RSV3),
AnnaBridge 167:e84263d55307 95 (FW_INFO_RSV4)
AnnaBridge 167:e84263d55307 96 };
AnnaBridge 167:e84263d55307 97
AnnaBridge 167:e84263d55307 98 void TRAP_NMIHandler(void)
AnnaBridge 167:e84263d55307 99 {
AnnaBridge 167:e84263d55307 100 #ifdef CONFIG_WDG_NORMAL
AnnaBridge 167:e84263d55307 101 uint32_t val;
AnnaBridge 167:e84263d55307 102 WDG_REG *ctl;
AnnaBridge 167:e84263d55307 103
AnnaBridge 167:e84263d55307 104 // Check if this NMI is triggered by Watchdog Timer
AnnaBridge 167:e84263d55307 105 val = __RTK_READ32(VENDOR_REG_BASE, 0);
AnnaBridge 167:e84263d55307 106 ctl = (WDG_REG*) &val;
AnnaBridge 167:e84263d55307 107 if (ctl->WdgToISR) {
AnnaBridge 167:e84263d55307 108 INTR_WatchdogHandler();
AnnaBridge 167:e84263d55307 109 }
AnnaBridge 167:e84263d55307 110 #endif
AnnaBridge 167:e84263d55307 111 }
AnnaBridge 167:e84263d55307 112
AnnaBridge 173:e131a1973e81 113 #if defined (__ICCARM__)
AnnaBridge 167:e84263d55307 114 void __TRAP_HardFaultHandler_Patch(uint32_t addr)
AnnaBridge 167:e84263d55307 115 {
AnnaBridge 167:e84263d55307 116 uint32_t cfsr;
AnnaBridge 167:e84263d55307 117 uint32_t bfar;
AnnaBridge 167:e84263d55307 118
AnnaBridge 167:e84263d55307 119 uint32_t stackpc;
AnnaBridge 167:e84263d55307 120 uint16_t asmcode;
AnnaBridge 167:e84263d55307 121
AnnaBridge 167:e84263d55307 122 cfsr = HAL_READ32(0xE000ED28, 0x0);
AnnaBridge 167:e84263d55307 123
AnnaBridge 167:e84263d55307 124 // Violation to memory access protection
AnnaBridge 167:e84263d55307 125 if (cfsr & 0x82) {
AnnaBridge 167:e84263d55307 126
AnnaBridge 167:e84263d55307 127 bfar = HAL_READ32(0xE000ED38, 0x0);
AnnaBridge 167:e84263d55307 128
AnnaBridge 167:e84263d55307 129 // invalid access to wifi register, usually happened in LPS 32K or IPS
AnnaBridge 167:e84263d55307 130 if (bfar >= WIFI_REG_BASE && bfar < WIFI_REG_BASE + 0x40000) {
AnnaBridge 167:e84263d55307 131
AnnaBridge 167:e84263d55307 132 //__BKPT(0);
AnnaBridge 167:e84263d55307 133
AnnaBridge 167:e84263d55307 134 /* Get the MemManage fault PC, and step to next command.
AnnaBridge 167:e84263d55307 135 * Otherwise it will keep hitting MemMange Fault on the same assembly code.
AnnaBridge 167:e84263d55307 136 *
AnnaBridge 167:e84263d55307 137 * To step to next command, we need parse the assembly code to check if
AnnaBridge 173:e131a1973e81 138 * it is 16-bit or 32-bit command.
AnnaBridge 167:e84263d55307 139 * Ref: ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
AnnaBridge 173:e131a1973e81 140 * Chapter A6 - Thumb Instruction Set Encoding
AnnaBridge 167:e84263d55307 141 *
AnnaBridge 167:e84263d55307 142 * However, the fault assembly code (Ex. LDR or ADR) is not actually executed,
AnnaBridge 167:e84263d55307 143 * So the register value is un-predictable.
AnnaBridge 167:e84263d55307 144 **/
AnnaBridge 167:e84263d55307 145 stackpc = HAL_READ32(addr, 0x18);
AnnaBridge 167:e84263d55307 146 asmcode = HAL_READ16(stackpc, 0);
AnnaBridge 167:e84263d55307 147 if ((asmcode & 0xF800) > 0xE000) {
AnnaBridge 167:e84263d55307 148 // 32-bit instruction, (opcode[15:11] = 0b11111, 0b11110, 0b11101)
AnnaBridge 167:e84263d55307 149 HAL_WRITE32(addr, 0x18, stackpc + 4);
AnnaBridge 167:e84263d55307 150 } else {
AnnaBridge 167:e84263d55307 151 // 16-bit instruction
AnnaBridge 167:e84263d55307 152 HAL_WRITE32(addr, 0x18, stackpc + 2);
AnnaBridge 167:e84263d55307 153 }
AnnaBridge 167:e84263d55307 154
AnnaBridge 167:e84263d55307 155 // clear Hard Fault Status Register
AnnaBridge 167:e84263d55307 156 HAL_WRITE32(0xE000ED2C, 0x0, HAL_READ32(0xE000ED2C, 0x0));
AnnaBridge 167:e84263d55307 157 return;
AnnaBridge 167:e84263d55307 158 }
AnnaBridge 167:e84263d55307 159 }
AnnaBridge 167:e84263d55307 160
AnnaBridge 167:e84263d55307 161 __TRAP_HardFaultHandler(addr);
AnnaBridge 167:e84263d55307 162 }
AnnaBridge 167:e84263d55307 163
AnnaBridge 167:e84263d55307 164 void TRAP_HardFaultHandler_Patch(void)
AnnaBridge 167:e84263d55307 165 {
AnnaBridge 167:e84263d55307 166 __asm("TST LR, #4 \n"
AnnaBridge 167:e84263d55307 167 "ITE EQ \n"
AnnaBridge 167:e84263d55307 168 "MRSEQ R0, MSP \n"
AnnaBridge 167:e84263d55307 169 "MRSNE R0, PSP \n"
AnnaBridge 167:e84263d55307 170 "B __TRAP_HardFaultHandler_Patch ");
AnnaBridge 167:e84263d55307 171 }
AnnaBridge 167:e84263d55307 172 #endif
AnnaBridge 167:e84263d55307 173
AnnaBridge 173:e131a1973e81 174 extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
AnnaBridge 173:e131a1973e81 175 // Image2 Entry Function
AnnaBridge 173:e131a1973e81 176 void PLAT_Start(void)
AnnaBridge 167:e84263d55307 177 {
AnnaBridge 167:e84263d55307 178 uint32_t val;
AnnaBridge 167:e84263d55307 179
AnnaBridge 173:e131a1973e81 180 #if defined (__ICCARM__)
AnnaBridge 173:e131a1973e81 181 __iar_data_init_app();
AnnaBridge 173:e131a1973e81 182 #endif
AnnaBridge 173:e131a1973e81 183
AnnaBridge 173:e131a1973e81 184 // Clear RAM BSS
AnnaBridge 173:e131a1973e81 185 #if defined (__ICCARM__)
AnnaBridge 173:e131a1973e81 186 __rtl_memset_v1_00((void *)__bss_start__, 0, __bss_end__ - __bss_start__);
AnnaBridge 173:e131a1973e81 187 #else
AnnaBridge 173:e131a1973e81 188 __rtl_memset_v1_00((void *)__bss_sram_start__, 0, __bss_sram_end__ - __bss_sram_start__);
AnnaBridge 173:e131a1973e81 189 __rtl_memset_v1_00((void *)__bss_dtcm_start__, 0, __bss_dtcm_end__ - __bss_dtcm_start__);
AnnaBridge 173:e131a1973e81 190 __rtl_memset_v1_00((void *)__bss_dram_start__, 0, __bss_dram_end__ - __bss_dram_start__);
AnnaBridge 173:e131a1973e81 191 #endif
AnnaBridge 173:e131a1973e81 192
AnnaBridge 173:e131a1973e81 193 // Set MSP
AnnaBridge 173:e131a1973e81 194 __set_MSP((uint32_t)&__stackp - 0x100);
AnnaBridge 173:e131a1973e81 195 // Overwrite vector table
AnnaBridge 173:e131a1973e81 196 NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
AnnaBridge 173:e131a1973e81 197 #if defined ( __ICCARM__ )
AnnaBridge 173:e131a1973e81 198 NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch;
AnnaBridge 173:e131a1973e81 199 #endif
AnnaBridge 173:e131a1973e81 200
AnnaBridge 173:e131a1973e81 201 extern HAL_TIMER_OP_EXT HalTimerOpExt;
AnnaBridge 173:e131a1973e81 202 __rtl_memset_v1_00((void *)&HalTimerOpExt, 0, sizeof(HalTimerOpExt));
AnnaBridge 173:e131a1973e81 203 __rtl_memset_v1_00((void *)&HalTimerOp, 0, sizeof(HalTimerOp));
AnnaBridge 173:e131a1973e81 204
AnnaBridge 173:e131a1973e81 205 HalTimerOpInit_Patch(&HalTimerOp);
AnnaBridge 173:e131a1973e81 206 SystemCoreClockUpdate();
AnnaBridge 173:e131a1973e81 207
AnnaBridge 173:e131a1973e81 208 // Set SPS lower voltage
AnnaBridge 167:e84263d55307 209 val = __RTK_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0);
AnnaBridge 167:e84263d55307 210 val &= 0xf0ffffff;
AnnaBridge 167:e84263d55307 211 val |= 0x6000000;
AnnaBridge 167:e84263d55307 212 __RTK_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0, val);
AnnaBridge 173:e131a1973e81 213
AnnaBridge 173:e131a1973e81 214 // xtal buffer driving current
AnnaBridge 167:e84263d55307 215 val = __RTK_CTRL_READ32(REG_SYS_XTAL_CTRL1);
AnnaBridge 167:e84263d55307 216 val &= ~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1);
AnnaBridge 167:e84263d55307 217 val |= BIT_SYS_XTAL_DRV_RF1(1);
AnnaBridge 167:e84263d55307 218 __RTK_CTRL_WRITE32(REG_SYS_XTAL_CTRL1, val);
AnnaBridge 167:e84263d55307 219
AnnaBridge 173:e131a1973e81 220 // Initialize SPIC, then disable it for power saving.
AnnaBridge 173:e131a1973e81 221 if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN) != 0) {
AnnaBridge 173:e131a1973e81 222 SpicNVMCalLoadAll();
AnnaBridge 173:e131a1973e81 223 SpicReadIDRtl8195A();
AnnaBridge 173:e131a1973e81 224 SpicDisableRtl8195A();
AnnaBridge 173:e131a1973e81 225 }
AnnaBridge 167:e84263d55307 226
AnnaBridge 167:e84263d55307 227 #ifdef CONFIG_TIMER_MODULE
AnnaBridge 173:e131a1973e81 228 Calibration32k();
AnnaBridge 167:e84263d55307 229 #endif
AnnaBridge 167:e84263d55307 230
AnnaBridge 167:e84263d55307 231 #ifndef CONFIG_SDIO_DEVICE_EN
AnnaBridge 167:e84263d55307 232 SDIO_DEV_Disable();
AnnaBridge 167:e84263d55307 233 #endif
AnnaBridge 167:e84263d55307 234
AnnaBridge 167:e84263d55307 235 // Enter App start function
AnnaBridge 167:e84263d55307 236 PLAT_Main();
AnnaBridge 167:e84263d55307 237 }
AnnaBridge 167:e84263d55307 238
AnnaBridge 167:e84263d55307 239 extern void SVC_Handler(void);
AnnaBridge 167:e84263d55307 240 extern void PendSV_Handler(void);
AnnaBridge 167:e84263d55307 241 extern void SysTick_Handler(void);
AnnaBridge 167:e84263d55307 242
AnnaBridge 173:e131a1973e81 243 // The Main App entry point
AnnaBridge 167:e84263d55307 244 #if defined (__CC_ARM)
AnnaBridge 167:e84263d55307 245 __asm void ARM_PLAT_Main(void)
AnnaBridge 167:e84263d55307 246 {
AnnaBridge 173:e131a1973e81 247 IMPORT SystemInit
AnnaBridge 173:e131a1973e81 248 IMPORT __main
AnnaBridge 173:e131a1973e81 249 BL SystemInit
AnnaBridge 173:e131a1973e81 250 BL __main
AnnaBridge 173:e131a1973e81 251 }
AnnaBridge 173:e131a1973e81 252 #elif defined (__ICCARM__)
AnnaBridge 173:e131a1973e81 253 extern void __iar_program_start(void);
AnnaBridge 173:e131a1973e81 254
AnnaBridge 173:e131a1973e81 255 void IAR_PLAT_Main(void)
AnnaBridge 173:e131a1973e81 256 {
AnnaBridge 173:e131a1973e81 257 SystemInit();
AnnaBridge 173:e131a1973e81 258 __iar_program_start();
AnnaBridge 167:e84263d55307 259 }
AnnaBridge 167:e84263d55307 260 #endif
AnnaBridge 167:e84263d55307 261
AnnaBridge 167:e84263d55307 262 void PLAT_Main(void)
AnnaBridge 167:e84263d55307 263 {
AnnaBridge 167:e84263d55307 264 TRAP_Init((void *)SVC_Handler, (void *)PendSV_Handler, (void *)SysTick_Handler);
AnnaBridge 167:e84263d55307 265
AnnaBridge 173:e131a1973e81 266 #if defined (__CC_ARM)
AnnaBridge 173:e131a1973e81 267 ARM_PLAT_Main();
AnnaBridge 173:e131a1973e81 268 #elif defined (__ICCARM__)
AnnaBridge 173:e131a1973e81 269 IAR_PLAT_Main();
AnnaBridge 173:e131a1973e81 270 #else
AnnaBridge 173:e131a1973e81 271 __asm ("ldr r0, =SystemInit \n"
AnnaBridge 167:e84263d55307 272 "blx r0 \n"
AnnaBridge 167:e84263d55307 273 "ldr r0, =_start \n"
AnnaBridge 167:e84263d55307 274 "bx r0 \n"
AnnaBridge 167:e84263d55307 275 );
AnnaBridge 167:e84263d55307 276 #endif
AnnaBridge 173:e131a1973e81 277
AnnaBridge 167:e84263d55307 278 // Never reached
AnnaBridge 173:e131a1973e81 279 for (;;);
AnnaBridge 167:e84263d55307 280 }