Diff: targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c

Revision:

187:0387e8f68319

Parent:

170:19eb464bc2be

Child:

188:bcfe06ba3d64

diff -r 707f6e361f3e -r 0387e8f68319 targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c	Fri Jun 22 16:45:37 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/system_clock.c	Thu Sep 06 13:40:20 2018 +0100
@@ -32,7 +32,7 @@
 
 #include "stm32l4xx.h"
 #include "nvic_addr.h"
-#include "mbed_assert.h"
+#include "mbed_error.h"
 
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
@@ -72,7 +72,7 @@
 {
     /* FPU settings ------------------------------------------------------------*/
 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
 #endif
     /* Reset the RCC clock configuration to the default reset state ------------*/
     /* Set MSION bit */
@@ -126,7 +126,7 @@
         {
 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
             /* 3- If fail start with HSI clock */
-            if (SetSysClock_PLL_HSI()==0)
+            if (SetSysClock_PLL_HSI() == 0)
 #endif
             {
 #if ((CLOCK_SOURCE) & USE_PLL_MSI)
@@ -134,8 +134,8 @@
                 if (SetSysClock_PLL_MSI() == 0)
 #endif
                 {
-                    while(1) {
-                        MBED_ASSERT(1);
+                    {
+                        error("SetSysClock failed\n");
                     }
                 }
             }
@@ -219,10 +219,11 @@
 
     // Output clock on MCO1 pin(PA8) for debugging purpose
 #if DEBUG_MCO == 2
-    if (bypass == 0)
-        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-    else
-        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+    if (bypass == 0) {
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2);    // 4 MHz
+    } else {
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1);    // 8 MHz
+    }
 #endif
 
     return 1; // OK